990{
993 unsigned int cur_loop_depth = 0, max_loop_depth = 0;
996 const DWORD *
ptr, *prev_ins, *current_ins;
997 void *fe_data =
shader->frontend_data;
1000
1001 memset(reg_maps, 0,
sizeof(*reg_maps));
1002 memset(input_signature_elements, 0,
sizeof(input_signature_elements));
1003 memset(output_signature_elements, 0,
sizeof(output_signature_elements));
1006
1008 prev_ins = current_ins =
ptr;
1010
1012
1014 sizeof(*reg_maps->
constf))))
1015 {
1016 ERR(
"Failed to allocate constant map memory.\n");
1018 }
1019
1021 {
1023
1025
1027
1028
1030 {
1031 WARN(
"Encountered unrecognised or invalid instruction.\n");
1033 }
1034
1035
1038 {
1040 unsigned int reg_idx = semantic->
reg.reg.idx[0].offset;
1041
1042 switch (semantic->
reg.reg.type)
1043 {
1044
1047 {
1048 ERR(
"Invalid input register index %u.\n", reg_idx);
1049 break;
1050 }
1056 break;
1057
1058
1061 {
1062 ERR(
"Invalid output register index %u.\n", reg_idx);
1063 break;
1064 }
1071 break;
1072
1077 {
1078 ERR(
"Invalid resource index %u.\n", reg_idx);
1079 break;
1080 }
1083 break;
1084
1087 {
1088 ERR(
"Invalid UAV resource index %u.\n", reg_idx);
1089 break;
1090 }
1093 if (ins.flags)
1094 FIXME(
"Ignoring typed UAV flags %#x.\n", ins.flags);
1095 break;
1096
1097 default:
1098 TRACE(
"Not recording DCL register type %#x.\n", semantic->
reg.reg.type);
1099 break;
1100 }
1101 }
1103 {
1106 ERR(
"Invalid CB index %u.\n",
reg->idx[0].offset);
1107 else
1109 }
1111 {
1113 {
1115 shader->u.ps.force_early_depth_stencil =
TRUE;
1116 else
1117 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1118 ins.handler_idx, shader_version.type);
1119 }
1120 else
1121 {
1122 WARN(
"Ignoring global flags %#x.\n", ins.flags);
1123 }
1124 }
1126 {
1128 shader->u.gs.instance_count = ins.declaration.count;
1129 else
1130 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1131 ins.handler_idx, shader_version.type);
1132 }
1135 {
1136 if (phase)
1138 else
1139 FIXME(
"Instruction %s outside of shader phase.\n",
1141 }
1143 {
1145 FIXME(
"Multiple immediate constant buffers.\n");
1146 reg_maps->
icb = ins.declaration.icb;
1147 }
1149 {
1150 if (phase)
1151 {
1152 FIXME(
"Indexable temporary registers not supported.\n");
1153 }
1154 else
1155 {
1157
1160
1161 *
reg = ins.declaration.indexable_temp;
1163 }
1164 }
1166 {
1168 shader->u.gs.input_type = ins.declaration.primitive_type.type;
1169 else
1170 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1171 ins.handler_idx, shader_version.type);
1172 }
1174 {
1175 unsigned int reg_idx = ins.declaration.dst.reg.idx[0].offset;
1177 {
1178 ERR(
"Invalid register index %u.\n", reg_idx);
1179 break;
1180 }
1183 else
1184 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1185 ins.handler_idx, shader_version.type);
1186 }
1188 {
1192 {
1194 shader->u.ps.depth_output = ins.declaration.dst.reg.type;
1195 else
1196 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1197 ins.handler_idx, shader_version.type);
1198 }
1199 }
1201 {
1203 shader->u.hs.output_vertex_count = ins.declaration.count;
1204 else
1205 FIXME(
"Invalid instruction %#x for shader type %#x.\n", ins.handler_idx, shader_version.type);
1206 }
1208 {
1210 shader->u.gs.output_type = ins.declaration.primitive_type.type;
1211 else
1212 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1213 ins.handler_idx, shader_version.type);
1214 }
1216 {
1217 unsigned int reg_idx = ins.declaration.dst.reg.idx[0].offset;
1219 {
1220 ERR(
"Invalid resource index %u.\n", reg_idx);
1221 break;
1222 }
1226 }
1228 {
1229 unsigned int reg_idx = ins.declaration.structured_resource.reg.reg.idx[0].offset;
1231 {
1232 ERR(
"Invalid resource index %u.\n", reg_idx);
1233 break;
1234 }
1238 reg_maps->
resource_info[reg_idx].stride = ins.declaration.structured_resource.byte_stride / 4;
1239 }
1241 {
1244 }
1246 {
1247 if (phase)
1249 else
1251 }
1253 {
1255 shader->u.ds.tessellator_domain = ins.declaration.tessellator_domain;
1257 FIXME(
"Invalid instruction %#x for shader type %#x.\n", ins.handler_idx, shader_version.type);
1258 }
1260 {
1262 shader->u.hs.tessellator_output_primitive = ins.declaration.tessellator_output_primitive;
1263 else
1264 FIXME(
"Invalid instruction %#x for shader type %#x.\n", ins.handler_idx, shader_version.type);
1265 }
1267 {
1269 shader->u.hs.tessellator_partitioning = ins.declaration.tessellator_partitioning;
1270 else
1271 FIXME(
"Invalid instruction %#x for shader type %#x.\n", ins.handler_idx, shader_version.type);
1272 }
1274 {
1276 ins.declaration.tgsm_raw.byte_count / 4, 0)))
1278 }
1280 {
1281 unsigned int stride = ins.declaration.tgsm_structured.byte_stride / 4;
1282 unsigned int size =
stride * ins.declaration.tgsm_structured.structure_count;
1284 ins.declaration.tgsm_structured.reg.reg.idx[0].offset,
size,
stride)))
1286 }
1288 {
1290 {
1291 shader->u.cs.thread_group_size = ins.declaration.thread_group_size;
1292 }
1293 else
1294 {
1295 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1296 ins.handler_idx, shader_version.type);
1297 }
1298 }
1300 {
1301 unsigned int reg_idx = ins.declaration.dst.reg.idx[0].offset;
1303 {
1304 ERR(
"Invalid UAV resource index %u.\n", reg_idx);
1305 break;
1306 }
1307 if (ins.flags)
1308 FIXME(
"Ignoring raw UAV flags %#x.\n", ins.flags);
1312 }
1314 {
1315 unsigned int reg_idx = ins.declaration.structured_resource.reg.reg.idx[0].offset;
1317 {
1318 ERR(
"Invalid UAV resource index %u.\n", reg_idx);
1319 break;
1320 }
1321 if (ins.flags)
1322 FIXME(
"Ignoring structured UAV flags %#x.\n", ins.flags);
1326 reg_maps->
uav_resource_info[reg_idx].stride = ins.declaration.structured_resource.byte_stride / 4;
1327 }
1329 {
1331 shader->u.gs.vertices_out = ins.declaration.count;
1332 else
1333 FIXME(
"Invalid instruction %#x for shader type %#x.\n",
1334 ins.handler_idx, shader_version.type);
1335 }
1337 {
1340
1343
1344 lconst->
idx = ins.dst[0].reg.idx[0].offset;
1347
1348
1350 {
1359 }
1360
1362
1365 {
1367 }
1368 }
1370 {
1372
1375
1376 lconst->
idx = ins.dst[0].reg.idx[0].offset;
1378
1381 }
1383 {
1385
1388
1389 lconst->
idx = ins.dst[0].reg.idx[0].offset;
1391
1394 }
1395
1399 {
1402 }
1403
1405 {
1406 reg_maps->
labels |= 1u << ins.src[0].reg.idx[0].offset;
1407 }
1408
1409 else
1410 {
1413
1414
1415
1416
1417
1418
1419
1420 for (
i = 0;
i < ins.dst_count; ++
i)
1421 {
1423 shader_version.type, constf_size))
1425
1427 {
1428 UINT idx = ins.dst[
i].reg.idx[0].offset;
1429
1430 switch (ins.dst[
i].reg.type)
1431 {
1433 if (shader_version.major >= 3)
1434 break;
1436 {
1437 case 0:
1441 break;
1442
1443 case 1:
1447 break;
1448
1449 case 2:
1453 break;
1454 }
1455 break;
1456
1458 if (shader_version.major >= 3)
1459 break;
1461 {
1464 {
1465 output_signature_elements[
idx].mask |= ins.dst[
i].write_mask;
1466 }
1467 else
1468 {
1472 }
1473 }
1474 break;
1475
1477 if (shader_version.major >= 3)
1478 {
1480 {
1481 WARN(
"Invalid output register index %u.\n",
idx);
1482 break;
1483 }
1485 break;
1486 }
1488 {
1489 WARN(
"Invalid texcoord index %u.\n",
idx);
1490 break;
1491 }
1494 {
1495 output_signature_elements[
idx].mask |= ins.dst[
i].write_mask;
1496 }
1497 else
1498 {
1502 }
1503 break;
1504
1505 default:
1506 break;
1507 }
1508 }
1509
1511 {
1513 {
1514
1515
1516
1517
1518
1519
1520
1524 {
1525
1527 }
1528 }
1529
1530
1531
1533 && ins.dst[
i].reg.idx[0].offset ==
shader->u.ps.color0_reg)
1534 {
1536 }
1537 }
1538
1539
1540 if (shader_version.major == 1
1552 {
1553 unsigned int reg_idx = ins.dst[
i].reg.idx[0].offset;
1554
1556 {
1557 WARN(
"Invalid 1.x sampler index %u.\n", reg_idx);
1558 continue;
1559 }
1560
1561 TRACE(
"Setting fake 2D resource for 1.x pixelshader.\n");
1565
1566
1569 {
1570 reg_maps->
bumpmat |= 1u << reg_idx;
1572 {
1574 }
1575 }
1576 }
1578 {
1579 reg_maps->
bumpmat |= 1u << ins.dst[
i].reg.idx[0].offset;
1580 }
1581 }
1582
1584 {
1585 unsigned int reg_idx = ins.src[0].reg.idx[0].offset;
1587 {
1588 ERR(
"Invalid UAV index %u.\n", reg_idx);
1589 break;
1590 }
1592 }
1599 {
1600 unsigned int reg_idx;
1602 reg_idx = ins.src[1].reg.idx[0].offset;
1604 reg_idx = ins.src[2].reg.idx[0].offset;
1606 reg_idx = ins.dst[0].reg.idx[0].offset;
1608 reg_idx = ins.src[0].reg.idx[0].offset;
1609 else
1610 reg_idx = ins.dst[1].reg.idx[0].offset;
1612 {
1613 ERR(
"Invalid UAV index %u.\n", reg_idx);
1614 break;
1615 }
1617 }
1619 {
1621 }
1625 {
1627 }
1631 {
1633 }
1642 {
1643 ++cur_loop_depth;
1644 if (cur_loop_depth > max_loop_depth)
1645 max_loop_depth = cur_loop_depth;
1646 }
1649 {
1650 --cur_loop_depth;
1651 }
1660 {
1662 ins.src[2].reg.idx[0].offset, reg_maps->
sampler_map.count);
1663 }
1666 {
1668 ins.src[3].reg.idx[0].offset, reg_maps->
sampler_map.count);
1669 }
1671 {
1674 }
1679 {
1682 }
1685 {
1688 }
1689
1690 if (ins.predicate)
1692 shader_version.type, constf_size))
1694
1695 for (
i = 0;
i < ins.src_count; ++
i)
1696 {
1699
1701 shader_version.type, constf_size))
1704 {
1705 ++
reg.idx[0].offset;
1707 shader_version.type, constf_size))
1710 }
1711
1712 if (color0_mov)
1713 {
1716 {
1718 shader->u.ps.color0_reg = ins.src[
i].reg.idx[0].offset;
1719 }
1720 }
1721 }
1722 }
1723
1724 prev_ins = current_ins;
1725 }
1727
1728 if (phase)
1729 {
1730 phase->
end = prev_ins;
1732 }
1733
1734
1735
1737 reg_maps->
rt_mask |= (1u << 0);
1738
1740 {
1742 {
1744 {
1746 {
1747 WARN(
"Invalid input signature register index %u.\n", input_signature->
elements[
i].register_idx);
1749 }
1750 }
1752 {
1757 }
1759 }
1760 }
1762 {
1766
1770
1773 {
1775 continue;
1776 input_signature_elements[
i].register_idx =
i;
1777 *
e++ = input_signature_elements[
i];
1778 }
1779 }
1780
1782 {
1784 {
1787
1790 {
1794 }
1796 {
1800 }
1801 }
1802 }
1804 {
1807
1811
1814 {
1816 continue;
1817 *
e++ = output_signature_elements[
i];
1818 }
1819 }
1820
1822}
static void * heap_alloc(size_t len)
static void list_add_tail(struct list_entry *head, struct list_entry *entry)
static void list_add_head(struct list_entry *head, struct list_entry *entry)
static HRESULT shader_calculate_clip_or_cull_distance_mask(const struct wined3d_shader_signature_element *e, unsigned int *mask)
static void shader_signature_from_usage(struct wined3d_shader_signature_element *e, enum wined3d_decl_usage usage, UINT usage_idx, UINT reg_idx, DWORD write_mask)
static void shader_set_limits(struct wined3d_shader *shader)
static unsigned int get_instr_extra_regcount(enum WINED3D_SHADER_INSTRUCTION_HANDLER instr, unsigned int param)
static void shader_signature_from_semantic(struct wined3d_shader_signature_element *e, const struct wined3d_shader_semantic *s)
static HRESULT shader_reg_maps_add_tgsm(struct wined3d_shader_reg_maps *reg_maps, unsigned int register_idx, unsigned int size, unsigned int stride)
static HRESULT shader_record_shader_phase(struct wined3d_shader *shader, struct wined3d_shader_phase **current_phase, const struct wined3d_shader_instruction *ins, const DWORD *current_instruction_ptr, const DWORD *previous_instruction_ptr)
static void shader_record_sample(struct wined3d_shader_reg_maps *reg_maps, unsigned int resource_idx, unsigned int sampler_idx, unsigned int bind_idx)
const char * debug_d3dshaderinstructionhandler(enum WINED3D_SHADER_INSTRUCTION_HANDLER handler_idx)
static BOOL shader_record_register_usage(struct wined3d_shader *shader, struct wined3d_shader_reg_maps *reg_maps, const struct wined3d_shader_register *reg, enum wined3d_shader_type shader_type, unsigned int constf_size)
static void wined3d_insert_interpolation_mode(DWORD *packed_interpolation_mode, unsigned int register_idx, enum wined3d_shader_interpolation_mode mode)
GLuint GLuint GLsizei count
unsigned int instance_count
unsigned int temporary_count
UINT cb_sizes[WINED3D_MAX_CBS]
DWORD sampler_comparison_mode
DWORD texcoord_mask[MAX_REG_TEXCRD]
const struct wined3d_shader_immediate_constant_buffer * icb
unsigned int min_rel_offset
unsigned int temporary_count
union wined3d_shader_reg_maps::@273 u
BYTE output_registers_mask[MAX_REG_OUTPUT]
struct wined3d_shader_resource_info uav_resource_info[MAX_UNORDERED_ACCESS_VIEWS]
struct wined3d_shader_signature_element * elements
@ WINED3D_SV_CULL_DISTANCE
@ WINED3D_SV_CLIP_DISTANCE
@ WINED3D_SV_IS_FRONT_FACE
#define WINED3D_VIEW_BUFFER_RAW
@ WINED3DSIH_DCL_TESSELLATOR_PARTITIONING
@ WINED3DSIH_GATHER4_PO_C
@ WINED3DSIH_IMM_ATOMIC_XOR
@ WINED3DSIH_DCL_CONSTANT_BUFFER
@ WINED3DSIH_TEXM3x3VSPEC
@ WINED3DSIH_DCL_IMMEDIATE_CONSTANT_BUFFER
@ WINED3DSIH_DCL_THREAD_GROUP
@ WINED3DSIH_DCL_TESSELLATOR_OUTPUT_PRIMITIVE
@ WINED3DSIH_HS_CONTROL_POINT_PHASE
@ WINED3DSIH_LD_STRUCTURED
@ WINED3DSIH_IMM_ATOMIC_AND
@ WINED3DSIH_IMM_ATOMIC_CONSUME
@ WINED3DSIH_HS_FORK_PHASE
@ WINED3DSIH_DCL_VERTICES_OUT
@ WINED3DSIH_HS_JOIN_PHASE
@ WINED3DSIH_DCL_OUTPUT_TOPOLOGY
@ WINED3DSIH_DCL_GS_INSTANCES
@ WINED3DSIH_DCL_TGSM_RAW
@ WINED3DSIH_DCL_UAV_TYPED
@ WINED3DSIH_DCL_INPUT_PS
@ WINED3DSIH_LD_UAV_TYPED
@ WINED3DSIH_DCL_UAV_STRUCTURED
@ WINED3DSIH_DCL_HS_FORK_PHASE_INSTANCE_COUNT
@ WINED3DSIH_DCL_GLOBAL_FLAGS
@ WINED3DSIH_IMM_ATOMIC_ALLOC
@ WINED3DSIH_DCL_TESSELLATOR_DOMAIN
@ WINED3DSIH_DCL_TGSM_STRUCTURED
@ WINED3DSIH_DCL_OUTPUT_CONTROL_POINT_COUNT
@ WINED3DSIH_DCL_INDEXABLE_TEMP
@ WINED3DSIH_DCL_RESOURCE_RAW
@ WINED3DSIH_DCL_INPUT_PRIMITIVE
@ WINED3DSIH_DCL_HS_JOIN_PHASE_INSTANCE_COUNT
@ WINED3DSIH_DCL_RESOURCE_STRUCTURED
#define WINED3DSI_SAMPLER_COMPARISON_MODE
#define MAX_UNORDERED_ACCESS_VIEWS
#define WINED3D_SAMPLER_DEFAULT
@ WINED3D_SHADER_TYPE_DOMAIN
@ WINED3D_SHADER_TYPE_COMPUTE
static unsigned int wined3d_popcount(unsigned int x)