ReactOS 0.4.15-dev-7674-gc0b4db1
ArchitecturalMsr.h
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1
18#ifndef __INTEL_ARCHITECTURAL_MSR_H__
19#define __INTEL_ARCHITECTURAL_MSR_H__
20
37#define MSR_IA32_P5_MC_ADDR 0x00000000
38
55#define MSR_IA32_P5_MC_TYPE 0x00000001
56
74#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
75
93#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
94
114#define MSR_IA32_PLATFORM_ID 0x00000017
115
119typedef union {
123 struct {
142 } Bits;
148
167#define MSR_IA32_APIC_BASE 0x0000001B
168
172typedef union {
176 struct {
200 } Bits;
206
226#define MSR_IA32_FEATURE_CONTROL 0x0000003A
227
231typedef union {
235 struct {
299 } Bits;
309
330#define MSR_IA32_TSC_ADJUST 0x0000003B
331
352#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
353
374#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
375
379typedef union {
383 struct {
395 } Bits;
401
426#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
427#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
428#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
429#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
431
451#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
452
456typedef union {
460 struct {
481 } Bits;
491
496typedef struct {
503 //
520 UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
522
526#define STM_FEATURES_IA32E 0x1
530
547#define MSR_IA32_SMBASE 0x0000009E
548
574#define MSR_IA32_PMC0 0x000000C1
575#define MSR_IA32_PMC1 0x000000C2
576#define MSR_IA32_PMC2 0x000000C3
577#define MSR_IA32_PMC3 0x000000C4
578#define MSR_IA32_PMC4 0x000000C5
579#define MSR_IA32_PMC5 0x000000C6
580#define MSR_IA32_PMC6 0x000000C7
581#define MSR_IA32_PMC7 0x000000C8
583
603#define MSR_IA32_MPERF 0x000000E7
604
624#define MSR_IA32_APERF 0x000000E8
625
644#define MSR_IA32_MTRRCAP 0x000000FE
645
649typedef union {
653 struct {
674 } Bits;
684
703#define MSR_IA32_SYSENTER_CS 0x00000174
704
708typedef union {
712 struct {
716 UINT32 CS : 16;
719 } Bits;
729
746#define MSR_IA32_SYSENTER_ESP 0x00000175
747
764#define MSR_IA32_SYSENTER_EIP 0x00000176
765
784#define MSR_IA32_MCG_CAP 0x00000179
785
789typedef union {
793 struct {
847 } Bits;
857
877#define MSR_IA32_MCG_STATUS 0x0000017A
878
882typedef union {
886 struct {
908 } Bits;
918
935#define MSR_IA32_MCG_CTL 0x0000017B
936
959#define MSR_IA32_PERFEVTSEL0 0x00000186
960#define MSR_IA32_PERFEVTSEL1 0x00000187
961#define MSR_IA32_PERFEVTSEL2 0x00000188
962#define MSR_IA32_PERFEVTSEL3 0x00000189
964
969typedef union {
973 struct {
1027 } Bits;
1037
1056#define MSR_IA32_PERF_STATUS 0x00000198
1057
1061typedef union {
1065 struct {
1072 } Bits;
1082
1101#define MSR_IA32_PERF_CTL 0x00000199
1102
1106typedef union {
1110 struct {
1122 } Bits;
1128
1148#define MSR_IA32_CLOCK_MODULATION 0x0000019A
1149
1153typedef union {
1157 struct {
1175 } Bits;
1185
1207#define MSR_IA32_THERM_INTERRUPT 0x0000019B
1208
1212typedef union {
1216 struct {
1261 } Bits;
1271
1291#define MSR_IA32_THERM_STATUS 0x0000019C
1292
1296typedef union {
1300 struct {
1381 } Bits;
1391
1411#define MSR_IA32_MISC_ENABLE 0x000001A0
1412
1416typedef union {
1420 struct {
1516 } Bits;
1522
1541#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1542
1546typedef union {
1550 struct {
1558 } Bits;
1568
1588#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1589
1593typedef union {
1597 struct {
1653 } Bits;
1663
1685#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1686
1690typedef union {
1694 struct {
1735 } Bits;
1745
1765#define MSR_IA32_DEBUGCTL 0x000001D9
1766
1770typedef union {
1774 struct {
1845 } Bits;
1855
1875#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1876
1880typedef union {
1884 struct {
1895 } Bits;
1905
1925#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1926
1930typedef union {
1934 struct {
1945 } Bits;
1955
1971#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1972
1989#define MSR_IA32_CPU_DCA_CAP 0x000001F9
1990
2009#define MSR_IA32_DCA_0_CAP 0x000001FA
2010
2014typedef union {
2018 struct {
2054 } Bits;
2064
2094#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2095#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2096#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2097#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2098#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2099#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2100#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2101#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2102#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2103#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2105
2110typedef union {
2114 struct {
2133 } Bits;
2139
2169#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2170#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2171#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2172#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2173#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2174#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2175#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2176#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2177#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2178#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2180
2185typedef union {
2189 struct {
2208 } Bits;
2214
2231#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2232
2249#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2250
2267#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2268
2285#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2286
2303#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2304
2321#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2322
2339#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2340
2357#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2358
2375#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2376
2393#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2394
2411#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2412
2431#define MSR_IA32_PAT 0x00000277
2432
2436typedef union {
2440 struct {
2481 } Bits;
2487
2539#define MSR_IA32_MC0_CTL2 0x00000280
2540#define MSR_IA32_MC1_CTL2 0x00000281
2541#define MSR_IA32_MC2_CTL2 0x00000282
2542#define MSR_IA32_MC3_CTL2 0x00000283
2543#define MSR_IA32_MC4_CTL2 0x00000284
2544#define MSR_IA32_MC5_CTL2 0x00000285
2545#define MSR_IA32_MC6_CTL2 0x00000286
2546#define MSR_IA32_MC7_CTL2 0x00000287
2547#define MSR_IA32_MC8_CTL2 0x00000288
2548#define MSR_IA32_MC9_CTL2 0x00000289
2549#define MSR_IA32_MC10_CTL2 0x0000028A
2550#define MSR_IA32_MC11_CTL2 0x0000028B
2551#define MSR_IA32_MC12_CTL2 0x0000028C
2552#define MSR_IA32_MC13_CTL2 0x0000028D
2553#define MSR_IA32_MC14_CTL2 0x0000028E
2554#define MSR_IA32_MC15_CTL2 0x0000028F
2555#define MSR_IA32_MC16_CTL2 0x00000290
2556#define MSR_IA32_MC17_CTL2 0x00000291
2557#define MSR_IA32_MC18_CTL2 0x00000292
2558#define MSR_IA32_MC19_CTL2 0x00000293
2559#define MSR_IA32_MC20_CTL2 0x00000294
2560#define MSR_IA32_MC21_CTL2 0x00000295
2561#define MSR_IA32_MC22_CTL2 0x00000296
2562#define MSR_IA32_MC23_CTL2 0x00000297
2563#define MSR_IA32_MC24_CTL2 0x00000298
2564#define MSR_IA32_MC25_CTL2 0x00000299
2565#define MSR_IA32_MC26_CTL2 0x0000029A
2566#define MSR_IA32_MC27_CTL2 0x0000029B
2567#define MSR_IA32_MC28_CTL2 0x0000029C
2568#define MSR_IA32_MC29_CTL2 0x0000029D
2569#define MSR_IA32_MC30_CTL2 0x0000029E
2570#define MSR_IA32_MC31_CTL2 0x0000029F
2572
2577typedef union {
2581 struct {
2593 } Bits;
2603
2622#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2623
2627typedef union {
2631 struct {
2647 } Bits;
2657
2675#define MSR_IA32_FIXED_CTR0 0x00000309
2676
2694#define MSR_IA32_FIXED_CTR1 0x0000030A
2695
2713#define MSR_IA32_FIXED_CTR2 0x0000030B
2714
2733#define MSR_IA32_PERF_CAPABILITIES 0x00000345
2734
2738typedef union {
2742 struct {
2769 } Bits;
2779
2801#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2802
2806typedef union {
2810 struct {
2873 } Bits;
2883
2901#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2902
2906typedef union {
2910 struct {
2988 } Bits;
2994
3016#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3017
3021typedef union {
3025 struct {
3038 } Bits;
3044
3064#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3065
3069typedef union {
3073 struct {
3106 } Bits;
3112
3132#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3133
3137typedef union {
3141 struct {
3186 } Bits;
3192
3212#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3213
3217typedef union {
3221 struct {
3261 } Bits;
3267
3286#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3287
3291typedef union {
3295 struct {
3313 } Bits;
3319
3338#define MSR_IA32_PEBS_ENABLE 0x000003F1
3339
3343typedef union {
3347 struct {
3363 } Bits;
3369
3415#define MSR_IA32_MC0_CTL 0x00000400
3416#define MSR_IA32_MC1_CTL 0x00000404
3417#define MSR_IA32_MC2_CTL 0x00000408
3418#define MSR_IA32_MC3_CTL 0x0000040C
3419#define MSR_IA32_MC4_CTL 0x00000410
3420#define MSR_IA32_MC5_CTL 0x00000414
3421#define MSR_IA32_MC6_CTL 0x00000418
3422#define MSR_IA32_MC7_CTL 0x0000041C
3423#define MSR_IA32_MC8_CTL 0x00000420
3424#define MSR_IA32_MC9_CTL 0x00000424
3425#define MSR_IA32_MC10_CTL 0x00000428
3426#define MSR_IA32_MC11_CTL 0x0000042C
3427#define MSR_IA32_MC12_CTL 0x00000430
3428#define MSR_IA32_MC13_CTL 0x00000434
3429#define MSR_IA32_MC14_CTL 0x00000438
3430#define MSR_IA32_MC15_CTL 0x0000043C
3431#define MSR_IA32_MC16_CTL 0x00000440
3432#define MSR_IA32_MC17_CTL 0x00000444
3433#define MSR_IA32_MC18_CTL 0x00000448
3434#define MSR_IA32_MC19_CTL 0x0000044C
3435#define MSR_IA32_MC20_CTL 0x00000450
3436#define MSR_IA32_MC21_CTL 0x00000454
3437#define MSR_IA32_MC22_CTL 0x00000458
3438#define MSR_IA32_MC23_CTL 0x0000045C
3439#define MSR_IA32_MC24_CTL 0x00000460
3440#define MSR_IA32_MC25_CTL 0x00000464
3441#define MSR_IA32_MC26_CTL 0x00000468
3442#define MSR_IA32_MC27_CTL 0x0000046C
3443#define MSR_IA32_MC28_CTL 0x00000470
3445
3491#define MSR_IA32_MC0_STATUS 0x00000401
3492#define MSR_IA32_MC1_STATUS 0x00000405
3493#define MSR_IA32_MC2_STATUS 0x00000409
3494#define MSR_IA32_MC3_STATUS 0x0000040D
3495#define MSR_IA32_MC4_STATUS 0x00000411
3496#define MSR_IA32_MC5_STATUS 0x00000415
3497#define MSR_IA32_MC6_STATUS 0x00000419
3498#define MSR_IA32_MC7_STATUS 0x0000041D
3499#define MSR_IA32_MC8_STATUS 0x00000421
3500#define MSR_IA32_MC9_STATUS 0x00000425
3501#define MSR_IA32_MC10_STATUS 0x00000429
3502#define MSR_IA32_MC11_STATUS 0x0000042D
3503#define MSR_IA32_MC12_STATUS 0x00000431
3504#define MSR_IA32_MC13_STATUS 0x00000435
3505#define MSR_IA32_MC14_STATUS 0x00000439
3506#define MSR_IA32_MC15_STATUS 0x0000043D
3507#define MSR_IA32_MC16_STATUS 0x00000441
3508#define MSR_IA32_MC17_STATUS 0x00000445
3509#define MSR_IA32_MC18_STATUS 0x00000449
3510#define MSR_IA32_MC19_STATUS 0x0000044D
3511#define MSR_IA32_MC20_STATUS 0x00000451
3512#define MSR_IA32_MC21_STATUS 0x00000455
3513#define MSR_IA32_MC22_STATUS 0x00000459
3514#define MSR_IA32_MC23_STATUS 0x0000045D
3515#define MSR_IA32_MC24_STATUS 0x00000461
3516#define MSR_IA32_MC25_STATUS 0x00000465
3517#define MSR_IA32_MC26_STATUS 0x00000469
3518#define MSR_IA32_MC27_STATUS 0x0000046D
3519#define MSR_IA32_MC28_STATUS 0x00000471
3521
3567#define MSR_IA32_MC0_ADDR 0x00000402
3568#define MSR_IA32_MC1_ADDR 0x00000406
3569#define MSR_IA32_MC2_ADDR 0x0000040A
3570#define MSR_IA32_MC3_ADDR 0x0000040E
3571#define MSR_IA32_MC4_ADDR 0x00000412
3572#define MSR_IA32_MC5_ADDR 0x00000416
3573#define MSR_IA32_MC6_ADDR 0x0000041A
3574#define MSR_IA32_MC7_ADDR 0x0000041E
3575#define MSR_IA32_MC8_ADDR 0x00000422
3576#define MSR_IA32_MC9_ADDR 0x00000426
3577#define MSR_IA32_MC10_ADDR 0x0000042A
3578#define MSR_IA32_MC11_ADDR 0x0000042E
3579#define MSR_IA32_MC12_ADDR 0x00000432
3580#define MSR_IA32_MC13_ADDR 0x00000436
3581#define MSR_IA32_MC14_ADDR 0x0000043A
3582#define MSR_IA32_MC15_ADDR 0x0000043E
3583#define MSR_IA32_MC16_ADDR 0x00000442
3584#define MSR_IA32_MC17_ADDR 0x00000446
3585#define MSR_IA32_MC18_ADDR 0x0000044A
3586#define MSR_IA32_MC19_ADDR 0x0000044E
3587#define MSR_IA32_MC20_ADDR 0x00000452
3588#define MSR_IA32_MC21_ADDR 0x00000456
3589#define MSR_IA32_MC22_ADDR 0x0000045A
3590#define MSR_IA32_MC23_ADDR 0x0000045E
3591#define MSR_IA32_MC24_ADDR 0x00000462
3592#define MSR_IA32_MC25_ADDR 0x00000466
3593#define MSR_IA32_MC26_ADDR 0x0000046A
3594#define MSR_IA32_MC27_ADDR 0x0000046E
3595#define MSR_IA32_MC28_ADDR 0x00000472
3597
3643#define MSR_IA32_MC0_MISC 0x00000403
3644#define MSR_IA32_MC1_MISC 0x00000407
3645#define MSR_IA32_MC2_MISC 0x0000040B
3646#define MSR_IA32_MC3_MISC 0x0000040F
3647#define MSR_IA32_MC4_MISC 0x00000413
3648#define MSR_IA32_MC5_MISC 0x00000417
3649#define MSR_IA32_MC6_MISC 0x0000041B
3650#define MSR_IA32_MC7_MISC 0x0000041F
3651#define MSR_IA32_MC8_MISC 0x00000423
3652#define MSR_IA32_MC9_MISC 0x00000427
3653#define MSR_IA32_MC10_MISC 0x0000042B
3654#define MSR_IA32_MC11_MISC 0x0000042F
3655#define MSR_IA32_MC12_MISC 0x00000433
3656#define MSR_IA32_MC13_MISC 0x00000437
3657#define MSR_IA32_MC14_MISC 0x0000043B
3658#define MSR_IA32_MC15_MISC 0x0000043F
3659#define MSR_IA32_MC16_MISC 0x00000443
3660#define MSR_IA32_MC17_MISC 0x00000447
3661#define MSR_IA32_MC18_MISC 0x0000044B
3662#define MSR_IA32_MC19_MISC 0x0000044F
3663#define MSR_IA32_MC20_MISC 0x00000453
3664#define MSR_IA32_MC21_MISC 0x00000457
3665#define MSR_IA32_MC22_MISC 0x0000045B
3666#define MSR_IA32_MC23_MISC 0x0000045F
3667#define MSR_IA32_MC24_MISC 0x00000463
3668#define MSR_IA32_MC25_MISC 0x00000467
3669#define MSR_IA32_MC26_MISC 0x0000046B
3670#define MSR_IA32_MC27_MISC 0x0000046F
3671#define MSR_IA32_MC28_MISC 0x00000473
3673
3690#define MSR_IA32_VMX_BASIC 0x00000480
3691
3695typedef union {
3699 struct {
3781 } Bits;
3787
3791#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3792#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3796
3813#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3814
3832#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3833
3850#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3851
3868#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3869
3886#define MSR_IA32_VMX_MISC 0x00000485
3887
3891typedef union {
3895 struct {
3979 } Bits;
3985
4002#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4003
4020#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4021
4038#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4039
4056#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4057
4074#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4075
4093#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4094
4112#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4113
4131#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4132
4150#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4151
4168#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4169
4186#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4187
4204#define MSR_IA32_VMX_VMFUNC 0x00000491
4205
4231#define MSR_IA32_A_PMC0 0x000004C1
4232#define MSR_IA32_A_PMC1 0x000004C2
4233#define MSR_IA32_A_PMC2 0x000004C3
4234#define MSR_IA32_A_PMC3 0x000004C4
4235#define MSR_IA32_A_PMC4 0x000004C5
4236#define MSR_IA32_A_PMC5 0x000004C6
4237#define MSR_IA32_A_PMC6 0x000004C7
4238#define MSR_IA32_A_PMC7 0x000004C8
4240
4259#define MSR_IA32_MCG_EXT_CTL 0x000004D0
4260
4264typedef union {
4268 struct {
4275 } Bits;
4285
4304#define MSR_IA32_SGX_SVN_STATUS 0x00000500
4305
4309typedef union {
4313 struct {
4327 } Bits;
4337
4358#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4359
4363typedef union {
4367 struct {
4377 } Bits;
4383
4404#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4405
4409typedef union {
4413 struct {
4423 } Bits;
4429
4433typedef union {
4437 struct {
4479 } Bits;
4485
4489typedef enum {
4507
4526#define MSR_IA32_RTIT_CTL 0x00000570
4527
4531typedef union {
4535 struct {
4624 } Bits;
4630
4649#define MSR_IA32_RTIT_STATUS 0x00000571
4650
4654typedef union {
4658 struct {
4687 } Bits;
4693
4713#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4714
4718typedef union {
4722 struct {
4732 } Bits;
4738
4761#define MSR_IA32_RTIT_ADDR0_A 0x00000580
4762#define MSR_IA32_RTIT_ADDR1_A 0x00000582
4763#define MSR_IA32_RTIT_ADDR2_A 0x00000584
4764#define MSR_IA32_RTIT_ADDR3_A 0x00000586
4766
4789#define MSR_IA32_RTIT_ADDR0_B 0x00000581
4790#define MSR_IA32_RTIT_ADDR1_B 0x00000583
4791#define MSR_IA32_RTIT_ADDR2_B 0x00000585
4792#define MSR_IA32_RTIT_ADDR3_B 0x00000587
4794
4800typedef union {
4804 struct {
4817 } Bits;
4823
4846#define MSR_IA32_DS_AREA 0x00000600
4847
4865#define MSR_IA32_TSC_DEADLINE 0x000006E0
4866
4885#define MSR_IA32_PM_ENABLE 0x00000770
4886
4890typedef union {
4894 struct {
4902 } Bits;
4912
4930#define MSR_IA32_HWP_CAPABILITIES 0x00000771
4931
4935typedef union {
4939 struct {
4961 } Bits;
4971
4991#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
4992
4996typedef union {
5000 struct {
5027 } Bits;
5033
5052#define MSR_IA32_HWP_INTERRUPT 0x00000773
5053
5057typedef union {
5061 struct {
5074 } Bits;
5084
5104#define MSR_IA32_HWP_REQUEST 0x00000774
5105
5109typedef union {
5113 struct {
5145 } Bits;
5151
5171#define MSR_IA32_HWP_STATUS 0x00000777
5172
5176typedef union {
5180 struct {
5194 } Bits;
5204
5221#define MSR_IA32_X2APIC_APICID 0x00000802
5222
5239#define MSR_IA32_X2APIC_VERSION 0x00000803
5240
5258#define MSR_IA32_X2APIC_TPR 0x00000808
5259
5276#define MSR_IA32_X2APIC_PPR 0x0000080A
5277
5295#define MSR_IA32_X2APIC_EOI 0x0000080B
5296
5313#define MSR_IA32_X2APIC_LDR 0x0000080D
5314
5332#define MSR_IA32_X2APIC_SIVR 0x0000080F
5333
5358#define MSR_IA32_X2APIC_ISR0 0x00000810
5359#define MSR_IA32_X2APIC_ISR1 0x00000811
5360#define MSR_IA32_X2APIC_ISR2 0x00000812
5361#define MSR_IA32_X2APIC_ISR3 0x00000813
5362#define MSR_IA32_X2APIC_ISR4 0x00000814
5363#define MSR_IA32_X2APIC_ISR5 0x00000815
5364#define MSR_IA32_X2APIC_ISR6 0x00000816
5365#define MSR_IA32_X2APIC_ISR7 0x00000817
5367
5392#define MSR_IA32_X2APIC_TMR0 0x00000818
5393#define MSR_IA32_X2APIC_TMR1 0x00000819
5394#define MSR_IA32_X2APIC_TMR2 0x0000081A
5395#define MSR_IA32_X2APIC_TMR3 0x0000081B
5396#define MSR_IA32_X2APIC_TMR4 0x0000081C
5397#define MSR_IA32_X2APIC_TMR5 0x0000081D
5398#define MSR_IA32_X2APIC_TMR6 0x0000081E
5399#define MSR_IA32_X2APIC_TMR7 0x0000081F
5401
5426#define MSR_IA32_X2APIC_IRR0 0x00000820
5427#define MSR_IA32_X2APIC_IRR1 0x00000821
5428#define MSR_IA32_X2APIC_IRR2 0x00000822
5429#define MSR_IA32_X2APIC_IRR3 0x00000823
5430#define MSR_IA32_X2APIC_IRR4 0x00000824
5431#define MSR_IA32_X2APIC_IRR5 0x00000825
5432#define MSR_IA32_X2APIC_IRR6 0x00000826
5433#define MSR_IA32_X2APIC_IRR7 0x00000827
5435
5453#define MSR_IA32_X2APIC_ESR 0x00000828
5454
5472#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5473
5491#define MSR_IA32_X2APIC_ICR 0x00000830
5492
5510#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5511
5529#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5530
5548#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5549
5567#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5568
5586#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5587
5605#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5606
5624#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5625
5642#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5643
5661#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5662
5680#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5681
5700#define MSR_IA32_TME_ACTIVATE 0x00000982
5701
5705typedef union {
5709 struct {
5775 } Bits;
5779 UINT32 Uint32[2];
5785
5804#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5805
5809typedef union {
5813 struct {
5832 } Bits;
5842
5861#define MSR_IA32_L3_QOS_CFG 0x00000C81
5862
5866typedef union {
5870 struct {
5878 } Bits;
5888
5907#define MSR_IA32_L2_QOS_CFG 0x00000C82
5908
5912typedef union {
5916 struct {
5924 } Bits;
5934
5954#define MSR_IA32_QM_EVTSEL 0x00000C8D
5955
5959typedef union {
5963 struct {
5976 } Bits;
5982
6001#define MSR_IA32_QM_CTR 0x00000C8E
6002
6006typedef union {
6010 struct {
6029 } Bits;
6035
6055#define MSR_IA32_PQR_ASSOC 0x00000C8F
6056
6060typedef union {
6064 struct {
6077 } Bits;
6083
6103#define MSR_IA32_BNDCFGS 0x00000D90
6104
6108typedef union {
6112 struct {
6131 } Bits;
6137
6156#define MSR_IA32_XSS 0x00000DA0
6157
6161typedef union {
6165 struct {
6173 } Bits;
6183
6202#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6203
6207typedef union {
6211 struct {
6220 } Bits;
6230
6249#define MSR_IA32_PM_CTL1 0x00000DB1
6250
6254typedef union {
6258 struct {
6267 } Bits;
6277
6295#define MSR_IA32_THREAD_STALL 0x00000DB2
6296
6316#define MSR_IA32_EFER 0xC0000080
6317
6321typedef union {
6325 struct {
6349 } Bits;
6359
6376#define MSR_IA32_STAR 0xC0000081
6377
6394#define MSR_IA32_LSTAR 0xC0000082
6395
6414#define MSR_IA32_CSTAR 0xC0000083
6415
6432#define MSR_IA32_FMASK 0xC0000084
6433
6450#define MSR_IA32_FS_BASE 0xC0000100
6451
6468#define MSR_IA32_GS_BASE 0xC0000101
6469
6486#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6487
6506#define MSR_IA32_TSC_AUX 0xC0000103
6507
6511typedef union {
6515 struct {
6521 } Bits;
6531
6532#endif
RTIT_TOPA_MEMORY_SIZE
@ RtitTopaMemorySize16M
@ RtitTopaMemorySize32K
@ RtitTopaMemorySize128K
@ RtitTopaMemorySize256K
@ RtitTopaMemorySize64K
@ RtitTopaMemorySize8K
@ RtitTopaMemorySize8M
@ RtitTopaMemorySize1M
@ RtitTopaMemorySize512K
@ RtitTopaMemorySize4K
@ RtitTopaMemorySize64M
@ RtitTopaMemorySize2M
@ RtitTopaMemorySize32M
@ RtitTopaMemorySize4M
@ RtitTopaMemorySize128M
@ RtitTopaMemorySize16K
#define SIZE_2KB
Definition: Base.h:276
unsigned long long UINT64
unsigned char UINT8
unsigned int UINT32
UINT32 GdtrBaseOffset
UINT32 MsegHeaderRevision
UINT32 MonitorFeatures
UINT32 Reserved2
UINT32 BaseHi
UINT32 Reserved1
UINT32 END
UINT32 INT
UINT32 Reserved4
UINT32 STOP
UINT64 Uint64
UINT32 Base
UINT32 Reserved3
UINT32 Size
_Reserved_ PVOID Reserved
Definition: winddi.h:3974