de/d4b/ArchitecturalMsr_8h_source.html

#ifndef __INTEL_ARCHITECTURAL_MSR_H__

#define __INTEL_ARCHITECTURAL_MSR_H__


#define MSR_IA32_P5_MC_ADDR  0x00000000


#define MSR_IA32_P5_MC_TYPE  0x00000001


#define MSR_IA32_MONITOR_FILTER_SIZE  0x00000006


#define MSR_IA32_TIME_STAMP_COUNTER  0x00000010


#define MSR_IA32_PLATFORM_ID  0x00000017


typedef union {

  struct {

    UINT32    Reserved1 : 32;

    UINT32    Reserved2 : 18;

    UINT32    PlatformId : 3;

    UINT32    Reserved3  : 11;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PLATFORM_ID_REGISTER;


#define MSR_IA32_APIC_BASE  0x0000001B


typedef union {

  struct {

    UINT32    Reserved1  : 8;

    UINT32    BSP        : 1;

    UINT32    Reserved2  : 1;

    UINT32    EXTD       : 1;

    UINT32    EN         : 1;

    UINT32    ApicBase   : 20;

    UINT32    ApicBaseHi : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_APIC_BASE_REGISTER;


#define MSR_IA32_FEATURE_CONTROL  0x0000003A


typedef union {

  struct {

    UINT32    Lock : 1;

    UINT32    EnableVmxInsideSmx         : 1;

    UINT32    EnableVmxOutsideSmx        : 1;

    UINT32    Reserved1                  : 5;

    UINT32    SenterLocalFunctionEnables : 7;

    UINT32    SenterGlobalEnable         : 1;

    UINT32    Reserved2                  : 1;

    UINT32    SgxLaunchControlEnable     : 1;

    UINT32    SgxEnable                  : 1;

    UINT32    Reserved3                  : 1;

    UINT32    LmceOn                     : 1;

    UINT32    Reserved4                  : 11;

    UINT32    Reserved5                  : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_FEATURE_CONTROL_REGISTER;


#define MSR_IA32_TSC_ADJUST  0x0000003B


#define MSR_IA32_BIOS_UPDT_TRIG  0x00000079


#define MSR_IA32_BIOS_SIGN_ID  0x0000008B


typedef union {

  struct {

    UINT32    Reserved : 32;

    UINT32    MicrocodeUpdateSignature : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_BIOS_SIGN_ID_REGISTER;


#define MSR_IA32_SGXLEPUBKEYHASH0  0x0000008C

#define MSR_IA32_SGXLEPUBKEYHASH1  0x0000008D

#define MSR_IA32_SGXLEPUBKEYHASH2  0x0000008E

#define MSR_IA32_SGXLEPUBKEYHASH3  0x0000008F


#define MSR_IA32_SMM_MONITOR_CTL  0x0000009B


typedef union {

  struct {

    UINT32    Valid     : 1;

    UINT32    Reserved1 : 1;

    UINT32    BlockSmi  : 1;

    UINT32    Reserved2 : 9;

    UINT32    MsegBase  : 20;

    UINT32    Reserved3 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_SMM_MONITOR_CTL_REGISTER;


typedef struct {

  //

  UINT32    MsegHeaderRevision;

  UINT32    MonitorFeatures;

  UINT32    GdtrLimit;

  UINT32    GdtrBaseOffset;

  UINT32    CsSelector;

  UINT32    EipOffset;

  UINT32    EspOffset;

  UINT32    Cr3Offset;

  UINT8     Reserved[SIZE_2KB - 8 * sizeof (UINT32)];

} MSEG_HEADER;


#define STM_FEATURES_IA32E  0x1


#define MSR_IA32_SMBASE  0x0000009E


#define MSR_IA32_PMC0  0x000000C1

#define MSR_IA32_PMC1  0x000000C2

#define MSR_IA32_PMC2  0x000000C3

#define MSR_IA32_PMC3  0x000000C4

#define MSR_IA32_PMC4  0x000000C5

#define MSR_IA32_PMC5  0x000000C6

#define MSR_IA32_PMC6  0x000000C7

#define MSR_IA32_PMC7  0x000000C8


#define MSR_IA32_MPERF  0x000000E7


#define MSR_IA32_APERF  0x000000E8


#define MSR_IA32_MTRRCAP  0x000000FE


typedef union {

  struct {

    UINT32    VCNT      : 8;

    UINT32    FIX       : 1;

    UINT32    Reserved1 : 1;

    UINT32    WC        : 1;

    UINT32    SMRR      : 1;

    UINT32    Reserved2 : 20;

    UINT32    Reserved3 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_MTRRCAP_REGISTER;


#define MSR_IA32_SYSENTER_CS  0x00000174


typedef union {

  struct {

    UINT32    CS        : 16;

    UINT32    Reserved1 : 16;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_SYSENTER_CS_REGISTER;


#define MSR_IA32_SYSENTER_ESP  0x00000175


#define MSR_IA32_SYSENTER_EIP  0x00000176


#define MSR_IA32_MCG_CAP  0x00000179


typedef union {

  struct {

    UINT32    Count       : 8;

    UINT32    MCG_CTL_P   : 1;

    UINT32    MCG_EXT_P   : 1;

    UINT32    MCP_CMCI_P  : 1;

    UINT32    MCG_TES_P   : 1;

    UINT32    Reserved1   : 4;

    UINT32    MCG_EXT_CNT : 8;

    UINT32    MCG_SER_P   : 1;

    UINT32    Reserved2   : 1;

    UINT32    MCG_ELOG_P : 1;

    UINT32    MCG_LMCE_P : 1;

    UINT32    Reserved3  : 4;

    UINT32    Reserved4  : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_MCG_CAP_REGISTER;


#define MSR_IA32_MCG_STATUS  0x0000017A


typedef union {

  struct {

    UINT32    RIPV      : 1;

    UINT32    EIPV      : 1;

    UINT32    MCIP      : 1;

    UINT32    LMCE_S    : 1;

    UINT32    Reserved1 : 28;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_MCG_STATUS_REGISTER;


#define MSR_IA32_MCG_CTL  0x0000017B


#define MSR_IA32_PERFEVTSEL0  0x00000186

#define MSR_IA32_PERFEVTSEL1  0x00000187

#define MSR_IA32_PERFEVTSEL2  0x00000188

#define MSR_IA32_PERFEVTSEL3  0x00000189


typedef union {

  struct {

    UINT32    EventSelect : 8;

    UINT32    UMASK       : 8;

    UINT32    USR         : 1;

    UINT32    OS          : 1;

    UINT32    E           : 1;

    UINT32    PC          : 1;

    UINT32    INT         : 1;

    UINT32    ANY         : 1;

    UINT32    EN          : 1;

    UINT32    INV         : 1;

    UINT32    CMASK       : 8;

    UINT32    Reserved    : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PERFEVTSEL_REGISTER;


#define MSR_IA32_PERF_STATUS  0x00000198


typedef union {

  struct {

    UINT32    State     : 16;

    UINT32    Reserved1 : 16;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PERF_STATUS_REGISTER;


#define MSR_IA32_PERF_CTL  0x00000199


typedef union {

  struct {

    UINT32    TargetState : 16;

    UINT32    Reserved1   : 16;

    UINT32    IDA         : 1;

    UINT32    Reserved2   : 31;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PERF_CTL_REGISTER;


#define MSR_IA32_CLOCK_MODULATION  0x0000019A


typedef union {

  struct {

    UINT32    ExtendedOnDemandClockModulationDutyCycle : 1;

    UINT32    OnDemandClockModulationDutyCycle         : 3;

    UINT32    OnDemandClockModulationEnable            : 1;

    UINT32    Reserved1                                : 27;

    UINT32    Reserved2                                : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_CLOCK_MODULATION_REGISTER;


#define MSR_IA32_THERM_INTERRUPT  0x0000019B


typedef union {

  struct {

    UINT32    HighTempEnable               : 1;

    UINT32    LowTempEnable                : 1;

    UINT32    PROCHOT_Enable               : 1;

    UINT32    FORCEPR_Enable               : 1;

    UINT32    CriticalTempEnable           : 1;

    UINT32    Reserved1                    : 3;

    UINT32    Threshold1                   : 7;

    UINT32    Threshold1Enable             : 1;

    UINT32    Threshold2                   : 7;

    UINT32    Threshold2Enable             : 1;

    UINT32    PowerLimitNotificationEnable : 1;

    UINT32    Reserved2                    : 7;

    UINT32    Reserved3                    : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_THERM_INTERRUPT_REGISTER;


#define MSR_IA32_THERM_STATUS  0x0000019C


typedef union {

  struct {

    UINT32    ThermalStatus              : 1;

    UINT32    ThermalStatusLog           : 1;

    UINT32    PROCHOT_FORCEPR_Event      : 1;

    UINT32    PROCHOT_FORCEPR_Log        : 1;

    UINT32    CriticalTempStatus         : 1;

    UINT32    CriticalTempStatusLog      : 1;

    UINT32    ThermalThreshold1Status    : 1;

    UINT32    ThermalThreshold1Log       : 1;

    UINT32    ThermalThreshold2Status    : 1;

    UINT32    ThermalThreshold2Log       : 1;

    UINT32    PowerLimitStatus           : 1;

    UINT32    PowerLimitLog              : 1;

    UINT32    CurrentLimitStatus         : 1;

    UINT32    CurrentLimitLog            : 1;

    UINT32    CrossDomainLimitStatus     : 1;

    UINT32    CrossDomainLimitLog        : 1;

    UINT32    DigitalReadout             : 7;

    UINT32    Reserved1                  : 4;

    UINT32    ResolutionInDegreesCelsius : 4;

    UINT32    ReadingValid               : 1;

    UINT32    Reserved2                  : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_THERM_STATUS_REGISTER;


#define MSR_IA32_MISC_ENABLE  0x000001A0


typedef union {

  struct {

    UINT32    FastStrings : 1;

    UINT32    Reserved1   : 2;

    UINT32    AutomaticThermalControlCircuit : 1;

    UINT32    Reserved2                      : 3;

    UINT32    PerformanceMonitoring          : 1;

    UINT32    Reserved3                      : 3;

    UINT32    BTS                            : 1;

    UINT32    PEBS                           : 1;

    UINT32    Reserved4                      : 3;

    UINT32    EIST                           : 1;

    UINT32    Reserved5                      : 1;

    UINT32    MONITOR   : 1;

    UINT32    Reserved6 : 3;

    UINT32    LimitCpuidMaxval     : 1;

    UINT32    xTPR_Message_Disable : 1;

    UINT32    Reserved7            : 8;

    UINT32    Reserved8            : 2;

    UINT32    XD        : 1;

    UINT32    Reserved9 : 29;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_MISC_ENABLE_REGISTER;


#define MSR_IA32_ENERGY_PERF_BIAS  0x000001B0


typedef union {

  struct {

    UINT32    PowerPolicyPreference : 4;

    UINT32    Reserved1             : 28;

    UINT32    Reserved2             : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;


#define MSR_IA32_PACKAGE_THERM_STATUS  0x000001B1


typedef union {

  struct {

    UINT32    ThermalStatus           : 1;

    UINT32    ThermalStatusLog        : 1;

    UINT32    PROCHOT_Event           : 1;

    UINT32    PROCHOT_Log             : 1;

    UINT32    CriticalTempStatus      : 1;

    UINT32    CriticalTempStatusLog   : 1;

    UINT32    ThermalThreshold1Status : 1;

    UINT32    ThermalThreshold1Log    : 1;

    UINT32    ThermalThreshold2Status : 1;

    UINT32    ThermalThreshold2Log    : 1;

    UINT32    PowerLimitStatus        : 1;

    UINT32    PowerLimitLog           : 1;

    UINT32    Reserved1               : 4;

    UINT32    DigitalReadout          : 7;

    UINT32    Reserved2               : 9;

    UINT32    Reserved3               : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;


#define MSR_IA32_PACKAGE_THERM_INTERRUPT  0x000001B2


typedef union {

  struct {

    UINT32    HighTempEnable               : 1;

    UINT32    LowTempEnable                : 1;

    UINT32    PROCHOT_Enable               : 1;

    UINT32    Reserved1                    : 1;

    UINT32    OverheatEnable               : 1;

    UINT32    Reserved2                    : 3;

    UINT32    Threshold1                   : 7;

    UINT32    Threshold1Enable             : 1;

    UINT32    Threshold2                   : 7;

    UINT32    Threshold2Enable             : 1;

    UINT32    PowerLimitNotificationEnable : 1;

    UINT32    Reserved3                    : 7;

    UINT32    Reserved4                    : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;


#define MSR_IA32_DEBUGCTL  0x000001D9


typedef union {

  struct {

    UINT32    LBR                   : 1;

    UINT32    BTF                   : 1;

    UINT32    Reserved1             : 4;

    UINT32    TR                    : 1;

    UINT32    BTS                   : 1;

    UINT32    BTINT                 : 1;

    UINT32    BTS_OFF_OS            : 1;

    UINT32    BTS_OFF_USR           : 1;

    UINT32    FREEZE_LBRS_ON_PMI    : 1;

    UINT32    FREEZE_PERFMON_ON_PMI : 1;

    UINT32    ENABLE_UNCORE_PMI     : 1;

    UINT32    FREEZE_WHILE_SMM      : 1;

    UINT32    RTM_DEBUG             : 1;

    UINT32    Reserved2             : 16;

    UINT32    Reserved3             : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_DEBUGCTL_REGISTER;


#define MSR_IA32_SMRR_PHYSBASE  0x000001F2


typedef union {

  struct {

    UINT32    Type      : 8;

    UINT32    Reserved1 : 4;

    UINT32    PhysBase  : 20;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_SMRR_PHYSBASE_REGISTER;


#define MSR_IA32_SMRR_PHYSMASK  0x000001F3


typedef union {

  struct {

    UINT32    Reserved1 : 11;

    UINT32    Valid     : 1;

    UINT32    PhysMask  : 20;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_SMRR_PHYSMASK_REGISTER;


#define MSR_IA32_PLATFORM_DCA_CAP  0x000001F8


#define MSR_IA32_CPU_DCA_CAP  0x000001F9


#define MSR_IA32_DCA_0_CAP  0x000001FA


typedef union {

  struct {

    UINT32    DCA_ACTIVE     : 1;

    UINT32    TRANSACTION    : 2;

    UINT32    DCA_TYPE       : 4;

    UINT32    DCA_QUEUE_SIZE : 4;

    UINT32    Reserved1      : 2;

    UINT32    DCA_DELAY      : 4;

    UINT32    Reserved2      : 7;

    UINT32    SW_BLOCK       : 1;

    UINT32    Reserved3      : 1;

    UINT32    HW_BLOCK       : 1;

    UINT32    Reserved4      : 5;

    UINT32    Reserved5      : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_DCA_0_CAP_REGISTER;


#define MSR_IA32_MTRR_PHYSBASE0  0x00000200

#define MSR_IA32_MTRR_PHYSBASE1  0x00000202

#define MSR_IA32_MTRR_PHYSBASE2  0x00000204

#define MSR_IA32_MTRR_PHYSBASE3  0x00000206

#define MSR_IA32_MTRR_PHYSBASE4  0x00000208

#define MSR_IA32_MTRR_PHYSBASE5  0x0000020A

#define MSR_IA32_MTRR_PHYSBASE6  0x0000020C

#define MSR_IA32_MTRR_PHYSBASE7  0x0000020E

#define MSR_IA32_MTRR_PHYSBASE8  0x00000210

#define MSR_IA32_MTRR_PHYSBASE9  0x00000212


typedef union {

  struct {

    UINT32    Type      : 8;

    UINT32    Reserved1 : 4;

    UINT32    PhysBase  : 20;

    UINT32    PhysBaseHi : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_MTRR_PHYSBASE_REGISTER;


#define MSR_IA32_MTRR_PHYSMASK0  0x00000201

#define MSR_IA32_MTRR_PHYSMASK1  0x00000203

#define MSR_IA32_MTRR_PHYSMASK2  0x00000205

#define MSR_IA32_MTRR_PHYSMASK3  0x00000207

#define MSR_IA32_MTRR_PHYSMASK4  0x00000209

#define MSR_IA32_MTRR_PHYSMASK5  0x0000020B

#define MSR_IA32_MTRR_PHYSMASK6  0x0000020D

#define MSR_IA32_MTRR_PHYSMASK7  0x0000020F

#define MSR_IA32_MTRR_PHYSMASK8  0x00000211

#define MSR_IA32_MTRR_PHYSMASK9  0x00000213


typedef union {

  struct {

    UINT32    Reserved1 : 11;

    UINT32    V         : 1;

    UINT32    PhysMask  : 20;

    UINT32    PhysMaskHi : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_MTRR_PHYSMASK_REGISTER;


#define MSR_IA32_MTRR_FIX64K_00000  0x00000250


#define MSR_IA32_MTRR_FIX16K_80000  0x00000258


#define MSR_IA32_MTRR_FIX16K_A0000  0x00000259


#define MSR_IA32_MTRR_FIX4K_C0000  0x00000268


#define MSR_IA32_MTRR_FIX4K_C8000  0x00000269


#define MSR_IA32_MTRR_FIX4K_D0000  0x0000026A


#define MSR_IA32_MTRR_FIX4K_D8000  0x0000026B


#define MSR_IA32_MTRR_FIX4K_E0000  0x0000026C


#define MSR_IA32_MTRR_FIX4K_E8000  0x0000026D


#define MSR_IA32_MTRR_FIX4K_F0000  0x0000026E


#define MSR_IA32_MTRR_FIX4K_F8000  0x0000026F


#define MSR_IA32_PAT  0x00000277


typedef union {

  struct {

    UINT32    PA0       : 3;

    UINT32    Reserved1 : 5;

    UINT32    PA1       : 3;

    UINT32    Reserved2 : 5;

    UINT32    PA2       : 3;

    UINT32    Reserved3 : 5;

    UINT32    PA3       : 3;

    UINT32    Reserved4 : 5;

    UINT32    PA4       : 3;

    UINT32    Reserved5 : 5;

    UINT32    PA5       : 3;

    UINT32    Reserved6 : 5;

    UINT32    PA6       : 3;

    UINT32    Reserved7 : 5;

    UINT32    PA7       : 3;

    UINT32    Reserved8 : 5;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PAT_REGISTER;


#define MSR_IA32_MC0_CTL2   0x00000280

#define MSR_IA32_MC1_CTL2   0x00000281

#define MSR_IA32_MC2_CTL2   0x00000282

#define MSR_IA32_MC3_CTL2   0x00000283

#define MSR_IA32_MC4_CTL2   0x00000284

#define MSR_IA32_MC5_CTL2   0x00000285

#define MSR_IA32_MC6_CTL2   0x00000286

#define MSR_IA32_MC7_CTL2   0x00000287

#define MSR_IA32_MC8_CTL2   0x00000288

#define MSR_IA32_MC9_CTL2   0x00000289

#define MSR_IA32_MC10_CTL2  0x0000028A

#define MSR_IA32_MC11_CTL2  0x0000028B

#define MSR_IA32_MC12_CTL2  0x0000028C

#define MSR_IA32_MC13_CTL2  0x0000028D

#define MSR_IA32_MC14_CTL2  0x0000028E

#define MSR_IA32_MC15_CTL2  0x0000028F

#define MSR_IA32_MC16_CTL2  0x00000290

#define MSR_IA32_MC17_CTL2  0x00000291

#define MSR_IA32_MC18_CTL2  0x00000292

#define MSR_IA32_MC19_CTL2  0x00000293

#define MSR_IA32_MC20_CTL2  0x00000294

#define MSR_IA32_MC21_CTL2  0x00000295

#define MSR_IA32_MC22_CTL2  0x00000296

#define MSR_IA32_MC23_CTL2  0x00000297

#define MSR_IA32_MC24_CTL2  0x00000298

#define MSR_IA32_MC25_CTL2  0x00000299

#define MSR_IA32_MC26_CTL2  0x0000029A

#define MSR_IA32_MC27_CTL2  0x0000029B

#define MSR_IA32_MC28_CTL2  0x0000029C

#define MSR_IA32_MC29_CTL2  0x0000029D

#define MSR_IA32_MC30_CTL2  0x0000029E

#define MSR_IA32_MC31_CTL2  0x0000029F


typedef union {

  struct {

    UINT32    CorrectedErrorCountThreshold : 15;

    UINT32    Reserved1                    : 15;

    UINT32    CMCI_EN                      : 1;

    UINT32    Reserved2                    : 1;

    UINT32    Reserved3                    : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_MC_CTL2_REGISTER;


#define MSR_IA32_MTRR_DEF_TYPE  0x000002FF


typedef union {

  struct {

    UINT32    Type      : 3;

    UINT32    Reserved1 : 7;

    UINT32    FE        : 1;

    UINT32    E         : 1;

    UINT32    Reserved2 : 20;

    UINT32    Reserved3 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_MTRR_DEF_TYPE_REGISTER;


#define MSR_IA32_FIXED_CTR0  0x00000309


#define MSR_IA32_FIXED_CTR1  0x0000030A


#define MSR_IA32_FIXED_CTR2  0x0000030B


#define MSR_IA32_PERF_CAPABILITIES  0x00000345


typedef union {

  struct {

    UINT32    LBR_FMT       : 6;

    UINT32    PEBS_TRAP     : 1;

    UINT32    PEBS_ARCH_REG : 1;

    UINT32    PEBS_REC_FMT  : 4;

    UINT32    SMM_FREEZE    : 1;

    UINT32    FW_WRITE      : 1;

    UINT32    Reserved1     : 18;

    UINT32    Reserved2     : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PERF_CAPABILITIES_REGISTER;


#define MSR_IA32_FIXED_CTR_CTRL  0x0000038D


typedef union {

  struct {

    UINT32    EN0_OS     : 1;

    UINT32    EN0_Usr    : 1;

    UINT32    AnyThread0 : 1;

    UINT32    EN0_PMI    : 1;

    UINT32    EN1_OS     : 1;

    UINT32    EN1_Usr    : 1;

    UINT32    AnyThread1 : 1;

    UINT32    EN1_PMI    : 1;

    UINT32    EN2_OS     : 1;

    UINT32    EN2_Usr    : 1;

    UINT32    AnyThread2 : 1;

    UINT32    EN2_PMI    : 1;

    UINT32    Reserved1  : 20;

    UINT32    Reserved2  : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_FIXED_CTR_CTRL_REGISTER;


#define MSR_IA32_PERF_GLOBAL_STATUS  0x0000038E


typedef union {

  struct {

    UINT32    Ovf_PMC0       : 1;

    UINT32    Ovf_PMC1       : 1;

    UINT32    Ovf_PMC2       : 1;

    UINT32    Ovf_PMC3       : 1;

    UINT32    Reserved1      : 28;

    UINT32    Ovf_FixedCtr0  : 1;

    UINT32    Ovf_FixedCtr1  : 1;

    UINT32    Ovf_FixedCtr2  : 1;

    UINT32    Reserved2      : 20;

    UINT32    Trace_ToPA_PMI : 1;

    UINT32    Reserved3      : 2;

    UINT32    LBR_Frz        : 1;

    UINT32    CTR_Frz        : 1;

    UINT32    ASCI           : 1;

    UINT32    Ovf_Uncore     : 1;

    UINT32    OvfBuf         : 1;

    UINT32    CondChgd       : 1;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;


#define MSR_IA32_PERF_GLOBAL_CTRL  0x0000038F


typedef union {

  struct {

    UINT32    EN_PMCn       : 32;

    UINT32    EN_FIXED_CTRn : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;


#define MSR_IA32_PERF_GLOBAL_OVF_CTRL  0x00000390


typedef union {

  struct {

    UINT32    Ovf_PMCn       : 32;

    UINT32    Ovf_FIXED_CTRn : 23;

    UINT32    Trace_ToPA_PMI : 1;

    UINT32    Reserved2      : 5;

    UINT32    Ovf_Uncore     : 1;

    UINT32    OvfBuf         : 1;

    UINT32    CondChgd       : 1;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;


#define MSR_IA32_PERF_GLOBAL_STATUS_RESET  0x00000390


typedef union {

  struct {

    UINT32    Ovf_PMCn       : 32;

    UINT32    Ovf_FIXED_CTRn : 23;

    UINT32    Trace_ToPA_PMI : 1;

    UINT32    Reserved2      : 2;

    UINT32    LBR_Frz        : 1;

    UINT32    CTR_Frz        : 1;

    UINT32    ASCI           : 1;

    UINT32    Ovf_Uncore     : 1;

    UINT32    OvfBuf         : 1;

    UINT32    CondChgd       : 1;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;


#define MSR_IA32_PERF_GLOBAL_STATUS_SET  0x00000391


typedef union {

  struct {

    UINT32    Ovf_PMCn       : 32;

    UINT32    Ovf_FIXED_CTRn : 23;

    UINT32    Trace_ToPA_PMI : 1;

    UINT32    Reserved2      : 2;

    UINT32    LBR_Frz        : 1;

    UINT32    CTR_Frz        : 1;

    UINT32    ASCI           : 1;

    UINT32    Ovf_Uncore     : 1;

    UINT32    OvfBuf         : 1;

    UINT32    Reserved3      : 1;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;


#define MSR_IA32_PERF_GLOBAL_INUSE  0x00000392


typedef union {

  struct {

    UINT32    IA32_PERFEVTSELn : 32;

    UINT32    IA32_FIXED_CTRn  : 31;

    UINT32    PMI              : 1;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;


#define MSR_IA32_PEBS_ENABLE  0x000003F1


typedef union {

  struct {

    UINT32    Enable    : 1;

    UINT32    Reserved1 : 3;

    UINT32    Reserved2 : 28;

    UINT32    Reserved3 : 4;

    UINT32    Reserved4 : 28;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PEBS_ENABLE_REGISTER;


#define MSR_IA32_MC0_CTL   0x00000400

#define MSR_IA32_MC1_CTL   0x00000404

#define MSR_IA32_MC2_CTL   0x00000408

#define MSR_IA32_MC3_CTL   0x0000040C

#define MSR_IA32_MC4_CTL   0x00000410

#define MSR_IA32_MC5_CTL   0x00000414

#define MSR_IA32_MC6_CTL   0x00000418

#define MSR_IA32_MC7_CTL   0x0000041C

#define MSR_IA32_MC8_CTL   0x00000420

#define MSR_IA32_MC9_CTL   0x00000424

#define MSR_IA32_MC10_CTL  0x00000428

#define MSR_IA32_MC11_CTL  0x0000042C

#define MSR_IA32_MC12_CTL  0x00000430

#define MSR_IA32_MC13_CTL  0x00000434

#define MSR_IA32_MC14_CTL  0x00000438

#define MSR_IA32_MC15_CTL  0x0000043C

#define MSR_IA32_MC16_CTL  0x00000440

#define MSR_IA32_MC17_CTL  0x00000444

#define MSR_IA32_MC18_CTL  0x00000448

#define MSR_IA32_MC19_CTL  0x0000044C

#define MSR_IA32_MC20_CTL  0x00000450

#define MSR_IA32_MC21_CTL  0x00000454

#define MSR_IA32_MC22_CTL  0x00000458

#define MSR_IA32_MC23_CTL  0x0000045C

#define MSR_IA32_MC24_CTL  0x00000460

#define MSR_IA32_MC25_CTL  0x00000464

#define MSR_IA32_MC26_CTL  0x00000468

#define MSR_IA32_MC27_CTL  0x0000046C

#define MSR_IA32_MC28_CTL  0x00000470


#define MSR_IA32_MC0_STATUS   0x00000401

#define MSR_IA32_MC1_STATUS   0x00000405

#define MSR_IA32_MC2_STATUS   0x00000409

#define MSR_IA32_MC3_STATUS   0x0000040D

#define MSR_IA32_MC4_STATUS   0x00000411

#define MSR_IA32_MC5_STATUS   0x00000415

#define MSR_IA32_MC6_STATUS   0x00000419

#define MSR_IA32_MC7_STATUS   0x0000041D

#define MSR_IA32_MC8_STATUS   0x00000421

#define MSR_IA32_MC9_STATUS   0x00000425

#define MSR_IA32_MC10_STATUS  0x00000429

#define MSR_IA32_MC11_STATUS  0x0000042D

#define MSR_IA32_MC12_STATUS  0x00000431

#define MSR_IA32_MC13_STATUS  0x00000435

#define MSR_IA32_MC14_STATUS  0x00000439

#define MSR_IA32_MC15_STATUS  0x0000043D

#define MSR_IA32_MC16_STATUS  0x00000441

#define MSR_IA32_MC17_STATUS  0x00000445

#define MSR_IA32_MC18_STATUS  0x00000449

#define MSR_IA32_MC19_STATUS  0x0000044D

#define MSR_IA32_MC20_STATUS  0x00000451

#define MSR_IA32_MC21_STATUS  0x00000455

#define MSR_IA32_MC22_STATUS  0x00000459

#define MSR_IA32_MC23_STATUS  0x0000045D

#define MSR_IA32_MC24_STATUS  0x00000461

#define MSR_IA32_MC25_STATUS  0x00000465

#define MSR_IA32_MC26_STATUS  0x00000469

#define MSR_IA32_MC27_STATUS  0x0000046D

#define MSR_IA32_MC28_STATUS  0x00000471


#define MSR_IA32_MC0_ADDR   0x00000402

#define MSR_IA32_MC1_ADDR   0x00000406

#define MSR_IA32_MC2_ADDR   0x0000040A

#define MSR_IA32_MC3_ADDR   0x0000040E

#define MSR_IA32_MC4_ADDR   0x00000412

#define MSR_IA32_MC5_ADDR   0x00000416

#define MSR_IA32_MC6_ADDR   0x0000041A

#define MSR_IA32_MC7_ADDR   0x0000041E

#define MSR_IA32_MC8_ADDR   0x00000422

#define MSR_IA32_MC9_ADDR   0x00000426

#define MSR_IA32_MC10_ADDR  0x0000042A

#define MSR_IA32_MC11_ADDR  0x0000042E

#define MSR_IA32_MC12_ADDR  0x00000432

#define MSR_IA32_MC13_ADDR  0x00000436

#define MSR_IA32_MC14_ADDR  0x0000043A

#define MSR_IA32_MC15_ADDR  0x0000043E

#define MSR_IA32_MC16_ADDR  0x00000442

#define MSR_IA32_MC17_ADDR  0x00000446

#define MSR_IA32_MC18_ADDR  0x0000044A

#define MSR_IA32_MC19_ADDR  0x0000044E

#define MSR_IA32_MC20_ADDR  0x00000452

#define MSR_IA32_MC21_ADDR  0x00000456

#define MSR_IA32_MC22_ADDR  0x0000045A

#define MSR_IA32_MC23_ADDR  0x0000045E

#define MSR_IA32_MC24_ADDR  0x00000462

#define MSR_IA32_MC25_ADDR  0x00000466

#define MSR_IA32_MC26_ADDR  0x0000046A

#define MSR_IA32_MC27_ADDR  0x0000046E

#define MSR_IA32_MC28_ADDR  0x00000472


#define MSR_IA32_MC0_MISC   0x00000403

#define MSR_IA32_MC1_MISC   0x00000407

#define MSR_IA32_MC2_MISC   0x0000040B

#define MSR_IA32_MC3_MISC   0x0000040F

#define MSR_IA32_MC4_MISC   0x00000413

#define MSR_IA32_MC5_MISC   0x00000417

#define MSR_IA32_MC6_MISC   0x0000041B

#define MSR_IA32_MC7_MISC   0x0000041F

#define MSR_IA32_MC8_MISC   0x00000423

#define MSR_IA32_MC9_MISC   0x00000427

#define MSR_IA32_MC10_MISC  0x0000042B

#define MSR_IA32_MC11_MISC  0x0000042F

#define MSR_IA32_MC12_MISC  0x00000433

#define MSR_IA32_MC13_MISC  0x00000437

#define MSR_IA32_MC14_MISC  0x0000043B

#define MSR_IA32_MC15_MISC  0x0000043F

#define MSR_IA32_MC16_MISC  0x00000443

#define MSR_IA32_MC17_MISC  0x00000447

#define MSR_IA32_MC18_MISC  0x0000044B

#define MSR_IA32_MC19_MISC  0x0000044F

#define MSR_IA32_MC20_MISC  0x00000453

#define MSR_IA32_MC21_MISC  0x00000457

#define MSR_IA32_MC22_MISC  0x0000045B

#define MSR_IA32_MC23_MISC  0x0000045F

#define MSR_IA32_MC24_MISC  0x00000463

#define MSR_IA32_MC25_MISC  0x00000467

#define MSR_IA32_MC26_MISC  0x0000046B

#define MSR_IA32_MC27_MISC  0x0000046F

#define MSR_IA32_MC28_MISC  0x00000473


#define MSR_IA32_VMX_BASIC  0x00000480


typedef union {

  struct {

    UINT32    VmcsRevisonId : 31;

    UINT32    MustBeZero    : 1;

    UINT32    VmcsSize      : 13;

    UINT32    Reserved1     : 3;

    UINT32    VmcsAddressWidth : 1;

    UINT32    DualMonitor      : 1;

    UINT32    MemoryType       : 4;

    UINT32    InsOutsReporting : 1;

    UINT32    VmxControls : 1;

    UINT32    Reserved2   : 8;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_VMX_BASIC_REGISTER;


#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE  0x00

#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK   0x06


#define MSR_IA32_VMX_PINBASED_CTLS  0x00000481


#define MSR_IA32_VMX_PROCBASED_CTLS  0x00000482


#define MSR_IA32_VMX_EXIT_CTLS  0x00000483


#define MSR_IA32_VMX_ENTRY_CTLS  0x00000484


#define MSR_IA32_VMX_MISC  0x00000485


typedef union {

  struct {

    UINT32    VmxTimerRatio                     : 5;

    UINT32    VmExitEferLma                     : 1;

    UINT32    HltActivityStateSupported         : 1;

    UINT32    ShutdownActivityStateSupported    : 1;

    UINT32    WaitForSipiActivityStateSupported : 1;

    UINT32    Reserved1                         : 5;

    UINT32    ProcessorTraceSupported : 1;

    UINT32    SmBaseMsrSupported      : 1;

    UINT32    NumberOfCr3TargetValues : 9;

    UINT32    MsrStoreListMaximum    : 3;

    UINT32    BlockSmiSupported      : 1;

    UINT32    VmWriteSupported       : 1;

    UINT32    VmInjectSupported      : 1;

    UINT32    Reserved2              : 1;

    UINT32    MsegRevisionIdentifier : 32;

  } Bits;

  UINT64    Uint64;

} IA32_VMX_MISC_REGISTER;


#define MSR_IA32_VMX_CR0_FIXED0  0x00000486


#define MSR_IA32_VMX_CR0_FIXED1  0x00000487


#define MSR_IA32_VMX_CR4_FIXED0  0x00000488


#define MSR_IA32_VMX_CR4_FIXED1  0x00000489


#define MSR_IA32_VMX_VMCS_ENUM  0x0000048A


#define MSR_IA32_VMX_PROCBASED_CTLS2  0x0000048B


#define MSR_IA32_VMX_EPT_VPID_CAP  0x0000048C


#define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048D


#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS  0x0000048E


#define MSR_IA32_VMX_TRUE_EXIT_CTLS  0x0000048F


#define MSR_IA32_VMX_TRUE_ENTRY_CTLS  0x00000490


#define MSR_IA32_VMX_VMFUNC  0x00000491


#define MSR_IA32_A_PMC0  0x000004C1

#define MSR_IA32_A_PMC1  0x000004C2

#define MSR_IA32_A_PMC2  0x000004C3

#define MSR_IA32_A_PMC3  0x000004C4

#define MSR_IA32_A_PMC4  0x000004C5

#define MSR_IA32_A_PMC5  0x000004C6

#define MSR_IA32_A_PMC6  0x000004C7

#define MSR_IA32_A_PMC7  0x000004C8


#define MSR_IA32_MCG_EXT_CTL  0x000004D0


typedef union {

  struct {

    UINT32    LMCE_EN   : 1;

    UINT32    Reserved1 : 31;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_MCG_EXT_CTL_REGISTER;


#define MSR_IA32_SGX_SVN_STATUS  0x00000500


typedef union {

  struct {

    UINT32    Lock          : 1;

    UINT32    Reserved1     : 15;

    UINT32    SGX_SVN_SINIT : 8;

    UINT32    Reserved2     : 8;

    UINT32    Reserved3     : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_SGX_SVN_STATUS_REGISTER;


#define MSR_IA32_RTIT_OUTPUT_BASE  0x00000560


typedef union {

  struct {

    UINT32    Reserved : 7;

    UINT32    Base     : 25;

    UINT32    BaseHi   : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;


#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS  0x00000561


typedef union {

  struct {

    UINT32    Reserved          : 7;

    UINT32    MaskOrTableOffset : 25;

    UINT32    OutputOffset      : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;


typedef union {

  struct {

    UINT32    END       : 1;

    UINT32    Reserved1 : 1;

    UINT32    INT       : 1;

    UINT32    Reserved2 : 1;

    UINT32    STOP      : 1;

    UINT32    Reserved3 : 1;

    UINT32    Size      : 4;

    UINT32    Reserved4 : 2;

    UINT32    Base : 20;

    UINT32    BaseHi : 32;

  } Bits;

  UINT64    Uint64;

} RTIT_TOPA_TABLE_ENTRY;


typedef enum {

  RtitTopaMemorySize4K = 0,

  RtitTopaMemorySize8K,

  RtitTopaMemorySize16K,

  RtitTopaMemorySize32K,

  RtitTopaMemorySize64K,

  RtitTopaMemorySize128K,

  RtitTopaMemorySize256K,

  RtitTopaMemorySize512K,

  RtitTopaMemorySize1M,

  RtitTopaMemorySize2M,

  RtitTopaMemorySize4M,

  RtitTopaMemorySize8M,

  RtitTopaMemorySize16M,

  RtitTopaMemorySize32M,

  RtitTopaMemorySize64M,

  RtitTopaMemorySize128M

} RTIT_TOPA_MEMORY_SIZE;


#define MSR_IA32_RTIT_CTL  0x00000570


typedef union {

  struct {

    UINT32    TraceEn   : 1;

    UINT32    CYCEn     : 1;

    UINT32    OS        : 1;

    UINT32    User      : 1;

    UINT32    PwrEvtEn  : 1;

    UINT32    FUPonPTW  : 1;

    UINT32    FabricEn  : 1;

    UINT32    CR3       : 1;

    UINT32    ToPA      : 1;

    UINT32    MTCEn     : 1;

    UINT32    TSCEn     : 1;

    UINT32    DisRETC   : 1;

    UINT32    PTWEn     : 1;

    UINT32    BranchEn  : 1;

    UINT32    MTCFreq   : 4;

    UINT32    Reserved3 : 1;

    UINT32    CYCThresh : 4;

    UINT32    Reserved4 : 1;

    UINT32    PSBFreq   : 4;

    UINT32    Reserved5 : 4;

    UINT32    ADDR0_CFG : 4;

    UINT32    ADDR1_CFG : 4;

    UINT32    ADDR2_CFG : 4;

    UINT32    ADDR3_CFG : 4;

    UINT32    Reserved6 : 16;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_RTIT_CTL_REGISTER;


#define MSR_IA32_RTIT_STATUS  0x00000571


typedef union {

  struct {

    UINT32    FilterEn      : 1;

    UINT32    ContexEn      : 1;

    UINT32    TriggerEn     : 1;

    UINT32    Reserved1     : 1;

    UINT32    Error         : 1;

    UINT32    Stopped       : 1;

    UINT32    Reserved2     : 26;

    UINT32    PacketByteCnt : 17;

    UINT32    Reserved3     : 15;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_RTIT_STATUS_REGISTER;


#define MSR_IA32_RTIT_CR3_MATCH  0x00000572


typedef union {

  struct {

    UINT32    Reserved : 5;

    UINT32    Cr3      : 27;

    UINT32    Cr3Hi    : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_RTIT_CR3_MATCH_REGISTER;


#define MSR_IA32_RTIT_ADDR0_A  0x00000580

#define MSR_IA32_RTIT_ADDR1_A  0x00000582

#define MSR_IA32_RTIT_ADDR2_A  0x00000584

#define MSR_IA32_RTIT_ADDR3_A  0x00000586


#define MSR_IA32_RTIT_ADDR0_B  0x00000581

#define MSR_IA32_RTIT_ADDR1_B  0x00000583

#define MSR_IA32_RTIT_ADDR2_B  0x00000585

#define MSR_IA32_RTIT_ADDR3_B  0x00000587


typedef union {

  struct {

    UINT32    VirtualAddress   : 32;

    UINT32    VirtualAddressHi : 16;

    UINT32    SignExt_VA       : 16;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_RTIT_ADDR_REGISTER;


#define MSR_IA32_DS_AREA  0x00000600


#define MSR_IA32_TSC_DEADLINE  0x000006E0


#define MSR_IA32_PM_ENABLE  0x00000770


typedef union {

  struct {

    UINT32    HWP_ENABLE : 1;

    UINT32    Reserved1  : 31;

    UINT32    Reserved2  : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PM_ENABLE_REGISTER;


#define MSR_IA32_HWP_CAPABILITIES  0x00000771


typedef union {

  struct {

    UINT32    Highest_Performance        : 8;

    UINT32    Guaranteed_Performance     : 8;

    UINT32    Most_Efficient_Performance : 8;

    UINT32    Lowest_Performance         : 8;

    UINT32    Reserved                   : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_HWP_CAPABILITIES_REGISTER;


#define MSR_IA32_HWP_REQUEST_PKG  0x00000772


typedef union {

  struct {

    UINT32    Minimum_Performance           : 8;

    UINT32    Maximum_Performance           : 8;

    UINT32    Desired_Performance           : 8;

    UINT32    Energy_Performance_Preference : 8;

    UINT32    Activity_Window               : 10;

    UINT32    Reserved                      : 22;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_HWP_REQUEST_PKG_REGISTER;


#define MSR_IA32_HWP_INTERRUPT  0x00000773


typedef union {

  struct {

    UINT32    EN_Guaranteed_Performance_Change : 1;

    UINT32    EN_Excursion_Minimum             : 1;

    UINT32    Reserved1                        : 30;

    UINT32    Reserved2                        : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_HWP_INTERRUPT_REGISTER;


#define MSR_IA32_HWP_REQUEST  0x00000774


typedef union {

  struct {

    UINT32    Minimum_Performance           : 8;

    UINT32    Maximum_Performance           : 8;

    UINT32    Desired_Performance           : 8;

    UINT32    Energy_Performance_Preference : 8;

    UINT32    Activity_Window               : 10;

    UINT32    Package_Control               : 1;

    UINT32    Reserved                      : 21;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_HWP_REQUEST_REGISTER;


#define MSR_IA32_HWP_STATUS  0x00000777


typedef union {

  struct {

    UINT32    Guaranteed_Performance_Change : 1;

    UINT32    Reserved1                     : 1;

    UINT32    Excursion_To_Minimum          : 1;

    UINT32    Reserved2                     : 29;

    UINT32    Reserved3                     : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_HWP_STATUS_REGISTER;


#define MSR_IA32_X2APIC_APICID  0x00000802


#define MSR_IA32_X2APIC_VERSION  0x00000803


#define MSR_IA32_X2APIC_TPR  0x00000808


#define MSR_IA32_X2APIC_PPR  0x0000080A


#define MSR_IA32_X2APIC_EOI  0x0000080B


#define MSR_IA32_X2APIC_LDR  0x0000080D


#define MSR_IA32_X2APIC_SIVR  0x0000080F


#define MSR_IA32_X2APIC_ISR0  0x00000810

#define MSR_IA32_X2APIC_ISR1  0x00000811

#define MSR_IA32_X2APIC_ISR2  0x00000812

#define MSR_IA32_X2APIC_ISR3  0x00000813

#define MSR_IA32_X2APIC_ISR4  0x00000814

#define MSR_IA32_X2APIC_ISR5  0x00000815

#define MSR_IA32_X2APIC_ISR6  0x00000816

#define MSR_IA32_X2APIC_ISR7  0x00000817


#define MSR_IA32_X2APIC_TMR0  0x00000818

#define MSR_IA32_X2APIC_TMR1  0x00000819

#define MSR_IA32_X2APIC_TMR2  0x0000081A

#define MSR_IA32_X2APIC_TMR3  0x0000081B

#define MSR_IA32_X2APIC_TMR4  0x0000081C

#define MSR_IA32_X2APIC_TMR5  0x0000081D

#define MSR_IA32_X2APIC_TMR6  0x0000081E

#define MSR_IA32_X2APIC_TMR7  0x0000081F


#define MSR_IA32_X2APIC_IRR0  0x00000820

#define MSR_IA32_X2APIC_IRR1  0x00000821

#define MSR_IA32_X2APIC_IRR2  0x00000822

#define MSR_IA32_X2APIC_IRR3  0x00000823

#define MSR_IA32_X2APIC_IRR4  0x00000824

#define MSR_IA32_X2APIC_IRR5  0x00000825

#define MSR_IA32_X2APIC_IRR6  0x00000826

#define MSR_IA32_X2APIC_IRR7  0x00000827


#define MSR_IA32_X2APIC_ESR  0x00000828


#define MSR_IA32_X2APIC_LVT_CMCI  0x0000082F


#define MSR_IA32_X2APIC_ICR  0x00000830


#define MSR_IA32_X2APIC_LVT_TIMER  0x00000832


#define MSR_IA32_X2APIC_LVT_THERMAL  0x00000833


#define MSR_IA32_X2APIC_LVT_PMI  0x00000834


#define MSR_IA32_X2APIC_LVT_LINT0  0x00000835


#define MSR_IA32_X2APIC_LVT_LINT1  0x00000836


#define MSR_IA32_X2APIC_LVT_ERROR  0x00000837


#define MSR_IA32_X2APIC_INIT_COUNT  0x00000838


#define MSR_IA32_X2APIC_CUR_COUNT  0x00000839


#define MSR_IA32_X2APIC_DIV_CONF  0x0000083E


#define MSR_IA32_X2APIC_SELF_IPI  0x0000083F


#define MSR_IA32_TME_ACTIVATE  0x00000982


typedef union {

  struct {

    UINT32    Lock              : 1;

    UINT32    TmeEnable         : 1;

    UINT32    KeySelect         : 1;

    UINT32    SaveKeyForStandby : 1;

    UINT32    TmePolicy : 4;

    UINT32    Reserved  : 23;

    UINT32    TmeBypassMode : 1;

    UINT32    MkTmeKeyidBits : 4;

    UINT32    Reserved2      : 12;

    UINT32    MkTmeCryptoAlgs : 16;

  } Bits;

  UINT32    Uint32[2];

  UINT64    Uint64;

} MSR_IA32_TME_ACTIVATE_REGISTER;


#define MSR_IA32_DEBUG_INTERFACE  0x00000C80


typedef union {

  struct {

    UINT32    Enable        : 1;

    UINT32    Reserved1     : 29;

    UINT32    Lock          : 1;

    UINT32    DebugOccurred : 1;

    UINT32    Reserved2     : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_DEBUG_INTERFACE_REGISTER;


#define MSR_IA32_L3_QOS_CFG  0x00000C81


typedef union {

  struct {

    UINT32    Enable    : 1;

    UINT32    Reserved1 : 31;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_L3_QOS_CFG_REGISTER;


#define MSR_IA32_L2_QOS_CFG  0x00000C82


typedef union {

  struct {

    UINT32    Enable    : 1;

    UINT32    Reserved1 : 31;

    UINT32    Reserved2 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_L2_QOS_CFG_REGISTER;


#define MSR_IA32_QM_EVTSEL  0x00000C8D


typedef union {

  struct {

    UINT32    EventID              : 8;

    UINT32    Reserved             : 24;

    UINT32    ResourceMonitoringID : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_QM_EVTSEL_REGISTER;


#define MSR_IA32_QM_CTR  0x00000C8E


typedef union {

  struct {

    UINT32    ResourceMonitoredData   : 32;

    UINT32    ResourceMonitoredDataHi : 30;

    UINT32    Unavailable             : 1;

    UINT32    Error                   : 1;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_QM_CTR_REGISTER;


#define MSR_IA32_PQR_ASSOC  0x00000C8F


typedef union {

  struct {

    UINT32    ResourceMonitoringID : 32;

    UINT32    COS                  : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_PQR_ASSOC_REGISTER;


#define MSR_IA32_BNDCFGS  0x00000D90


typedef union {

  struct {

    UINT32    EN          : 1;

    UINT32    BNDPRESERVE : 1;

    UINT32    Reserved    : 10;

    UINT32    Base        : 20;

    UINT32    BaseHi      : 32;

  } Bits;

  UINT64    Uint64;

} MSR_IA32_BNDCFGS_REGISTER;


#define MSR_IA32_XSS  0x00000DA0


typedef union {

  struct {

    UINT32    Reserved1                     : 8;

    UINT32    TracePacketConfigurationState : 1;

    UINT32    Reserved2                     : 23;

    UINT32    Reserved3                     : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_XSS_REGISTER;


#define MSR_IA32_PKG_HDC_CTL  0x00000DB0


typedef union {

  struct {

    UINT32    HDC_Pkg_Enable : 1;

    UINT32    Reserved1      : 31;

    UINT32    Reserved2      : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PKG_HDC_CTL_REGISTER;


#define MSR_IA32_PM_CTL1  0x00000DB1


typedef union {

  struct {

    UINT32    HDC_Allow_Block : 1;

    UINT32    Reserved1       : 31;

    UINT32    Reserved2       : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_PM_CTL1_REGISTER;


#define MSR_IA32_THREAD_STALL  0x00000DB2


#define MSR_IA32_EFER  0xC0000080


typedef union {

  struct {

    UINT32    SCE       : 1;

    UINT32    Reserved1 : 7;

    UINT32    LME       : 1;

    UINT32    Reserved2 : 1;

    UINT32    LMA       : 1;

    UINT32    NXE       : 1;

    UINT32    Reserved3 : 20;

    UINT32    Reserved4 : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_EFER_REGISTER;


#define MSR_IA32_STAR  0xC0000081


#define MSR_IA32_LSTAR  0xC0000082


#define MSR_IA32_CSTAR  0xC0000083


#define MSR_IA32_FMASK  0xC0000084


#define MSR_IA32_FS_BASE  0xC0000100


#define MSR_IA32_GS_BASE  0xC0000101


#define MSR_IA32_KERNEL_GS_BASE  0xC0000102


#define MSR_IA32_TSC_AUX  0xC0000103


typedef union {

  struct {

    UINT32    AUX      : 32;

    UINT32    Reserved : 32;

  } Bits;

  UINT32    Uint32;

  UINT64    Uint64;

} MSR_IA32_TSC_AUX_REGISTER;


#endif

RTIT_TOPA_MEMORY_SIZE
RTIT_TOPA_MEMORY_SIZE
Definition: ArchitecturalMsr.h:4489

RtitTopaMemorySize16M
@ RtitTopaMemorySize16M
Definition: ArchitecturalMsr.h:4502

RtitTopaMemorySize32K
@ RtitTopaMemorySize32K
Definition: ArchitecturalMsr.h:4493

RtitTopaMemorySize128K
@ RtitTopaMemorySize128K
Definition: ArchitecturalMsr.h:4495

RtitTopaMemorySize256K
@ RtitTopaMemorySize256K
Definition: ArchitecturalMsr.h:4496

RtitTopaMemorySize64K
@ RtitTopaMemorySize64K
Definition: ArchitecturalMsr.h:4494

RtitTopaMemorySize8K
@ RtitTopaMemorySize8K
Definition: ArchitecturalMsr.h:4491

RtitTopaMemorySize8M
@ RtitTopaMemorySize8M
Definition: ArchitecturalMsr.h:4501

RtitTopaMemorySize1M
@ RtitTopaMemorySize1M
Definition: ArchitecturalMsr.h:4498

RtitTopaMemorySize512K
@ RtitTopaMemorySize512K
Definition: ArchitecturalMsr.h:4497

RtitTopaMemorySize4K
@ RtitTopaMemorySize4K
Definition: ArchitecturalMsr.h:4490

RtitTopaMemorySize64M
@ RtitTopaMemorySize64M
Definition: ArchitecturalMsr.h:4504

RtitTopaMemorySize2M
@ RtitTopaMemorySize2M
Definition: ArchitecturalMsr.h:4499

RtitTopaMemorySize32M
@ RtitTopaMemorySize32M
Definition: ArchitecturalMsr.h:4503

RtitTopaMemorySize4M
@ RtitTopaMemorySize4M
Definition: ArchitecturalMsr.h:4500

RtitTopaMemorySize128M
@ RtitTopaMemorySize128M
Definition: ArchitecturalMsr.h:4505

RtitTopaMemorySize16K
@ RtitTopaMemorySize16K
Definition: ArchitecturalMsr.h:4492

SIZE_2KB
#define SIZE_2KB
Definition: Base.h:276

UINT64
unsigned long long UINT64
Definition: ProcessorBind.h:155

UINT8
unsigned char UINT8
Definition: ProcessorBind.h:189

UINT32
unsigned int UINT32
Definition: ProcessorBind.h:163

MSEG_HEADER
Definition: ArchitecturalMsr.h:496

MSEG_HEADER::EipOffset
UINT32 EipOffset
Definition: ArchitecturalMsr.h:514

MSEG_HEADER::GdtrBaseOffset
UINT32 GdtrBaseOffset
Definition: ArchitecturalMsr.h:512

MSEG_HEADER::EspOffset
UINT32 EspOffset
Definition: ArchitecturalMsr.h:515

MSEG_HEADER::MsegHeaderRevision
UINT32 MsegHeaderRevision
Definition: ArchitecturalMsr.h:504

MSEG_HEADER::CsSelector
UINT32 CsSelector
Definition: ArchitecturalMsr.h:513

MSEG_HEADER::GdtrLimit
UINT32 GdtrLimit
Definition: ArchitecturalMsr.h:511

MSEG_HEADER::Cr3Offset
UINT32 Cr3Offset
Definition: ArchitecturalMsr.h:516

MSEG_HEADER::MonitorFeatures
UINT32 MonitorFeatures
Definition: ArchitecturalMsr.h:510

IA32_VMX_MISC_REGISTER
Definition: ArchitecturalMsr.h:3891

IA32_VMX_MISC_REGISTER::VmInjectSupported
UINT32 VmInjectSupported
Definition: ArchitecturalMsr.h:3972

IA32_VMX_MISC_REGISTER::BlockSmiSupported
UINT32 BlockSmiSupported
Definition: ArchitecturalMsr.h:3960

IA32_VMX_MISC_REGISTER::MsrStoreListMaximum
UINT32 MsrStoreListMaximum
Definition: ArchitecturalMsr.h:3954

IA32_VMX_MISC_REGISTER::HltActivityStateSupported
UINT32 HltActivityStateSupported
Definition: ArchitecturalMsr.h:3913

IA32_VMX_MISC_REGISTER::WaitForSipiActivityStateSupported
UINT32 WaitForSipiActivityStateSupported
Definition: ArchitecturalMsr.h:3921

IA32_VMX_MISC_REGISTER::NumberOfCr3TargetValues
UINT32 NumberOfCr3TargetValues
Definition: ArchitecturalMsr.h:3944

IA32_VMX_MISC_REGISTER::ShutdownActivityStateSupported
UINT32 ShutdownActivityStateSupported
Definition: ArchitecturalMsr.h:3917

IA32_VMX_MISC_REGISTER::VmWriteSupported
UINT32 VmWriteSupported
Definition: ArchitecturalMsr.h:3966

IA32_VMX_MISC_REGISTER::VmxTimerRatio
UINT32 VmxTimerRatio
Definition: ArchitecturalMsr.h:3902

IA32_VMX_MISC_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3983

IA32_VMX_MISC_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:3922

IA32_VMX_MISC_REGISTER::VmExitEferLma
UINT32 VmExitEferLma
Definition: ArchitecturalMsr.h:3909

IA32_VMX_MISC_REGISTER::SmBaseMsrSupported
UINT32 SmBaseMsrSupported
Definition: ArchitecturalMsr.h:3938

IA32_VMX_MISC_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:3973

IA32_VMX_MISC_REGISTER::ProcessorTraceSupported
UINT32 ProcessorTraceSupported
Definition: ArchitecturalMsr.h:3932

IA32_VMX_MISC_REGISTER::MsegRevisionIdentifier
UINT32 MsegRevisionIdentifier
Definition: ArchitecturalMsr.h:3978

MSR_IA32_APIC_BASE_REGISTER
Definition: ArchitecturalMsr.h:172

MSR_IA32_APIC_BASE_REGISTER::BSP
UINT32 BSP
Definition: ArchitecturalMsr.h:181

MSR_IA32_APIC_BASE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:182

MSR_IA32_APIC_BASE_REGISTER::ApicBaseHi
UINT32 ApicBaseHi
Definition: ArchitecturalMsr.h:199

MSR_IA32_APIC_BASE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:177

MSR_IA32_APIC_BASE_REGISTER::ApicBase
UINT32 ApicBase
Definition: ArchitecturalMsr.h:195

MSR_IA32_APIC_BASE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:204

MSR_IA32_APIC_BASE_REGISTER::EN
UINT32 EN
Definition: ArchitecturalMsr.h:191

MSR_IA32_APIC_BASE_REGISTER::EXTD
UINT32 EXTD
Definition: ArchitecturalMsr.h:187

MSR_IA32_BIOS_SIGN_ID_REGISTER
Definition: ArchitecturalMsr.h:379

MSR_IA32_BIOS_SIGN_ID_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:384

MSR_IA32_BIOS_SIGN_ID_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:399

MSR_IA32_BIOS_SIGN_ID_REGISTER::MicrocodeUpdateSignature
UINT32 MicrocodeUpdateSignature
Definition: ArchitecturalMsr.h:394

MSR_IA32_BNDCFGS_REGISTER
Definition: ArchitecturalMsr.h:6108

MSR_IA32_BNDCFGS_REGISTER::EN
UINT32 EN
Definition: ArchitecturalMsr.h:6116

MSR_IA32_BNDCFGS_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:6122

MSR_IA32_BNDCFGS_REGISTER::BaseHi
UINT32 BaseHi
Definition: ArchitecturalMsr.h:6130

MSR_IA32_BNDCFGS_REGISTER::Base
UINT32 Base
Definition: ArchitecturalMsr.h:6126

MSR_IA32_BNDCFGS_REGISTER::BNDPRESERVE
UINT32 BNDPRESERVE
Definition: ArchitecturalMsr.h:6121

MSR_IA32_BNDCFGS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6135

MSR_IA32_CLOCK_MODULATION_REGISTER
Definition: ArchitecturalMsr.h:1153

MSR_IA32_CLOCK_MODULATION_REGISTER::OnDemandClockModulationDutyCycle
UINT32 OnDemandClockModulationDutyCycle
Definition: ArchitecturalMsr.h:1167

MSR_IA32_CLOCK_MODULATION_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1173

MSR_IA32_CLOCK_MODULATION_REGISTER::ExtendedOnDemandClockModulationDutyCycle
UINT32 ExtendedOnDemandClockModulationDutyCycle
Definition: ArchitecturalMsr.h:1162

MSR_IA32_CLOCK_MODULATION_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1183

MSR_IA32_CLOCK_MODULATION_REGISTER::OnDemandClockModulationEnable
UINT32 OnDemandClockModulationEnable
Definition: ArchitecturalMsr.h:1172

MSR_IA32_CLOCK_MODULATION_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1179

MSR_IA32_CLOCK_MODULATION_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1174

MSR_IA32_DCA_0_CAP_REGISTER
Definition: ArchitecturalMsr.h:2014

MSR_IA32_DCA_0_CAP_REGISTER::DCA_TYPE
UINT32 DCA_TYPE
Definition: ArchitecturalMsr.h:2031

MSR_IA32_DCA_0_CAP_REGISTER::HW_BLOCK
UINT32 HW_BLOCK
Definition: ArchitecturalMsr.h:2051

MSR_IA32_DCA_0_CAP_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:2047

MSR_IA32_DCA_0_CAP_REGISTER::TRANSACTION
UINT32 TRANSACTION
Definition: ArchitecturalMsr.h:2027

MSR_IA32_DCA_0_CAP_REGISTER::SW_BLOCK
UINT32 SW_BLOCK
Definition: ArchitecturalMsr.h:2046

MSR_IA32_DCA_0_CAP_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2036

MSR_IA32_DCA_0_CAP_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:2052

MSR_IA32_DCA_0_CAP_REGISTER::Reserved5
UINT32 Reserved5
Definition: ArchitecturalMsr.h:2053

MSR_IA32_DCA_0_CAP_REGISTER::DCA_DELAY
UINT32 DCA_DELAY
Definition: ArchitecturalMsr.h:2041

MSR_IA32_DCA_0_CAP_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:2042

MSR_IA32_DCA_0_CAP_REGISTER::DCA_ACTIVE
UINT32 DCA_ACTIVE
Definition: ArchitecturalMsr.h:2023

MSR_IA32_DCA_0_CAP_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:2058

MSR_IA32_DCA_0_CAP_REGISTER::DCA_QUEUE_SIZE
UINT32 DCA_QUEUE_SIZE
Definition: ArchitecturalMsr.h:2035

MSR_IA32_DCA_0_CAP_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2062

MSR_IA32_DEBUGCTL_REGISTER
Definition: ArchitecturalMsr.h:1770

MSR_IA32_DEBUGCTL_REGISTER::BTS_OFF_OS
UINT32 BTS_OFF_OS
Definition: ArchitecturalMsr.h:1810

MSR_IA32_DEBUGCTL_REGISTER::BTS
UINT32 BTS
Definition: ArchitecturalMsr.h:1798

MSR_IA32_DEBUGCTL_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1849

MSR_IA32_DEBUGCTL_REGISTER::FREEZE_WHILE_SMM
UINT32 FREEZE_WHILE_SMM
Definition: ArchitecturalMsr.h:1837

MSR_IA32_DEBUGCTL_REGISTER::LBR
UINT32 LBR
Definition: ArchitecturalMsr.h:1780

MSR_IA32_DEBUGCTL_REGISTER::FREEZE_PERFMON_ON_PMI
UINT32 FREEZE_PERFMON_ON_PMI
Definition: ArchitecturalMsr.h:1826

MSR_IA32_DEBUGCTL_REGISTER::RTM_DEBUG
UINT32 RTM_DEBUG
Definition: ArchitecturalMsr.h:1842

MSR_IA32_DEBUGCTL_REGISTER::BTF
UINT32 BTF
Definition: ArchitecturalMsr.h:1786

MSR_IA32_DEBUGCTL_REGISTER::FREEZE_LBRS_ON_PMI
UINT32 FREEZE_LBRS_ON_PMI
Definition: ArchitecturalMsr.h:1820

MSR_IA32_DEBUGCTL_REGISTER::BTINT
UINT32 BTINT
Definition: ArchitecturalMsr.h:1805

MSR_IA32_DEBUGCTL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1843

MSR_IA32_DEBUGCTL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1853

MSR_IA32_DEBUGCTL_REGISTER::BTS_OFF_USR
UINT32 BTS_OFF_USR
Definition: ArchitecturalMsr.h:1815

MSR_IA32_DEBUGCTL_REGISTER::TR
UINT32 TR
Definition: ArchitecturalMsr.h:1792

MSR_IA32_DEBUGCTL_REGISTER::ENABLE_UNCORE_PMI
UINT32 ENABLE_UNCORE_PMI
Definition: ArchitecturalMsr.h:1832

MSR_IA32_DEBUGCTL_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:1844

MSR_IA32_DEBUGCTL_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1787

MSR_IA32_DEBUG_INTERFACE_REGISTER
Definition: ArchitecturalMsr.h:5809

MSR_IA32_DEBUG_INTERFACE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:5819

MSR_IA32_DEBUG_INTERFACE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:5831

MSR_IA32_DEBUG_INTERFACE_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:5836

MSR_IA32_DEBUG_INTERFACE_REGISTER::Lock
UINT32 Lock
Definition: ArchitecturalMsr.h:5825

MSR_IA32_DEBUG_INTERFACE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5840

MSR_IA32_DEBUG_INTERFACE_REGISTER::Enable
UINT32 Enable
Definition: ArchitecturalMsr.h:5818

MSR_IA32_DEBUG_INTERFACE_REGISTER::DebugOccurred
UINT32 DebugOccurred
Definition: ArchitecturalMsr.h:5830

MSR_IA32_EFER_REGISTER
Definition: ArchitecturalMsr.h:6321

MSR_IA32_EFER_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:6348

MSR_IA32_EFER_REGISTER::LMA
UINT32 LMA
Definition: ArchitecturalMsr.h:6342

MSR_IA32_EFER_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6357

MSR_IA32_EFER_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:6353

MSR_IA32_EFER_REGISTER::NXE
UINT32 NXE
Definition: ArchitecturalMsr.h:6346

MSR_IA32_EFER_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:6331

MSR_IA32_EFER_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:6337

MSR_IA32_EFER_REGISTER::LME
UINT32 LME
Definition: ArchitecturalMsr.h:6336

MSR_IA32_EFER_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:6347

MSR_IA32_EFER_REGISTER::SCE
UINT32 SCE
Definition: ArchitecturalMsr.h:6330

MSR_IA32_ENERGY_PERF_BIAS_REGISTER
Definition: ArchitecturalMsr.h:1546

MSR_IA32_ENERGY_PERF_BIAS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1557

MSR_IA32_ENERGY_PERF_BIAS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1566

MSR_IA32_ENERGY_PERF_BIAS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1562

MSR_IA32_ENERGY_PERF_BIAS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1556

MSR_IA32_ENERGY_PERF_BIAS_REGISTER::PowerPolicyPreference
UINT32 PowerPolicyPreference
Definition: ArchitecturalMsr.h:1555

MSR_IA32_FEATURE_CONTROL_REGISTER
Definition: ArchitecturalMsr.h:231

MSR_IA32_FEATURE_CONTROL_REGISTER::Reserved5
UINT32 Reserved5
Definition: ArchitecturalMsr.h:298

MSR_IA32_FEATURE_CONTROL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:307

MSR_IA32_FEATURE_CONTROL_REGISTER::SgxLaunchControlEnable
UINT32 SgxLaunchControlEnable
Definition: ArchitecturalMsr.h:284

MSR_IA32_FEATURE_CONTROL_REGISTER::LmceOn
UINT32 LmceOn
Definition: ArchitecturalMsr.h:296

MSR_IA32_FEATURE_CONTROL_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:290

MSR_IA32_FEATURE_CONTROL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:278

MSR_IA32_FEATURE_CONTROL_REGISTER::EnableVmxInsideSmx
UINT32 EnableVmxInsideSmx
Definition: ArchitecturalMsr.h:256

MSR_IA32_FEATURE_CONTROL_REGISTER::SgxEnable
UINT32 SgxEnable
Definition: ArchitecturalMsr.h:289

MSR_IA32_FEATURE_CONTROL_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:297

MSR_IA32_FEATURE_CONTROL_REGISTER::Lock
UINT32 Lock
Definition: ArchitecturalMsr.h:247

MSR_IA32_FEATURE_CONTROL_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:264

MSR_IA32_FEATURE_CONTROL_REGISTER::EnableVmxOutsideSmx
UINT32 EnableVmxOutsideSmx
Definition: ArchitecturalMsr.h:263

MSR_IA32_FEATURE_CONTROL_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:303

MSR_IA32_FEATURE_CONTROL_REGISTER::SenterGlobalEnable
UINT32 SenterGlobalEnable
Definition: ArchitecturalMsr.h:277

MSR_IA32_FEATURE_CONTROL_REGISTER::SenterLocalFunctionEnables
UINT32 SenterLocalFunctionEnables
Definition: ArchitecturalMsr.h:271

MSR_IA32_FIXED_CTR_CTRL_REGISTER
Definition: ArchitecturalMsr.h:2806

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN0_PMI
UINT32 EN0_PMI
Definition: ArchitecturalMsr.h:2830

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN2_OS
UINT32 EN2_OS
Definition: ArchitecturalMsr.h:2854

MSR_IA32_FIXED_CTR_CTRL_REGISTER::AnyThread1
UINT32 AnyThread1
Definition: ArchitecturalMsr.h:2846

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN1_PMI
UINT32 EN1_PMI
Definition: ArchitecturalMsr.h:2850

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN1_Usr
UINT32 EN1_Usr
Definition: ArchitecturalMsr.h:2838

MSR_IA32_FIXED_CTR_CTRL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2881

MSR_IA32_FIXED_CTR_CTRL_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2871

MSR_IA32_FIXED_CTR_CTRL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:2872

MSR_IA32_FIXED_CTR_CTRL_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:2877

MSR_IA32_FIXED_CTR_CTRL_REGISTER::AnyThread0
UINT32 AnyThread0
Definition: ArchitecturalMsr.h:2826

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN0_Usr
UINT32 EN0_Usr
Definition: ArchitecturalMsr.h:2818

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN0_OS
UINT32 EN0_OS
Definition: ArchitecturalMsr.h:2814

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN1_OS
UINT32 EN1_OS
Definition: ArchitecturalMsr.h:2834

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN2_Usr
UINT32 EN2_Usr
Definition: ArchitecturalMsr.h:2858

MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN2_PMI
UINT32 EN2_PMI
Definition: ArchitecturalMsr.h:2870

MSR_IA32_FIXED_CTR_CTRL_REGISTER::AnyThread2
UINT32 AnyThread2
Definition: ArchitecturalMsr.h:2866

MSR_IA32_HWP_CAPABILITIES_REGISTER
Definition: ArchitecturalMsr.h:4935

MSR_IA32_HWP_CAPABILITIES_REGISTER::Lowest_Performance
UINT32 Lowest_Performance
Definition: ArchitecturalMsr.h:4959

MSR_IA32_HWP_CAPABILITIES_REGISTER::Highest_Performance
UINT32 Highest_Performance
Definition: ArchitecturalMsr.h:4944

MSR_IA32_HWP_CAPABILITIES_REGISTER::Most_Efficient_Performance
UINT32 Most_Efficient_Performance
Definition: ArchitecturalMsr.h:4954

MSR_IA32_HWP_CAPABILITIES_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:4965

MSR_IA32_HWP_CAPABILITIES_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4969

MSR_IA32_HWP_CAPABILITIES_REGISTER::Guaranteed_Performance
UINT32 Guaranteed_Performance
Definition: ArchitecturalMsr.h:4949

MSR_IA32_HWP_CAPABILITIES_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:4960

MSR_IA32_HWP_INTERRUPT_REGISTER
Definition: ArchitecturalMsr.h:5057

MSR_IA32_HWP_INTERRUPT_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:5073

MSR_IA32_HWP_INTERRUPT_REGISTER::EN_Excursion_Minimum
UINT32 EN_Excursion_Minimum
Definition: ArchitecturalMsr.h:5071

MSR_IA32_HWP_INTERRUPT_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:5078

MSR_IA32_HWP_INTERRUPT_REGISTER::EN_Guaranteed_Performance_Change
UINT32 EN_Guaranteed_Performance_Change
Definition: ArchitecturalMsr.h:5066

MSR_IA32_HWP_INTERRUPT_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5082

MSR_IA32_HWP_INTERRUPT_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:5072

MSR_IA32_HWP_REQUEST_PKG_REGISTER
Definition: ArchitecturalMsr.h:4996

MSR_IA32_HWP_REQUEST_PKG_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:5026

MSR_IA32_HWP_REQUEST_PKG_REGISTER::Activity_Window
UINT32 Activity_Window
Definition: ArchitecturalMsr.h:5025

MSR_IA32_HWP_REQUEST_PKG_REGISTER::Desired_Performance
UINT32 Desired_Performance
Definition: ArchitecturalMsr.h:5015

MSR_IA32_HWP_REQUEST_PKG_REGISTER::Energy_Performance_Preference
UINT32 Energy_Performance_Preference
Definition: ArchitecturalMsr.h:5020

MSR_IA32_HWP_REQUEST_PKG_REGISTER::Maximum_Performance
UINT32 Maximum_Performance
Definition: ArchitecturalMsr.h:5010

MSR_IA32_HWP_REQUEST_PKG_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5031

MSR_IA32_HWP_REQUEST_PKG_REGISTER::Minimum_Performance
UINT32 Minimum_Performance
Definition: ArchitecturalMsr.h:5005

MSR_IA32_HWP_REQUEST_REGISTER
Definition: ArchitecturalMsr.h:5109

MSR_IA32_HWP_REQUEST_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:5144

MSR_IA32_HWP_REQUEST_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5149

MSR_IA32_HWP_REQUEST_REGISTER::Activity_Window
UINT32 Activity_Window
Definition: ArchitecturalMsr.h:5138

MSR_IA32_HWP_REQUEST_REGISTER::Minimum_Performance
UINT32 Minimum_Performance
Definition: ArchitecturalMsr.h:5118

MSR_IA32_HWP_REQUEST_REGISTER::Package_Control
UINT32 Package_Control
Definition: ArchitecturalMsr.h:5143

MSR_IA32_HWP_REQUEST_REGISTER::Energy_Performance_Preference
UINT32 Energy_Performance_Preference
Definition: ArchitecturalMsr.h:5133

MSR_IA32_HWP_REQUEST_REGISTER::Desired_Performance
UINT32 Desired_Performance
Definition: ArchitecturalMsr.h:5128

MSR_IA32_HWP_REQUEST_REGISTER::Maximum_Performance
UINT32 Maximum_Performance
Definition: ArchitecturalMsr.h:5123

MSR_IA32_HWP_STATUS_REGISTER
Definition: ArchitecturalMsr.h:5176

MSR_IA32_HWP_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:5192

MSR_IA32_HWP_STATUS_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:5193

MSR_IA32_HWP_STATUS_REGISTER::Guaranteed_Performance_Change
UINT32 Guaranteed_Performance_Change
Definition: ArchitecturalMsr.h:5185

MSR_IA32_HWP_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:5186

MSR_IA32_HWP_STATUS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:5198

MSR_IA32_HWP_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5202

MSR_IA32_HWP_STATUS_REGISTER::Excursion_To_Minimum
UINT32 Excursion_To_Minimum
Definition: ArchitecturalMsr.h:5191

MSR_IA32_L2_QOS_CFG_REGISTER
Definition: ArchitecturalMsr.h:5912

MSR_IA32_L2_QOS_CFG_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:5922

MSR_IA32_L2_QOS_CFG_REGISTER::Enable
UINT32 Enable
Definition: ArchitecturalMsr.h:5921

MSR_IA32_L2_QOS_CFG_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5932

MSR_IA32_L2_QOS_CFG_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:5928

MSR_IA32_L2_QOS_CFG_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:5923

MSR_IA32_L3_QOS_CFG_REGISTER
Definition: ArchitecturalMsr.h:5866

MSR_IA32_L3_QOS_CFG_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5886

MSR_IA32_L3_QOS_CFG_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:5876

MSR_IA32_L3_QOS_CFG_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:5882

MSR_IA32_L3_QOS_CFG_REGISTER::Enable
UINT32 Enable
Definition: ArchitecturalMsr.h:5875

MSR_IA32_L3_QOS_CFG_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:5877

MSR_IA32_MCG_CAP_REGISTER
Definition: ArchitecturalMsr.h:789

MSR_IA32_MCG_CAP_REGISTER::MCG_ELOG_P
UINT32 MCG_ELOG_P
Definition: ArchitecturalMsr.h:837

MSR_IA32_MCG_CAP_REGISTER::MCG_LMCE_P
UINT32 MCG_LMCE_P
Definition: ArchitecturalMsr.h:844

MSR_IA32_MCG_CAP_REGISTER::MCG_TES_P
UINT32 MCG_TES_P
Definition: ArchitecturalMsr.h:816

MSR_IA32_MCG_CAP_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:828

MSR_IA32_MCG_CAP_REGISTER::MCG_EXT_CNT
UINT32 MCG_EXT_CNT
Definition: ArchitecturalMsr.h:822

MSR_IA32_MCG_CAP_REGISTER::Count
UINT32 Count
Definition: ArchitecturalMsr.h:797

MSR_IA32_MCG_CAP_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:855

MSR_IA32_MCG_CAP_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:851

MSR_IA32_MCG_CAP_REGISTER::MCG_CTL_P
UINT32 MCG_CTL_P
Definition: ArchitecturalMsr.h:801

MSR_IA32_MCG_CAP_REGISTER::MCG_EXT_P
UINT32 MCG_EXT_P
Definition: ArchitecturalMsr.h:806

MSR_IA32_MCG_CAP_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:846

MSR_IA32_MCG_CAP_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:845

MSR_IA32_MCG_CAP_REGISTER::MCG_SER_P
UINT32 MCG_SER_P
Definition: ArchitecturalMsr.h:827

MSR_IA32_MCG_CAP_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:817

MSR_IA32_MCG_CAP_REGISTER::MCP_CMCI_P
UINT32 MCP_CMCI_P
Definition: ArchitecturalMsr.h:811

MSR_IA32_MCG_EXT_CTL_REGISTER
Definition: ArchitecturalMsr.h:4264

MSR_IA32_MCG_EXT_CTL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:4274

MSR_IA32_MCG_EXT_CTL_REGISTER::LMCE_EN
UINT32 LMCE_EN
Definition: ArchitecturalMsr.h:4272

MSR_IA32_MCG_EXT_CTL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4283

MSR_IA32_MCG_EXT_CTL_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:4279

MSR_IA32_MCG_EXT_CTL_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:4273

MSR_IA32_MCG_STATUS_REGISTER
Definition: ArchitecturalMsr.h:882

MSR_IA32_MCG_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:916

MSR_IA32_MCG_STATUS_REGISTER::LMCE_S
UINT32 LMCE_S
Definition: ArchitecturalMsr.h:905

MSR_IA32_MCG_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:907

MSR_IA32_MCG_STATUS_REGISTER::MCIP
UINT32 MCIP
Definition: ArchitecturalMsr.h:901

MSR_IA32_MCG_STATUS_REGISTER::RIPV
UINT32 RIPV
Definition: ArchitecturalMsr.h:891

MSR_IA32_MCG_STATUS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:912

MSR_IA32_MCG_STATUS_REGISTER::EIPV
UINT32 EIPV
Definition: ArchitecturalMsr.h:896

MSR_IA32_MCG_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:906

MSR_IA32_MC_CTL2_REGISTER
Definition: ArchitecturalMsr.h:2577

MSR_IA32_MC_CTL2_REGISTER::CMCI_EN
UINT32 CMCI_EN
Definition: ArchitecturalMsr.h:2590

MSR_IA32_MC_CTL2_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:2591

MSR_IA32_MC_CTL2_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2586

MSR_IA32_MC_CTL2_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:2597

MSR_IA32_MC_CTL2_REGISTER::CorrectedErrorCountThreshold
UINT32 CorrectedErrorCountThreshold
Definition: ArchitecturalMsr.h:2585

MSR_IA32_MC_CTL2_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2601

MSR_IA32_MC_CTL2_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:2592

MSR_IA32_MISC_ENABLE_REGISTER
Definition: ArchitecturalMsr.h:1416

MSR_IA32_MISC_ENABLE_REGISTER::PEBS
UINT32 PEBS
Definition: ArchitecturalMsr.h:1459

MSR_IA32_MISC_ENABLE_REGISTER::Reserved5
UINT32 Reserved5
Definition: ArchitecturalMsr.h:1467

MSR_IA32_MISC_ENABLE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1520

MSR_IA32_MISC_ENABLE_REGISTER::XD
UINT32 XD
Definition: ArchitecturalMsr.h:1514

MSR_IA32_MISC_ENABLE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1427

MSR_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit
UINT32 AutomaticThermalControlCircuit
Definition: ArchitecturalMsr.h:1439

MSR_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval
UINT32 LimitCpuidMaxval
Definition: ArchitecturalMsr.h:1495

MSR_IA32_MISC_ENABLE_REGISTER::EIST
UINT32 EIST
Definition: ArchitecturalMsr.h:1466

MSR_IA32_MISC_ENABLE_REGISTER::Reserved6
UINT32 Reserved6
Definition: ArchitecturalMsr.h:1481

MSR_IA32_MISC_ENABLE_REGISTER::Reserved9
UINT32 Reserved9
Definition: ArchitecturalMsr.h:1515

MSR_IA32_MISC_ENABLE_REGISTER::Reserved7
UINT32 Reserved7
Definition: ArchitecturalMsr.h:1502

MSR_IA32_MISC_ENABLE_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:1447

MSR_IA32_MISC_ENABLE_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:1460

MSR_IA32_MISC_ENABLE_REGISTER::MONITOR
UINT32 MONITOR
Definition: ArchitecturalMsr.h:1480

MSR_IA32_MISC_ENABLE_REGISTER::Reserved8
UINT32 Reserved8
Definition: ArchitecturalMsr.h:1503

MSR_IA32_MISC_ENABLE_REGISTER::BTS
UINT32 BTS
Definition: ArchitecturalMsr.h:1453

MSR_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable
UINT32 xTPR_Message_Disable
Definition: ArchitecturalMsr.h:1501

MSR_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring
UINT32 PerformanceMonitoring
Definition: ArchitecturalMsr.h:1446

MSR_IA32_MISC_ENABLE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1440

MSR_IA32_MISC_ENABLE_REGISTER::FastStrings
UINT32 FastStrings
Definition: ArchitecturalMsr.h:1426

MSR_IA32_MTRRCAP_REGISTER
Definition: ArchitecturalMsr.h:649

MSR_IA32_MTRRCAP_REGISTER::FIX
UINT32 FIX
Definition: ArchitecturalMsr.h:662

MSR_IA32_MTRRCAP_REGISTER::VCNT
UINT32 VCNT
Definition: ArchitecturalMsr.h:658

MSR_IA32_MTRRCAP_REGISTER::WC
UINT32 WC
Definition: ArchitecturalMsr.h:667

MSR_IA32_MTRRCAP_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:673

MSR_IA32_MTRRCAP_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:678

MSR_IA32_MTRRCAP_REGISTER::SMRR
UINT32 SMRR
Definition: ArchitecturalMsr.h:671

MSR_IA32_MTRRCAP_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:682

MSR_IA32_MTRRCAP_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:663

MSR_IA32_MTRRCAP_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:672

MSR_IA32_MTRR_DEF_TYPE_REGISTER
Definition: ArchitecturalMsr.h:2627

MSR_IA32_MTRR_DEF_TYPE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:2645

MSR_IA32_MTRR_DEF_TYPE_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:2646

MSR_IA32_MTRR_DEF_TYPE_REGISTER::Type
UINT32 Type
Definition: ArchitecturalMsr.h:2635

MSR_IA32_MTRR_DEF_TYPE_REGISTER::FE
UINT32 FE
Definition: ArchitecturalMsr.h:2640

MSR_IA32_MTRR_DEF_TYPE_REGISTER::E
UINT32 E
Definition: ArchitecturalMsr.h:2644

MSR_IA32_MTRR_DEF_TYPE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2655

MSR_IA32_MTRR_DEF_TYPE_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:2651

MSR_IA32_MTRR_DEF_TYPE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2636

MSR_IA32_MTRR_PHYSBASE_REGISTER
Definition: ArchitecturalMsr.h:2110

MSR_IA32_MTRR_PHYSBASE_REGISTER::Type
UINT32 Type
Definition: ArchitecturalMsr.h:2118

MSR_IA32_MTRR_PHYSBASE_REGISTER::PhysBase
UINT32 PhysBase
Definition: ArchitecturalMsr.h:2123

MSR_IA32_MTRR_PHYSBASE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2119

MSR_IA32_MTRR_PHYSBASE_REGISTER::PhysBaseHi
UINT32 PhysBaseHi
Definition: ArchitecturalMsr.h:2132

MSR_IA32_MTRR_PHYSBASE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2137

MSR_IA32_MTRR_PHYSMASK_REGISTER
Definition: ArchitecturalMsr.h:2185

MSR_IA32_MTRR_PHYSMASK_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2212

MSR_IA32_MTRR_PHYSMASK_REGISTER::PhysMaskHi
UINT32 PhysMaskHi
Definition: ArchitecturalMsr.h:2207

MSR_IA32_MTRR_PHYSMASK_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2190

MSR_IA32_MTRR_PHYSMASK_REGISTER::PhysMask
UINT32 PhysMask
Definition: ArchitecturalMsr.h:2198

MSR_IA32_MTRR_PHYSMASK_REGISTER::V
UINT32 V
Definition: ArchitecturalMsr.h:2194

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
Definition: ArchitecturalMsr.h:1690

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:1733

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::LowTempEnable
UINT32 LowTempEnable
Definition: ArchitecturalMsr.h:1702

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold1
UINT32 Threshold1
Definition: ArchitecturalMsr.h:1716

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold2
UINT32 Threshold2
Definition: ArchitecturalMsr.h:1724

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:1734

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::PROCHOT_Enable
UINT32 PROCHOT_Enable
Definition: ArchitecturalMsr.h:1706

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1739

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::HighTempEnable
UINT32 HighTempEnable
Definition: ArchitecturalMsr.h:1698

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1707

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1743

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1712

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::PowerLimitNotificationEnable
UINT32 PowerLimitNotificationEnable
Definition: ArchitecturalMsr.h:1732

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::OverheatEnable
UINT32 OverheatEnable
Definition: ArchitecturalMsr.h:1711

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold1Enable
UINT32 Threshold1Enable
Definition: ArchitecturalMsr.h:1720

MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold2Enable
UINT32 Threshold2Enable
Definition: ArchitecturalMsr.h:1728

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
Definition: ArchitecturalMsr.h:1593

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1651

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::DigitalReadout
UINT32 DigitalReadout
Definition: ArchitecturalMsr.h:1650

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PowerLimitStatus
UINT32 PowerLimitStatus
Definition: ArchitecturalMsr.h:1641

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PROCHOT_Log
UINT32 PROCHOT_Log
Definition: ArchitecturalMsr.h:1613

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PowerLimitLog
UINT32 PowerLimitLog
Definition: ArchitecturalMsr.h:1645

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalStatus
UINT32 ThermalStatus
Definition: ArchitecturalMsr.h:1601

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::CriticalTempStatus
UINT32 CriticalTempStatus
Definition: ArchitecturalMsr.h:1617

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:1652

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::CriticalTempStatusLog
UINT32 CriticalTempStatusLog
Definition: ArchitecturalMsr.h:1621

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PROCHOT_Event
UINT32 PROCHOT_Event
Definition: ArchitecturalMsr.h:1609

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold2Log
UINT32 ThermalThreshold2Log
Definition: ArchitecturalMsr.h:1637

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold1Log
UINT32 ThermalThreshold1Log
Definition: ArchitecturalMsr.h:1629

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalStatusLog
UINT32 ThermalStatusLog
Definition: ArchitecturalMsr.h:1605

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold1Status
UINT32 ThermalThreshold1Status
Definition: ArchitecturalMsr.h:1625

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold2Status
UINT32 ThermalThreshold2Status
Definition: ArchitecturalMsr.h:1633

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1646

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1661

MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1657

MSR_IA32_PAT_REGISTER
Definition: ArchitecturalMsr.h:2436

MSR_IA32_PAT_REGISTER::PA4
UINT32 PA4
Definition: ArchitecturalMsr.h:2464

MSR_IA32_PAT_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2445

MSR_IA32_PAT_REGISTER::PA0
UINT32 PA0
Definition: ArchitecturalMsr.h:2444

MSR_IA32_PAT_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:2455

MSR_IA32_PAT_REGISTER::PA3
UINT32 PA3
Definition: ArchitecturalMsr.h:2459

MSR_IA32_PAT_REGISTER::PA6
UINT32 PA6
Definition: ArchitecturalMsr.h:2474

MSR_IA32_PAT_REGISTER::Reserved5
UINT32 Reserved5
Definition: ArchitecturalMsr.h:2465

MSR_IA32_PAT_REGISTER::Reserved8
UINT32 Reserved8
Definition: ArchitecturalMsr.h:2480

MSR_IA32_PAT_REGISTER::PA1
UINT32 PA1
Definition: ArchitecturalMsr.h:2449

MSR_IA32_PAT_REGISTER::Reserved7
UINT32 Reserved7
Definition: ArchitecturalMsr.h:2475

MSR_IA32_PAT_REGISTER::PA2
UINT32 PA2
Definition: ArchitecturalMsr.h:2454

MSR_IA32_PAT_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2485

MSR_IA32_PAT_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:2450

MSR_IA32_PAT_REGISTER::Reserved6
UINT32 Reserved6
Definition: ArchitecturalMsr.h:2470

MSR_IA32_PAT_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:2460

MSR_IA32_PAT_REGISTER::PA7
UINT32 PA7
Definition: ArchitecturalMsr.h:2479

MSR_IA32_PAT_REGISTER::PA5
UINT32 PA5
Definition: ArchitecturalMsr.h:2469

MSR_IA32_PEBS_ENABLE_REGISTER
Definition: ArchitecturalMsr.h:3343

MSR_IA32_PEBS_ENABLE_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:3362

MSR_IA32_PEBS_ENABLE_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:3361

MSR_IA32_PEBS_ENABLE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:3357

MSR_IA32_PEBS_ENABLE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3367

MSR_IA32_PEBS_ENABLE_REGISTER::Enable
UINT32 Enable
Definition: ArchitecturalMsr.h:3352

MSR_IA32_PEBS_ENABLE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:3356

MSR_IA32_PERFEVTSEL_REGISTER
Definition: ArchitecturalMsr.h:969

MSR_IA32_PERFEVTSEL_REGISTER::PC
UINT32 PC
Definition: ArchitecturalMsr.h:998

MSR_IA32_PERFEVTSEL_REGISTER::USR
UINT32 USR
Definition: ArchitecturalMsr.h:986

MSR_IA32_PERFEVTSEL_REGISTER::EN
UINT32 EN
Definition: ArchitecturalMsr.h:1015

MSR_IA32_PERFEVTSEL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1035

MSR_IA32_PERFEVTSEL_REGISTER::OS
UINT32 OS
Definition: ArchitecturalMsr.h:990

MSR_IA32_PERFEVTSEL_REGISTER::INV
UINT32 INV
Definition: ArchitecturalMsr.h:1019

MSR_IA32_PERFEVTSEL_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1031

MSR_IA32_PERFEVTSEL_REGISTER::E
UINT32 E
Definition: ArchitecturalMsr.h:994

MSR_IA32_PERFEVTSEL_REGISTER::INT
UINT32 INT
Definition: ArchitecturalMsr.h:1002

MSR_IA32_PERFEVTSEL_REGISTER::ANY
UINT32 ANY
Definition: ArchitecturalMsr.h:1010

MSR_IA32_PERFEVTSEL_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:1026

MSR_IA32_PERFEVTSEL_REGISTER::EventSelect
UINT32 EventSelect
Definition: ArchitecturalMsr.h:977

MSR_IA32_PERFEVTSEL_REGISTER::CMASK
UINT32 CMASK
Definition: ArchitecturalMsr.h:1025

MSR_IA32_PERFEVTSEL_REGISTER::UMASK
UINT32 UMASK
Definition: ArchitecturalMsr.h:982

MSR_IA32_PERF_CAPABILITIES_REGISTER
Definition: ArchitecturalMsr.h:2738

MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_TRAP
UINT32 PEBS_TRAP
Definition: ArchitecturalMsr.h:2750

MSR_IA32_PERF_CAPABILITIES_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2767

MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_REC_FMT
UINT32 PEBS_REC_FMT
Definition: ArchitecturalMsr.h:2758

MSR_IA32_PERF_CAPABILITIES_REGISTER::SMM_FREEZE
UINT32 SMM_FREEZE
Definition: ArchitecturalMsr.h:2762

MSR_IA32_PERF_CAPABILITIES_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:2773

MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_ARCH_REG
UINT32 PEBS_ARCH_REG
Definition: ArchitecturalMsr.h:2754

MSR_IA32_PERF_CAPABILITIES_REGISTER::LBR_FMT
UINT32 LBR_FMT
Definition: ArchitecturalMsr.h:2746

MSR_IA32_PERF_CAPABILITIES_REGISTER::FW_WRITE
UINT32 FW_WRITE
Definition: ArchitecturalMsr.h:2766

MSR_IA32_PERF_CAPABILITIES_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2777

MSR_IA32_PERF_CAPABILITIES_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:2768

MSR_IA32_PERF_CTL_REGISTER
Definition: ArchitecturalMsr.h:1106

MSR_IA32_PERF_CTL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1126

MSR_IA32_PERF_CTL_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1115

MSR_IA32_PERF_CTL_REGISTER::TargetState
UINT32 TargetState
Definition: ArchitecturalMsr.h:1114

MSR_IA32_PERF_CTL_REGISTER::IDA
UINT32 IDA
Definition: ArchitecturalMsr.h:1120

MSR_IA32_PERF_CTL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1121

MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
Definition: ArchitecturalMsr.h:3021

MSR_IA32_PERF_GLOBAL_CTRL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3042

MSR_IA32_PERF_GLOBAL_CTRL_REGISTER::EN_FIXED_CTRn
UINT32 EN_FIXED_CTRn
Definition: ArchitecturalMsr.h:3037

MSR_IA32_PERF_GLOBAL_CTRL_REGISTER::EN_PMCn
UINT32 EN_PMCn
Definition: ArchitecturalMsr.h:3031

MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
Definition: ArchitecturalMsr.h:3291

MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::IA32_PERFEVTSELn
UINT32 IA32_PERFEVTSELn
Definition: ArchitecturalMsr.h:3301

MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3317

MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::IA32_FIXED_CTRn
UINT32 IA32_FIXED_CTRn
Definition: ArchitecturalMsr.h:3308

MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::PMI
UINT32 PMI
Definition: ArchitecturalMsr.h:3312

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
Definition: ArchitecturalMsr.h:3069

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3110

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMCn
UINT32 Ovf_PMCn
Definition: ArchitecturalMsr.h:3079

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_Uncore
UINT32 Ovf_Uncore
Definition: ArchitecturalMsr.h:3097

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::CondChgd
UINT32 CondChgd
Definition: ArchitecturalMsr.h:3105

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:3092

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_FIXED_CTRn
UINT32 Ovf_FIXED_CTRn
Definition: ArchitecturalMsr.h:3086

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Trace_ToPA_PMI
UINT32 Trace_ToPA_PMI
Definition: ArchitecturalMsr.h:3091

MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::OvfBuf
UINT32 OvfBuf
Definition: ArchitecturalMsr.h:3101

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
Definition: ArchitecturalMsr.h:2906

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:2931

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_Uncore
UINT32 Ovf_Uncore
Definition: ArchitecturalMsr.h:2977

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC2
UINT32 Ovf_PMC2
Definition: ArchitecturalMsr.h:2925

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:2992

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:2947

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::CTR_Frz
UINT32 CTR_Frz
Definition: ArchitecturalMsr.h:2966

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC1
UINT32 Ovf_PMC1
Definition: ArchitecturalMsr.h:2920

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr1
UINT32 Ovf_FixedCtr1
Definition: ArchitecturalMsr.h:2941

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr2
UINT32 Ovf_FixedCtr2
Definition: ArchitecturalMsr.h:2946

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Trace_ToPA_PMI
UINT32 Trace_ToPA_PMI
Definition: ArchitecturalMsr.h:2953

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr0
UINT32 Ovf_FixedCtr0
Definition: ArchitecturalMsr.h:2936

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::OvfBuf
UINT32 OvfBuf
Definition: ArchitecturalMsr.h:2982

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:2954

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::ASCI
UINT32 ASCI
Definition: ArchitecturalMsr.h:2972

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::CondChgd
UINT32 CondChgd
Definition: ArchitecturalMsr.h:2987

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC0
UINT32 Ovf_PMC0
Definition: ArchitecturalMsr.h:2915

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC3
UINT32 Ovf_PMC3
Definition: ArchitecturalMsr.h:2930

MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::LBR_Frz
UINT32 LBR_Frz
Definition: ArchitecturalMsr.h:2960

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
Definition: ArchitecturalMsr.h:3137

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3190

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_Uncore
UINT32 Ovf_Uncore
Definition: ArchitecturalMsr.h:3177

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CTR_Frz
UINT32 CTR_Frz
Definition: ArchitecturalMsr.h:3168

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FIXED_CTRn
UINT32 Ovf_FIXED_CTRn
Definition: ArchitecturalMsr.h:3154

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::ASCI
UINT32 ASCI
Definition: ArchitecturalMsr.h:3172

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::LBR_Frz
UINT32 LBR_Frz
Definition: ArchitecturalMsr.h:3164

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CondChgd
UINT32 CondChgd
Definition: ArchitecturalMsr.h:3185

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMCn
UINT32 Ovf_PMCn
Definition: ArchitecturalMsr.h:3147

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:3160

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::OvfBuf
UINT32 OvfBuf
Definition: ArchitecturalMsr.h:3181

MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Trace_ToPA_PMI
UINT32 Trace_ToPA_PMI
Definition: ArchitecturalMsr.h:3159

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
Definition: ArchitecturalMsr.h:3217

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FIXED_CTRn
UINT32 Ovf_FIXED_CTRn
Definition: ArchitecturalMsr.h:3234

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::ASCI
UINT32 ASCI
Definition: ArchitecturalMsr.h:3251

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Trace_ToPA_PMI
UINT32 Trace_ToPA_PMI
Definition: ArchitecturalMsr.h:3238

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3265

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:3260

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::CTR_Frz
UINT32 CTR_Frz
Definition: ArchitecturalMsr.h:3247

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_Uncore
UINT32 Ovf_Uncore
Definition: ArchitecturalMsr.h:3255

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:3239

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMCn
UINT32 Ovf_PMCn
Definition: ArchitecturalMsr.h:3227

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::LBR_Frz
UINT32 LBR_Frz
Definition: ArchitecturalMsr.h:3243

MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::OvfBuf
UINT32 OvfBuf
Definition: ArchitecturalMsr.h:3259

MSR_IA32_PERF_STATUS_REGISTER
Definition: ArchitecturalMsr.h:1061

MSR_IA32_PERF_STATUS_REGISTER::State
UINT32 State
Definition: ArchitecturalMsr.h:1069

MSR_IA32_PERF_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1080

MSR_IA32_PERF_STATUS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1076

MSR_IA32_PERF_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1070

MSR_IA32_PERF_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1071

MSR_IA32_PKG_HDC_CTL_REGISTER
Definition: ArchitecturalMsr.h:6207

MSR_IA32_PKG_HDC_CTL_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:6224

MSR_IA32_PKG_HDC_CTL_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:6218

MSR_IA32_PKG_HDC_CTL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:6219

MSR_IA32_PKG_HDC_CTL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6228

MSR_IA32_PKG_HDC_CTL_REGISTER::HDC_Pkg_Enable
UINT32 HDC_Pkg_Enable
Definition: ArchitecturalMsr.h:6217

MSR_IA32_PLATFORM_ID_REGISTER
Definition: ArchitecturalMsr.h:119

MSR_IA32_PLATFORM_ID_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:141

MSR_IA32_PLATFORM_ID_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:146

MSR_IA32_PLATFORM_ID_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:125

MSR_IA32_PLATFORM_ID_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:124

MSR_IA32_PLATFORM_ID_REGISTER::PlatformId
UINT32 PlatformId
Definition: ArchitecturalMsr.h:140

MSR_IA32_PM_CTL1_REGISTER
Definition: ArchitecturalMsr.h:6254

MSR_IA32_PM_CTL1_REGISTER::HDC_Allow_Block
UINT32 HDC_Allow_Block
Definition: ArchitecturalMsr.h:6264

MSR_IA32_PM_CTL1_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:6271

MSR_IA32_PM_CTL1_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:6266

MSR_IA32_PM_CTL1_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6275

MSR_IA32_PM_CTL1_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:6265

MSR_IA32_PM_ENABLE_REGISTER
Definition: ArchitecturalMsr.h:4890

MSR_IA32_PM_ENABLE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:4901

MSR_IA32_PM_ENABLE_REGISTER::HWP_ENABLE
UINT32 HWP_ENABLE
Definition: ArchitecturalMsr.h:4899

MSR_IA32_PM_ENABLE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:4900

MSR_IA32_PM_ENABLE_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:4906

MSR_IA32_PM_ENABLE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4910

MSR_IA32_PQR_ASSOC_REGISTER
Definition: ArchitecturalMsr.h:6060

MSR_IA32_PQR_ASSOC_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6081

MSR_IA32_PQR_ASSOC_REGISTER::ResourceMonitoringID
UINT32 ResourceMonitoringID
Definition: ArchitecturalMsr.h:6070

MSR_IA32_PQR_ASSOC_REGISTER::COS
UINT32 COS
Definition: ArchitecturalMsr.h:6076

MSR_IA32_QM_CTR_REGISTER
Definition: ArchitecturalMsr.h:6006

MSR_IA32_QM_CTR_REGISTER::Unavailable
UINT32 Unavailable
Definition: ArchitecturalMsr.h:6023

MSR_IA32_QM_CTR_REGISTER::ResourceMonitoredData
UINT32 ResourceMonitoredData
Definition: ArchitecturalMsr.h:6014

MSR_IA32_QM_CTR_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6033

MSR_IA32_QM_CTR_REGISTER::Error
UINT32 Error
Definition: ArchitecturalMsr.h:6028

MSR_IA32_QM_CTR_REGISTER::ResourceMonitoredDataHi
UINT32 ResourceMonitoredDataHi
Definition: ArchitecturalMsr.h:6018

MSR_IA32_QM_EVTSEL_REGISTER
Definition: ArchitecturalMsr.h:5959

MSR_IA32_QM_EVTSEL_REGISTER::ResourceMonitoringID
UINT32 ResourceMonitoringID
Definition: ArchitecturalMsr.h:5975

MSR_IA32_QM_EVTSEL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5980

MSR_IA32_QM_EVTSEL_REGISTER::EventID
UINT32 EventID
Definition: ArchitecturalMsr.h:5968

MSR_IA32_QM_EVTSEL_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:5969

MSR_IA32_RTIT_ADDR_REGISTER
Definition: ArchitecturalMsr.h:4800

MSR_IA32_RTIT_ADDR_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4821

MSR_IA32_RTIT_ADDR_REGISTER::VirtualAddress
UINT32 VirtualAddress
Definition: ArchitecturalMsr.h:4808

MSR_IA32_RTIT_ADDR_REGISTER::VirtualAddressHi
UINT32 VirtualAddressHi
Definition: ArchitecturalMsr.h:4812

MSR_IA32_RTIT_ADDR_REGISTER::SignExt_VA
UINT32 SignExt_VA
Definition: ArchitecturalMsr.h:4816

MSR_IA32_RTIT_CR3_MATCH_REGISTER
Definition: ArchitecturalMsr.h:4718

MSR_IA32_RTIT_CR3_MATCH_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4736

MSR_IA32_RTIT_CR3_MATCH_REGISTER::Cr3
UINT32 Cr3
Definition: ArchitecturalMsr.h:4727

MSR_IA32_RTIT_CR3_MATCH_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:4723

MSR_IA32_RTIT_CR3_MATCH_REGISTER::Cr3Hi
UINT32 Cr3Hi
Definition: ArchitecturalMsr.h:4731

MSR_IA32_RTIT_CTL_REGISTER
Definition: ArchitecturalMsr.h:4531

MSR_IA32_RTIT_CTL_REGISTER::PwrEvtEn
UINT32 PwrEvtEn
Definition: ArchitecturalMsr.h:4555

MSR_IA32_RTIT_CTL_REGISTER::CR3
UINT32 CR3
Definition: ArchitecturalMsr.h:4567

MSR_IA32_RTIT_CTL_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:4596

MSR_IA32_RTIT_CTL_REGISTER::ADDR0_CFG
UINT32 ADDR0_CFG
Definition: ArchitecturalMsr.h:4610

MSR_IA32_RTIT_CTL_REGISTER::MTCEn
UINT32 MTCEn
Definition: ArchitecturalMsr.h:4575

MSR_IA32_RTIT_CTL_REGISTER::ADDR3_CFG
UINT32 ADDR3_CFG
Definition: ArchitecturalMsr.h:4622

MSR_IA32_RTIT_CTL_REGISTER::Reserved5
UINT32 Reserved5
Definition: ArchitecturalMsr.h:4606

MSR_IA32_RTIT_CTL_REGISTER::PTWEn
UINT32 PTWEn
Definition: ArchitecturalMsr.h:4587

MSR_IA32_RTIT_CTL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4628

MSR_IA32_RTIT_CTL_REGISTER::CYCThresh
UINT32 CYCThresh
Definition: ArchitecturalMsr.h:4600

MSR_IA32_RTIT_CTL_REGISTER::TSCEn
UINT32 TSCEn
Definition: ArchitecturalMsr.h:4579

MSR_IA32_RTIT_CTL_REGISTER::ADDR1_CFG
UINT32 ADDR1_CFG
Definition: ArchitecturalMsr.h:4614

MSR_IA32_RTIT_CTL_REGISTER::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:4601

MSR_IA32_RTIT_CTL_REGISTER::Reserved6
UINT32 Reserved6
Definition: ArchitecturalMsr.h:4623

MSR_IA32_RTIT_CTL_REGISTER::CYCEn
UINT32 CYCEn
Definition: ArchitecturalMsr.h:4543

MSR_IA32_RTIT_CTL_REGISTER::User
UINT32 User
Definition: ArchitecturalMsr.h:4551

MSR_IA32_RTIT_CTL_REGISTER::FUPonPTW
UINT32 FUPonPTW
Definition: ArchitecturalMsr.h:4559

MSR_IA32_RTIT_CTL_REGISTER::MTCFreq
UINT32 MTCFreq
Definition: ArchitecturalMsr.h:4595

MSR_IA32_RTIT_CTL_REGISTER::FabricEn
UINT32 FabricEn
Definition: ArchitecturalMsr.h:4563

MSR_IA32_RTIT_CTL_REGISTER::TraceEn
UINT32 TraceEn
Definition: ArchitecturalMsr.h:4539

MSR_IA32_RTIT_CTL_REGISTER::ADDR2_CFG
UINT32 ADDR2_CFG
Definition: ArchitecturalMsr.h:4618

MSR_IA32_RTIT_CTL_REGISTER::DisRETC
UINT32 DisRETC
Definition: ArchitecturalMsr.h:4583

MSR_IA32_RTIT_CTL_REGISTER::PSBFreq
UINT32 PSBFreq
Definition: ArchitecturalMsr.h:4605

MSR_IA32_RTIT_CTL_REGISTER::ToPA
UINT32 ToPA
Definition: ArchitecturalMsr.h:4571

MSR_IA32_RTIT_CTL_REGISTER::OS
UINT32 OS
Definition: ArchitecturalMsr.h:4547

MSR_IA32_RTIT_CTL_REGISTER::BranchEn
UINT32 BranchEn
Definition: ArchitecturalMsr.h:4591

MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
Definition: ArchitecturalMsr.h:4363

MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4381

MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::Base
UINT32 Base
Definition: ArchitecturalMsr.h:4372

MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:4368

MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::BaseHi
UINT32 BaseHi
Definition: ArchitecturalMsr.h:4376

MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
Definition: ArchitecturalMsr.h:4409

MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:4414

MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::OutputOffset
UINT32 OutputOffset
Definition: ArchitecturalMsr.h:4422

MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::MaskOrTableOffset
UINT32 MaskOrTableOffset
Definition: ArchitecturalMsr.h:4418

MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4427

MSR_IA32_RTIT_STATUS_REGISTER
Definition: ArchitecturalMsr.h:4654

MSR_IA32_RTIT_STATUS_REGISTER::Stopped
UINT32 Stopped
Definition: ArchitecturalMsr.h:4680

MSR_IA32_RTIT_STATUS_REGISTER::FilterEn
UINT32 FilterEn
Definition: ArchitecturalMsr.h:4663

MSR_IA32_RTIT_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:4672

MSR_IA32_RTIT_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4691

MSR_IA32_RTIT_STATUS_REGISTER::PacketByteCnt
UINT32 PacketByteCnt
Definition: ArchitecturalMsr.h:4685

MSR_IA32_RTIT_STATUS_REGISTER::Error
UINT32 Error
Definition: ArchitecturalMsr.h:4676

MSR_IA32_RTIT_STATUS_REGISTER::ContexEn
UINT32 ContexEn
Definition: ArchitecturalMsr.h:4667

MSR_IA32_RTIT_STATUS_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:4686

MSR_IA32_RTIT_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:4681

MSR_IA32_RTIT_STATUS_REGISTER::TriggerEn
UINT32 TriggerEn
Definition: ArchitecturalMsr.h:4671

MSR_IA32_SGX_SVN_STATUS_REGISTER
Definition: ArchitecturalMsr.h:4309

MSR_IA32_SGX_SVN_STATUS_REGISTER::SGX_SVN_SINIT
UINT32 SGX_SVN_SINIT
Definition: ArchitecturalMsr.h:4324

MSR_IA32_SGX_SVN_STATUS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:4331

MSR_IA32_SGX_SVN_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:4325

MSR_IA32_SGX_SVN_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:4319

MSR_IA32_SGX_SVN_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4335

MSR_IA32_SGX_SVN_STATUS_REGISTER::Lock
UINT32 Lock
Definition: ArchitecturalMsr.h:4318

MSR_IA32_SGX_SVN_STATUS_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:4326

MSR_IA32_SMM_MONITOR_CTL_REGISTER
Definition: ArchitecturalMsr.h:456

MSR_IA32_SMM_MONITOR_CTL_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:469

MSR_IA32_SMM_MONITOR_CTL_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:480

MSR_IA32_SMM_MONITOR_CTL_REGISTER::Valid
UINT32 Valid
Definition: ArchitecturalMsr.h:468

MSR_IA32_SMM_MONITOR_CTL_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:475

MSR_IA32_SMM_MONITOR_CTL_REGISTER::BlockSmi
UINT32 BlockSmi
Definition: ArchitecturalMsr.h:474

MSR_IA32_SMM_MONITOR_CTL_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:489

MSR_IA32_SMM_MONITOR_CTL_REGISTER::MsegBase
UINT32 MsegBase
Definition: ArchitecturalMsr.h:479

MSR_IA32_SMM_MONITOR_CTL_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:485

MSR_IA32_SMRR_PHYSBASE_REGISTER
Definition: ArchitecturalMsr.h:1880

MSR_IA32_SMRR_PHYSBASE_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1899

MSR_IA32_SMRR_PHYSBASE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1903

MSR_IA32_SMRR_PHYSBASE_REGISTER::Type
UINT32 Type
Definition: ArchitecturalMsr.h:1888

MSR_IA32_SMRR_PHYSBASE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1894

MSR_IA32_SMRR_PHYSBASE_REGISTER::PhysBase
UINT32 PhysBase
Definition: ArchitecturalMsr.h:1893

MSR_IA32_SMRR_PHYSBASE_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1889

MSR_IA32_SMRR_PHYSMASK_REGISTER
Definition: ArchitecturalMsr.h:1930

MSR_IA32_SMRR_PHYSMASK_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1944

MSR_IA32_SMRR_PHYSMASK_REGISTER::Valid
UINT32 Valid
Definition: ArchitecturalMsr.h:1939

MSR_IA32_SMRR_PHYSMASK_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1935

MSR_IA32_SMRR_PHYSMASK_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1953

MSR_IA32_SMRR_PHYSMASK_REGISTER::PhysMask
UINT32 PhysMask
Definition: ArchitecturalMsr.h:1943

MSR_IA32_SMRR_PHYSMASK_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1949

MSR_IA32_SYSENTER_CS_REGISTER
Definition: ArchitecturalMsr.h:708

MSR_IA32_SYSENTER_CS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:723

MSR_IA32_SYSENTER_CS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:718

MSR_IA32_SYSENTER_CS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:727

MSR_IA32_SYSENTER_CS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:717

MSR_IA32_SYSENTER_CS_REGISTER::CS
UINT32 CS
Definition: ArchitecturalMsr.h:716

MSR_IA32_THERM_INTERRUPT_REGISTER
Definition: ArchitecturalMsr.h:1212

MSR_IA32_THERM_INTERRUPT_REGISTER::PROCHOT_Enable
UINT32 PROCHOT_Enable
Definition: ArchitecturalMsr.h:1228

MSR_IA32_THERM_INTERRUPT_REGISTER::PowerLimitNotificationEnable
UINT32 PowerLimitNotificationEnable
Definition: ArchitecturalMsr.h:1258

MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold2
UINT32 Threshold2
Definition: ArchitecturalMsr.h:1250

MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold2Enable
UINT32 Threshold2Enable
Definition: ArchitecturalMsr.h:1254

MSR_IA32_THERM_INTERRUPT_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1238

MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold1Enable
UINT32 Threshold1Enable
Definition: ArchitecturalMsr.h:1246

MSR_IA32_THERM_INTERRUPT_REGISTER::FORCEPR_Enable
UINT32 FORCEPR_Enable
Definition: ArchitecturalMsr.h:1232

MSR_IA32_THERM_INTERRUPT_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1265

MSR_IA32_THERM_INTERRUPT_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1259

MSR_IA32_THERM_INTERRUPT_REGISTER::CriticalTempEnable
UINT32 CriticalTempEnable
Definition: ArchitecturalMsr.h:1237

MSR_IA32_THERM_INTERRUPT_REGISTER::LowTempEnable
UINT32 LowTempEnable
Definition: ArchitecturalMsr.h:1224

MSR_IA32_THERM_INTERRUPT_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:1260

MSR_IA32_THERM_INTERRUPT_REGISTER::HighTempEnable
UINT32 HighTempEnable
Definition: ArchitecturalMsr.h:1220

MSR_IA32_THERM_INTERRUPT_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1269

MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold1
UINT32 Threshold1
Definition: ArchitecturalMsr.h:1242

MSR_IA32_THERM_STATUS_REGISTER
Definition: ArchitecturalMsr.h:1296

MSR_IA32_THERM_STATUS_REGISTER::PROCHOT_FORCEPR_Log
UINT32 PROCHOT_FORCEPR_Log
Definition: ArchitecturalMsr.h:1316

MSR_IA32_THERM_STATUS_REGISTER::ReadingValid
UINT32 ReadingValid
Definition: ArchitecturalMsr.h:1379

MSR_IA32_THERM_STATUS_REGISTER::DigitalReadout
UINT32 DigitalReadout
Definition: ArchitecturalMsr.h:1369

MSR_IA32_THERM_STATUS_REGISTER::CriticalTempStatusLog
UINT32 CriticalTempStatusLog
Definition: ArchitecturalMsr.h:1325

MSR_IA32_THERM_STATUS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:1370

MSR_IA32_THERM_STATUS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:1385

MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold2Log
UINT32 ThermalThreshold2Log
Definition: ArchitecturalMsr.h:1341

MSR_IA32_THERM_STATUS_REGISTER::CrossDomainLimitLog
UINT32 CrossDomainLimitLog
Definition: ArchitecturalMsr.h:1365

MSR_IA32_THERM_STATUS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:1380

MSR_IA32_THERM_STATUS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:1389

MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold1Log
UINT32 ThermalThreshold1Log
Definition: ArchitecturalMsr.h:1333

MSR_IA32_THERM_STATUS_REGISTER::CurrentLimitStatus
UINT32 CurrentLimitStatus
Definition: ArchitecturalMsr.h:1353

MSR_IA32_THERM_STATUS_REGISTER::ResolutionInDegreesCelsius
UINT32 ResolutionInDegreesCelsius
Definition: ArchitecturalMsr.h:1375

MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold1Status
UINT32 ThermalThreshold1Status
Definition: ArchitecturalMsr.h:1329

MSR_IA32_THERM_STATUS_REGISTER::PowerLimitStatus
UINT32 PowerLimitStatus
Definition: ArchitecturalMsr.h:1345

MSR_IA32_THERM_STATUS_REGISTER::CrossDomainLimitStatus
UINT32 CrossDomainLimitStatus
Definition: ArchitecturalMsr.h:1361

MSR_IA32_THERM_STATUS_REGISTER::CriticalTempStatus
UINT32 CriticalTempStatus
Definition: ArchitecturalMsr.h:1320

MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold2Status
UINT32 ThermalThreshold2Status
Definition: ArchitecturalMsr.h:1337

MSR_IA32_THERM_STATUS_REGISTER::CurrentLimitLog
UINT32 CurrentLimitLog
Definition: ArchitecturalMsr.h:1357

MSR_IA32_THERM_STATUS_REGISTER::PowerLimitLog
UINT32 PowerLimitLog
Definition: ArchitecturalMsr.h:1349

MSR_IA32_THERM_STATUS_REGISTER::PROCHOT_FORCEPR_Event
UINT32 PROCHOT_FORCEPR_Event
Definition: ArchitecturalMsr.h:1312

MSR_IA32_THERM_STATUS_REGISTER::ThermalStatus
UINT32 ThermalStatus
Definition: ArchitecturalMsr.h:1304

MSR_IA32_THERM_STATUS_REGISTER::ThermalStatusLog
UINT32 ThermalStatusLog
Definition: ArchitecturalMsr.h:1308

MSR_IA32_TME_ACTIVATE_REGISTER
Definition: ArchitecturalMsr.h:5705

MSR_IA32_TME_ACTIVATE_REGISTER::MkTmeKeyidBits
UINT32 MkTmeKeyidBits
Definition: ArchitecturalMsr.h:5763

MSR_IA32_TME_ACTIVATE_REGISTER::TmeBypassMode
UINT32 TmeBypassMode
Definition: ArchitecturalMsr.h:5752

MSR_IA32_TME_ACTIVATE_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:5764

MSR_IA32_TME_ACTIVATE_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:5783

MSR_IA32_TME_ACTIVATE_REGISTER::TmeEnable
UINT32 TmeEnable
Definition: ArchitecturalMsr.h:5719

MSR_IA32_TME_ACTIVATE_REGISTER::Lock
UINT32 Lock
Definition: ArchitecturalMsr.h:5714

MSR_IA32_TME_ACTIVATE_REGISTER::KeySelect
UINT32 KeySelect
Definition: ArchitecturalMsr.h:5725

MSR_IA32_TME_ACTIVATE_REGISTER::SaveKeyForStandby
UINT32 SaveKeyForStandby
Definition: ArchitecturalMsr.h:5731

MSR_IA32_TME_ACTIVATE_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:5742

MSR_IA32_TME_ACTIVATE_REGISTER::MkTmeCryptoAlgs
UINT32 MkTmeCryptoAlgs
Definition: ArchitecturalMsr.h:5774

MSR_IA32_TME_ACTIVATE_REGISTER::TmePolicy
UINT32 TmePolicy
Definition: ArchitecturalMsr.h:5741

MSR_IA32_TSC_AUX_REGISTER
Definition: ArchitecturalMsr.h:6511

MSR_IA32_TSC_AUX_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6529

MSR_IA32_TSC_AUX_REGISTER::AUX
UINT32 AUX
Definition: ArchitecturalMsr.h:6519

MSR_IA32_TSC_AUX_REGISTER::Reserved
UINT32 Reserved
Definition: ArchitecturalMsr.h:6520

MSR_IA32_TSC_AUX_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:6525

MSR_IA32_VMX_BASIC_REGISTER
Definition: ArchitecturalMsr.h:3695

MSR_IA32_VMX_BASIC_REGISTER::InsOutsReporting
UINT32 InsOutsReporting
Definition: ArchitecturalMsr.h:3770

MSR_IA32_VMX_BASIC_REGISTER::MustBeZero
UINT32 MustBeZero
Definition: ArchitecturalMsr.h:3711

MSR_IA32_VMX_BASIC_REGISTER::VmcsAddressWidth
UINT32 VmcsAddressWidth
Definition: ArchitecturalMsr.h:3731

MSR_IA32_VMX_BASIC_REGISTER::VmxControls
UINT32 VmxControls
Definition: ArchitecturalMsr.h:3779

MSR_IA32_VMX_BASIC_REGISTER::MemoryType
UINT32 MemoryType
Definition: ArchitecturalMsr.h:3763

MSR_IA32_VMX_BASIC_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:3718

MSR_IA32_VMX_BASIC_REGISTER::VmcsSize
UINT32 VmcsSize
Definition: ArchitecturalMsr.h:3717

MSR_IA32_VMX_BASIC_REGISTER::DualMonitor
UINT32 DualMonitor
Definition: ArchitecturalMsr.h:3737

MSR_IA32_VMX_BASIC_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:3780

MSR_IA32_VMX_BASIC_REGISTER::VmcsRevisonId
UINT32 VmcsRevisonId
Definition: ArchitecturalMsr.h:3710

MSR_IA32_VMX_BASIC_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:3785

MSR_IA32_XSS_REGISTER
Definition: ArchitecturalMsr.h:6161

MSR_IA32_XSS_REGISTER::Uint32
UINT32 Uint32
Definition: ArchitecturalMsr.h:6177

MSR_IA32_XSS_REGISTER::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:6166

MSR_IA32_XSS_REGISTER::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:6172

MSR_IA32_XSS_REGISTER::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:6171

MSR_IA32_XSS_REGISTER::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:6181

MSR_IA32_XSS_REGISTER::TracePacketConfigurationState
UINT32 TracePacketConfigurationState
Definition: ArchitecturalMsr.h:6170

RTIT_TOPA_TABLE_ENTRY
Definition: ArchitecturalMsr.h:4433

RTIT_TOPA_TABLE_ENTRY::Reserved2
UINT32 Reserved2
Definition: ArchitecturalMsr.h:4447

RTIT_TOPA_TABLE_ENTRY::BaseHi
UINT32 BaseHi
Definition: ArchitecturalMsr.h:4478

RTIT_TOPA_TABLE_ENTRY::Reserved1
UINT32 Reserved1
Definition: ArchitecturalMsr.h:4442

RTIT_TOPA_TABLE_ENTRY::END
UINT32 END
Definition: ArchitecturalMsr.h:4441

RTIT_TOPA_TABLE_ENTRY::INT
UINT32 INT
Definition: ArchitecturalMsr.h:4446

RTIT_TOPA_TABLE_ENTRY::Reserved4
UINT32 Reserved4
Definition: ArchitecturalMsr.h:4458

RTIT_TOPA_TABLE_ENTRY::STOP
UINT32 STOP
Definition: ArchitecturalMsr.h:4451

RTIT_TOPA_TABLE_ENTRY::Uint64
UINT64 Uint64
Definition: ArchitecturalMsr.h:4483

RTIT_TOPA_TABLE_ENTRY::Base
UINT32 Base
Definition: ArchitecturalMsr.h:4468

RTIT_TOPA_TABLE_ENTRY::Reserved3
UINT32 Reserved3
Definition: ArchitecturalMsr.h:4452

RTIT_TOPA_TABLE_ENTRY::Size
UINT32 Size
Definition: ArchitecturalMsr.h:4457

Reserved
_Reserved_ PVOID Reserved
Definition: winddi.h:3974