#include <ArchitecturalMsr.h>
Public Attributes | |
| struct { | |
| UINT32 Type: 8 | |
| UINT32 Reserved1: 4 | |
| UINT32 PhysBase: 20 | |
| UINT32 PhysBaseHi: 32 | |
| } | Bits |
| UINT64 | Uint64 |
Detailed Description
MSR information returned for MSR indexes MSR_IA32_MTRR_PHYSBASE0 to MSR_IA32_MTRR_PHYSBASE9
Definition at line 2110 of file ArchitecturalMsr.h.
Member Data Documentation
◆
| struct { ... } MSR_IA32_MTRR_PHYSBASE_REGISTER::Bits |
Individual bit fields
◆ PhysBase
| UINT32 MSR_IA32_MTRR_PHYSBASE_REGISTER::PhysBase |
[Bits 31:12] PhysBase. MTRR physical Base Address.
Definition at line 2123 of file ArchitecturalMsr.h.
◆ PhysBaseHi
| UINT32 MSR_IA32_MTRR_PHYSBASE_REGISTER::PhysBaseHi |
[Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address. MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the maximum physical address range supported by the processor. It is reported by CPUID leaf function 80000008H. If CPUID does not support leaf 80000008H, the processor supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
Definition at line 2132 of file ArchitecturalMsr.h.
◆ Reserved1
| UINT32 MSR_IA32_MTRR_PHYSBASE_REGISTER::Reserved1 |
Definition at line 2119 of file ArchitecturalMsr.h.
◆ Type
| UINT32 MSR_IA32_MTRR_PHYSBASE_REGISTER::Type |
[Bits 7:0] Type. Specifies memory type of the range.
Definition at line 2118 of file ArchitecturalMsr.h.
◆ Uint64
| UINT64 MSR_IA32_MTRR_PHYSBASE_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 2137 of file ArchitecturalMsr.h.
The documentation for this union was generated from the following file:
- sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h
