ReactOS 0.4.15-dev-7942-gd23573b
MSEG_HEADER Struct Reference

#include <ArchitecturalMsr.h>

Public Attributes

UINT32 MsegHeaderRevision
UINT32 MonitorFeatures
UINT32 GdtrLimit
UINT32 GdtrBaseOffset
UINT32 CsSelector
UINT32 EipOffset
UINT32 EspOffset
UINT32 Cr3Offset
UINT8 Reserved [SIZE_2KB - 8 *sizeof(UINT32)]

Detailed Description

MSEG header that is located at the physical address specified by the MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Definition at line 496 of file ArchitecturalMsr.h.

Member Data Documentation

◆ Cr3Offset


Definition at line 516 of file ArchitecturalMsr.h.

◆ CsSelector


Definition at line 513 of file ArchitecturalMsr.h.

◆ EipOffset


Definition at line 514 of file ArchitecturalMsr.h.

◆ EspOffset


Definition at line 515 of file ArchitecturalMsr.h.

◆ GdtrBaseOffset

UINT32 MSEG_HEADER::GdtrBaseOffset

Definition at line 512 of file ArchitecturalMsr.h.

◆ GdtrLimit


Definition at line 511 of file ArchitecturalMsr.h.

◆ MonitorFeatures

UINT32 MSEG_HEADER::MonitorFeatures

Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field is the IA-32e mode SMM feature bit. It indicates whether the logical processor will be in IA-32e mode after the STM is activated.

Definition at line 510 of file ArchitecturalMsr.h.

◆ MsegHeaderRevision

UINT32 MSEG_HEADER::MsegHeaderRevision

Different processors may use different MSEG revision identifiers. These identifiers enable software to avoid using an MSEG header formatted for one processor on a processor that uses a different format. Software can discover the MSEG revision identifier that a processor uses by reading the VMX capability MSR IA32_VMX_MISC.

Definition at line 504 of file ArchitecturalMsr.h.

◆ Reserved

UINT8 MSEG_HEADER::Reserved[SIZE_2KB - 8 *sizeof(UINT32)]

Pad header so total size is 2KB

Definition at line 520 of file ArchitecturalMsr.h.

The documentation for this struct was generated from the following file: