#include <ArchitecturalMsr.h>
Public Attributes | |
| struct { | |
| UINT32 RIPV: 1 | |
| UINT32 EIPV: 1 | |
| UINT32 MCIP: 1 | |
| UINT32 LMCE_S: 1 | |
| UINT32 Reserved1: 28 | |
| UINT32 Reserved2: 32 | |
| } | Bits |
| UINT32 | Uint32 |
| UINT64 | Uint64 |
Detailed Description
MSR information returned for MSR index MSR_IA32_MCG_STATUS
Definition at line 882 of file ArchitecturalMsr.h.
Member Data Documentation
◆
| struct { ... } MSR_IA32_MCG_STATUS_REGISTER::Bits |
Individual bit fields
◆ EIPV
| UINT32 MSR_IA32_MCG_STATUS_REGISTER::EIPV |
[Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display Model 06_01H.
Definition at line 896 of file ArchitecturalMsr.h.
◆ LMCE_S
| UINT32 MSR_IA32_MCG_STATUS_REGISTER::LMCE_S |
[Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
Definition at line 905 of file ArchitecturalMsr.h.
◆ MCIP
| UINT32 MSR_IA32_MCG_STATUS_REGISTER::MCIP |
[Bit 2] MCIP. Machine check in progress. Introduced at Display Family / Display Model 06_01H.
Definition at line 901 of file ArchitecturalMsr.h.
◆ Reserved1
| UINT32 MSR_IA32_MCG_STATUS_REGISTER::Reserved1 |
Definition at line 906 of file ArchitecturalMsr.h.
◆ Reserved2
| UINT32 MSR_IA32_MCG_STATUS_REGISTER::Reserved2 |
Definition at line 907 of file ArchitecturalMsr.h.
◆ RIPV
| UINT32 MSR_IA32_MCG_STATUS_REGISTER::RIPV |
[Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display Model 06_01H.
Definition at line 891 of file ArchitecturalMsr.h.
◆ Uint32
| UINT32 MSR_IA32_MCG_STATUS_REGISTER::Uint32 |
All bit fields as a 32-bit value
Definition at line 912 of file ArchitecturalMsr.h.
◆ Uint64
| UINT64 MSR_IA32_MCG_STATUS_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 916 of file ArchitecturalMsr.h.
The documentation for this union was generated from the following file:
- sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h
