ReactOS 0.4.16-dev-1138-g6efbed5
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MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Collaboration diagram for MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER:
Collaboration graph
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Public Attributes

struct {
   UINT32   Ovf_PMCn: 32
 
   UINT32   Ovf_FIXED_CTRn: 23
 
   UINT32   Trace_ToPA_PMI: 1
 
   UINT32   Reserved2: 2
 
   UINT32   LBR_Frz: 1
 
   UINT32   CTR_Frz: 1
 
   UINT32   ASCI: 1
 
   UINT32   Ovf_Uncore: 1
 
   UINT32   OvfBuf: 1
 
   UINT32   CondChgd: 1
 
} Bits
 
UINT64 Uint64
 

Detailed Description

MSR information returned for MSR index MSR_IA32_PERF_GLOBAL_STATUS_RESET

Definition at line 3137 of file ArchitecturalMsr.h.

Member Data Documentation

◆ ASCI

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::ASCI

[Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.

Definition at line 3172 of file ArchitecturalMsr.h.

◆ 

struct { ... } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Bits

Individual bit fields

◆ CondChgd

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CondChgd

[Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.

Definition at line 3185 of file ArchitecturalMsr.h.

◆ CTR_Frz

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CTR_Frz

[Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.

Definition at line 3168 of file ArchitecturalMsr.h.

◆ LBR_Frz

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::LBR_Frz

[Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.

Definition at line 3164 of file ArchitecturalMsr.h.

◆ Ovf_FIXED_CTRn

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FIXED_CTRn

[Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 22:n are reserved.

Definition at line 3154 of file ArchitecturalMsr.h.

◆ Ovf_PMCn

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMCn

[Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

Definition at line 3147 of file ArchitecturalMsr.h.

◆ Ovf_Uncore

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / Display Model 06_2EH.

Definition at line 3177 of file ArchitecturalMsr.h.

◆ OvfBuf

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::OvfBuf

[Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.

Definition at line 3181 of file ArchitecturalMsr.h.

◆ Reserved2

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Reserved2

Definition at line 3160 of file ArchitecturalMsr.h.

◆ Trace_ToPA_PMI

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.

Definition at line 3159 of file ArchitecturalMsr.h.

◆ Uint64

UINT64 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 3190 of file ArchitecturalMsr.h.

The documentation for this union was generated from the following file: