ReactOS 0.4.15-dev-7889-g76290a6
atapi.h File Reference
#include "config.h"
#include "scsi.h"
#include "stdio.h"
#include "string.h"
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Classes

union  _IDE_REGISTERS_1
 
struct  _IDE_REGISTERS_1::_o
 
struct  _IDE_REGISTERS_1::_i
 
union  _IDE_REGISTERS_2
 
struct  _MODE_SENSE_10
 
struct  _MODE_SELECT_10
 
struct  _MODE_PARAMETER_HEADER_10
 
union  _ATAPI_REGISTERS_1
 
struct  _ATAPI_REGISTERS_1::_o
 
struct  _ATAPI_REGISTERS_1::_i
 
struct  _IDENTIFY_DATA
 
struct  _TRIM_DATA
 

Macros

#define PRINT_PREFIX   "UniATA: "
 
#define KdPrint3(_x_)   {;}
 
#define KdPrint2(_x_)   {;}
 
#define KdPrint(_x_)   {;}
 
#define Connect_DbgPrint()   {;}
 
#define AtapiStallExecution(dt)   ScsiPortStallExecution(dt)
 
#define IDX_IO1   0
 
#define IDX_IO1_SZ   sizeof(IDE_REGISTERS_1)
 
#define IDX_IO1   0
 
#define IDX_IO1_SZ   sizeof(IDE_REGISTERS_1)
 
#define IDX_IO1_i_Data   (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1)
 
#define IDX_IO1_i_Error   (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1)
 
#define IDX_IO1_i_BlockCount   (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1)
 
#define IDX_IO1_i_BlockNumber   (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1)
 
#define IDX_IO1_i_CylinderLow   (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1)
 
#define IDX_IO1_i_CylinderHigh   (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1)
 
#define IDX_IO1_i_DriveSelect   (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1)
 
#define IDX_IO1_i_Status   (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1)
 
#define IDX_IO1_o   IDX_IO1_SZ
 
#define IDX_IO1_o_SZ   sizeof(IDE_REGISTERS_1)
 
#define IDX_IO1_o_Data   (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o)
 
#define IDX_IO1_o_Feature   (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o)
 
#define IDX_IO1_o_BlockCount   (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o)
 
#define IDX_IO1_o_BlockNumber   (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o)
 
#define IDX_IO1_o_CylinderLow   (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o)
 
#define IDX_IO1_o_CylinderHigh   (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o)
 
#define IDX_IO1_o_DriveSelect   (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o)
 
#define IDX_IO1_o_Command   (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o)
 
#define IDX_IO2   (IDX_IO1_o+IDX_IO1_o_SZ)
 
#define IDX_IO2_SZ   sizeof(IDE_REGISTERS_2)
 
#define IDX_IO2_AltStatus   (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2)
 
#define IDX_IO2_o   (IDX_IO2+IDX_IO2_SZ)
 
#define IDX_IO2_o_SZ   sizeof(IDE_REGISTERS_2)
 
#define IDX_IO2_o_Control   (FIELD_OFFSET(IDE_REGISTERS_2, Control)+IDX_IO2_o)
 
#define DFLAGS_DEVICE_PRESENT   0x0001
 
#define DFLAGS_ATAPI_DEVICE   0x0002
 
#define DFLAGS_TAPE_DEVICE   0x0004
 
#define DFLAGS_INT_DRQ   0x0008
 
#define DFLAGS_REMOVABLE_DRIVE   0x0010
 
#define DFLAGS_MEDIA_STATUS_ENABLED   0x0020
 
#define DFLAGS_ATAPI_CHANGER   0x0040
 
#define DFLAGS_SANYO_ATAPI_CHANGER   0x0080
 
#define DFLAGS_CHANGER_INITED   0x0100
 
#define DFLAGS_LBA_ENABLED   0x0200
 
#define DFLAGS_DWORDIO_ENABLED   0x0400
 
#define DFLAGS_WCACHE_ENABLED   0x0800
 
#define DFLAGS_RCACHE_ENABLED   0x1000
 
#define DFLAGS_ORIG_GEOMETRY   0x2000
 
#define DFLAGS_REINIT_DMA   0x4000
 
#define DFLAGS_HIDDEN   0x8000
 
#define DFLAGS_MANUAL_CHS   0x10000
 
#define DFLAGS_LBA32plus   0x20000
 
#define MAX_ERRORS   4
 
#define ATAPI_MODE_SENSE   0x5A
 
#define ATAPI_MODE_SELECT   0x55
 
#define ATAPI_FORMAT_UNIT   0x24
 
#define ATA_PIO   0x00
 
#define ATA_PIO_NRDY   0x01
 
#define ATA_PIO0   0x08
 
#define ATA_PIO1   0x09
 
#define ATA_PIO2   0x0a
 
#define ATA_PIO3   0x0b
 
#define ATA_PIO4   0x0c
 
#define ATA_PIO5   0x0d
 
#define ATA_DMA   0x10
 
#define ATA_SDMA   0x10
 
#define ATA_SDMA0   0x10
 
#define ATA_SDMA1   0x11
 
#define ATA_SDMA2   0x12
 
#define ATA_WDMA   0x20
 
#define ATA_WDMA0   0x20
 
#define ATA_WDMA1   0x21
 
#define ATA_WDMA2   0x22
 
#define ATA_UDMA   0x40
 
#define ATA_UDMA0   0x40
 
#define ATA_UDMA1   0x41
 
#define ATA_UDMA2   0x42
 
#define ATA_UDMA3   0x43
 
#define ATA_UDMA4   0x44
 
#define ATA_UDMA5   0x45
 
#define ATA_UDMA6   0x46
 
#define ATA_SA150   0x47 /*0x80*/
 
#define ATA_SA300   0x48 /*0x81*/
 
#define ATA_SA600   0x49 /*0x82*/
 
#define ATA_MODE_NOT_SPEC   ((ULONG)(-1)) /*0x82*/
 
#define IDE_COMMAND_DATA_SET_MGMT   0x06
 
#define IDE_COMMAND_ATAPI_RESET   0x08
 
#define IDE_COMMAND_RECALIBRATE   0x10
 
#define IDE_COMMAND_READ   0x20
 
#define IDE_COMMAND_READ_NO_RETR   0x21
 
#define IDE_COMMAND_READ48   0x24
 
#define IDE_COMMAND_READ_DMA48   0x25
 
#define IDE_COMMAND_READ_DMA_Q48   0x26
 
#define IDE_COMMAND_READ_NATIVE_SIZE48   0x27
 
#define IDE_COMMAND_READ_MUL48   0x29
 
#define IDE_COMMAND_READ_STREAM_DMA48   0x2A
 
#define IDE_COMMAND_READ_STREAM48   0x2B
 
#define IDE_COMMAND_READ_LOG48   0x2f
 
#define IDE_COMMAND_WRITE   0x30
 
#define IDE_COMMAND_WRITE_NO_RETR   0x31
 
#define IDE_COMMAND_WRITE48   0x34
 
#define IDE_COMMAND_WRITE_DMA48   0x35
 
#define IDE_COMMAND_WRITE_DMA_Q48   0x36
 
#define IDE_COMMAND_SET_NATIVE_SIZE48   0x37
 
#define IDE_COMMAND_WRITE_MUL48   0x39
 
#define IDE_COMMAND_WRITE_STREAM_DMA48   0x3a
 
#define IDE_COMMAND_WRITE_STREAM48   0x3b
 
#define IDE_COMMAND_WRITE_FUA_DMA48   0x3d
 
#define IDE_COMMAND_WRITE_FUA_DMA_Q48   0x3e
 
#define IDE_COMMAND_WRITE_LOG48   0x3f
 
#define IDE_COMMAND_VERIFY   0x40
 
#define IDE_COMMAND_VERIFY48   0x42
 
#define IDE_COMMAND_READ_LOG_DMA48   0x47
 
#define IDE_COMMAND_WRITE_LOG_DMA48   0x57
 
#define IDE_COMMAND_TRUSTED_RCV   0x5c
 
#define IDE_COMMAND_TRUSTED_RCV_DMA   0x5d
 
#define IDE_COMMAND_TRUSTED_SEND   0x5e
 
#define IDE_COMMAND_TRUSTED_SEND_DMA   0x5f
 
#define IDE_COMMAND_SEEK   0x70
 
#define IDE_COMMAND_SET_DRIVE_PARAMETERS   0x91
 
#define IDE_COMMAND_ATAPI_PACKET   0xA0
 
#define IDE_COMMAND_ATAPI_IDENTIFY   0xA1
 
#define IDE_COMMAND_READ_MULTIPLE   0xC4
 
#define IDE_COMMAND_WRITE_MULTIPLE   0xC5
 
#define IDE_COMMAND_SET_MULTIPLE   0xC6
 
#define IDE_COMMAND_READ_DMA_Q   0xC7
 
#define IDE_COMMAND_READ_DMA   0xC8
 
#define IDE_COMMAND_WRITE_DMA   0xCA
 
#define IDE_COMMAND_WRITE_DMA_Q   0xCC
 
#define IDE_COMMAND_WRITE_MUL_FUA48   0xCE
 
#define IDE_COMMAND_GET_MEDIA_STATUS   0xDA
 
#define IDE_COMMAND_DOOR_LOCK   0xDE
 
#define IDE_COMMAND_DOOR_UNLOCK   0xDF
 
#define IDE_COMMAND_STANDBY_IMMED   0xE0
 
#define IDE_COMMAND_IDLE_IMMED   0xE1
 
#define IDE_COMMAND_STANDBY   0xE2
 
#define IDE_COMMAND_IDLE   0xE3
 
#define IDE_COMMAND_READ_PM   0xE4
 
#define IDE_COMMAND_SLEEP   0xE6
 
#define IDE_COMMAND_FLUSH_CACHE   0xE7
 
#define IDE_COMMAND_WRITE_PM   0xE8
 
#define IDE_COMMAND_IDENTIFY   0xEC
 
#define IDE_COMMAND_MEDIA_EJECT   0xED
 
#define IDE_COMMAND_FLUSH_CACHE48   0xEA
 
#define IDE_COMMAND_ENABLE_MEDIA_STATUS   0xEF
 
#define IDE_COMMAND_SET_FEATURES
 
#define IDE_COMMAND_READ_NATIVE_SIZE   0xF8
 
#define IDE_COMMAND_SET_NATIVE_SIZE   0xF9
 
#define SCSIOP_ATA_PASSTHROUGH   0xCC
 
#define IDE_STATUS_SUCCESS   0x00
 
#define IDE_STATUS_ERROR   0x01
 
#define IDE_STATUS_INDEX   0x02
 
#define IDE_STATUS_CORRECTED_ERROR   0x04
 
#define IDE_STATUS_DRQ   0x08
 
#define IDE_STATUS_DSC   0x10
 
#define IDE_STATUS_DMA   0x20 /* DMA ready */
 
#define IDE_STATUS_DWF   0x20 /* drive write fault */
 
#define IDE_STATUS_DRDY   0x40
 
#define IDE_STATUS_IDLE   0x50
 
#define IDE_STATUS_BUSY   0x80
 
#define IDE_STATUS_WRONG   0xff
 
#define IDE_STATUS_MASK   0xff
 
#define IDE_DRIVE_SELECT   0xA0
 
#define IDE_DRIVE_1   0x00
 
#define IDE_DRIVE_2   0x10
 
#define IDE_DRIVE_SELECT_1   (IDE_DRIVE_SELECT | IDE_DRIVE_1)
 
#define IDE_DRIVE_SELECT_2   (IDE_DRIVE_SELECT | IDE_DRIVE_2)
 
#define IDE_DRIVE_MASK   (IDE_DRIVE_SELECT_1 | IDE_DRIVE_SELECT_2)
 
#define IDE_USE_LBA   0x40
 
#define IDE_DC_DISABLE_INTERRUPTS   0x02
 
#define IDE_DC_RESET_CONTROLLER   0x04
 
#define IDE_DC_A_4BIT   0x80
 
#define IDE_DC_USE_HOB   0x80
 
#define IDE_DC_REENABLE_CONTROLLER   0x00
 
#define IDE_ERROR_ICRC   0x80
 
#define IDE_ERROR_BAD_BLOCK   0x80
 
#define IDE_ERROR_DATA_ERROR   0x40
 
#define IDE_ERROR_MEDIA_CHANGE   0x20
 
#define IDE_ERROR_ID_NOT_FOUND   0x10
 
#define IDE_ERROR_MEDIA_CHANGE_REQ   0x08
 
#define IDE_ERROR_COMMAND_ABORTED   0x04
 
#define IDE_ERROR_END_OF_MEDIA   0x02
 
#define IDE_ERROR_NO_MEDIA   0x02
 
#define IDE_ERROR_ILLEGAL_LENGTH   0x01
 
#define IDX_ATAPI_IO1   IDX_IO1
 
#define IDX_ATAPI_IO1_SZ   sizeof(ATAPI_REGISTERS_1)
 
#define IDX_ATAPI_IO1_i_Data   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_i_Error   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_i_InterruptReason   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_i_Unused1   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_i_ByteCountLow   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_i_ByteCountHigh   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_i_DriveSelect   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_i_Status   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_Data   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_Feature   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_Unused0   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_Unused1   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_ByteCountLow   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_ByteCountHigh   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_DriveSelect   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1)
 
#define IDX_ATAPI_IO1_o_Command   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1)
 
#define ATAPI_IR_COD   0x01
 
#define ATAPI_IR_COD_Data   0x0
 
#define ATAPI_IR_COD_Cmd   0x1
 
#define ATAPI_IR_IO   0x02
 
#define ATAPI_IR_IO_toDev   0x00
 
#define ATAPI_IR_IO_toHost   0x02
 
#define ATAPI_IR_Mask   0x03
 
#define ATA_F_DMA   0x01 /* enable DMA */
 
#define ATA_F_OVL   0x02 /* enable overlap */
 
#define ATA_F_DMAREAD   0x04 /* DMA Packet (ATAPI) read */
 
#define ATA_C_F_SETXFER   0x03 /* set transfer mode */
 
#define ATA_C_F_ENAB_WCACHE   0x02 /* enable write cache */
 
#define ATA_C_F_DIS_WCACHE   0x82 /* disable write cache */
 
#define ATA_C_F_ENAB_RCACHE   0xaa /* enable readahead cache */
 
#define ATA_C_F_DIS_RCACHE   0x55 /* disable readahead cache */
 
#define ATA_C_F_ENAB_RELIRQ   0x5d /* enable release interrupt */
 
#define ATA_C_F_DIS_RELIRQ   0xdd /* disable release interrupt */
 
#define ATA_C_F_ENAB_SRVIRQ   0x5e /* enable service interrupt */
 
#define ATA_C_F_DIS_SRVIRQ   0xde /* disable service interrupt */
 
#define ATA_C_F_ENAB_MEDIASTAT   0x95 /* enable media status */
 
#define ATA_C_F_DIS_MEDIASTAT   0x31 /* disable media status */
 
#define ATA_C_F_ENAB_APM   0x05 /* enable advanced power management */
 
#define ATA_C_F_DIS_APM   0x85 /* disable advanced power management */
 
#define ATA_C_F_APM_CNT_MAX_PERF   0xfe /* maximum performance */
 
#define ATA_C_F_APM_CNT_MIN_NO_STANDBY   0x80 /* min. power w/o standby */
 
#define ATA_C_F_APM_CNT_MIN_STANDBY   0x01 /* min. power with standby */
 
#define ATA_C_F_ENAB_ACOUSTIC   0x42 /* enable acoustic management */
 
#define ATA_C_F_DIS_ACOUSTIC   0xc2 /* disable acoustic management */
 
#define ATA_C_F_AAM_CNT_MAX_PERF   0xfe /* maximum performance */
 
#define ATA_C_F_AAM_CNT_MAX_POWER_SAVE   0x80 /* min. power */
 
#define READ_LOG_SECTOR   0xD5
 
#define WRITE_LOG_SECTOR   0xD6
 
#define WRITE_THRESHOLDS   0xD7
 
#define AUTO_OFFLINE   0xDB
 
#define ATA_I_CMD   0x01 /* cmd (1) | data (0) */
 
#define ATA_I_IN   0x02 /* read (1) | write (0) */
 
#define ATA_I_RELEASE   0x04 /* released bus (1) */
 
#define ATA_I_TAGMASK   0xf8 /* tag mask */
 
#define ATAPI_PSIZE_12   0 /* 12 bytes */
 
#define ATAPI_PSIZE_16   1 /* 16 bytes */
 
#define ATAPI_DRQT_MPROC   0 /* cpu 3 ms delay */
 
#define ATAPI_DRQT_INTR   1 /* intr 10 ms delay */
 
#define ATAPI_DRQT_ACCEL   2 /* accel 50 us delay */
 
#define ATAPI_TYPE_DIRECT   0 /* disk/floppy */
 
#define ATAPI_TYPE_TAPE   1 /* streaming tape */
 
#define ATAPI_TYPE_CDROM   5 /* CD-ROM device */
 
#define ATAPI_TYPE_OPTICAL   7 /* optical disk */
 
#define ATAPI_PROTO_ATAPI   2
 
#define ATA_BT_SINGLEPORTSECTOR   1 /* 1 port, 1 sector buffer */
 
#define ATA_BT_DUALPORTMULTI   2 /* 2 port, mult sector buffer */
 
#define ATA_BT_DUALPORTMULTICACHE   3 /* above plus track cache */
 
#define AdvancedPIOModes_3   1
 
#define AdvancedPIOModes_4   2
 
#define AdvancedPIOModes_5   4
 
#define ATA_SATA_GEN1   0x0002
 
#define ATA_SATA_GEN2   0x0004
 
#define ATA_SATA_GEN3   0x0008
 
#define ATA_SUPPORT_NCQ   0x0100
 
#define ATA_SUPPORT_IFPWRMNGTRCV   0x0200
 
#define ATA_SUPPORT_PHY_EVENT_COUNTER   0x0400
 
#define ATA_SUPPORT_NCQ_UNLOAD   0x0800
 
#define ATA_SUPPORT_NCQ_PRI_INFO   0x1000
 
#define ATA_SUPPORT_NONZERO   0x0002
 
#define ATA_SUPPORT_AUTOACTIVATE   0x0004
 
#define ATA_SUPPORT_IFPWRMNGT   0x0008
 
#define ATA_SUPPORT_INORDERDATA   0x0010
 
#define ATA_VER_MJ_ATA4   0x0010
 
#define ATA_VER_MJ_ATA5   0x0020
 
#define ATA_VER_MJ_ATA6   0x0040
 
#define ATA_VER_MJ_ATA7   0x0080
 
#define ATA_VER_MJ_ATA8_ASC   0x0100
 
#define IDENTIFY_CABLE_ID_VALID   0x01
 
#define ATA_ChecksumValid   0xA5
 
#define IDENTIFY_DATA2   IDENTIFY_DATA
 
#define PIDENTIFY_DATA2   PIDENTIFY_DATA
 
#define IDENTIFY_DATA_SIZE   sizeof(IDENTIFY_DATA)
 
#define IDENTIFY_DMA_CYCLES_MODE_0   0x00
 
#define IDENTIFY_DMA_CYCLES_MODE_1   0x01
 
#define IDENTIFY_DMA_CYCLES_MODE_2   0x02
 
#define GetStatus(chan, Status)    Status = AtapiReadPort1(chan, IDX_IO2_AltStatus);
 
#define GetBaseStatus(chan, pStatus)    pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status);
 
#define WriteCommand(chan, _Command)    AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);
 
#define ReadBuffer(chan, Buffer, Count, timing)
 
#define WriteBuffer(chan, Buffer, Count, timing)
 
#define ReadBuffer2(chan, Buffer, Count, timing)
 
#define WriteBuffer2(chan, Buffer, Count, timing)
 
#define IS_RDP(OperationCode)
 
#define AtapiCopyMemory   RtlCopyMemory
 
#define AtapiStringCmp(s1, s2, n)   _strnicmp(s1, s2, n)
 
#define INTERRUPT_REASON_IGNORE   0
 
#define INTERRUPT_REASON_OUR   1
 
#define INTERRUPT_REASON_UNEXPECTED   2
 
#define UNIATA_FIND_DEV_UNHIDE   0x01
 
#define CHAN_NOT_SPECIFIED   (0xffffffffL)
 
#define CHAN_NOT_SPECIFIED_CHECK_CABLE   (0xfffffffeL)
 
#define DEVNUM_NOT_SPECIFIED   (0xffffffffL)
 
#define IOMODE_NOT_SPECIFIED   (0xffffffffL)
 
#define ATA_AT_HOME_HDD   0x01
 
#define ATA_AT_HOME_ATAPI   0x02
 
#define ATA_AT_HOME_XXX   0x04
 
#define ATA_AT_HOME_NOBODY   0x00
 
#define ATA_CMD_FLAG_LBAIOsupp   0x01
 
#define ATA_CMD_FLAG_48supp   0x02
 
#define ATA_CMD_FLAG_48   0x04
 
#define ATA_CMD_FLAG_DMA   0x08
 
#define ATA_CMD_FLAG_FUA   0x10
 
#define ATA_CMD_FLAG_In   0x40
 
#define ATA_CMD_FLAG_Out   0x80
 
#define UniAta_need_lba48(command, lba, count, supp48)
 
#define UniAtaClearAtaReq(AtaReq)
 
#define ATAPI_DEVICE(chan, dev)   ((chan->lun[dev]->DeviceFlags & DFLAGS_ATAPI_DEVICE) ? TRUE : FALSE)
 
#define PrintNtConsole(x)   {;}
 
#define IDENT_MODE_MAX   FALSE
 
#define IDENT_MODE_ACTIVE   TRUE
 

Typedefs

typedef union _IDE_REGISTERS_1 IDE_REGISTERS_1
 
typedef union _IDE_REGISTERS_1PIDE_REGISTERS_1
 
typedef union _IDE_REGISTERS_2 IDE_REGISTERS_2
 
typedef union _IDE_REGISTERS_2PIDE_REGISTERS_2
 
typedef struct _MODE_SENSE_10 MODE_SENSE_10
 
typedef struct _MODE_SENSE_10PMODE_SENSE_10
 
typedef struct _MODE_SELECT_10 MODE_SELECT_10
 
typedef struct _MODE_SELECT_10PMODE_SELECT_10
 
typedef struct _MODE_PARAMETER_HEADER_10 MODE_PARAMETER_HEADER_10
 
typedef struct _MODE_PARAMETER_HEADER_10PMODE_PARAMETER_HEADER_10
 
typedef union _ATAPI_REGISTERS_1 ATAPI_REGISTERS_1
 
typedef union _ATAPI_REGISTERS_1PATAPI_REGISTERS_1
 
typedef struct _IDENTIFY_DATA IDENTIFY_DATA
 
typedef struct _IDENTIFY_DATAPIDENTIFY_DATA
 
typedef struct _TRIM_DATA TRIM_DATA
 
typedef struct _TRIM_DATAPTRIM_DATA
 

Functions

UCHAR DDKFASTAPI SelectDrive (IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)
 
UCHAR DDKFASTAPI WaitOnBusy (IN struct _HW_CHANNEL *chan)
 
UCHAR DDKFASTAPI WaitOnBusyLong (IN struct _HW_CHANNEL *chan)
 
UCHAR DDKFASTAPI WaitOnBaseBusy (IN struct _HW_CHANNEL *chan)
 
UCHAR DDKFASTAPI WaitOnBaseBusyLong (IN struct _HW_CHANNEL *chan)
 
UCHAR DDKFASTAPI WaitForDrq (IN struct _HW_CHANNEL *chan)
 
UCHAR DDKFASTAPI WaitShortForDrq (IN struct _HW_CHANNEL *chan)
 
VOID DDKFASTAPI AtapiSoftReset (IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)
 
VOID DDKFASTAPI AtapiHardReset (IN struct _HW_CHANNEL *chan, IN BOOLEAN DisableInterrupts, IN ULONG Delay)
 
PSCSI_REQUEST_BLOCK NTAPI BuildMechanismStatusSrb (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)
 
PSCSI_REQUEST_BLOCK NTAPI BuildRequestSenseSrb (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)
 
VOID NTAPI AtapiHwInitializeChanger (IN PVOID HwDeviceExtension, IN ULONG TargetId, IN PMECHANICAL_STATUS_INFORMATION_HEADER MechanismStatus)
 
ULONG NTAPI AtapiSendCommand (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb, IN ULONG CmdAction)
 
ULONG NTAPI IdeSendCommand (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb, IN ULONG CmdAction)
 
VOID NTAPI AtapiHexToString (ULONG Value, PCHAR *Buffer)
 
BOOLEAN NTAPI AtapiInterrupt (IN PVOID HwDeviceExtension)
 
BOOLEAN NTAPI AtapiInterrupt__ (IN PVOID HwDeviceExtension, IN UCHAR c)
 
UCHAR NTAPI AtapiCheckInterrupt__ (IN PVOID HwDeviceExtension, IN UCHAR c)
 
BOOLEAN NTAPI AtapiHwInitialize (IN PVOID HwDeviceExtension)
 
ULONG NTAPI IdeBuildSenseBuffer (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)
 
VOID NTAPI IdeMediaStatus (BOOLEAN EnableMSN, IN PVOID HwDeviceExtension, IN ULONG lChannel, IN ULONG DeviceNumber)
 
ULONG NTAPI AtapiFindIsaController (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
ULONG NTAPI AtapiReadArgumentString (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
ULONG NTAPI AtapiParseArgumentString (IN PCCH String, IN PCCH KeyWord)
 
BOOLEAN NTAPI IssueIdentify (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG Channel, IN UCHAR Command, IN BOOLEAN NoSetup)
 
BOOLEAN NTAPI SetDriveParameters (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG Channel)
 
ULONG NTAPI CheckDevice (IN PVOID HwDeviceExtension, IN ULONG Channel, IN ULONG deviceNumber, IN BOOLEAN ResetBus)
 
BOOLEAN NTAPI FindDevices (IN PVOID HwDeviceExtension, IN ULONG Flags, IN ULONG Channel)
 
BOOLEAN NTAPI AtapiResetController (IN PVOID HwDeviceExtension, IN ULONG PathId)
 
BOOLEAN NTAPI AtapiStartIo (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)
 
BOOLEAN NTAPI AtapiStartIo__ (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb, IN BOOLEAN TopLevel)
 
UCHAR NTAPI AtaCommand48 (IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN ULONG DeviceNumber, IN ULONG Channel, IN UCHAR command, IN ULONGLONG lba, IN USHORT count, IN USHORT feature, IN ULONG flags)
 
UCHAR NTAPI AtaCommand (IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN ULONG DeviceNumber, IN ULONG Channel, IN UCHAR command, IN USHORT cylinder, IN UCHAR head, IN UCHAR sector, IN UCHAR count, IN UCHAR feature, IN ULONG flags)
 
LONG NTAPI AtaPioMode (PIDENTIFY_DATA2 ident)
 
LONG NTAPI AtaWmode (PIDENTIFY_DATA2 ident)
 
LONG NTAPI AtaUmode (PIDENTIFY_DATA2 ident)
 
VOID NTAPI AtapiDpcDispatch (IN PKDPC Dpc, IN PVOID DeferredContext, IN PVOID SystemArgument1, IN PVOID SystemArgument2)
 
LONG NTAPI AtaPio2Mode (LONG pio)
 
VOID NTAPI AtapiEnableInterrupts (IN PVOID HwDeviceExtension, IN ULONG c)
 
VOID NTAPI AtapiDisableInterrupts (IN PVOID HwDeviceExtension, IN ULONG c)
 
VOID UniataExpectChannelInterrupt (IN struct _HW_CHANNEL *chan, IN BOOLEAN Expecting)
 
ULONG NTAPI AtapiRegCheckDevValue (IN PVOID HwDeviceExtension, IN ULONG chan, IN ULONG dev, IN PCWSTR Name, IN ULONG Default)
 
ULONG NTAPI AtapiRegCheckParameterValue (IN PVOID HwDeviceExtension, IN PCWSTR PathSuffix, IN PCWSTR Name, IN ULONG Default)
 
VOID _cdecl _PrintNtConsole (PCCH DebugMessage,...)
 
VOID NTAPI UniataInitMapBM (IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN struct _IDE_BUSMASTER_REGISTERS *BaseIoAddressBM_0, IN BOOLEAN MemIo)
 
VOID NTAPI UniataInitMapBase (IN struct _HW_CHANNEL *chan, IN PIDE_REGISTERS_1 BaseIoAddress1, IN PIDE_REGISTERS_2 BaseIoAddress2)
 
VOID NTAPI UniataInitSyncBaseIO (IN struct _HW_CHANNEL *chan)
 
VOID UniataInitIoRes (IN struct _HW_CHANNEL *chan, IN ULONG idx, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)
 
VOID UniataInitIoResEx (IN struct _IORES *IoRes, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)
 
UCHAR DDKFASTAPI UniataIsIdle (IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN UCHAR Status)
 
VOID NTAPI UniataDumpATARegs (IN struct _HW_CHANNEL *chan)
 
ULONG NTAPI EncodeVendorStr (OUT PWCHAR Buffer, IN PUCHAR Str, IN ULONG Length)
 
ULONGLONG NTAPI UniAtaCalculateLBARegsBack (struct _HW_LU_EXTENSION *LunExt, ULONGLONG lba)
 
ULONG NTAPI UniataAnybodyHome (IN PVOID HwDeviceExtension, IN ULONG Channel, IN ULONG deviceNumber)
 
__inline BOOLEAN ata_is_sata (PIDENTIFY_DATA ident)
 
__inline LONG ata_cur_mode_from_ident (PIDENTIFY_DATA ident, BOOLEAN Active)
 

Variables

ULONG g_LogToDisplay
 
UCHAR const AtaCommands48 [256]
 
UCHAR const AtaCommandFlags [256]
 

Macro Definition Documentation

◆ AdvancedPIOModes_3

#define AdvancedPIOModes_3   1

Definition at line 726 of file atapi.h.

◆ AdvancedPIOModes_4

#define AdvancedPIOModes_4   2

Definition at line 727 of file atapi.h.

◆ AdvancedPIOModes_5

#define AdvancedPIOModes_5   4

Definition at line 728 of file atapi.h.

◆ ATA_AT_HOME_ATAPI

#define ATA_AT_HOME_ATAPI   0x02

Definition at line 1593 of file atapi.h.

◆ ATA_AT_HOME_HDD

#define ATA_AT_HOME_HDD   0x01

Definition at line 1592 of file atapi.h.

◆ ATA_AT_HOME_NOBODY

#define ATA_AT_HOME_NOBODY   0x00

Definition at line 1595 of file atapi.h.

◆ ATA_AT_HOME_XXX

#define ATA_AT_HOME_XXX   0x04

Definition at line 1594 of file atapi.h.

◆ ATA_BT_DUALPORTMULTI

#define ATA_BT_DUALPORTMULTI   2 /* 2 port, mult sector buffer */

Definition at line 642 of file atapi.h.

◆ ATA_BT_DUALPORTMULTICACHE

#define ATA_BT_DUALPORTMULTICACHE   3 /* above plus track cache */

Definition at line 643 of file atapi.h.

◆ ATA_BT_SINGLEPORTSECTOR

#define ATA_BT_SINGLEPORTSECTOR   1 /* 1 port, 1 sector buffer */

Definition at line 641 of file atapi.h.

◆ ATA_C_F_AAM_CNT_MAX_PERF

#define ATA_C_F_AAM_CNT_MAX_PERF   0xfe /* maximum performance */

Definition at line 586 of file atapi.h.

◆ ATA_C_F_AAM_CNT_MAX_POWER_SAVE

#define ATA_C_F_AAM_CNT_MAX_POWER_SAVE   0x80 /* min. power */

Definition at line 587 of file atapi.h.

◆ ATA_C_F_APM_CNT_MAX_PERF

#define ATA_C_F_APM_CNT_MAX_PERF   0xfe /* maximum performance */

Definition at line 580 of file atapi.h.

◆ ATA_C_F_APM_CNT_MIN_NO_STANDBY

#define ATA_C_F_APM_CNT_MIN_NO_STANDBY   0x80 /* min. power w/o standby */

Definition at line 581 of file atapi.h.

◆ ATA_C_F_APM_CNT_MIN_STANDBY

#define ATA_C_F_APM_CNT_MIN_STANDBY   0x01 /* min. power with standby */

Definition at line 582 of file atapi.h.

◆ ATA_C_F_DIS_ACOUSTIC

#define ATA_C_F_DIS_ACOUSTIC   0xc2 /* disable acoustic management */

Definition at line 585 of file atapi.h.

◆ ATA_C_F_DIS_APM

#define ATA_C_F_DIS_APM   0x85 /* disable advanced power management */

Definition at line 579 of file atapi.h.

◆ ATA_C_F_DIS_MEDIASTAT

#define ATA_C_F_DIS_MEDIASTAT   0x31 /* disable media status */

Definition at line 576 of file atapi.h.

◆ ATA_C_F_DIS_RCACHE

#define ATA_C_F_DIS_RCACHE   0x55 /* disable readahead cache */

Definition at line 567 of file atapi.h.

◆ ATA_C_F_DIS_RELIRQ

#define ATA_C_F_DIS_RELIRQ   0xdd /* disable release interrupt */

Definition at line 570 of file atapi.h.

◆ ATA_C_F_DIS_SRVIRQ

#define ATA_C_F_DIS_SRVIRQ   0xde /* disable service interrupt */

Definition at line 573 of file atapi.h.

◆ ATA_C_F_DIS_WCACHE

#define ATA_C_F_DIS_WCACHE   0x82 /* disable write cache */

Definition at line 564 of file atapi.h.

◆ ATA_C_F_ENAB_ACOUSTIC

#define ATA_C_F_ENAB_ACOUSTIC   0x42 /* enable acoustic management */

Definition at line 584 of file atapi.h.

◆ ATA_C_F_ENAB_APM

#define ATA_C_F_ENAB_APM   0x05 /* enable advanced power management */

Definition at line 578 of file atapi.h.

◆ ATA_C_F_ENAB_MEDIASTAT

#define ATA_C_F_ENAB_MEDIASTAT   0x95 /* enable media status */

Definition at line 575 of file atapi.h.

◆ ATA_C_F_ENAB_RCACHE

#define ATA_C_F_ENAB_RCACHE   0xaa /* enable readahead cache */

Definition at line 566 of file atapi.h.

◆ ATA_C_F_ENAB_RELIRQ

#define ATA_C_F_ENAB_RELIRQ   0x5d /* enable release interrupt */

Definition at line 569 of file atapi.h.

◆ ATA_C_F_ENAB_SRVIRQ

#define ATA_C_F_ENAB_SRVIRQ   0x5e /* enable service interrupt */

Definition at line 572 of file atapi.h.

◆ ATA_C_F_ENAB_WCACHE

#define ATA_C_F_ENAB_WCACHE   0x02 /* enable write cache */

Definition at line 563 of file atapi.h.

◆ ATA_C_F_SETXFER

#define ATA_C_F_SETXFER   0x03 /* set transfer mode */

Definition at line 561 of file atapi.h.

◆ ATA_ChecksumValid

#define ATA_ChecksumValid   0xA5

Definition at line 978 of file atapi.h.

◆ ATA_CMD_FLAG_48

#define ATA_CMD_FLAG_48   0x04

Definition at line 1599 of file atapi.h.

◆ ATA_CMD_FLAG_48supp

#define ATA_CMD_FLAG_48supp   0x02

Definition at line 1598 of file atapi.h.

◆ ATA_CMD_FLAG_DMA

#define ATA_CMD_FLAG_DMA   0x08

Definition at line 1600 of file atapi.h.

◆ ATA_CMD_FLAG_FUA

#define ATA_CMD_FLAG_FUA   0x10

Definition at line 1601 of file atapi.h.

◆ ATA_CMD_FLAG_In

#define ATA_CMD_FLAG_In   0x40

Definition at line 1602 of file atapi.h.

◆ ATA_CMD_FLAG_LBAIOsupp

#define ATA_CMD_FLAG_LBAIOsupp   0x01

Definition at line 1597 of file atapi.h.

◆ ATA_CMD_FLAG_Out

#define ATA_CMD_FLAG_Out   0x80

Definition at line 1603 of file atapi.h.

◆ ATA_DMA

#define ATA_DMA   0x10

Definition at line 316 of file atapi.h.

◆ ATA_F_DMA

#define ATA_F_DMA   0x01 /* enable DMA */

Definition at line 557 of file atapi.h.

◆ ATA_F_DMAREAD

#define ATA_F_DMAREAD   0x04 /* DMA Packet (ATAPI) read */

Definition at line 559 of file atapi.h.

◆ ATA_F_OVL

#define ATA_F_OVL   0x02 /* enable overlap */

Definition at line 558 of file atapi.h.

◆ ATA_I_CMD

#define ATA_I_CMD   0x01 /* cmd (1) | data (0) */

Definition at line 601 of file atapi.h.

◆ ATA_I_IN

#define ATA_I_IN   0x02 /* read (1) | write (0) */

Definition at line 602 of file atapi.h.

◆ ATA_I_RELEASE

#define ATA_I_RELEASE   0x04 /* released bus (1) */

Definition at line 603 of file atapi.h.

◆ ATA_I_TAGMASK

#define ATA_I_TAGMASK   0xf8 /* tag mask */

Definition at line 604 of file atapi.h.

◆ ATA_MODE_NOT_SPEC

#define ATA_MODE_NOT_SPEC   ((ULONG)(-1)) /*0x82*/

Definition at line 341 of file atapi.h.

◆ ATA_PIO

#define ATA_PIO   0x00

Definition at line 306 of file atapi.h.

◆ ATA_PIO0

#define ATA_PIO0   0x08

Definition at line 309 of file atapi.h.

◆ ATA_PIO1

#define ATA_PIO1   0x09

Definition at line 310 of file atapi.h.

◆ ATA_PIO2

#define ATA_PIO2   0x0a

Definition at line 311 of file atapi.h.

◆ ATA_PIO3

#define ATA_PIO3   0x0b

Definition at line 312 of file atapi.h.

◆ ATA_PIO4

#define ATA_PIO4   0x0c

Definition at line 313 of file atapi.h.

◆ ATA_PIO5

#define ATA_PIO5   0x0d

Definition at line 314 of file atapi.h.

◆ ATA_PIO_NRDY

#define ATA_PIO_NRDY   0x01

Definition at line 307 of file atapi.h.

◆ ATA_SA150

#define ATA_SA150   0x47 /*0x80*/

Definition at line 337 of file atapi.h.

◆ ATA_SA300

#define ATA_SA300   0x48 /*0x81*/

Definition at line 338 of file atapi.h.

◆ ATA_SA600

#define ATA_SA600   0x49 /*0x82*/

Definition at line 339 of file atapi.h.

◆ ATA_SATA_GEN1

#define ATA_SATA_GEN1   0x0002

Definition at line 757 of file atapi.h.

◆ ATA_SATA_GEN2

#define ATA_SATA_GEN2   0x0004

Definition at line 758 of file atapi.h.

◆ ATA_SATA_GEN3

#define ATA_SATA_GEN3   0x0008

Definition at line 759 of file atapi.h.

◆ ATA_SDMA

#define ATA_SDMA   0x10

Definition at line 317 of file atapi.h.

◆ ATA_SDMA0

#define ATA_SDMA0   0x10

Definition at line 318 of file atapi.h.

◆ ATA_SDMA1

#define ATA_SDMA1   0x11

Definition at line 319 of file atapi.h.

◆ ATA_SDMA2

#define ATA_SDMA2   0x12

Definition at line 320 of file atapi.h.

◆ ATA_SUPPORT_AUTOACTIVATE

#define ATA_SUPPORT_AUTOACTIVATE   0x0004

Definition at line 770 of file atapi.h.

◆ ATA_SUPPORT_IFPWRMNGT

#define ATA_SUPPORT_IFPWRMNGT   0x0008

Definition at line 771 of file atapi.h.

◆ ATA_SUPPORT_IFPWRMNGTRCV

#define ATA_SUPPORT_IFPWRMNGTRCV   0x0200

Definition at line 761 of file atapi.h.

◆ ATA_SUPPORT_INORDERDATA

#define ATA_SUPPORT_INORDERDATA   0x0010

Definition at line 772 of file atapi.h.

◆ ATA_SUPPORT_NCQ

#define ATA_SUPPORT_NCQ   0x0100

Definition at line 760 of file atapi.h.

◆ ATA_SUPPORT_NCQ_PRI_INFO

#define ATA_SUPPORT_NCQ_PRI_INFO   0x1000

Definition at line 764 of file atapi.h.

◆ ATA_SUPPORT_NCQ_UNLOAD

#define ATA_SUPPORT_NCQ_UNLOAD   0x0800

Definition at line 763 of file atapi.h.

◆ ATA_SUPPORT_NONZERO

#define ATA_SUPPORT_NONZERO   0x0002

Definition at line 769 of file atapi.h.

◆ ATA_SUPPORT_PHY_EVENT_COUNTER

#define ATA_SUPPORT_PHY_EVENT_COUNTER   0x0400

Definition at line 762 of file atapi.h.

◆ ATA_UDMA

#define ATA_UDMA   0x40

Definition at line 327 of file atapi.h.

◆ ATA_UDMA0

#define ATA_UDMA0   0x40

Definition at line 328 of file atapi.h.

◆ ATA_UDMA1

#define ATA_UDMA1   0x41

Definition at line 329 of file atapi.h.

◆ ATA_UDMA2

#define ATA_UDMA2   0x42

Definition at line 330 of file atapi.h.

◆ ATA_UDMA3

#define ATA_UDMA3   0x43

Definition at line 331 of file atapi.h.

◆ ATA_UDMA4

#define ATA_UDMA4   0x44

Definition at line 332 of file atapi.h.

◆ ATA_UDMA5

#define ATA_UDMA5   0x45

Definition at line 333 of file atapi.h.

◆ ATA_UDMA6

#define ATA_UDMA6   0x46

Definition at line 334 of file atapi.h.

◆ ATA_VER_MJ_ATA4

#define ATA_VER_MJ_ATA4   0x0010

Definition at line 778 of file atapi.h.

◆ ATA_VER_MJ_ATA5

#define ATA_VER_MJ_ATA5   0x0020

Definition at line 779 of file atapi.h.

◆ ATA_VER_MJ_ATA6

#define ATA_VER_MJ_ATA6   0x0040

Definition at line 780 of file atapi.h.

◆ ATA_VER_MJ_ATA7

#define ATA_VER_MJ_ATA7   0x0080

Definition at line 781 of file atapi.h.

◆ ATA_VER_MJ_ATA8_ASC

#define ATA_VER_MJ_ATA8_ASC   0x0100

Definition at line 782 of file atapi.h.

◆ ATA_WDMA

#define ATA_WDMA   0x20

Definition at line 322 of file atapi.h.

◆ ATA_WDMA0

#define ATA_WDMA0   0x20

Definition at line 323 of file atapi.h.

◆ ATA_WDMA1

#define ATA_WDMA1   0x21

Definition at line 324 of file atapi.h.

◆ ATA_WDMA2

#define ATA_WDMA2   0x22

Definition at line 325 of file atapi.h.

◆ ATAPI_DEVICE

#define ATAPI_DEVICE (   chan,
  dev 
)    ((chan->lun[dev]->DeviceFlags & DFLAGS_ATAPI_DEVICE) ? TRUE : FALSE)

Definition at line 1624 of file atapi.h.

◆ ATAPI_DRQT_ACCEL

#define ATAPI_DRQT_ACCEL   2 /* accel 50 us delay */

Definition at line 617 of file atapi.h.

◆ ATAPI_DRQT_INTR

#define ATAPI_DRQT_INTR   1 /* intr 10 ms delay */

Definition at line 616 of file atapi.h.

◆ ATAPI_DRQT_MPROC

#define ATAPI_DRQT_MPROC   0 /* cpu 3 ms delay */

Definition at line 615 of file atapi.h.

◆ ATAPI_FORMAT_UNIT

#define ATAPI_FORMAT_UNIT   0x24

Definition at line 270 of file atapi.h.

◆ ATAPI_IR_COD

#define ATAPI_IR_COD   0x01

Definition at line 543 of file atapi.h.

◆ ATAPI_IR_COD_Cmd

#define ATAPI_IR_COD_Cmd   0x1

Definition at line 545 of file atapi.h.

◆ ATAPI_IR_COD_Data

#define ATAPI_IR_COD_Data   0x0

Definition at line 544 of file atapi.h.

◆ ATAPI_IR_IO

#define ATAPI_IR_IO   0x02

Definition at line 547 of file atapi.h.

◆ ATAPI_IR_IO_toDev

#define ATAPI_IR_IO_toDev   0x00

Definition at line 548 of file atapi.h.

◆ ATAPI_IR_IO_toHost

#define ATAPI_IR_IO_toHost   0x02

Definition at line 549 of file atapi.h.

◆ ATAPI_IR_Mask

#define ATAPI_IR_Mask   0x03

Definition at line 551 of file atapi.h.

◆ ATAPI_MODE_SELECT

#define ATAPI_MODE_SELECT   0x55

Definition at line 269 of file atapi.h.

◆ ATAPI_MODE_SENSE

#define ATAPI_MODE_SENSE   0x5A

Definition at line 268 of file atapi.h.

◆ ATAPI_PROTO_ATAPI

#define ATAPI_PROTO_ATAPI   2

Definition at line 627 of file atapi.h.

◆ ATAPI_PSIZE_12

#define ATAPI_PSIZE_12   0 /* 12 bytes */

Definition at line 611 of file atapi.h.

◆ ATAPI_PSIZE_16

#define ATAPI_PSIZE_16   1 /* 16 bytes */

Definition at line 612 of file atapi.h.

◆ ATAPI_TYPE_CDROM

#define ATAPI_TYPE_CDROM   5 /* CD-ROM device */

Definition at line 623 of file atapi.h.

◆ ATAPI_TYPE_DIRECT

#define ATAPI_TYPE_DIRECT   0 /* disk/floppy */

Definition at line 621 of file atapi.h.

◆ ATAPI_TYPE_OPTICAL

#define ATAPI_TYPE_OPTICAL   7 /* optical disk */

Definition at line 624 of file atapi.h.

◆ ATAPI_TYPE_TAPE

#define ATAPI_TYPE_TAPE   1 /* streaming tape */

Definition at line 622 of file atapi.h.

◆ AtapiCopyMemory

#define AtapiCopyMemory   RtlCopyMemory

Definition at line 1247 of file atapi.h.

◆ AtapiStallExecution

#define AtapiStallExecution (   dt)    ScsiPortStallExecution(dt)

Definition at line 158 of file atapi.h.

◆ AtapiStringCmp

#define AtapiStringCmp (   s1,
  s2,
  n 
)    _strnicmp(s1, s2, n)

Definition at line 1256 of file atapi.h.

◆ AUTO_OFFLINE

#define AUTO_OFFLINE   0xDB

Definition at line 594 of file atapi.h.

◆ CHAN_NOT_SPECIFIED

#define CHAN_NOT_SPECIFIED   (0xffffffffL)

Definition at line 1481 of file atapi.h.

◆ CHAN_NOT_SPECIFIED_CHECK_CABLE

#define CHAN_NOT_SPECIFIED_CHECK_CABLE   (0xfffffffeL)

Definition at line 1482 of file atapi.h.

◆ Connect_DbgPrint

#define Connect_DbgPrint ( )    {;}

Definition at line 156 of file atapi.h.

◆ DEVNUM_NOT_SPECIFIED

#define DEVNUM_NOT_SPECIFIED   (0xffffffffL)

Definition at line 1483 of file atapi.h.

◆ DFLAGS_ATAPI_CHANGER

#define DFLAGS_ATAPI_CHANGER   0x0040

Definition at line 244 of file atapi.h.

◆ DFLAGS_ATAPI_DEVICE

#define DFLAGS_ATAPI_DEVICE   0x0002

Definition at line 237 of file atapi.h.

◆ DFLAGS_CHANGER_INITED

#define DFLAGS_CHANGER_INITED   0x0100

Definition at line 246 of file atapi.h.

◆ DFLAGS_DEVICE_PRESENT

#define DFLAGS_DEVICE_PRESENT   0x0001

Definition at line 236 of file atapi.h.

◆ DFLAGS_DWORDIO_ENABLED

#define DFLAGS_DWORDIO_ENABLED   0x0400

Definition at line 248 of file atapi.h.

◆ DFLAGS_HIDDEN

#define DFLAGS_HIDDEN   0x8000

Definition at line 253 of file atapi.h.

◆ DFLAGS_INT_DRQ

#define DFLAGS_INT_DRQ   0x0008

Definition at line 239 of file atapi.h.

◆ DFLAGS_LBA32plus

#define DFLAGS_LBA32plus   0x20000

Definition at line 256 of file atapi.h.

◆ DFLAGS_LBA_ENABLED

#define DFLAGS_LBA_ENABLED   0x0200

Definition at line 247 of file atapi.h.

◆ DFLAGS_MANUAL_CHS

#define DFLAGS_MANUAL_CHS   0x10000

Definition at line 255 of file atapi.h.

◆ DFLAGS_MEDIA_STATUS_ENABLED

#define DFLAGS_MEDIA_STATUS_ENABLED   0x0020

Definition at line 243 of file atapi.h.

◆ DFLAGS_ORIG_GEOMETRY

#define DFLAGS_ORIG_GEOMETRY   0x2000

Definition at line 251 of file atapi.h.

◆ DFLAGS_RCACHE_ENABLED

#define DFLAGS_RCACHE_ENABLED   0x1000

Definition at line 250 of file atapi.h.

◆ DFLAGS_REINIT_DMA

#define DFLAGS_REINIT_DMA   0x4000

Definition at line 252 of file atapi.h.

◆ DFLAGS_REMOVABLE_DRIVE

#define DFLAGS_REMOVABLE_DRIVE   0x0010

Definition at line 241 of file atapi.h.

◆ DFLAGS_SANYO_ATAPI_CHANGER

#define DFLAGS_SANYO_ATAPI_CHANGER   0x0080

Definition at line 245 of file atapi.h.

◆ DFLAGS_TAPE_DEVICE

#define DFLAGS_TAPE_DEVICE   0x0004

Definition at line 238 of file atapi.h.

◆ DFLAGS_WCACHE_ENABLED

#define DFLAGS_WCACHE_ENABLED   0x0800

Definition at line 249 of file atapi.h.

◆ GetBaseStatus

#define GetBaseStatus (   chan,
  pStatus 
)     pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status);

Definition at line 1092 of file atapi.h.

◆ GetStatus

#define GetStatus (   chan,
  Status 
)     Status = AtapiReadPort1(chan, IDX_IO2_AltStatus);

Definition at line 1089 of file atapi.h.

◆ IDE_COMMAND_ATAPI_IDENTIFY

#define IDE_COMMAND_ATAPI_IDENTIFY   0xA1

Definition at line 383 of file atapi.h.

◆ IDE_COMMAND_ATAPI_PACKET

#define IDE_COMMAND_ATAPI_PACKET   0xA0

Definition at line 382 of file atapi.h.

◆ IDE_COMMAND_ATAPI_RESET

#define IDE_COMMAND_ATAPI_RESET   0x08

Definition at line 348 of file atapi.h.

◆ IDE_COMMAND_DATA_SET_MGMT

#define IDE_COMMAND_DATA_SET_MGMT   0x06

Definition at line 347 of file atapi.h.

◆ IDE_COMMAND_DOOR_LOCK

#define IDE_COMMAND_DOOR_LOCK   0xDE

Definition at line 393 of file atapi.h.

◆ IDE_COMMAND_DOOR_UNLOCK

#define IDE_COMMAND_DOOR_UNLOCK   0xDF

Definition at line 394 of file atapi.h.

◆ IDE_COMMAND_ENABLE_MEDIA_STATUS

#define IDE_COMMAND_ENABLE_MEDIA_STATUS   0xEF

Definition at line 406 of file atapi.h.

◆ IDE_COMMAND_FLUSH_CACHE

#define IDE_COMMAND_FLUSH_CACHE   0xE7

Definition at line 401 of file atapi.h.

◆ IDE_COMMAND_FLUSH_CACHE48

#define IDE_COMMAND_FLUSH_CACHE48   0xEA

Definition at line 405 of file atapi.h.

◆ IDE_COMMAND_GET_MEDIA_STATUS

#define IDE_COMMAND_GET_MEDIA_STATUS   0xDA

Definition at line 392 of file atapi.h.

◆ IDE_COMMAND_IDENTIFY

#define IDE_COMMAND_IDENTIFY   0xEC

Definition at line 403 of file atapi.h.

◆ IDE_COMMAND_IDLE

#define IDE_COMMAND_IDLE   0xE3

Definition at line 398 of file atapi.h.

◆ IDE_COMMAND_IDLE_IMMED

#define IDE_COMMAND_IDLE_IMMED   0xE1

Definition at line 396 of file atapi.h.

◆ IDE_COMMAND_MEDIA_EJECT

#define IDE_COMMAND_MEDIA_EJECT   0xED

Definition at line 404 of file atapi.h.

◆ IDE_COMMAND_READ

#define IDE_COMMAND_READ   0x20

Definition at line 350 of file atapi.h.

◆ IDE_COMMAND_READ48

#define IDE_COMMAND_READ48   0x24

Definition at line 352 of file atapi.h.

◆ IDE_COMMAND_READ_DMA

#define IDE_COMMAND_READ_DMA   0xC8

Definition at line 388 of file atapi.h.

◆ IDE_COMMAND_READ_DMA48

#define IDE_COMMAND_READ_DMA48   0x25

Definition at line 353 of file atapi.h.

◆ IDE_COMMAND_READ_DMA_Q

#define IDE_COMMAND_READ_DMA_Q   0xC7

Definition at line 387 of file atapi.h.

◆ IDE_COMMAND_READ_DMA_Q48

#define IDE_COMMAND_READ_DMA_Q48   0x26

Definition at line 354 of file atapi.h.

◆ IDE_COMMAND_READ_LOG48

#define IDE_COMMAND_READ_LOG48   0x2f

Definition at line 359 of file atapi.h.

◆ IDE_COMMAND_READ_LOG_DMA48

#define IDE_COMMAND_READ_LOG_DMA48   0x47

Definition at line 374 of file atapi.h.

◆ IDE_COMMAND_READ_MUL48

#define IDE_COMMAND_READ_MUL48   0x29

Definition at line 356 of file atapi.h.

◆ IDE_COMMAND_READ_MULTIPLE

#define IDE_COMMAND_READ_MULTIPLE   0xC4

Definition at line 384 of file atapi.h.

◆ IDE_COMMAND_READ_NATIVE_SIZE

#define IDE_COMMAND_READ_NATIVE_SIZE   0xF8

Definition at line 408 of file atapi.h.

◆ IDE_COMMAND_READ_NATIVE_SIZE48

#define IDE_COMMAND_READ_NATIVE_SIZE48   0x27

Definition at line 355 of file atapi.h.

◆ IDE_COMMAND_READ_NO_RETR

#define IDE_COMMAND_READ_NO_RETR   0x21

Definition at line 351 of file atapi.h.

◆ IDE_COMMAND_READ_PM

#define IDE_COMMAND_READ_PM   0xE4

Definition at line 399 of file atapi.h.

◆ IDE_COMMAND_READ_STREAM48

#define IDE_COMMAND_READ_STREAM48   0x2B

Definition at line 358 of file atapi.h.

◆ IDE_COMMAND_READ_STREAM_DMA48

#define IDE_COMMAND_READ_STREAM_DMA48   0x2A

Definition at line 357 of file atapi.h.

◆ IDE_COMMAND_RECALIBRATE

#define IDE_COMMAND_RECALIBRATE   0x10

Definition at line 349 of file atapi.h.

◆ IDE_COMMAND_SEEK

#define IDE_COMMAND_SEEK   0x70

Definition at line 380 of file atapi.h.

◆ IDE_COMMAND_SET_DRIVE_PARAMETERS

#define IDE_COMMAND_SET_DRIVE_PARAMETERS   0x91

Definition at line 381 of file atapi.h.

◆ IDE_COMMAND_SET_FEATURES

#define IDE_COMMAND_SET_FEATURES
Value:
0xEF /* features command,
IDE_COMMAND_ENABLE_MEDIA_STATUS */

Definition at line 407 of file atapi.h.

◆ IDE_COMMAND_SET_MULTIPLE

#define IDE_COMMAND_SET_MULTIPLE   0xC6

Definition at line 386 of file atapi.h.

◆ IDE_COMMAND_SET_NATIVE_SIZE

#define IDE_COMMAND_SET_NATIVE_SIZE   0xF9

Definition at line 409 of file atapi.h.

◆ IDE_COMMAND_SET_NATIVE_SIZE48

#define IDE_COMMAND_SET_NATIVE_SIZE48   0x37

Definition at line 365 of file atapi.h.

◆ IDE_COMMAND_SLEEP

#define IDE_COMMAND_SLEEP   0xE6

Definition at line 400 of file atapi.h.

◆ IDE_COMMAND_STANDBY

#define IDE_COMMAND_STANDBY   0xE2

Definition at line 397 of file atapi.h.

◆ IDE_COMMAND_STANDBY_IMMED

#define IDE_COMMAND_STANDBY_IMMED   0xE0

Definition at line 395 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_RCV

#define IDE_COMMAND_TRUSTED_RCV   0x5c

Definition at line 376 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_RCV_DMA

#define IDE_COMMAND_TRUSTED_RCV_DMA   0x5d

Definition at line 377 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_SEND

#define IDE_COMMAND_TRUSTED_SEND   0x5e

Definition at line 378 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_SEND_DMA

#define IDE_COMMAND_TRUSTED_SEND_DMA   0x5f

Definition at line 379 of file atapi.h.

◆ IDE_COMMAND_VERIFY

#define IDE_COMMAND_VERIFY   0x40

Definition at line 372 of file atapi.h.

◆ IDE_COMMAND_VERIFY48

#define IDE_COMMAND_VERIFY48   0x42

Definition at line 373 of file atapi.h.

◆ IDE_COMMAND_WRITE

#define IDE_COMMAND_WRITE   0x30

Definition at line 360 of file atapi.h.

◆ IDE_COMMAND_WRITE48

#define IDE_COMMAND_WRITE48   0x34

Definition at line 362 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA

#define IDE_COMMAND_WRITE_DMA   0xCA

Definition at line 389 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA48

#define IDE_COMMAND_WRITE_DMA48   0x35

Definition at line 363 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA_Q

#define IDE_COMMAND_WRITE_DMA_Q   0xCC

Definition at line 390 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA_Q48

#define IDE_COMMAND_WRITE_DMA_Q48   0x36

Definition at line 364 of file atapi.h.

◆ IDE_COMMAND_WRITE_FUA_DMA48

#define IDE_COMMAND_WRITE_FUA_DMA48   0x3d

Definition at line 369 of file atapi.h.

◆ IDE_COMMAND_WRITE_FUA_DMA_Q48

#define IDE_COMMAND_WRITE_FUA_DMA_Q48   0x3e

Definition at line 370 of file atapi.h.

◆ IDE_COMMAND_WRITE_LOG48

#define IDE_COMMAND_WRITE_LOG48   0x3f

Definition at line 371 of file atapi.h.

◆ IDE_COMMAND_WRITE_LOG_DMA48

#define IDE_COMMAND_WRITE_LOG_DMA48   0x57

Definition at line 375 of file atapi.h.

◆ IDE_COMMAND_WRITE_MUL48

#define IDE_COMMAND_WRITE_MUL48   0x39

Definition at line 366 of file atapi.h.

◆ IDE_COMMAND_WRITE_MUL_FUA48

#define IDE_COMMAND_WRITE_MUL_FUA48   0xCE

Definition at line 391 of file atapi.h.

◆ IDE_COMMAND_WRITE_MULTIPLE

#define IDE_COMMAND_WRITE_MULTIPLE   0xC5

Definition at line 385 of file atapi.h.

◆ IDE_COMMAND_WRITE_NO_RETR

#define IDE_COMMAND_WRITE_NO_RETR   0x31

Definition at line 361 of file atapi.h.

◆ IDE_COMMAND_WRITE_PM

#define IDE_COMMAND_WRITE_PM   0xE8

Definition at line 402 of file atapi.h.

◆ IDE_COMMAND_WRITE_STREAM48

#define IDE_COMMAND_WRITE_STREAM48   0x3b

Definition at line 368 of file atapi.h.

◆ IDE_COMMAND_WRITE_STREAM_DMA48

#define IDE_COMMAND_WRITE_STREAM_DMA48   0x3a

Definition at line 367 of file atapi.h.

◆ IDE_DC_A_4BIT

#define IDE_DC_A_4BIT   0x80

Definition at line 453 of file atapi.h.

◆ IDE_DC_DISABLE_INTERRUPTS

#define IDE_DC_DISABLE_INTERRUPTS   0x02

Definition at line 451 of file atapi.h.

◆ IDE_DC_REENABLE_CONTROLLER

#define IDE_DC_REENABLE_CONTROLLER   0x00

Definition at line 455 of file atapi.h.

◆ IDE_DC_RESET_CONTROLLER

#define IDE_DC_RESET_CONTROLLER   0x04

Definition at line 452 of file atapi.h.

◆ IDE_DC_USE_HOB

#define IDE_DC_USE_HOB   0x80

Definition at line 454 of file atapi.h.

◆ IDE_DRIVE_1

#define IDE_DRIVE_1   0x00

Definition at line 439 of file atapi.h.

◆ IDE_DRIVE_2

#define IDE_DRIVE_2   0x10

Definition at line 440 of file atapi.h.

◆ IDE_DRIVE_MASK

#define IDE_DRIVE_MASK   (IDE_DRIVE_SELECT_1 | IDE_DRIVE_SELECT_2)

Definition at line 443 of file atapi.h.

◆ IDE_DRIVE_SELECT

#define IDE_DRIVE_SELECT   0xA0

Definition at line 438 of file atapi.h.

◆ IDE_DRIVE_SELECT_1

#define IDE_DRIVE_SELECT_1   (IDE_DRIVE_SELECT | IDE_DRIVE_1)

Definition at line 441 of file atapi.h.

◆ IDE_DRIVE_SELECT_2

#define IDE_DRIVE_SELECT_2   (IDE_DRIVE_SELECT | IDE_DRIVE_2)

Definition at line 442 of file atapi.h.

◆ IDE_ERROR_BAD_BLOCK

#define IDE_ERROR_BAD_BLOCK   0x80

Definition at line 461 of file atapi.h.

◆ IDE_ERROR_COMMAND_ABORTED

#define IDE_ERROR_COMMAND_ABORTED   0x04

Definition at line 466 of file atapi.h.

◆ IDE_ERROR_DATA_ERROR

#define IDE_ERROR_DATA_ERROR   0x40

Definition at line 462 of file atapi.h.

◆ IDE_ERROR_END_OF_MEDIA

#define IDE_ERROR_END_OF_MEDIA   0x02

Definition at line 467 of file atapi.h.

◆ IDE_ERROR_ICRC

#define IDE_ERROR_ICRC   0x80

Definition at line 460 of file atapi.h.

◆ IDE_ERROR_ID_NOT_FOUND

#define IDE_ERROR_ID_NOT_FOUND   0x10

Definition at line 464 of file atapi.h.

◆ IDE_ERROR_ILLEGAL_LENGTH

#define IDE_ERROR_ILLEGAL_LENGTH   0x01

Definition at line 469 of file atapi.h.

◆ IDE_ERROR_MEDIA_CHANGE

#define IDE_ERROR_MEDIA_CHANGE   0x20

Definition at line 463 of file atapi.h.

◆ IDE_ERROR_MEDIA_CHANGE_REQ

#define IDE_ERROR_MEDIA_CHANGE_REQ   0x08

Definition at line 465 of file atapi.h.

◆ IDE_ERROR_NO_MEDIA

#define IDE_ERROR_NO_MEDIA   0x02

Definition at line 468 of file atapi.h.

◆ IDE_STATUS_BUSY

#define IDE_STATUS_BUSY   0x80

Definition at line 428 of file atapi.h.

◆ IDE_STATUS_CORRECTED_ERROR

#define IDE_STATUS_CORRECTED_ERROR   0x04

Definition at line 420 of file atapi.h.

◆ IDE_STATUS_DMA

#define IDE_STATUS_DMA   0x20 /* DMA ready */

Definition at line 424 of file atapi.h.

◆ IDE_STATUS_DRDY

#define IDE_STATUS_DRDY   0x40

Definition at line 426 of file atapi.h.

◆ IDE_STATUS_DRQ

#define IDE_STATUS_DRQ   0x08

Definition at line 421 of file atapi.h.

◆ IDE_STATUS_DSC

#define IDE_STATUS_DSC   0x10

Definition at line 422 of file atapi.h.

◆ IDE_STATUS_DWF

#define IDE_STATUS_DWF   0x20 /* drive write fault */

Definition at line 425 of file atapi.h.

◆ IDE_STATUS_ERROR

#define IDE_STATUS_ERROR   0x01

Definition at line 418 of file atapi.h.

◆ IDE_STATUS_IDLE

#define IDE_STATUS_IDLE   0x50

Definition at line 427 of file atapi.h.

◆ IDE_STATUS_INDEX

#define IDE_STATUS_INDEX   0x02

Definition at line 419 of file atapi.h.

◆ IDE_STATUS_MASK

#define IDE_STATUS_MASK   0xff

Definition at line 431 of file atapi.h.

◆ IDE_STATUS_SUCCESS

#define IDE_STATUS_SUCCESS   0x00

Definition at line 417 of file atapi.h.

◆ IDE_STATUS_WRONG

#define IDE_STATUS_WRONG   0xff

Definition at line 430 of file atapi.h.

◆ IDE_USE_LBA

#define IDE_USE_LBA   0x40

Definition at line 445 of file atapi.h.

◆ IDENT_MODE_ACTIVE

#define IDENT_MODE_ACTIVE   TRUE

Definition at line 1644 of file atapi.h.

◆ IDENT_MODE_MAX

#define IDENT_MODE_MAX   FALSE

Definition at line 1643 of file atapi.h.

◆ IDENTIFY_CABLE_ID_VALID

#define IDENTIFY_CABLE_ID_VALID   0x01

Definition at line 844 of file atapi.h.

◆ IDENTIFY_DATA2

Definition at line 989 of file atapi.h.

◆ IDENTIFY_DATA_SIZE

#define IDENTIFY_DATA_SIZE   sizeof(IDENTIFY_DATA)

Definition at line 1033 of file atapi.h.

◆ IDENTIFY_DMA_CYCLES_MODE_0

#define IDENTIFY_DMA_CYCLES_MODE_0   0x00

Definition at line 1037 of file atapi.h.

◆ IDENTIFY_DMA_CYCLES_MODE_1

#define IDENTIFY_DMA_CYCLES_MODE_1   0x01

Definition at line 1038 of file atapi.h.

◆ IDENTIFY_DMA_CYCLES_MODE_2

#define IDENTIFY_DMA_CYCLES_MODE_2   0x02

Definition at line 1039 of file atapi.h.

◆ IDX_ATAPI_IO1

#define IDX_ATAPI_IO1   IDX_IO1

Definition at line 502 of file atapi.h.

◆ IDX_ATAPI_IO1_i_ByteCountHigh

#define IDX_ATAPI_IO1_i_ByteCountHigh   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1)

Definition at line 510 of file atapi.h.

◆ IDX_ATAPI_IO1_i_ByteCountLow

#define IDX_ATAPI_IO1_i_ByteCountLow   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1)

Definition at line 509 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Data

#define IDX_ATAPI_IO1_i_Data   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1)

Definition at line 505 of file atapi.h.

◆ IDX_ATAPI_IO1_i_DriveSelect

#define IDX_ATAPI_IO1_i_DriveSelect   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1)

Definition at line 511 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Error

#define IDX_ATAPI_IO1_i_Error   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1)

Definition at line 506 of file atapi.h.

◆ IDX_ATAPI_IO1_i_InterruptReason

#define IDX_ATAPI_IO1_i_InterruptReason   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1)

Definition at line 507 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Status

#define IDX_ATAPI_IO1_i_Status   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1)

Definition at line 512 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Unused1

#define IDX_ATAPI_IO1_i_Unused1   (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1)

Definition at line 508 of file atapi.h.

◆ IDX_ATAPI_IO1_o_ByteCountHigh

#define IDX_ATAPI_IO1_o_ByteCountHigh   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1)

Definition at line 519 of file atapi.h.

◆ IDX_ATAPI_IO1_o_ByteCountLow

#define IDX_ATAPI_IO1_o_ByteCountLow   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1)

Definition at line 518 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Command

#define IDX_ATAPI_IO1_o_Command   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1)

Definition at line 521 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Data

#define IDX_ATAPI_IO1_o_Data   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1)

Definition at line 514 of file atapi.h.

◆ IDX_ATAPI_IO1_o_DriveSelect

#define IDX_ATAPI_IO1_o_DriveSelect   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1)

Definition at line 520 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Feature

#define IDX_ATAPI_IO1_o_Feature   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1)

Definition at line 515 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Unused0

#define IDX_ATAPI_IO1_o_Unused0   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1)

Definition at line 516 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Unused1

#define IDX_ATAPI_IO1_o_Unused1   (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1)

Definition at line 517 of file atapi.h.

◆ IDX_ATAPI_IO1_SZ

#define IDX_ATAPI_IO1_SZ   sizeof(ATAPI_REGISTERS_1)

Definition at line 503 of file atapi.h.

◆ IDX_IO1 [1/2]

#define IDX_IO1   0

Definition at line 194 of file atapi.h.

◆ IDX_IO1 [2/2]

#define IDX_IO1   0

Definition at line 194 of file atapi.h.

◆ IDX_IO1_i_BlockCount

#define IDX_IO1_i_BlockCount   (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1)

Definition at line 198 of file atapi.h.

◆ IDX_IO1_i_BlockNumber

#define IDX_IO1_i_BlockNumber   (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1)

Definition at line 199 of file atapi.h.

◆ IDX_IO1_i_CylinderHigh

#define IDX_IO1_i_CylinderHigh   (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1)

Definition at line 201 of file atapi.h.

◆ IDX_IO1_i_CylinderLow

#define IDX_IO1_i_CylinderLow   (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1)

Definition at line 200 of file atapi.h.

◆ IDX_IO1_i_Data

#define IDX_IO1_i_Data   (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1)

Definition at line 196 of file atapi.h.

◆ IDX_IO1_i_DriveSelect

#define IDX_IO1_i_DriveSelect   (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1)

Definition at line 202 of file atapi.h.

◆ IDX_IO1_i_Error

#define IDX_IO1_i_Error   (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1)

Definition at line 197 of file atapi.h.

◆ IDX_IO1_i_Status

#define IDX_IO1_i_Status   (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1)

Definition at line 203 of file atapi.h.

◆ IDX_IO1_o

#define IDX_IO1_o   IDX_IO1_SZ

Definition at line 205 of file atapi.h.

◆ IDX_IO1_o_BlockCount

#define IDX_IO1_o_BlockCount   (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o)

Definition at line 210 of file atapi.h.

◆ IDX_IO1_o_BlockNumber

#define IDX_IO1_o_BlockNumber   (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o)

Definition at line 211 of file atapi.h.

◆ IDX_IO1_o_Command

#define IDX_IO1_o_Command   (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o)

Definition at line 215 of file atapi.h.

◆ IDX_IO1_o_CylinderHigh

#define IDX_IO1_o_CylinderHigh   (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o)

Definition at line 213 of file atapi.h.

◆ IDX_IO1_o_CylinderLow

#define IDX_IO1_o_CylinderLow   (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o)

Definition at line 212 of file atapi.h.

◆ IDX_IO1_o_Data

#define IDX_IO1_o_Data   (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o)

Definition at line 208 of file atapi.h.

◆ IDX_IO1_o_DriveSelect

#define IDX_IO1_o_DriveSelect   (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o)

Definition at line 214 of file atapi.h.

◆ IDX_IO1_o_Feature

#define IDX_IO1_o_Feature   (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o)

Definition at line 209 of file atapi.h.

◆ IDX_IO1_o_SZ

#define IDX_IO1_o_SZ   sizeof(IDE_REGISTERS_1)

Definition at line 206 of file atapi.h.

◆ IDX_IO1_SZ [1/2]

#define IDX_IO1_SZ   sizeof(IDE_REGISTERS_1)

Definition at line 195 of file atapi.h.

◆ IDX_IO1_SZ [2/2]

#define IDX_IO1_SZ   sizeof(IDE_REGISTERS_1)

Definition at line 195 of file atapi.h.

◆ IDX_IO2

#define IDX_IO2   (IDX_IO1_o+IDX_IO1_o_SZ)

Definition at line 222 of file atapi.h.

◆ IDX_IO2_AltStatus

#define IDX_IO2_AltStatus   (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2)

Definition at line 225 of file atapi.h.

◆ IDX_IO2_o

#define IDX_IO2_o   (IDX_IO2+IDX_IO2_SZ)

Definition at line 228 of file atapi.h.

◆ IDX_IO2_o_Control

#define IDX_IO2_o_Control   (FIELD_OFFSET(IDE_REGISTERS_2, Control)+IDX_IO2_o)

Definition at line 231 of file atapi.h.

◆ IDX_IO2_o_SZ

#define IDX_IO2_o_SZ   sizeof(IDE_REGISTERS_2)

Definition at line 229 of file atapi.h.

◆ IDX_IO2_SZ

#define IDX_IO2_SZ   sizeof(IDE_REGISTERS_2)

Definition at line 223 of file atapi.h.

◆ INTERRUPT_REASON_IGNORE

#define INTERRUPT_REASON_IGNORE   0

Definition at line 1278 of file atapi.h.

◆ INTERRUPT_REASON_OUR

#define INTERRUPT_REASON_OUR   1

Definition at line 1279 of file atapi.h.

◆ INTERRUPT_REASON_UNEXPECTED

#define INTERRUPT_REASON_UNEXPECTED   2

Definition at line 1280 of file atapi.h.

◆ IOMODE_NOT_SPECIFIED

#define IOMODE_NOT_SPECIFIED   (0xffffffffL)

Definition at line 1484 of file atapi.h.

◆ IS_RDP

#define IS_RDP (   OperationCode)
Value:
((OperationCode == SCSIOP_ERASE)||\
(OperationCode == SCSIOP_LOAD_UNLOAD)||\
(OperationCode == SCSIOP_LOCATE)||\
(OperationCode == SCSIOP_REWIND) ||\
(OperationCode == SCSIOP_SPACE)||\
(OperationCode == SCSIOP_SEEK)||\
/* (OperationCode == SCSIOP_FORMAT_UNIT)||\
(OperationCode == SCSIOP_BLANK)||*/ \
(OperationCode == SCSIOP_WRITE_FILEMARKS))
#define SCSIOP_LOCATE
Definition: cdrw_hw.h:909
#define SCSIOP_REWIND
Definition: cdrw_hw.h:868
#define SCSIOP_SEEK
Definition: cdrw_hw.h:908
#define SCSIOP_WRITE_FILEMARKS
Definition: cdrw_hw.h:885
#define SCSIOP_ERASE
Definition: cdrw_hw.h:895
#define SCSIOP_SPACE
Definition: cdrw_hw.h:887
#define SCSIOP_LOAD_UNLOAD
Definition: cdrw_hw.h:899

Definition at line 1197 of file atapi.h.

◆ KdPrint

#define KdPrint (   _x_)    {;}

Definition at line 155 of file atapi.h.

◆ KdPrint2

#define KdPrint2 (   _x_)    {;}

Definition at line 154 of file atapi.h.

◆ KdPrint3

#define KdPrint3 (   _x_)    {;}

Definition at line 153 of file atapi.h.

◆ MAX_ERRORS

#define MAX_ERRORS   4

Definition at line 262 of file atapi.h.

◆ PIDENTIFY_DATA2

Definition at line 990 of file atapi.h.

◆ PRINT_PREFIX

#define PRINT_PREFIX   "UniATA: "

Definition at line 150 of file atapi.h.

◆ PrintNtConsole

#define PrintNtConsole (   x)    {;}

Definition at line 1629 of file atapi.h.

◆ READ_LOG_SECTOR

#define READ_LOG_SECTOR   0xD5

Definition at line 591 of file atapi.h.

◆ ReadBuffer

#define ReadBuffer (   chan,
  Buffer,
  Count,
  timing 
)
Value:
Buffer, \
Count, \
VOID DDKFASTAPI AtapiReadBuffer2(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
Definition: bufpool.h:45
int Count
Definition: noreturn.cpp:7
#define IDX_IO1_i_Data
Definition: atapi.h:196
static int timing
Definition: xmllint.c:163

Definition at line 1105 of file atapi.h.

◆ ReadBuffer2

#define ReadBuffer2 (   chan,
  Buffer,
  Count,
  timing 
)
Value:
Buffer, \
Count, \
VOID DDKFASTAPI AtapiReadBuffer4(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)

Definition at line 1117 of file atapi.h.

◆ SCSIOP_ATA_PASSTHROUGH

#define SCSIOP_ATA_PASSTHROUGH   0xCC

Definition at line 411 of file atapi.h.

◆ UNIATA_FIND_DEV_UNHIDE

#define UNIATA_FIND_DEV_UNHIDE   0x01

Definition at line 1360 of file atapi.h.

◆ UniAta_need_lba48

#define UniAta_need_lba48 (   command,
  lba,
  count,
  supp48 
)
Value:
( ((AtaCommandFlags[command] & ATA_CMD_FLAG_LBAIOsupp) && (supp48) && (((lba+count) >= ATA_MAX_IOLBA28) || (count > 256)) ) || \
(lba > ATA_MAX_LBA28) || (count > 255) )
#define ATA_MAX_LBA28
Definition: bsmaster.h:95
#define ATA_MAX_IOLBA28
Definition: bsmaster.h:94
GLuint GLuint GLsizei count
Definition: gl.h:1545
#define lba
UCHAR const AtaCommandFlags[256]
Definition: atacmd_map.h:25
#define ATA_CMD_FLAG_LBAIOsupp
Definition: atapi.h:1597

Definition at line 1609 of file atapi.h.

◆ UniAtaClearAtaReq

#define UniAtaClearAtaReq (   AtaReq)
Value:
{ \
RtlZeroMemory((PCHAR)(AtaReq), FIELD_OFFSET(ATA_REQ, ata)); \
}
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
char * PCHAR
Definition: typedefs.h:51

Definition at line 1615 of file atapi.h.

◆ WRITE_LOG_SECTOR

#define WRITE_LOG_SECTOR   0xD6

Definition at line 592 of file atapi.h.

◆ WRITE_THRESHOLDS

#define WRITE_THRESHOLDS   0xD7

Definition at line 593 of file atapi.h.

◆ WriteBuffer

#define WriteBuffer (   chan,
  Buffer,
  Count,
  timing 
)
Value:
Buffer, \
Count, \
VOID DDKFASTAPI AtapiWriteBuffer2(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
#define IDX_IO1_o_Data
Definition: atapi.h:208

Definition at line 1111 of file atapi.h.

◆ WriteBuffer2

#define WriteBuffer2 (   chan,
  Buffer,
  Count,
  timing 
)
Value:
Buffer, \
Count, \
VOID DDKFASTAPI AtapiWriteBuffer4(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)

Definition at line 1123 of file atapi.h.

◆ WriteCommand

#define WriteCommand (   chan,
  _Command 
)     AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);

Definition at line 1095 of file atapi.h.

Typedef Documentation

◆ ATAPI_REGISTERS_1

◆ IDE_REGISTERS_1

◆ IDE_REGISTERS_2

◆ IDENTIFY_DATA

◆ MODE_PARAMETER_HEADER_10

◆ MODE_SELECT_10

◆ MODE_SENSE_10

◆ PATAPI_REGISTERS_1

◆ PIDE_REGISTERS_1

◆ PIDE_REGISTERS_2

◆ PIDENTIFY_DATA

◆ PMODE_PARAMETER_HEADER_10

◆ PMODE_SELECT_10

◆ PMODE_SENSE_10

◆ PTRIM_DATA

◆ TRIM_DATA

Function Documentation

◆ _PrintNtConsole()

VOID _cdecl _PrintNtConsole ( PCCH  DebugMessage,
  ... 
)

Definition at line 11689 of file id_ata.cpp.

11693{
11694 //int len;
11695 UCHAR dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE];
11696// UNICODE_STRING msgBuff;
11697 va_list ap;
11698 va_start(ap, DebugMessage);
11699
11700 /*len =*/ _vsnprintf((PCHAR)&dbg_print_tmp_buff[0], DEBUG_MSG_BUFFER_SIZE-1, DebugMessage, ap);
11701
11702 dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE-1] = 0;
11703
11704 //DbgPrint(((PCHAR)&(dbg_print_tmp_buff[0]))); // already done in KdPrint macro
11705 HalDisplayString(dbg_print_tmp_buff);
11706
11707#ifdef _DEBUG
11708 if(g_LogToDisplay > 1) {
11710 }
11711#endif // _DEBUG
11712
11713 va_end(ap);
11714
11715} // end PrintNtConsole()
char * va_list
Definition: acmsvcex.h:78
#define va_end(ap)
Definition: acmsvcex.h:90
#define va_start(ap, A)
Definition: acmsvcex.h:91
NTHALAPI VOID NTAPI HalDisplayString(PUCHAR String)
#define DEBUG_MSG_BUFFER_SIZE
Definition: id_ata.cpp:11684
#define AtapiStallExecution(dt)
Definition: atapi.h:158
ULONG g_LogToDisplay
void int int ULONGLONG int va_list * ap
Definition: winesup.h:36
#define _vsnprintf
Definition: xmlstorage.h:202
unsigned char UCHAR
Definition: xmlstorage.h:181

Referenced by DriverEntry().

◆ ata_cur_mode_from_ident()

__inline LONG ata_cur_mode_from_ident ( PIDENTIFY_DATA  ident,
BOOLEAN  Active 
)

Definition at line 1648 of file atapi.h.

1654{
1655 USHORT mode;
1656 if(ata_is_sata(ident)) {
1657 if(ident->SataCapabilities & ATA_SATA_GEN3) {
1658 return ATA_SA600;
1659 } else
1660 if(ident->SataCapabilities & ATA_SATA_GEN2) {
1661 return ATA_SA300;
1662 } else
1663 if(ident->SataCapabilities & ATA_SATA_GEN1) {
1664 return ATA_SA150;
1665 }
1666 return ATA_SA150;
1667 }
1668
1669 if (ident->UdmaModesValid) {
1670 mode = Active ? ident->UltraDMAActive : ident->UltraDMASupport;
1671 if (mode & 0x40)
1672 return ATA_UDMA0+6;
1673 if (mode & 0x20)
1674 return ATA_UDMA0+5;
1675 if (mode & 0x10)
1676 return ATA_UDMA0+4;
1677 if (mode & 0x08)
1678 return ATA_UDMA0+3;
1679 if (mode & 0x04)
1680 return ATA_UDMA0+2;
1681 if (mode & 0x02)
1682 return ATA_UDMA0+1;
1683 if (mode & 0x01)
1684 return ATA_UDMA0+0;
1685 }
1686
1687 mode = Active ? ident->MultiWordDMAActive : ident->MultiWordDMASupport;
1688 if (ident->MultiWordDMAActive & 0x04)
1689 return ATA_WDMA0+2;
1690 if (ident->MultiWordDMAActive & 0x02)
1691 return ATA_WDMA0+1;
1692 if (ident->MultiWordDMAActive & 0x01)
1693 return ATA_WDMA0+0;
1694
1695 mode = Active ? ident->SingleWordDMAActive : ident->SingleWordDMASupport;
1696 if (ident->SingleWordDMAActive & 0x04)
1697 return ATA_SDMA0+2;
1698 if (ident->SingleWordDMAActive & 0x02)
1699 return ATA_SDMA0+1;
1700 if (ident->SingleWordDMAActive & 0x01)
1701 return ATA_SDMA0+0;
1702
1703 if (ident->PioTimingsValid) {
1704 mode = ident->AdvancedPIOModes;
1706 return ATA_PIO0+5;
1708 return ATA_PIO0+4;
1710 return ATA_PIO0+3;
1711 }
1712 mode = ident->PioCycleTimingMode;
1713 if (ident->PioCycleTimingMode == 2)
1714 return ATA_PIO0+2;
1715 if (ident->PioCycleTimingMode == 1)
1716 return ATA_PIO0+1;
1717 if (ident->PioCycleTimingMode == 0)
1718 return ATA_PIO0+0;
1719
GLenum mode
Definition: glext.h:6217
unsigned short USHORT
Definition: pedump.c:61
#define ATA_WDMA0
Definition: atapi.h:323
#define AdvancedPIOModes_3
Definition: atapi.h:726
#define ATA_SATA_GEN3
Definition: atapi.h:759
#define ATA_SATA_GEN2
Definition: atapi.h:758
#define ATA_SA150
Definition: atapi.h:337
#define ATA_SA300
Definition: atapi.h:338
#define ATA_SDMA0
Definition: atapi.h:318
#define AdvancedPIOModes_4
Definition: atapi.h:727
#define ATA_SATA_GEN1
Definition: atapi.h:757
#define ATA_SA600
Definition: atapi.h:339
#define AdvancedPIOModes_5
Definition: atapi.h:728
#define ATA_UDMA0
Definition: atapi.h:328
__inline BOOLEAN ata_is_sata(PIDENTIFY_DATA ident)
Definition: atapi.h:1636
#define ATA_PIO0
Definition: atapi.h:309
_In_ ULONG _In_ ULONG_PTR ident
Definition: winddi.h:3994
_In_ ULONG _In_ BOOLEAN Active
Definition: potypes.h:561

Referenced by ata_check_unit(), and IssueIdentify().

◆ ata_is_sata()

__inline BOOLEAN ata_is_sata ( PIDENTIFY_DATA  ident)

Definition at line 1636 of file atapi.h.

1641{

Referenced by ata_cur_mode_from_ident(), and AtapiDmaInit().

◆ AtaCommand()

UCHAR NTAPI AtaCommand ( IN struct _HW_DEVICE_EXTENSION deviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  Channel,
IN UCHAR  command,
IN USHORT  cylinder,
IN UCHAR  head,
IN UCHAR  sector,
IN UCHAR  count,
IN UCHAR  feature,
IN ULONG  flags 
)

Referenced by AtaSetTransferMode().

◆ AtaCommand48()

UCHAR NTAPI AtaCommand48 ( IN struct _HW_DEVICE_EXTENSION deviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  Channel,
IN UCHAR  command,
IN ULONGLONG  lba,
IN USHORT  count,
IN USHORT  feature,
IN ULONG  flags 
)

◆ AtapiCheckInterrupt__()

UCHAR NTAPI AtapiCheckInterrupt__ ( IN PVOID  HwDeviceExtension,
IN UCHAR  c 
)
  • clear interrupt and get status *‍/

Definition at line 4512 of file id_ata.cpp.

4516{
4517 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
4518 PHW_CHANNEL chan = &(deviceExtension->chan[c]);
4519 PHW_LU_EXTENSION LunExt;
4520
4521 ULONG VendorID = deviceExtension->DevID & 0xffff;
4522 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
4523
4524 ULONG status;
4525 ULONG pr_status = 0;
4526 UCHAR dma_status = 0;
4527 UCHAR reg8 = 0;
4528 ULONG reg32 = 0;
4529 UCHAR statusByte = 0;
4530 ULONG slotNumber = deviceExtension->slotNumber;
4531 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
4532 ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
4533 UCHAR Channel;
4534 UCHAR lChannel;
4535 BOOLEAN DmaTransfer = FALSE;
4536 BOOLEAN OurInterrupt = FALSE;
4537 BOOLEAN StatusValid = FALSE;
4538// ULONG k;
4539 UCHAR interruptReason;
4540 BOOLEAN EarlyIntr = FALSE;
4541 BOOLEAN SingleBlockIntr = FALSE;
4542
4543 KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__:\n"));
4544
4545 lChannel = c;
4546 Channel = (UCHAR)(deviceExtension->Channel + lChannel);
4547 LunExt = chan->lun[chan->cur_cdev];
4548
4549 //KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__ chan %#x:\n", chan));
4550 //KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__ (%d/%d):\n", Channel, chan->cur_cdev));
4551
4552 if((ChipFlags & UNIATA_AHCI) &&
4553 UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
4554
4555 if(!UniataAhciChanImplemented(deviceExtension, lChannel)) {
4556 return OurInterrupt;
4557 }
4558
4559 OurInterrupt = UniataAhciStatus(HwDeviceExtension, lChannel, DEVNUM_NOT_SPECIFIED);
4560 if((OurInterrupt == INTERRUPT_REASON_UNEXPECTED) &&
4561 (LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE)) {
4562 UniataAhciWaitCommandReady(chan, 2 /* ms */ );
4563 statusByte = (UCHAR)UniataAhciWaitReady(chan, 0 /* immediate */);
4564 if(!(statusByte & (IDE_STATUS_BUSY)) ) {
4565 KdPrint2((PRINT_PREFIX "ATAPI special case READY\n"));
4566 //deviceExtension->ExpectingInterrupt++; // will be updated in ISR on ReturnEnableInterrupts
4567 OurInterrupt = INTERRUPT_REASON_OUR;
4568 } else
4569 if((statusByte & (IDE_STATUS_BUSY | IDE_STATUS_DRDY)) == (IDE_STATUS_BUSY | IDE_STATUS_DRDY) ) {
4570 KdPrint2((PRINT_PREFIX "ATAPI special case pre ERR-READY\n"));
4571 OurInterrupt = INTERRUPT_REASON_OUR;
4572 } else
4573 if(statusByte & IDE_STATUS_ERROR) {
4574 KdPrint2((PRINT_PREFIX "ATAPI special case ERR-READY\n"));
4575 OurInterrupt = INTERRUPT_REASON_OUR;
4576 } else {
4577 KdPrint2((PRINT_PREFIX "ATAPI special case ? %x\n", statusByte));
4578 OurInterrupt = INTERRUPT_REASON_OUR;
4579 }
4580 }
4581 return OurInterrupt;
4582 }
4583
4585 DmaTransfer = TRUE;
4586 KdPrint2((PRINT_PREFIX " cntrlr %#x:%#x, lch %#x DmaTransfer = TRUE\n", deviceExtension->DevIndex,
4587 deviceExtension->Channel + c, c));
4588 } else {
4589 KdPrint2((PRINT_PREFIX " cntrlr %#x:%#x, lch %#x DmaTransfer = FALSE\n", deviceExtension->DevIndex,
4590 deviceExtension->Channel + c, c));
4591 dma_status = GetDmaStatus(deviceExtension, lChannel);
4592 KdPrint2((PRINT_PREFIX " DMA status %#x\n", dma_status));
4593 }
4594
4595 // do controller-specific interrupt servicing staff
4596 if(deviceExtension->UnknownDev) {
4597 KdPrint2((PRINT_PREFIX " UnknownDev\n"));
4598 goto check_unknown;
4599 }
4600
4601 // Attention !
4602 // We can catch (BM_STATUS_ACTIVE + BM_STATUS_INTR) when operation is actually completed
4603 // Such behavior was observed with Intel ICH-xxx chips
4604 // This condition shall also be treated as 'our interrupt' because of BM_STATUS_INTR flag
4605
4606 switch(VendorID) {
4607
4608 case ATA_PROMISE_ID: {
4609 switch(ChipType) {
4610 case PROLD:
4611 case PRNEW:
4612 status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1c);
4613 if (!DmaTransfer)
4614 break;
4615 if (!(status &
4616 ((Channel) ? 0x00004000 : 0x00000400))) {
4617 KdPrint2((PRINT_PREFIX " Promise old/new unexpected\n"));
4619 }
4620 break;
4621 case PRTX:
4624 if (!DmaTransfer)
4625 break;
4626 if(!(status & 0x20)) {
4627 KdPrint2((PRINT_PREFIX " Promise tx unexpected\n"));
4629 }
4630 break;
4631 case PRMIO: {
4632 ULONG stat_reg = (ChipFlags & PRG2) ? 0x60 : 0x6c;
4633 status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x40);
4634 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x40, status);
4635
4636 if(status & (1 << (Channel+1))) {
4637 // our
4638 } else {
4639 KdPrint2((PRINT_PREFIX " Promise mio unexpected\n"));
4641 }
4642
4643 if(!(ChipFlags & UNIATA_SATA))
4644 break;
4645
4646 pr_status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),stat_reg);
4647 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),stat_reg, (pr_status & (0x11 << Channel)));
4648 if(pr_status & (0x11 << Channel)) {
4649 // TODO: reset channel
4650 KdPrint2((PRINT_PREFIX " Promise mio unexpected + reset req\n"));
4651 UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH, 0);
4652 }
4653 if(!(status & (0x01 << Channel))) {
4654 // Connect event
4655 KdPrint2((PRINT_PREFIX " Promise mio unexpected attach\n"));
4656 UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH, 0);
4657 }
4658 if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
4659 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4660 } else {
4662 }
4663
4664 AtapiWritePort4(chan, IDX_BM_DeviceSpecific0, 0x00000001);
4665 break; }
4666 }
4667 break; }
4668 case ATA_NVIDIA_ID: {
4669 if(!(ChipFlags & UNIATA_SATA) || (ChipFlags & NVGEN))
4670 break;
4671
4672 KdPrint2((PRINT_PREFIX "NVIDIA\n"));
4673
4674 ULONG offs = (ChipFlags & NV4OFF) ? 0x0440 : 0x0010;
4675 ULONG shift = Channel * ((ChipFlags & NVQ) ? 4 : 16);
4676
4677 /* get and clear interrupt status */
4678 if(ChipFlags & NVQ) {
4679 pr_status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs);
4680 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, (0x0fUL << shift) | 0x00f000f0);
4681 } else {
4682 pr_status = AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs);
4683 AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, (0x0f << shift));
4684 }
4685 KdPrint2((PRINT_PREFIX " pr_status %x, shift %x\n", pr_status, shift));
4686
4687 /* check for and handle connect events */
4688 if(((pr_status & (0x0cUL << shift)) == (0x04UL << shift)) ) {
4689 UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH, 0);
4690 }
4691 /* check for and handle disconnect events */
4692 if((pr_status & (0x08UL << shift)) &&
4693 !((pr_status & (0x04UL << shift) &&
4695 UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH, 0);
4696 }
4697 /* do we have any device action ? */
4698 if(!(pr_status & (0x01UL << shift))) {
4699 KdPrint2((PRINT_PREFIX " nVidia unexpected\n"));
4700 if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
4701 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4702 } else {
4704 }
4705 }
4706
4707 break; }
4708 case ATA_ATI_ID:
4709 KdPrint2((PRINT_PREFIX "ATI\n"));
4710 if(ChipType == SIIMIO) {
4711 // fall to SiI
4712 } else {
4713 break;
4714 }
4716
4717 if(ChipType == SIIMIO) {
4718
4720 KdPrint2((PRINT_PREFIX " Sii DS0 %x\n", reg32));
4721 if(reg32 == 0xffffffff) {
4722 KdPrint2((PRINT_PREFIX " Sii mio unexpected\n"));
4724 }
4726 KdPrint2((PRINT_PREFIX " Sii mio unexpected (2)\n"));
4728 }
4729
4730 if(ChipFlags & UNIATA_SATA) {
4731 if(reg32 & (BM_DS0_SII_DMA_SATA_IRQ | BM_DS0_SII_IRQ)) {
4732
4733 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
4734 * controllers continue to assert IRQ as long as
4735 * SError bits are pending. Clear SError immediately.
4736 */
4737 if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
4738 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4739 }
4740 }
4741 }
4742
4743 if (!DmaTransfer)
4744 break;
4745 if (!((dma_status = GetDmaStatus(deviceExtension, lChannel)) & BM_STATUS_INTR)) {
4746 KdPrint2((PRINT_PREFIX " Sii mio unexpected (3)\n"));
4747 return OurInterrupt;
4748 }
4749 AtapiWritePort1(chan, IDX_BM_Status, dma_status & ~BM_STATUS_ERR);
4750 goto skip_dma_stat_check;
4751
4752 } else {
4753 if(!(deviceExtension->HwFlags & SIIINTR))
4754 break;
4755 GetPciConfig1(0x71, reg8);
4756 KdPrint2((PRINT_PREFIX " 0x71 = %#x\n", reg8));
4757 if (!(reg8 &
4758 (Channel ? 0x08 : 0x04))) {
4760 }
4761 if (!DmaTransfer) {
4762 KdPrint2((PRINT_PREFIX " cmd our\n"));
4763 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4764 }
4765 SetPciConfig1(0x71, (Channel ? 0x08 : 0x04));
4766 }
4767 break;
4768
4769 case ATA_ACARD_ID:
4770 if (!DmaTransfer)
4771 break;
4772 //dma_status = GetDmaStatus(deviceExtension, lChannel);
4773 if (!((dma_status = GetDmaStatus(deviceExtension, lChannel)) & BM_STATUS_INTR)) {
4774 KdPrint2((PRINT_PREFIX " Acard unexpected\n"));
4776 }
4777 AtapiWritePort1(chan, IDX_BM_Status, dma_status | BM_STATUS_INTR);
4781 goto skip_dma_stat_check;
4782 case ATA_INTEL_ID:
4783 if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
4784 if(ChipFlags & UNIATA_AHCI) {
4785 // Do nothing here
4786 } else
4787 if(ChipFlags & UNIATA_SATA) {
4788 if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
4789 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4790 }
4791 if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
4793 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4794 }
4795 }
4796 }
4797 }
4798 break;
4799 default:
4800 if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
4801 if(ChipFlags & UNIATA_AHCI) {
4802 // Do nothing here
4803 } else
4804 if(ChipFlags & UNIATA_SATA) {
4805 if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
4806 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4807 }
4808 }
4809 }
4810 }
4811check_unknown:
4812 KdPrint2((PRINT_PREFIX " perform generic check\n"));
4813 if (DmaTransfer) {
4814 if (!((dma_status = GetDmaStatus(deviceExtension, lChannel)) & BM_STATUS_INTR)) {
4815 KdPrint2((PRINT_PREFIX " DmaTransfer + !BM_STATUS_INTR (%x)\n", dma_status));
4816 if(dma_status & BM_STATUS_ERR) {
4817 KdPrint2((PRINT_PREFIX " DmaTransfer + BM_STATUS_ERR -> our\n"));
4818 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4819 } else {
4820 KdPrint2((PRINT_PREFIX " getting status...\n"));
4821 GetStatus(chan, statusByte);
4822 StatusValid = 1;
4823 KdPrint2((PRINT_PREFIX " status %#x\n", statusByte));
4824 if(statusByte & IDE_STATUS_ERROR) {
4825 KdPrint2((PRINT_PREFIX " IDE_STATUS_ERROR -> our\n", statusByte));
4826 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4827 } else
4828 if ((statusByte & IDE_STATUS_DSC) &&
4829 (LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) &&
4830 (dma_status == BM_STATUS_ACTIVE)) {
4831 KdPrint2((PRINT_PREFIX " special case DMA + ATAPI + IDE_STATUS_DSC -> our\n", statusByte));
4832 // some devices interrupts on each block transfer even in DMA mode
4833 if(LunExt->TransferMode >= ATA_SDMA && LunExt->TransferMode <= ATA_WDMA2) {
4834 KdPrint2((PRINT_PREFIX " wait for completion\n"));
4836 //GetBaseStatus(chan, statusByte);
4837 //return INTERRUPT_REASON_IGNORE;
4838 SingleBlockIntr = TRUE;
4839 }
4840 } else {
4842 }
4843 }
4844 }
4845 } else {
4846 if(dma_status & BM_STATUS_INTR) {
4847 // bullshit, we have DMA interrupt, but had never initiate DMA operation
4848 KdPrint2((PRINT_PREFIX " clear unexpected DMA intr\n"));
4849 AtapiDmaDone(deviceExtension, DEVNUM_NOT_SPECIFIED ,lChannel, NULL);
4850 // catch it !
4851 OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
4852 }
4853 }
4854skip_dma_stat_check:
4855 if(!(ChipFlags & UNIATA_SATA) && chan->ExpectingInterrupt) {
4857 }
4858
4859 /* if drive is busy it didn't interrupt */
4860 /* the exception is DCS + BSY state of ATAPI devices */
4861 if(!StatusValid) {
4862 KdPrint2((PRINT_PREFIX " getting status...\n"));
4863 GetStatus(chan, statusByte);
4864 }
4865 if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
4866 KdPrint3((PRINT_PREFIX " ATAPI status %#x\n", statusByte));
4867 } else {
4868 KdPrint2((PRINT_PREFIX " IDE status %#x\n", statusByte));
4869 }
4870 if (statusByte == IDE_STATUS_WRONG) {
4871 // interrupt from empty controller ?
4872 } else
4873 if (statusByte & IDE_STATUS_BUSY) {
4874 if(!chan->ExpectingInterrupt) {
4875 KdPrint3((PRINT_PREFIX " unexpected intr + BUSY\n"));
4876 return OurInterrupt;
4877 }
4878
4879 if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
4880 KdPrint2((PRINT_PREFIX " ATAPI additional check\n"));
4881 } else {
4882 KdPrint2((PRINT_PREFIX " expecting intr + BUSY (3), non ATAPI\n"));
4884 }
4885 if((statusByte & ~(IDE_STATUS_DRQ | IDE_STATUS_INDEX)) !=
4887 KdPrint3((PRINT_PREFIX " unexpected status, seems it is not our\n"));
4889 }
4890 if(!(LunExt->DeviceFlags & DFLAGS_INT_DRQ) && (statusByte & IDE_STATUS_DRQ)) {
4891 KdPrint3((PRINT_PREFIX " unexpected DRQ, seems it is not our\n"));
4893 }
4894
4895 EarlyIntr = TRUE;
4896
4897 if(dma_status & BM_STATUS_INTR) {
4898 KdPrint3((PRINT_PREFIX " our interrupt with BSY set, try wait in ISR or post to DPC\n"));
4899 /* clear interrupt and get status */
4900 GetBaseStatus(chan, statusByte);
4901 if(!(dma_status & BM_STATUS_ACTIVE)) {
4902 AtapiDmaDone(deviceExtension, DEVNUM_NOT_SPECIFIED ,lChannel, NULL);
4903 }
4904 KdPrint3((PRINT_PREFIX " base status %#x (+BM_STATUS_INTR)\n", statusByte));
4905 return INTERRUPT_REASON_OUR;
4906 }
4907
4908 if(g_WaitBusyInISR) {
4909 GetStatus(chan, statusByte);
4910 KdPrint2((PRINT_PREFIX " status re-check %#x\n", statusByte));
4911 reg8 = AtapiReadPort1(chan, IDX_IO1_i_Error);
4912 KdPrint2((PRINT_PREFIX " Error reg (%#x)\n", reg8));
4913 if (!(statusByte & IDE_STATUS_BUSY)) {
4914 KdPrint2((PRINT_PREFIX " expecting intr + cleared BUSY\n"));
4915 }
4916 if (statusByte & IDE_STATUS_BUSY) {
4917 KdPrint2((PRINT_PREFIX " still BUSY, seems it is not our\n"));
4919 }
4920 }
4921
4922 }
4923
4924 /* clear interrupt and get status */
4925 GetBaseStatus(chan, statusByte);
4926 KdPrint2((PRINT_PREFIX " base status %#x\n", statusByte));
4927 if (statusByte == IDE_STATUS_WRONG) {
4928 // interrupt from empty controller ?
4929 } else
4930 if(!(statusByte & (IDE_STATUS_DRQ | IDE_STATUS_DRDY))) {
4931 KdPrint2((PRINT_PREFIX " no DRQ/DRDY set\n"));
4932 return OurInterrupt;
4933 }
4934
4935#ifndef UNIATA_PIO_ONLY
4936 if(DmaTransfer) {
4937 if(!SingleBlockIntr && (!EarlyIntr || g_WaitBusyInISR)) {
4938 dma_status = AtapiDmaDone(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, lChannel, NULL/*srb*/);
4939 } else {
4941 PATA_REQ AtaReq = srb ? (PATA_REQ)(srb->SrbExtension) : NULL;
4942
4943 //ASSERT(AtaReq);
4944
4945 if(SingleBlockIntr) {
4946 KdPrint2((PRINT_PREFIX " set REQ_STATE_ATAPI_EXPECTING_DATA_INTR2.\n"));
4947 } else {
4948 KdPrint2((PRINT_PREFIX " set REQ_STATE_EARLY_INTR.\n"));
4949 }
4950 if(AtaReq) {
4952 }
4953 }
4954 }
4955#endif //
4956
4957 if (!(chan->ExpectingInterrupt)) {
4958
4959 KdPrint2((PRINT_PREFIX " Unexpected interrupt.\n"));
4960
4961 if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
4962 KdPrint2((PRINT_PREFIX " ATAPI additional check\n"));
4963 } else {
4964 KdPrint2((PRINT_PREFIX " OurInterrupt = %d\n", OurInterrupt));
4965 return OurInterrupt;
4966 }
4968 KdPrint3((PRINT_PREFIX "AtapiCheckInterrupt__: ATAPI int reason %x\n", interruptReason));
4969 return OurInterrupt;
4970 }
4971 //ASSERT(!chan->queue_depth || chan->cur_req);
4972
4973 KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__: exit with TRUE\n"));
4974 return INTERRUPT_REASON_OUR;
4975
4976} // end AtapiCheckInterrupt__()
unsigned char BOOLEAN
#define DFLAGS_ATAPI_DEVICE
Definition: atapi.h:41
#define GetBaseStatus(BaseIoAddress, Status)
Definition: atapi.h:331
#define GetStatus(BaseIoAddress, Status)
Definition: atapi.h:328
#define DFLAGS_INT_DRQ
Definition: atapi.h:43
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
#define ATA_INTEL_ID
Definition: bm_devs_decl.h:184
#define NV4OFF
Definition: bm_devs_decl.h:697
#define PRNEW
Definition: bm_devs_decl.h:646
#define NVQ
Definition: bm_devs_decl.h:698
#define PRTX
Definition: bm_devs_decl.h:647
#define CHIPTYPE_MASK
Definition: bm_devs_decl.h:620
#define SIIMIO
Definition: bm_devs_decl.h:665
#define UNIATA_SATA
Definition: bm_devs_decl.h:626
#define ATA_ACARD_ID
Definition: bm_devs_decl.h:111
#define PRG2
Definition: bm_devs_decl.h:654
#define UNIATA_AHCI
Definition: bm_devs_decl.h:629
#define NVGEN
Definition: bm_devs_decl.h:699
#define PROLD
Definition: bm_devs_decl.h:645
#define ATA_PROMISE_ID
Definition: bm_devs_decl.h:454
#define PRMIO
Definition: bm_devs_decl.h:648
#define ATA_NVIDIA_ID
Definition: bm_devs_decl.h:355
#define ATA_ATI_ID
Definition: bm_devs_decl.h:147
#define SIIINTR
Definition: bm_devs_decl.h:668
#define CHIPFLAG_MASK
Definition: bm_devs_decl.h:621
#define ATA_SILICON_IMAGE_ID
Definition: bm_devs_decl.h:507
#define BM_DS0_SII_DMA_COMPLETE
Definition: bsmaster.h:160
UCHAR NTAPI AtapiDmaDone(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
Definition: id_dma.cpp:685
#define BM_STATUS_ERR
Definition: bsmaster.h:143
VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
#define IDX_BM_DeviceSpecific1
Definition: bsmaster.h:170
#define BM_DS0_SII_DMA_ENABLE
Definition: bsmaster.h:156
#define IDX_BM_DeviceSpecific0
Definition: bsmaster.h:168
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
ULONG DDKFASTAPI AtapiReadPort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
#define GetPciConfig1(offs, op)
Definition: bsmaster.h:1620
#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2
Definition: bsmaster.h:953
#define BM_STATUS_ACTIVE
Definition: bsmaster.h:142
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
#define BM_DS0_SII_DMA_ERROR
Definition: bsmaster.h:159
#define IDX_BM_Status
Definition: bsmaster.h:169
#define BM_DS0_SII_IRQ
Definition: bsmaster.h:157
ULONG DDKFASTAPI AtapiReadPortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
#define BM_DS0_SII_DMA_SATA_IRQ
Definition: bsmaster.h:158
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
union _ATA_REQ * PATA_REQ
#define IDX_BM_Command
Definition: bsmaster.h:167
#define REQ_STATE_EARLY_INTR
Definition: bsmaster.h:956
#define BM_STATUS_INTR
Definition: bsmaster.h:144
VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
#define CTRFLAGS_NO_SLAVE
Definition: bsmaster.h:1139
#define IDX_SATA_SStatus
Definition: bsmaster.h:457
#define BM_COMMAND_START_STOP
Definition: bsmaster.h:150
UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
#define GetDmaStatus(de, c)
Definition: bsmaster.h:1711
#define SetPciConfig1(offs, op)
Definition: bsmaster.h:1630
#define CTRFLAGS_DMA_ACTIVE
Definition: bsmaster.h:1131
#define NULL
Definition: types.h:112
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
#define ULONGIO_PTR
Definition: config.h:102
const GLubyte * c
Definition: glext.h:8905
#define IDE_STATUS_WRONG
Definition: hwide.h:121
#define IDE_STATUS_INDEX
Definition: hwide.h:111
#define IDE_STATUS_DRDY
Definition: hwide.h:117
#define IDX_ATAPI_IO1_i_InterruptReason
Definition: hwide.h:89
#define IDE_STATUS_BUSY
Definition: hwide.h:119
#define IDE_STATUS_ERROR
Definition: hwide.h:110
#define IDE_STATUS_DRQ
Definition: hwide.h:113
#define IDE_STATUS_DSC
Definition: hwide.h:114
#define IDX_IO1_i_Error
Definition: hwide.h:42
ULONG g_WaitBusyInISR
Definition: id_ata.cpp:87
PSCSI_REQUEST_BLOCK NTAPI UniataGetCurRequest(IN PHW_CHANNEL chan)
Definition: id_queue.cpp:358
ULONG NTAPI UniataAhciWaitReady(IN PHW_CHANNEL chan, IN ULONG timeout)
Definition: id_sata.cpp:1853
UCHAR NTAPI UniataAhciStatus(IN PVOID HwDeviceExtension, IN ULONG lChannel, IN ULONG DeviceNumber)
Definition: id_sata.cpp:1131
BOOLEAN NTAPI UniataSataClearErr(IN PVOID HwDeviceExtension, IN ULONG lChannel, IN BOOLEAN do_connect, IN ULONG pm_port)
Definition: id_sata.cpp:186
UCHAR NTAPI UniataAhciWaitCommandReady(IN PHW_CHANNEL chan, IN ULONG timeout)
Definition: id_sata.cpp:1434
ULONG NTAPI UniataSataReadPort4(IN PHW_CHANNEL chan, IN ULONG io_port_ndx, IN ULONG pm_port)
Definition: id_sata.cpp:270
BOOLEAN NTAPI UniataSataEvent(IN PVOID HwDeviceExtension, IN ULONG lChannel, IN ULONG Action, IN ULONG pm_port)
Definition: id_sata.cpp:233
#define UNIATA_SATA_IGNORE_CONNECT
Definition: id_sata.h:61
#define UNIATA_SATA_EVENT_ATTACH
Definition: id_sata.h:72
__inline BOOLEAN UniataAhciChanImplemented(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
Definition: id_sata.h:415
#define UNIATA_SATA_DO_CONNECT
Definition: id_sata.h:60
__inline BOOLEAN UniataIsSATARangeAvailable(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG lChannel)
Definition: id_sata.h:91
#define UNIATA_SATA_EVENT_DETACH
Definition: id_sata.h:73
#define c
Definition: ke_i.h:80
#define shift
Definition: input.c:1755
ULONG ChannelCtrlFlags
Definition: bsmaster.h:1059
ULONG cur_cdev
Definition: bsmaster.h:1022
ULONG lChannel
Definition: bsmaster.h:1064
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]
Definition: bsmaster.h:1088
BOOLEAN ExpectingInterrupt
Definition: bsmaster.h:1032
struct _HW_DEVICE_EXTENSION * DeviceExtension
Definition: bsmaster.h:1087
PHW_CHANNEL chan
Definition: bsmaster.h:1257
UCHAR TransferMode
Definition: bsmaster.h:1171
PVOID SrbExtension
Definition: srb.h:267
Definition: ps.c:97
uint32_t ULONG
Definition: typedefs.h:59
#define INTERRUPT_REASON_UNEXPECTED
Definition: atapi.h:1280
#define ATA_SDMA
Definition: atapi.h:317
#define ATA_WDMA2
Definition: atapi.h:325
#define ATAPI_IR_Mask
Definition: atapi.h:551
#define KdPrint3(_x_)
Definition: atapi.h:153
#define KdPrint2(_x_)
Definition: atapi.h:154
#define DEVNUM_NOT_SPECIFIED
Definition: atapi.h:1483
#define INTERRUPT_REASON_IGNORE
Definition: atapi.h:1278
#define PRINT_PREFIX
Definition: atapi.h:150
#define INTERRUPT_REASON_OUR
Definition: atapi.h:1279
UCHAR ReqState
Definition: bsmaster.h:893

Referenced by AtapiInterrupt(), AtapiInterrupt2(), and IdeSendCommand().

◆ AtapiDisableInterrupts()

VOID NTAPI AtapiDisableInterrupts ( IN PVOID  HwDeviceExtension,
IN ULONG  c 
)

Definition at line 4457 of file id_ata.cpp.

4461{
4462 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
4463 PHW_CHANNEL chan;
4464 if(c >= deviceExtension->NumberChannels) {
4465 KdPrint2((PRINT_PREFIX "AtapiDisableInterrupts_%d: WRONG CHANNEL\n",c));
4466 return;
4467 }
4468 chan = &(deviceExtension->chan[c]);
4469 KdPrint2((PRINT_PREFIX "AtapiDisableInterrupts_%d: %d\n",c, chan->DisableIntr));
4470 // mark channel as busy
4471 if(InterlockedIncrement(&chan->DisableIntr)) {
4472 if(deviceExtension->HwFlags & UNIATA_AHCI) {
4474 } else {
4475 //SelectDrive(chan, 0);
4477 IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
4478 //if(chan->NumberLuns) {
4479 // SelectDrive(chan, 1);
4480 // AtapiWritePort1(chan, IDX_IO2_o_Control,
4481 // IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
4482 // SelectDrive(chan, chan->cur_cdev);
4483 //}
4484 }
4486 }
4487
4488 return;
4489} // end AtapiDisableInterrupts()
#define InterlockedIncrement
Definition: armddk.h:53
#define IDX_AHCI_P_IE
Definition: bsmaster.h:685
#define CTRFLAGS_INTR_DISABLED
Definition: bsmaster.h:1134
#define IDE_DC_DISABLE_INTERRUPTS
Definition: hwide.h:138
#define IDX_IO2_o_Control
Definition: hwide.h:62
__inline VOID UniataAhciWriteChannelPort4(IN PHW_CHANNEL chan, IN ULONG io_port_ndx, IN ULONG data)
Definition: id_sata.h:302
LONG DisableIntr
Definition: bsmaster.h:1061
ULONG NumberChannels
Definition: atapi.c:68

Referenced by AtapiAdapterControl(), AtapiHwInitialize__(), AtapiInterrupt(), AtapiInterrupt__(), AtapiResetController__(), AtapiSendCommand(), AtapiStartIo__(), AtaSetTransferMode(), FindDevices(), IdeSendCommand(), IssueIdentify(), and UniataUserDeviceReset().

◆ AtapiDpcDispatch()

VOID NTAPI AtapiDpcDispatch ( IN PKDPC  Dpc,
IN PVOID  DeferredContext,
IN PVOID  SystemArgument1,
IN PVOID  SystemArgument2 
)

◆ AtapiEnableInterrupts()

VOID NTAPI AtapiEnableInterrupts ( IN PVOID  HwDeviceExtension,
IN ULONG  c 
)

Definition at line 4397 of file id_ata.cpp.

4401{
4402 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
4403 PHW_CHANNEL chan;
4404 //UCHAR statusByte;
4405
4406 if(c >= deviceExtension->NumberChannels) {
4407 KdPrint2((PRINT_PREFIX "AtapiEnableInterrupts_%d: WRONG CHANNEL\n",c));
4408 return;
4409 }
4410 if((deviceExtension->HwFlags & UNIATA_AHCI) &&
4411 !UniataAhciChanImplemented(deviceExtension, c)) {
4412 KdPrint2((PRINT_PREFIX "AtapiEnableInterrupts_%d: not imp. CHANNEL\n",c));
4413 return;
4414 }
4415
4416 chan = &(deviceExtension->chan[c]);
4417 KdPrint2((PRINT_PREFIX "AtapiEnableInterrupts_%d: %d\n",c, chan->DisableIntr));
4418 if(!InterlockedDecrement(&chan->DisableIntr)) {
4419 if(deviceExtension->HwFlags & UNIATA_AHCI) {
4423 ((/*ch->pm_level == */0) ? ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC : 0) |
4424 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | /* DEBUG */
4428 );
4429 } else {
4430 //SelectDrive(chan, 0);
4431 //GetBaseStatus(chan, statusByte);
4433 0 | IDE_DC_A_4BIT );
4434 //if(chan->NumberLuns) {
4435 // SelectDrive(chan, 1);
4436 // GetBaseStatus(chan, statusByte);
4437 // AtapiWritePort1(chan, IDX_IO2_o_Control,
4438 // IDE_DC_A_4BIT );
4439 // SelectDrive(chan, chan->cur_cdev);
4440 //}
4441 }
4442 chan->ChannelCtrlFlags &= ~CTRFLAGS_INTR_DISABLED;
4443 } else {
4444 if(deviceExtension->HwFlags & UNIATA_AHCI) {
4445 // keep interrupts disabled
4447 } else {
4449 IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
4450 }
4451 }
4452 return;
4453} // end AtapiEnableInterrupts()
#define InterlockedDecrement
Definition: armddk.h:52
#define ATA_AHCI_P_IX_PC
Definition: bsmaster.h:505
#define ATA_AHCI_P_IX_HBD
Definition: bsmaster.h:513
#define ATA_AHCI_P_IX_DS
Definition: bsmaster.h:501
#define ATA_AHCI_P_IX_TFE
Definition: bsmaster.h:515
#define ATA_AHCI_P_IX_DI
Definition: bsmaster.h:506
#define ATA_AHCI_P_IX_HBF
Definition: bsmaster.h:514
#define ATA_AHCI_P_IX_SDB
Definition: bsmaster.h:502
#define ATA_AHCI_P_IX_IF
Definition: bsmaster.h:512
#define ATA_AHCI_P_IX_DHR
Definition: bsmaster.h:499
#define ATA_AHCI_P_IX_DP
Definition: bsmaster.h:504
#define ATA_AHCI_P_IX_INF
Definition: bsmaster.h:511
#define ATA_AHCI_P_IX_PRC
Definition: bsmaster.h:508
#define ATA_AHCI_P_IX_UF
Definition: bsmaster.h:503
#define ATA_AHCI_P_IX_CPD
Definition: bsmaster.h:516
#define ATA_AHCI_P_IX_PS
Definition: bsmaster.h:500
#define ATA_AHCI_P_IX_OF
Definition: bsmaster.h:510
#define IDE_DC_A_4BIT
Definition: hwide.h:140

Referenced by AtapiAdapterControl(), AtapiCallBack__(), AtapiEnableInterrupts__(), AtapiHwInitialize__(), AtapiInterrupt(), AtapiInterrupt__(), AtapiResetController__(), AtapiSendCommand(), AtapiStartIo__(), AtaSetTransferMode(), FindDevices(), IdeSendCommand(), IssueIdentify(), and UniataUserDeviceReset().

◆ AtapiFindIsaController()

ULONG NTAPI AtapiFindIsaController ( IN PVOID  HwDeviceExtension,
IN PVOID  Context,
IN PVOID  BusInformation,
IN PCHAR  ArgumentString,
IN OUT PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
OUT PBOOLEAN  Again 
)

Definition at line 2243 of file id_probe.cpp.

2251{
2252 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
2253 PHW_CHANNEL chan;
2254 PULONG adapterCount = (PULONG)Context;
2255 PUCHAR ioSpace = NULL;
2256 ULONG i;
2257 ULONG irq=0;
2258 ULONG portBase=0;
2259 ULONG retryCount;
2260// BOOLEAN atapiOnly;
2261 UCHAR statusByte, statusByte2;
2262 BOOLEAN preConfig = FALSE;
2263 //
2264 PIDE_REGISTERS_1 BaseIoAddress1;
2265 PIDE_REGISTERS_2 BaseIoAddress2 = NULL;
2266
2267 // The following table specifies the ports to be checked when searching for
2268 // an IDE controller. A zero entry terminates the search.
2269 static CONST ULONG AdapterAddresses[5] = {IO_WD1, IO_WD2, IO_WD1-8, IO_WD2-8, 0};
2270// CONST UCHAR Channels[5] = {0, 1, 0, 1, 0};
2271
2272 // The following table specifies interrupt levels corresponding to the
2273 // port addresses in the previous table.
2274 static CONST ULONG InterruptLevels[5] = {14, 15, 11, 10, 0};
2275
2276 KdPrint2((PRINT_PREFIX "AtapiFindIsaController (ISA):\n"));
2277
2278 if (!deviceExtension) {
2279 return SP_RETURN_ERROR;
2280 }
2281 RtlZeroMemory(deviceExtension, sizeof(HW_DEVICE_EXTENSION));
2282
2283 KdPrint2((PRINT_PREFIX " assume max PIO4\n"));
2284 deviceExtension->MaxTransferMode = ATA_PIO4;
2285 deviceExtension->NumberChannels = 1;
2286 deviceExtension->NumberLuns = IDE_MAX_LUN_PER_CHAN; // default
2287
2288 if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
2289 goto exit_error;
2290 }
2291
2292 chan = &(deviceExtension->chan[0]);
2293 AtapiSetupLunPtrs(chan, deviceExtension, 0);
2294
2295 deviceExtension->AdapterInterfaceType =
2296 deviceExtension->OrigAdapterInterfaceType
2297 = ConfigInfo->AdapterInterfaceType;
2298
2299#ifndef UNIATA_CORE
2300
2301 /* do extra chipset specific setups */
2304
2305 // Check to see if this is a special configuration environment.
2306 portBase = irq = 0;
2307 if (ArgumentString) {
2308
2309 irq = AtapiParseArgumentString(ArgumentString, "Interrupt");
2310 if (irq ) {
2311
2312 // Both parameters must be present to proceed
2313 portBase = AtapiParseArgumentString(ArgumentString, "BaseAddress");
2314 if (!portBase) {
2315
2316 // Try a default search for the part.
2317 irq = 0;
2318 }
2319 }
2320 }
2321
2322#endif //UNIATA_CORE
2323/*
2324 for(i=0; i<2; i++) {
2325 if((*ConfigInfo->AccessRanges)[i].RangeStart) {
2326 KdPrint2((PRINT_PREFIX " IoRange[%d], start %#x, len %#x, mem %#x\n",
2327 i,
2328 ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[i].RangeStart),
2329 (*ConfigInfo->AccessRanges)[i].RangeLength,
2330 (*ConfigInfo->AccessRanges)[i].RangeInMemory
2331 ));
2332 }
2333 }
2334*/
2335// if((*ConfigInfo->AccessRanges)[0].RangeStart) {
2336 portBase = ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[0].RangeStart);
2337// }
2338 if(portBase) {
2339 if(!AtapiCheckIOInterference(ConfigInfo, portBase)) {
2340 ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
2341 ConfigInfo->AdapterInterfaceType,
2342 ConfigInfo->SystemIoBusNumber,
2343 (*ConfigInfo->AccessRanges)[0].RangeStart,
2344 (*ConfigInfo->AccessRanges)[0].RangeLength,
2345 (BOOLEAN) !((*ConfigInfo->AccessRanges)[0].RangeInMemory));
2346 } else {
2347 // do not touch resources, just fail later inside loop on next call to
2348 // AtapiCheckIOInterference()
2349 }
2350 *Again = FALSE;
2351 // Since we have pre-configured information we only need to go through this loop once
2352 preConfig = TRUE;
2353 KdPrint2((PRINT_PREFIX " preconfig, portBase=%x, len=%x\n", portBase, (*ConfigInfo->AccessRanges)[0].RangeLength));
2354 }
2355
2356 // Scan through the adapter address looking for adapters.
2357#ifndef UNIATA_CORE
2358 while (AdapterAddresses[*adapterCount] != 0) {
2359#else
2360 do {
2361#endif //UNIATA_CORE
2362
2363 retryCount = 4;
2364 deviceExtension->DevIndex = (*adapterCount); // this is used inside AtapiRegCheckDevValue()
2365 KdPrint2((PRINT_PREFIX "AtapiFindIsaController: adapterCount=%d\n", *adapterCount));
2366
2367 for (i = 0; i < deviceExtension->NumberLuns; i++) {
2368 // Zero device fields to ensure that if earlier devices were found,
2369 // but not claimed, the fields are cleared.
2371 }
2372 // Get the system physical address for this IO range.
2373
2374 // Check if configInfo has the default information
2375 // if not, we go and find ourselves
2376 if (preConfig == FALSE) {
2377
2378 ULONG portBase_reg = 0;
2379 ULONG irq_reg = 0;
2380
2381 if (!portBase) {
2382 portBase = AdapterAddresses[*adapterCount];
2383 KdPrint2((PRINT_PREFIX "portBase[%d]=%x\n", *adapterCount, portBase));
2384 } else {
2385 KdPrint2((PRINT_PREFIX "portBase=%x\n", portBase));
2386 }
2387
2388 portBase_reg = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"PortBase", 0);
2389 irq_reg = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"Irq", 0);
2390 if(portBase_reg && irq_reg) {
2391 KdPrint2((PRINT_PREFIX "use registry settings portBase=%x, irq=%d\n", portBase_reg, irq_reg));
2392 portBase = portBase_reg;
2393 irq = irq_reg;
2394 }
2395 // check if Primary/Secondary Master IDE claimed
2396 if(AtapiCheckIOInterference(ConfigInfo, portBase)) {
2397 goto next_adapter;
2398 }
2399 ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
2400 ConfigInfo->AdapterInterfaceType,
2401 ConfigInfo->SystemIoBusNumber,
2403 ATA_IOSIZE,
2404 TRUE);
2405
2406 } else {
2407 KdPrint2((PRINT_PREFIX "preconfig portBase=%x\n", portBase));
2408 // Check if Primary/Secondary Master IDE claimed
2409 // We can also get here from preConfig branc with conflicting portBase
2410 // (and thus, w/o ioSpace allocated)
2411 if(AtapiCheckIOInterference(ConfigInfo, portBase)) {
2412 goto not_found;
2413 }
2414 }
2415 BaseIoAddress1 = (PIDE_REGISTERS_1)ioSpace;
2416next_adapter:
2417 // Update the adapter count.
2418 (*adapterCount)++;
2419
2420 // Check if ioSpace accessible.
2421 if (!ioSpace) {
2422 KdPrint2((PRINT_PREFIX "AtapiFindIsaController: !ioSpace\n"));
2423 portBase = 0;
2424 continue;
2425 }
2426
2427 // Get the system physical address for the second IO range.
2428 if (BaseIoAddress1) {
2429 if(preConfig &&
2430 !ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[1].RangeStart)) {
2431 KdPrint2((PRINT_PREFIX "AtapiFindIsaController: PCMCIA ?\n"));
2432 ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
2433 ConfigInfo->AdapterInterfaceType,
2434 ConfigInfo->SystemIoBusNumber,
2435 ScsiPortConvertUlongToPhysicalAddress((ULONGIO_PTR)BaseIoAddress1 + 0x0E),
2437 TRUE);
2438 } else {
2439 ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
2440 ConfigInfo->AdapterInterfaceType,
2441 ConfigInfo->SystemIoBusNumber,
2444 TRUE);
2445 }
2446 }
2447 BaseIoAddress2 = (PIDE_REGISTERS_2)ioSpace;
2448 KdPrint2((PRINT_PREFIX " BaseIoAddress1=%x\n", BaseIoAddress1));
2449 KdPrint2((PRINT_PREFIX " BaseIoAddress2=%x\n", BaseIoAddress2));
2450 if(!irq) {
2451 KdPrint2((PRINT_PREFIX " expected InterruptLevel=%x\n", InterruptLevels[*adapterCount - 1]));
2452 }
2453
2454 UniataInitMapBase(chan, BaseIoAddress1, BaseIoAddress2);
2455 UniataInitMapBM(deviceExtension, 0, FALSE);
2456
2457#ifdef _DEBUG
2458 UniataDumpATARegs(chan);
2459#endif
2460
2461 // Select master.
2462 SelectDrive(chan, 0);
2463
2464 statusByte = AtapiReadPort1(chan, IDX_IO1_i_Status);
2465 statusByte2 = AtapiReadPort1(chan, IDX_IO2_AltStatus);
2466 if((statusByte ^ statusByte2) & ~IDE_STATUS_INDEX) {
2467 KdPrint2((PRINT_PREFIX "AtapiFindIsaController: Status %x vs AltStatus %x missmatch, abort init ?\n", statusByte, statusByte2));
2468
2469 if(BaseIoAddress2) {
2470 ScsiPortFreeDeviceBase(HwDeviceExtension,
2471 (PCHAR)BaseIoAddress2);
2472 BaseIoAddress2 = NULL;
2473 }
2474 BaseIoAddress2 = (PIDE_REGISTERS_2)((ULONGIO_PTR)BaseIoAddress1 + 0x0E);
2475 KdPrint2((PRINT_PREFIX " try BaseIoAddress2=%x\n", BaseIoAddress2));
2476 ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
2477 ConfigInfo->AdapterInterfaceType,
2478 ConfigInfo->SystemIoBusNumber,
2481 TRUE);
2482 if(!ioSpace) {
2483 BaseIoAddress2 = NULL;
2484 KdPrint2((PRINT_PREFIX " abort (0)\n"));
2485 goto not_found;
2486 }
2487 UniataInitMapBase(chan, BaseIoAddress1, BaseIoAddress2);
2488 statusByte = AtapiReadPort1(chan, IDX_IO1_i_Status);
2489 statusByte2 = AtapiReadPort1(chan, IDX_IO2_AltStatus);
2490 if((statusByte ^ statusByte2) & ~IDE_STATUS_INDEX) {
2491 KdPrint2((PRINT_PREFIX " abort: Status %x vs AltStatus %x missmatch\n", statusByte, statusByte2));
2492 goto not_found;
2493 }
2494 }
2495
2496retryIdentifier:
2497
2498 // Select master.
2499 SelectDrive(chan, 0);
2500
2501 // Check if card at this address.
2503 statusByte = AtapiReadPort1(chan, IDX_IO1_i_CylinderLow);
2504
2505 // Check if indentifier can be read back.
2506 if (AtapiReadPort1(chan, IDX_IO1_i_CylinderLow) != 0xAA ||
2507 statusByte == IDE_STATUS_WRONG) {
2508
2509 KdPrint2((PRINT_PREFIX "AtapiFindIsaController: Identifier read back from Master (%#x)\n",
2510 statusByte));
2511
2512 statusByte = AtapiReadPort1(chan, IDX_IO2_AltStatus);
2513
2514 if (statusByte != IDE_STATUS_WRONG && (statusByte & IDE_STATUS_BUSY)) {
2515
2516 i = 0;
2517
2518 // Could be the TEAC in a thinkpad. Their dos driver puts it in a sleep-mode that
2519 // warm boots don't clear.
2520 do {
2521 AtapiStallExecution(1000);
2522 statusByte = AtapiReadPort1(chan, IDX_ATAPI_IO1_i_Status);
2524 "AtapiFindIsaController: First access to status %#x\n",
2525 statusByte));
2526 } while ((statusByte & IDE_STATUS_BUSY) && ++i < 10);
2527
2528 if (retryCount-- && (!(statusByte & IDE_STATUS_BUSY))) {
2529 goto retryIdentifier;
2530 }
2531 }
2532
2533 // Select slave.
2534 SelectDrive(chan, 1);
2535 statusByte = AtapiReadPort1(chan, IDX_IO2_AltStatus);
2536
2537 // See if slave is present.
2539
2540 if (AtapiReadPort1(chan, IDX_IO1_i_CylinderLow) != 0xAA ||
2541 statusByte == IDE_STATUS_WRONG) {
2542
2544 "AtapiFindIsaController: Identifier read back from Slave (%#x)\n",
2545 statusByte));
2546 goto not_found;
2547 }
2548 }
2549
2550 // Fill in the access array information only if default params are not in there.
2551 if (preConfig == FALSE) {
2552
2553 // An adapter has been found request another call, only if we didn't get preconfigured info.
2554 *Again = TRUE;
2555
2556 if (portBase) {
2557 (*ConfigInfo->AccessRanges)[0].RangeStart = ScsiPortConvertUlongToPhysicalAddress(portBase);
2558 } else {
2559 (*ConfigInfo->AccessRanges)[0].RangeStart =
2560 ScsiPortConvertUlongToPhysicalAddress(AdapterAddresses[*adapterCount - 1]);
2561 }
2562
2563 (*ConfigInfo->AccessRanges)[0].RangeLength = ATA_IOSIZE;
2564 (*ConfigInfo->AccessRanges)[0].RangeInMemory = FALSE;
2565
2566 if(BaseIoAddress2) {
2567 if(hasPCI) {
2568 (*ConfigInfo->AccessRanges)[1].RangeStart = ScsiPortConvertUlongToPhysicalAddress((ULONG_PTR)BaseIoAddress2);
2569 (*ConfigInfo->AccessRanges)[1].RangeLength = ATA_ALTIOSIZE;
2570 (*ConfigInfo->AccessRanges)[1].RangeInMemory = FALSE;
2571 } else {
2572 // NT4 and NT3.51 on ISA-only hardware definitly fail floppy.sys load
2573 // when this range is claimed by other driver.
2574 // However, floppy should use only 0x3f0-3f5,3f7
2575 if((ULONGIO_PTR)BaseIoAddress2 >= 0x3f0 && (ULONGIO_PTR)BaseIoAddress2 <= 0x3f7) {
2576 KdPrint2((PRINT_PREFIX "!!! Possible AltStatus vs Floppy IO range interference !!!\n"));
2577 }
2578 KdPrint2((PRINT_PREFIX "Do not expose to OS on old ISA\n"));
2579 (*ConfigInfo->AccessRanges)[1].RangeStart = ScsiPortConvertUlongToPhysicalAddress(0);
2580 (*ConfigInfo->AccessRanges)[1].RangeLength = 0;
2581 }
2582 }
2583
2584 // Indicate the interrupt level corresponding to this IO range.
2585 if (irq) {
2586 ConfigInfo->BusInterruptLevel = irq;
2587 } else {
2588 ConfigInfo->BusInterruptLevel = InterruptLevels[*adapterCount - 1];
2589 }
2590
2591 if (ConfigInfo->AdapterInterfaceType == MicroChannel) {
2592 ConfigInfo->InterruptMode = LevelSensitive;
2593 } else {
2594 ConfigInfo->InterruptMode = Latched;
2595 }
2596 }
2597
2598 ConfigInfo->NumberOfBuses = 1;
2599 ConfigInfo->MaximumNumberOfTargets = IDE_MAX_LUN_PER_CHAN;
2600
2601 // Indicate maximum transfer length is 64k.
2602 ConfigInfo->MaximumTransferLength = 0x10000;
2603 deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength;
2604
2605 KdPrint2((PRINT_PREFIX "de %#x, Channel ???\n", deviceExtension));
2606 //PrintNtConsole("de %#x, Channel %#x, nchan %#x\n",deviceExtension, channel, deviceExtension->NumberChannels);
2607
2608 KdPrint2((PRINT_PREFIX "chan = %#x\n", chan));
2609 //PrintNtConsole("chan = %#x, c=%#x\n", chan, c);
2610/*
2611 // should be already set up in AtapiSetupLunPtrs(chan, deviceExtension, 0);
2612
2613 chan->DeviceExtension = deviceExtension;
2614 chan->lChannel = 0;
2615 chan->lun[0] = &(deviceExtension->lun[0]);
2616 chan->lun[1] = &(deviceExtension->lun[1]);*/
2617
2618 /* do extra channel-specific setups */
2619 AtapiReadChipConfig(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, 0);
2620 AtapiChipInit(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, 0);
2621
2623 "AtapiFindIsaController: Found IDE at %#x\n",
2624 BaseIoAddress1));
2625
2626 // For Daytona, the atdisk driver gets the first shot at the
2627 // primary and secondary controllers.
2628 if (preConfig == FALSE) {
2629
2630 if (*adapterCount - 1 < 2) {
2631
2632 // Determine whether this driver is being initialized by the
2633 // system or as a crash dump driver.
2634 if (g_Dump) {
2635#ifndef UNIATA_CORE
2636 deviceExtension->DriverMustPoll = TRUE;
2637#endif //UNIATA_CORE
2638 } else {
2639 deviceExtension->DriverMustPoll = FALSE;
2640 }
2641
2642 } else {
2643 //atapiOnly = FALSE;
2644 }
2645
2646 } else {
2647
2648 //atapiOnly = FALSE;
2649 deviceExtension->DriverMustPoll = FALSE;
2650
2651 }// preConfig check
2652
2653 // Save the Interrupe Mode for later use
2654 deviceExtension->InterruptMode = ConfigInfo->InterruptMode;
2655 deviceExtension->BusInterruptLevel = ConfigInfo->BusInterruptLevel;
2656 deviceExtension->BusInterruptVector = ConfigInfo->BusInterruptVector;
2657
2659 "AtapiFindIsaController: look for devices\n"));
2660 // Search for devices on this controller.
2661 if (FindDevices(HwDeviceExtension,
2662 0,
2663 0 /* Channel */)) {
2664
2666 "AtapiFindIsaController: detected\n"));
2667 // Claim primary or secondary ATA IO range.
2668 if (portBase) {
2669 switch (portBase) {
2670 case IO_WD2:
2671 ConfigInfo->AtdiskSecondaryClaimed = TRUE;
2672 chan->PrimaryAddress = FALSE;
2673 break;
2674 case IO_WD1:
2675 ConfigInfo->AtdiskPrimaryClaimed = TRUE;
2676 chan->PrimaryAddress = TRUE;
2677 break;
2678 default:
2679 break;
2680 }
2681 } else {
2682 if (*adapterCount == 1) {
2683 ConfigInfo->AtdiskPrimaryClaimed = TRUE;
2684 chan->PrimaryAddress = TRUE;
2685 } else if (*adapterCount == 2) {
2686 ConfigInfo->AtdiskSecondaryClaimed = TRUE;
2687 chan->PrimaryAddress = FALSE;
2688 }
2689 }
2690
2691 if(deviceExtension->AdapterInterfaceType == Isa) {
2692 IsaCount++;
2693 } else
2694 if(deviceExtension->AdapterInterfaceType == MicroChannel) {
2695 MCACount++;
2696 }
2697
2698 ConfigInfo->NumberOfBuses++; // add virtual channel for communication port
2700 "AtapiFindIsaController: return SP_RETURN_FOUND\n"));
2701 return(SP_RETURN_FOUND);
2702 } else {
2703not_found:
2704 // No controller at this base address.
2705 if(BaseIoAddress1) {
2706 ScsiPortFreeDeviceBase(HwDeviceExtension,
2707 (PCHAR)BaseIoAddress1);
2708 BaseIoAddress1 = NULL;
2709 }
2710 if(BaseIoAddress2) {
2711 ScsiPortFreeDeviceBase(HwDeviceExtension,
2712 (PCHAR)BaseIoAddress2);
2713 BaseIoAddress2 = NULL;
2714 }
2715 for(i=0; i<2; i++) {
2717 "AtapiFindIsaController: cleanup AccessRanges %d\n", i));
2718 (*ConfigInfo->AccessRanges)[i].RangeStart = ScsiPortConvertUlongToPhysicalAddress(0);
2719 (*ConfigInfo->AccessRanges)[i].RangeLength = 0;
2720 (*ConfigInfo->AccessRanges)[i].RangeInMemory = FALSE;
2721 }
2722 irq = 0;
2723 portBase = 0;
2724 }
2725#ifndef UNIATA_CORE
2726 }
2727#else
2728 } while(FALSE);
2729#endif //UNIATA_CORE
2730
2731 // The entire table has been searched and no adapters have been found.
2732 // There is no need to call again and the device base can now be freed.
2733 // Clear the adapter count for the next bus.
2734 *Again = FALSE;
2735 *(adapterCount) = 0;
2736
2738 "AtapiFindIsaController: return SP_RETURN_NOT_FOUND\n"));
2739 UniataFreeLunExt(deviceExtension);
2740 return(SP_RETURN_NOT_FOUND);
2741
2742exit_error:
2743 UniataFreeLunExt(deviceExtension);
2744 return SP_RETURN_ERROR;
2745
2746} // end AtapiFindIsaController()
struct _IDE_REGISTERS_2 * PIDE_REGISTERS_2
#define DFLAGS_TAPE_DEVICE
Definition: atapi.h:42
#define DFLAGS_DEVICE_PRESENT
Definition: atapi.h:40
struct _IDE_REGISTERS_1 * PIDE_REGISTERS_1
ULONG NTAPI AtapiParseArgumentString(IN PCHAR String, IN PCHAR KeyWord)
Definition: atapi.c:1852
#define IDE_MAX_LUN_PER_CHAN
Definition: bm_devs_decl.h:46
SCSI_PHYSICAL_ADDRESS NTAPI ScsiPortConvertUlongToPhysicalAddress(IN ULONG_PTR UlongAddress)
Definition: scsiport.c:529
VOID NTAPI ScsiPortFreeDeviceBase(IN PVOID HwDeviceExtension, IN PVOID MappedAddress)
Definition: scsiport.c:549
PVOID NTAPI ScsiPortGetDeviceBase(IN PVOID HwDeviceExtension, IN INTERFACE_TYPE BusType, IN ULONG SystemIoBusNumber, IN SCSI_PHYSICAL_ADDRESS IoAddress, IN ULONG NumberOfBytes, IN BOOLEAN InIoSpace)
Definition: scsiport.c:571
BOOLEAN NTAPI UniataAllocateLunExt(PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
Definition: id_init.cpp:2891
#define ATA_ALTOFFSET
Definition: bsmaster.h:87
VOID NTAPI AtapiSetupLunPtrs(IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
Definition: id_init.cpp:2846
#define UNIATA_ALLOCATE_NEW_LUNS
Definition: bsmaster.h:1398
BOOLEAN g_Dump
Definition: id_ata.cpp:108
#define ATA_IOSIZE
Definition: bsmaster.h:86
BOOLEAN NTAPI AtapiReadChipConfig(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
Definition: id_init.cpp:1782
#define IO_WD2
Definition: bsmaster.h:79
#define ATA_ALTIOSIZE
Definition: bsmaster.h:89
VOID NTAPI UniataFreeLunExt(PHW_DEVICE_EXTENSION deviceExtension)
Definition: id_init.cpp:2956
BOOLEAN NTAPI AtapiChipInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG c)
Definition: id_init.cpp:1879
#define IO_WD1
Definition: bsmaster.h:78
BOOLEAN hasPCI
Definition: id_ata.cpp:103
MMRESULT FindDevices()
Definition: utils.c:159
#define SP_RETURN_ERROR
Definition: srb.h:523
#define SP_RETURN_FOUND
Definition: srb.h:522
#define ScsiPortConvertPhysicalAddressToUlong(Address)
Definition: srb.h:957
#define SP_RETURN_NOT_FOUND
Definition: srb.h:521
unsigned char irq
Definition: dsp.h:13
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
#define IDX_IO1_i_Status
Definition: hwide.h:48
#define IDX_IO1_i_CylinderLow
Definition: hwide.h:45
#define IDX_ATAPI_IO1_i_Status
Definition: hwide.h:94
#define IDX_IO1_o_CylinderLow
Definition: hwide.h:57
@ MicroChannel
Definition: hwresource.cpp:140
@ Isa
Definition: hwresource.cpp:138
ULONG IsaCount
Definition: id_probe.cpp:55
ULONG MCACount
Definition: id_probe.cpp:56
BOOLEAN NTAPI AtapiCheckIOInterference(IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, ULONG portBase)
Definition: id_probe.cpp:2203
#define L(x)
Definition: ntvdm.h:50
#define CONST
Definition: pedump.c:81
@ Latched
Definition: miniport.h:81
@ LevelSensitive
Definition: miniport.h:80
BOOLEAN PrimaryAddress
Definition: bsmaster.h:1036
BOOLEAN DriverMustPoll
Definition: atapi.c:111
PHW_LU_EXTENSION lun
Definition: bsmaster.h:1256
INTERFACE_TYPE AdapterInterfaceType
Definition: bsmaster.h:1316
ULONG MaximumDmaTransferLength
Definition: bsmaster.h:1317
INTERFACE_TYPE OrigAdapterInterfaceType
Definition: bsmaster.h:1315
ULONG InterruptMode
Definition: atapi.c:47
uint32_t * PULONG
Definition: typedefs.h:59
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
uint32_t ULONG_PTR
Definition: typedefs.h:65
unsigned char * PUCHAR
Definition: typedefs.h:53
ULONG NTAPI AtapiRegCheckDevValue(IN PVOID HwDeviceExtension, IN ULONG chan, IN ULONG dev, IN PCWSTR Name, IN ULONG Default)
Definition: id_ata.cpp:11365
VOID NTAPI UniataDumpATARegs(IN struct _HW_CHANNEL *chan)
#define ATA_PIO4
Definition: atapi.h:313
#define IDX_IO2_AltStatus
Definition: atapi.h:225
VOID NTAPI UniataInitMapBase(IN struct _HW_CHANNEL *chan, IN PIDE_REGISTERS_1 BaseIoAddress1, IN PIDE_REGISTERS_2 BaseIoAddress2)
UCHAR DDKFASTAPI SelectDrive(IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)
VOID NTAPI UniataInitMapBM(IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN struct _IDE_BUSMASTER_REGISTERS *BaseIoAddressBM_0, IN BOOLEAN MemIo)
#define CHAN_NOT_SPECIFIED
Definition: atapi.h:1481

Referenced by DriverEntry().

◆ AtapiHardReset()

VOID DDKFASTAPI AtapiHardReset ( IN struct _HW_CHANNEL chan,
IN BOOLEAN  DisableInterrupts,
IN ULONG  Delay 
)

Definition at line 948 of file id_ata.cpp.

953{
954 KdPrint2((PRINT_PREFIX "AtapiHardReset: %d, dis=%d\n", Delay, DisableInterrupts));
956 (DisableInterrupts ? IDE_DC_DISABLE_INTERRUPTS : 0));
957 chan->last_devsel = -1;
958 AtapiStallExecution(Delay);
960} // end AtapiHardReset()
#define IDE_DC_RESET_CONTROLLER
Definition: hwide.h:139
#define IDE_DC_REENABLE_CONTROLLER
Definition: hwide.h:142

Referenced by AtapiResetController__(), CheckDevice(), and FindDevices().

◆ AtapiHexToString()

VOID NTAPI AtapiHexToString ( ULONG  Value,
PCHAR Buffer 
)

◆ AtapiHwInitialize()

BOOLEAN NTAPI AtapiHwInitialize ( IN PVOID  HwDeviceExtension)

Definition at line 1282 of file atapi.c.

1301{
1302 PHW_DEVICE_EXTENSION deviceExtension = HwDeviceExtension;
1303 PIDE_REGISTERS_1 baseIoAddress;
1304 ULONG i;
1305 UCHAR statusByte, errorByte;
1306
1307
1308 for (i = 0; i < 4; i++) {
1309 if (deviceExtension->DeviceFlags[i] & DFLAGS_DEVICE_PRESENT) {
1310
1311 if (!(deviceExtension->DeviceFlags[i] & DFLAGS_ATAPI_DEVICE)) {
1312
1313 //
1314 // Enable media status notification
1315 //
1316
1317 baseIoAddress = deviceExtension->BaseIoAddress1[i >> 1];
1318
1319 IdeMediaStatus(TRUE,HwDeviceExtension,i);
1320
1321 //
1322 // If supported, setup Multi-block transfers.
1323 //
1324 if (deviceExtension->MaximumBlockXfer[i]) {
1325
1326 //
1327 // Select the device.
1328 //
1329
1330 ScsiPortWritePortUchar(&baseIoAddress->DriveSelect,
1331 (UCHAR)(((i & 0x1) << 4) | 0xA0));
1332
1333 //
1334 // Setup sector count to reflect the # of blocks.
1335 //
1336
1337 ScsiPortWritePortUchar(&baseIoAddress->BlockCount,
1338 deviceExtension->MaximumBlockXfer[i]);
1339
1340 //
1341 // Issue the command.
1342 //
1343
1344 ScsiPortWritePortUchar(&baseIoAddress->Command,
1346
1347 //
1348 // Wait for busy to drop.
1349 //
1350
1351 WaitOnBaseBusy(baseIoAddress,statusByte);
1352
1353 //
1354 // Check for errors. Reset the value to 0 (disable MultiBlock) if the
1355 // command was aborted.
1356 //
1357
1358 if (statusByte & IDE_STATUS_ERROR) {
1359
1360 //
1361 // Read the error register.
1362 //
1363
1364 errorByte = ScsiPortReadPortUchar((PUCHAR)baseIoAddress + 1);
1365
1366 DebugPrint((1,
1367 "AtapiHwInitialize: Error setting multiple mode. Status %x, error byte %x\n",
1368 statusByte,
1369 errorByte));
1370 //
1371 // Adjust the devExt. value, if necessary.
1372 //
1373
1374 deviceExtension->MaximumBlockXfer[i] = 0;
1375
1376 } else {
1377 DebugPrint((2,
1378 "AtapiHwInitialize: Using Multiblock on Device %d. Blocks / int - %d\n",
1379 i,
1380 deviceExtension->MaximumBlockXfer[i]));
1381 }
1382 }
1383 } else if (!(deviceExtension->DeviceFlags[i] & DFLAGS_CHANGER_INITED)){
1384
1385 ULONG j;
1386 UCHAR vendorId[26];
1387
1388 //
1389 // Attempt to identify any special-case devices - psuedo-atapi changers, atapi changers, etc.
1390 //
1391
1392 for (j = 0; j < 13; j += 2) {
1393
1394 //
1395 // Build a buffer based on the identify data.
1396 //
1397
1398 vendorId[j] = ((PUCHAR)deviceExtension->IdentifyData[i].ModelNumber)[j + 1];
1399 vendorId[j+1] = ((PUCHAR)deviceExtension->IdentifyData[i].ModelNumber)[j];
1400 }
1401
1402 if (!AtapiStringCmp ((PCHAR)vendorId, "CD-ROM CDR", 11)) {
1403
1404 //
1405 // Inquiry string for older model had a '-', newer is '_'
1406 //
1407
1408 if (vendorId[12] == 'C') {
1409
1410 //
1411 // Torisan changer. Set the bit. This will be used in several places
1412 // acting like 1) a multi-lun device and 2) building the 'special' TUR's.
1413 //
1414
1416 deviceExtension->DiscsPresent[i] = 3;
1417 }
1418 }
1419 }
1420
1421 //
1422 // We need to get our device ready for action before
1423 // returning from this function
1424 //
1425 // According to the atapi spec 2.5 or 2.6, an atapi device
1426 // clears its status BSY bit when it is ready for atapi commands.
1427 // However, some devices (Panasonic SQ-TC500N) are still
1428 // not ready even when the status BSY is clear. They don't react
1429 // to atapi commands.
1430 //
1431 // Since there is really no other indication that tells us
1432 // the drive is really ready for action. We are going to check BSY
1433 // is clear and then just wait for an arbitrary amount of time!
1434 //
1435 if (deviceExtension->DeviceFlags[i] & DFLAGS_ATAPI_DEVICE) {
1436 //PIDE_REGISTERS_1 baseIoAddress1 = deviceExtension->BaseIoAddress1[i >> 1];
1437 PIDE_REGISTERS_2 baseIoAddress2 = deviceExtension->BaseIoAddress2[i >> 1];
1438 ULONG waitCount;
1439
1440 // have to get out of the loop sometime!
1441 // 10000 * 100us = 1000,000us = 1000ms = 1s
1442 waitCount = 10000;
1443 GetStatus(baseIoAddress2, statusByte);
1444 while ((statusByte & IDE_STATUS_BUSY) && waitCount) {
1445 //
1446 // Wait for Busy to drop.
1447 //
1449 GetStatus(baseIoAddress2, statusByte);
1450 waitCount--;
1451 }
1452
1453 // 5000 * 100us = 500,000us = 500ms = 0.5s
1454 waitCount = 5000;
1455 do {
1457 } while (waitCount--);
1458 }
1459 }
1460 }
1461
1462 return TRUE;
1463
1464} // end AtapiHwInitialize()
#define DFLAGS_SANYO_ATAPI_CHANGER
Definition: atapi.h:49
#define DFLAGS_CHANGER_INITED
Definition: atapi.h:50
#define WaitOnBaseBusy(BaseIoAddress, Status)
Definition: atapi.h:373
#define IDE_COMMAND_SET_MULTIPLE
Definition: atapi.h:113
VOID NTAPI IdeMediaStatus(IN BOOLEAN EnableMSN, IN PVOID HwDeviceExtension, IN ULONG Channel)
VOID NTAPI ScsiPortWritePortUchar(IN PUCHAR Port, IN UCHAR Value)
Definition: scsiport.c:1547
VOID NTAPI ScsiPortStallExecution(IN ULONG Delay)
Definition: scsiport.c:1489
UCHAR NTAPI ScsiPortReadPortUchar(IN PUCHAR Port)
Definition: scsiport.c:1390
#define DebugPrint(x)
Definition: classpnp.h:125
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
ULONG DiscsPresent[4]
Definition: atapi.c:80
PIDE_REGISTERS_2 BaseIoAddress2[2]
Definition: atapi.c:35
UCHAR MaximumBlockXfer[4]
Definition: atapi.c:93
PIDE_REGISTERS_1 BaseIoAddress1[2]
Definition: atapi.c:34
IDENTIFY_DATA2 IdentifyData[4]
Definition: atapi.c:146
USHORT DeviceFlags[4]
Definition: atapi.c:86
USHORT ModelNumber[20]
Definition: atapi.h:262
UCHAR BlockCount
Definition: atapi.h:18
UCHAR Command
Definition: atapi.h:23
UCHAR DriveSelect
Definition: atapi.h:22
#define AtapiStringCmp(s1, s2, n)
Definition: atapi.h:1256

Referenced by AtapiResetController(), and DriverEntry().

◆ AtapiHwInitializeChanger()

VOID NTAPI AtapiHwInitializeChanger ( IN PVOID  HwDeviceExtension,
IN ULONG  TargetId,
IN PMECHANICAL_STATUS_INFORMATION_HEADER  MechanismStatus 
)

Definition at line 1469 of file atapi.c.

1473{
1474 PHW_DEVICE_EXTENSION deviceExtension = HwDeviceExtension;
1475
1476 if (MechanismStatus) {
1477 deviceExtension->DiscsPresent[TargetId] = MechanismStatus->NumberAvailableSlots;
1478 if (deviceExtension->DiscsPresent[TargetId] > 1) {
1479 deviceExtension->DeviceFlags[TargetId] |= DFLAGS_ATAPI_CHANGER;
1480 }
1481 }
1482 return;
1483}
#define DFLAGS_ATAPI_CHANGER
Definition: atapi.h:48
_In_ ULONG _In_ BOOLEAN _In_ ULONG _In_ UCHAR _In_ UCHAR TargetId
Definition: classpnp.h:1314

Referenced by AtapiInterrupt(), and AtapiSendCommand().

◆ AtapiInterrupt()

BOOLEAN NTAPI AtapiInterrupt ( IN PVOID  HwDeviceExtension)

Definition at line 3484 of file atapi.c.

3504{
3505 PHW_DEVICE_EXTENSION deviceExtension = HwDeviceExtension;
3506 PSCSI_REQUEST_BLOCK srb = deviceExtension->CurrentSrb;
3507 PATAPI_REGISTERS_1 baseIoAddress1;
3508 PATAPI_REGISTERS_2 baseIoAddress2;
3509 ULONG wordCount = 0, wordsThisInterrupt = 256;
3510 ULONG status;
3511 ULONG i;
3512 UCHAR statusByte,interruptReason;
3513 BOOLEAN atapiDev = FALSE;
3514
3515 if (srb) {
3516 baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[srb->TargetId >> 1];
3517 baseIoAddress2 = (PATAPI_REGISTERS_2)deviceExtension->BaseIoAddress2[srb->TargetId >> 1];
3518 } else {
3519 DebugPrint((2,
3520 "AtapiInterrupt: CurrentSrb is NULL\n"));
3521 //
3522 // We can only support one ATAPI IDE master on Carolina, so find
3523 // the base address that is non NULL and clear its interrupt before
3524 // returning.
3525 //
3526
3527#ifdef _PPC_
3528
3529 if ((PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[0] != NULL) {
3530 baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[0];
3531 } else {
3532 baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[1];
3533 }
3534
3535 GetBaseStatus(baseIoAddress1, statusByte);
3536#else
3537
3538 if (deviceExtension->InterruptMode == LevelSensitive) {
3539 if (deviceExtension->BaseIoAddress1[0] != NULL) {
3540 baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[0];
3541 GetBaseStatus(baseIoAddress1, statusByte);
3542 }
3543 if (deviceExtension->BaseIoAddress1[1] != NULL) {
3544 baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[1];
3545 GetBaseStatus(baseIoAddress1, statusByte);
3546 }
3547 }
3548#endif
3549 return FALSE;
3550 }
3551
3552 if (!(deviceExtension->ExpectingInterrupt)) {
3553
3554 DebugPrint((3,
3555 "AtapiInterrupt: Unexpected interrupt.\n"));
3556 return FALSE;
3557 }
3558
3559 //
3560 // Clear interrupt by reading status.
3561 //
3562
3563 GetBaseStatus(baseIoAddress1, statusByte);
3564
3565 DebugPrint((3,
3566 "AtapiInterrupt: Entered with status (%x)\n",
3567 statusByte));
3568
3569
3570 if (statusByte & IDE_STATUS_BUSY) {
3571 if (deviceExtension->DriverMustPoll) {
3572
3573 //
3574 // Crashdump is polling and we got caught with busy asserted.
3575 // Just go away, and we will be polled again shortly.
3576 //
3577
3578 DebugPrint((3,
3579 "AtapiInterrupt: Hit BUSY while polling during crashdump.\n"));
3580
3581 return TRUE;
3582 }
3583
3584 //
3585 // Ensure BUSY is non-asserted.
3586 //
3587
3588 for (i = 0; i < 10; i++) {
3589
3590 GetBaseStatus(baseIoAddress1, statusByte);
3591 if (!(statusByte & IDE_STATUS_BUSY)) {
3592 break;
3593 }
3595 }
3596
3597 if (i == 10) {
3598
3599 DebugPrint((2,
3600 "AtapiInterrupt: BUSY on entry. Status %x, Base IO %x\n",
3601 statusByte,
3602 baseIoAddress1));
3603
3605 HwDeviceExtension,
3607 500);
3608 return TRUE;
3609 }
3610 }
3611
3612
3613 //
3614 // Check for error conditions.
3615 //
3616
3617 if (statusByte & IDE_STATUS_ERROR) {
3618
3619 if (srb->Cdb[0] != SCSIOP_REQUEST_SENSE) {
3620
3621 //
3622 // Fail this request.
3623 //
3624
3626 goto CompleteRequest;
3627 }
3628 }
3629
3630 //
3631 // check reason for this interrupt.
3632 //
3633
3634 if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
3635
3636 interruptReason = (ScsiPortReadPortUchar(&baseIoAddress1->InterruptReason) & 0x3);
3637 atapiDev = TRUE;
3638 wordsThisInterrupt = 256;
3639
3640 } else {
3641
3642 if (statusByte & IDE_STATUS_DRQ) {
3643
3644 if (deviceExtension->MaximumBlockXfer[srb->TargetId]) {
3645 wordsThisInterrupt = 256 * deviceExtension->MaximumBlockXfer[srb->TargetId];
3646
3647 }
3648
3649 if (srb->SrbFlags & SRB_FLAGS_DATA_IN) {
3650
3651 interruptReason = 0x2;
3652
3653 } else if (srb->SrbFlags & SRB_FLAGS_DATA_OUT) {
3654 interruptReason = 0x0;
3655
3656 } else {
3658 goto CompleteRequest;
3659 }
3660
3661 } else if (statusByte & IDE_STATUS_BUSY) {
3662
3663 return FALSE;
3664
3665 } else {
3666
3667 if (deviceExtension->WordsLeft) {
3668
3669 ULONG k;
3670
3671 //
3672 // Funky behaviour seen with PCI IDE (not all, just one).
3673 // The ISR hits with DRQ low, but comes up later.
3674 //
3675
3676 for (k = 0; k < 5000; k++) {
3677 GetStatus(baseIoAddress2,statusByte);
3678 if (!(statusByte & IDE_STATUS_DRQ)) {
3680 } else {
3681 break;
3682 }
3683 }
3684
3685 if (k == 5000) {
3686
3687 //
3688 // reset the controller.
3689 //
3690
3691 DebugPrint((1,
3692 "AtapiInterrupt: Resetting due to DRQ not up. Status %x, Base IO %x\n",
3693 statusByte,
3694 baseIoAddress1));
3695
3696 AtapiResetController(HwDeviceExtension,srb->PathId);
3697 return TRUE;
3698 } else {
3699
3700 interruptReason = (srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x2 : 0x0;
3701 }
3702
3703 } else {
3704
3705 //
3706 // Command complete - verify, write, or the SMART enable/disable.
3707 //
3708 // Also get_media_status
3709
3710 interruptReason = 0x3;
3711 }
3712 }
3713 }
3714
3715 if (interruptReason == 0x1 && (statusByte & IDE_STATUS_DRQ)) {
3716
3717 //
3718 // Write the packet.
3719 //
3720
3721 DebugPrint((2,
3722 "AtapiInterrupt: Writing Atapi packet.\n"));
3723
3724 //
3725 // Send CDB to device.
3726 //
3727
3728 WriteBuffer(baseIoAddress1,
3729 (PUSHORT)srb->Cdb,
3730 6);
3731
3732 return TRUE;
3733
3734 } else if (interruptReason == 0x0 && (statusByte & IDE_STATUS_DRQ)) {
3735
3736 //
3737 // Write the data.
3738 //
3739
3740 if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
3741
3742 //
3743 // Pick up bytes to transfer and convert to words.
3744 //
3745
3746 wordCount =
3747 ScsiPortReadPortUchar(&baseIoAddress1->ByteCountLow);
3748
3749 wordCount |=
3750 ScsiPortReadPortUchar(&baseIoAddress1->ByteCountHigh) << 8;
3751
3752 //
3753 // Covert bytes to words.
3754 //
3755
3756 wordCount >>= 1;
3757
3758 if (wordCount != deviceExtension->WordsLeft) {
3759 DebugPrint((3,
3760 "AtapiInterrupt: %d words requested; %d words xferred\n",
3761 deviceExtension->WordsLeft,
3762 wordCount));
3763 }
3764
3765 //
3766 // Verify this makes sense.
3767 //
3768
3769 if (wordCount > deviceExtension->WordsLeft) {
3770 wordCount = deviceExtension->WordsLeft;
3771 }
3772
3773 } else {
3774
3775 //
3776 // IDE path. Check if words left is at least 256.
3777 //
3778
3779 if (deviceExtension->WordsLeft < wordsThisInterrupt) {
3780
3781 //
3782 // Transfer only words requested.
3783 //
3784
3785 wordCount = deviceExtension->WordsLeft;
3786
3787 } else {
3788
3789 //
3790 // Transfer next block.
3791 //
3792
3793 wordCount = wordsThisInterrupt;
3794 }
3795 }
3796
3797 //
3798 // Ensure that this is a write command.
3799 //
3800
3801 if (srb->SrbFlags & SRB_FLAGS_DATA_OUT) {
3802
3803 DebugPrint((3,
3804 "AtapiInterrupt: Write interrupt\n"));
3805
3806 WaitOnBusy(baseIoAddress2,statusByte);
3807
3808 if (atapiDev || !deviceExtension->DWordIO) {
3809
3810 WriteBuffer(baseIoAddress1,
3811 deviceExtension->DataBuffer,
3812 wordCount);
3813 } else {
3814
3815 PIDE_REGISTERS_3 address3 = (PIDE_REGISTERS_3)baseIoAddress1;
3816
3817 WriteBuffer2(address3,
3818 (PULONG)(deviceExtension->DataBuffer),
3819 wordCount / 2);
3820 }
3821 } else {
3822
3823 DebugPrint((1,
3824 "AtapiInterrupt: Int reason %x, but srb is for a write %x.\n",
3825 interruptReason,
3826 srb));
3827
3828 //
3829 // Fail this request.
3830 //
3831
3833 goto CompleteRequest;
3834 }
3835
3836
3837 //
3838 // Advance data buffer pointer and bytes left.
3839 //
3840
3841 deviceExtension->DataBuffer += wordCount;
3842 deviceExtension->WordsLeft -= wordCount;
3843
3844 return TRUE;
3845
3846 } else if (interruptReason == 0x2 && (statusByte & IDE_STATUS_DRQ)) {
3847
3848
3849 if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
3850
3851 //
3852 // Pick up bytes to transfer and convert to words.
3853 //
3854
3855 wordCount =
3856 ScsiPortReadPortUchar(&baseIoAddress1->ByteCountLow);
3857
3858 wordCount |=
3859 ScsiPortReadPortUchar(&baseIoAddress1->ByteCountHigh) << 8;
3860
3861 //
3862 // Covert bytes to words.
3863 //
3864
3865 wordCount >>= 1;
3866
3867 if (wordCount != deviceExtension->WordsLeft) {
3868 DebugPrint((3,
3869 "AtapiInterrupt: %d words requested; %d words xferred\n",
3870 deviceExtension->WordsLeft,
3871 wordCount));
3872 }
3873
3874 //
3875 // Verify this makes sense.
3876 //
3877
3878 if (wordCount > deviceExtension->WordsLeft) {
3879 wordCount = deviceExtension->WordsLeft;
3880 }
3881
3882 } else {
3883
3884 //
3885 // Check if words left is at least 256.
3886 //
3887
3888 if (deviceExtension->WordsLeft < wordsThisInterrupt) {
3889
3890 //
3891 // Transfer only words requested.
3892 //
3893
3894 wordCount = deviceExtension->WordsLeft;
3895
3896 } else {
3897
3898 //
3899 // Transfer next block.
3900 //
3901
3902 wordCount = wordsThisInterrupt;
3903 }
3904 }
3905
3906 //
3907 // Ensure that this is a read command.
3908 //
3909
3910 if (srb->SrbFlags & SRB_FLAGS_DATA_IN) {
3911
3912 DebugPrint((3,
3913 "AtapiInterrupt: Read interrupt\n"));
3914
3915 WaitOnBusy(baseIoAddress2,statusByte);
3916
3917 if (atapiDev || !deviceExtension->DWordIO) {
3918 ReadBuffer(baseIoAddress1,
3919 deviceExtension->DataBuffer,
3920 wordCount);
3921
3922 } else {
3923 PIDE_REGISTERS_3 address3 = (PIDE_REGISTERS_3)baseIoAddress1;
3924
3925 ReadBuffer2(address3,
3926 (PULONG)(deviceExtension->DataBuffer),
3927 wordCount / 2);
3928 }
3929 } else {
3930
3931 DebugPrint((1,
3932 "AtapiInterrupt: Int reason %x, but srb is for a read %x.\n",
3933 interruptReason,
3934 srb));
3935
3936 //
3937 // Fail this request.
3938 //
3939
3941 goto CompleteRequest;
3942 }
3943
3944 //
3945 // Translate ATAPI data back to SCSI data if needed
3946 //
3947
3948 if (srb->Cdb[0] == ATAPI_MODE_SENSE &&
3949 deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
3950
3951 //
3952 //convert and adjust the wordCount
3953 //
3954
3955 wordCount -= Atapi2Scsi(srb, (char *)deviceExtension->DataBuffer,
3956 wordCount << 1);
3957 }
3958 //
3959 // Advance data buffer pointer and bytes left.
3960 //
3961
3962 deviceExtension->DataBuffer += wordCount;
3963 deviceExtension->WordsLeft -= wordCount;
3964
3965 //
3966 // Check for read command complete.
3967 //
3968
3969 if (deviceExtension->WordsLeft == 0) {
3970
3971 if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
3972
3973 //
3974 // Work around to make many atapi devices return correct sector size
3975 // of 2048. Also certain devices will have sector count == 0x00, check
3976 // for that also.
3977 //
3978
3979 if ((srb->Cdb[0] == 0x25) &&
3980 ((deviceExtension->IdentifyData[srb->TargetId].GeneralConfiguration >> 8) & 0x1f) == 0x05) {
3981
3982 deviceExtension->DataBuffer -= wordCount;
3983 if (deviceExtension->DataBuffer[0] == 0x00) {
3984
3985 *((ULONG *) &(deviceExtension->DataBuffer[0])) = 0xFFFFFF7F;
3986
3987 }
3988
3989 *((ULONG *) &(deviceExtension->DataBuffer[2])) = 0x00080000;
3990 deviceExtension->DataBuffer += wordCount;
3991 }
3992 } else {
3993
3994 //
3995 // Completion for IDE drives.
3996 //
3997
3998
3999 if (deviceExtension->WordsLeft) {
4000
4002
4003 } else {
4004
4006
4007 }
4008
4009 goto CompleteRequest;
4010
4011 }
4012 }
4013
4014 return TRUE;
4015
4016 } else if (interruptReason == 0x3 && !(statusByte & IDE_STATUS_DRQ)) {
4017
4018 //
4019 // Command complete.
4020 //
4021
4022 if (deviceExtension->WordsLeft) {
4023
4025
4026 } else {
4027
4029
4030 }
4031
4033
4034 //
4035 // Check and see if we are processing our secret (mechanism status/request sense) srb
4036 //
4037 if (deviceExtension->OriginalSrb) {
4038
4039 ULONG srbStatus;
4040
4041 if (srb->Cdb[0] == SCSIOP_MECHANISM_STATUS) {
4042
4043 if (status == SRB_STATUS_SUCCESS) {
4044 // Bingo!!
4045 AtapiHwInitializeChanger (HwDeviceExtension,
4046 srb->TargetId,
4048
4049 // Get ready to issue the original srb
4050 srb = deviceExtension->CurrentSrb = deviceExtension->OriginalSrb;
4051 deviceExtension->OriginalSrb = NULL;
4052
4053 } else {
4054 // failed! Get the sense key and maybe try again
4055 srb = deviceExtension->CurrentSrb = BuildRequestSenseSrb (
4056 HwDeviceExtension,
4057 deviceExtension->OriginalSrb->PathId,
4058 deviceExtension->OriginalSrb->TargetId);
4059 }
4060
4061 srbStatus = AtapiSendCommand(HwDeviceExtension, deviceExtension->CurrentSrb);
4062 if (srbStatus == SRB_STATUS_PENDING) {
4063 return TRUE;
4064 }
4065
4066 } else { // srb->Cdb[0] == SCSIOP_REQUEST_SENSE)
4067
4068 PSENSE_DATA senseData = (PSENSE_DATA) srb->DataBuffer;
4069
4071 // Check to see if we at least get minimum number of bytes
4072 if ((srb->DataTransferLength - deviceExtension->WordsLeft) >
4073 (FIELD_OFFSET (SENSE_DATA, AdditionalSenseLength) + sizeof(senseData->AdditionalSenseLength))) {
4075 }
4076 }
4077
4078 if (status == SRB_STATUS_SUCCESS) {
4079 if ((senseData->SenseKey != SCSI_SENSE_ILLEGAL_REQUEST) &&
4080 deviceExtension->MechStatusRetryCount) {
4081
4082 // The sense key doesn't say the last request is illegal, so try again
4083 deviceExtension->MechStatusRetryCount--;
4084 srb = deviceExtension->CurrentSrb = BuildMechanismStatusSrb (
4085 HwDeviceExtension,
4086 deviceExtension->OriginalSrb->PathId,
4087 deviceExtension->OriginalSrb->TargetId);
4088 } else {
4089
4090 // last request was illegal. No point trying again
4091
4092 AtapiHwInitializeChanger (HwDeviceExtension,
4093 srb->TargetId,
4095
4096 // Get ready to issue the original srb
4097 srb = deviceExtension->CurrentSrb = deviceExtension->OriginalSrb;
4098 deviceExtension->OriginalSrb = NULL;
4099 }
4100
4101 srbStatus = AtapiSendCommand(HwDeviceExtension, deviceExtension->CurrentSrb);
4102 if (srbStatus == SRB_STATUS_PENDING) {
4103 return TRUE;
4104 }
4105 }
4106 }
4107
4108 // If we get here, it means AtapiSendCommand() has failed
4109 // Can't recover. Pretend the original srb has failed and complete it.
4110
4111 if (deviceExtension->OriginalSrb) {
4112 AtapiHwInitializeChanger (HwDeviceExtension,
4113 srb->TargetId,
4114