#include "config.h"
#include "scsi.h"
#include "stdio.h"
#include "string.h"

Include dependency graph for atapi.h:

This graph shows which files directly or indirectly include this file:

Classes
union	_IDE_REGISTERS_1

struct	_IDE_REGISTERS_1::_o

struct	_IDE_REGISTERS_1::_i

union	_IDE_REGISTERS_2

struct	_MODE_SENSE_10

struct	_MODE_SELECT_10

struct	_MODE_PARAMETER_HEADER_10

union	_ATAPI_REGISTERS_1

struct	_ATAPI_REGISTERS_1::_o

struct	_ATAPI_REGISTERS_1::_i

struct	_IDENTIFY_DATA

struct	_TRIM_DATA

Macros
#define	PRINT_PREFIX "UniATA: "

#define	KdPrint3(_x_) {;}

#define	KdPrint2(_x_) {;}

#define	KdPrint(_x_) {;}

#define	Connect_DbgPrint() {;}

#define	AtapiStallExecution(dt) ScsiPortStallExecution(dt)

#define	IDX_IO1 0

#define	IDX_IO1_SZ sizeof(IDE_REGISTERS_1)

#define	IDX_IO1 0

#define	IDX_IO1_SZ sizeof(IDE_REGISTERS_1)

#define	IDX_IO1_i_Data (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1)

#define	IDX_IO1_i_Error (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1)

#define	IDX_IO1_i_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1)

#define	IDX_IO1_i_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1)

#define	IDX_IO1_i_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1)

#define	IDX_IO1_i_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1)

#define	IDX_IO1_i_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1)

#define	IDX_IO1_i_Status (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1)

#define	IDX_IO1_o IDX_IO1_SZ

#define	IDX_IO1_o_SZ sizeof(IDE_REGISTERS_1)

#define	IDX_IO1_o_Data (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o)

#define	IDX_IO1_o_Feature (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o)

#define	IDX_IO1_o_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o)

#define	IDX_IO1_o_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o)

#define	IDX_IO1_o_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o)

#define	IDX_IO1_o_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o)

#define	IDX_IO1_o_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o)

#define	IDX_IO1_o_Command (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o)

#define	IDX_IO2 (IDX_IO1_o+IDX_IO1_o_SZ)

#define	IDX_IO2_SZ sizeof(IDE_REGISTERS_2)

#define	IDX_IO2_AltStatus (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2)

#define	IDX_IO2_o (IDX_IO2+IDX_IO2_SZ)

#define	IDX_IO2_o_SZ sizeof(IDE_REGISTERS_2)

#define	IDX_IO2_o_Control (FIELD_OFFSET(IDE_REGISTERS_2, Control)+IDX_IO2_o)

#define	DFLAGS_DEVICE_PRESENT 0x0001

#define	DFLAGS_ATAPI_DEVICE 0x0002

#define	DFLAGS_TAPE_DEVICE 0x0004

#define	DFLAGS_INT_DRQ 0x0008

#define	DFLAGS_REMOVABLE_DRIVE 0x0010

#define	DFLAGS_MEDIA_STATUS_ENABLED 0x0020

#define	DFLAGS_ATAPI_CHANGER 0x0040

#define	DFLAGS_SANYO_ATAPI_CHANGER 0x0080

#define	DFLAGS_CHANGER_INITED 0x0100

#define	DFLAGS_LBA_ENABLED 0x0200

#define	DFLAGS_DWORDIO_ENABLED 0x0400

#define	DFLAGS_WCACHE_ENABLED 0x0800

#define	DFLAGS_RCACHE_ENABLED 0x1000

#define	DFLAGS_ORIG_GEOMETRY 0x2000

#define	DFLAGS_REINIT_DMA 0x4000

#define	DFLAGS_HIDDEN 0x8000

#define	DFLAGS_MANUAL_CHS 0x10000

#define	DFLAGS_LBA32plus 0x20000

#define	MAX_ERRORS 4

#define	ATAPI_MODE_SENSE 0x5A

#define	ATAPI_MODE_SELECT 0x55

#define	ATAPI_FORMAT_UNIT 0x24

#define	ATA_PIO 0x00

#define	ATA_PIO_NRDY 0x01

#define	ATA_PIO0 0x08

#define	ATA_PIO1 0x09

#define	ATA_PIO2 0x0a

#define	ATA_PIO3 0x0b

#define	ATA_PIO4 0x0c

#define	ATA_PIO5 0x0d

#define	ATA_DMA 0x10

#define	ATA_SDMA 0x10

#define	ATA_SDMA0 0x10

#define	ATA_SDMA1 0x11

#define	ATA_SDMA2 0x12

#define	ATA_WDMA 0x20

#define	ATA_WDMA0 0x20

#define	ATA_WDMA1 0x21

#define	ATA_WDMA2 0x22

#define	ATA_UDMA 0x40

#define	ATA_UDMA0 0x40

#define	ATA_UDMA1 0x41

#define	ATA_UDMA2 0x42

#define	ATA_UDMA3 0x43

#define	ATA_UDMA4 0x44

#define	ATA_UDMA5 0x45

#define	ATA_UDMA6 0x46

#define	ATA_SA150 0x47 /0x80/

#define	ATA_SA300 0x48 /0x81/

#define	ATA_SA600 0x49 /0x82/

#define	ATA_MODE_NOT_SPEC ((ULONG)(-1)) /0x82/

#define	IDE_COMMAND_DATA_SET_MGMT 0x06

#define	IDE_COMMAND_ATAPI_RESET 0x08

#define	IDE_COMMAND_RECALIBRATE 0x10

#define	IDE_COMMAND_READ 0x20

#define	IDE_COMMAND_READ_NO_RETR 0x21

#define	IDE_COMMAND_READ48 0x24

#define	IDE_COMMAND_READ_DMA48 0x25

#define	IDE_COMMAND_READ_DMA_Q48 0x26

#define	IDE_COMMAND_READ_NATIVE_SIZE48 0x27

#define	IDE_COMMAND_READ_MUL48 0x29

#define	IDE_COMMAND_READ_STREAM_DMA48 0x2A

#define	IDE_COMMAND_READ_STREAM48 0x2B

#define	IDE_COMMAND_READ_LOG48 0x2f

#define	IDE_COMMAND_WRITE 0x30

#define	IDE_COMMAND_WRITE_NO_RETR 0x31

#define	IDE_COMMAND_WRITE48 0x34

#define	IDE_COMMAND_WRITE_DMA48 0x35

#define	IDE_COMMAND_WRITE_DMA_Q48 0x36

#define	IDE_COMMAND_SET_NATIVE_SIZE48 0x37

#define	IDE_COMMAND_WRITE_MUL48 0x39

#define	IDE_COMMAND_WRITE_STREAM_DMA48 0x3a

#define	IDE_COMMAND_WRITE_STREAM48 0x3b

#define	IDE_COMMAND_WRITE_FUA_DMA48 0x3d

#define	IDE_COMMAND_WRITE_FUA_DMA_Q48 0x3e

#define	IDE_COMMAND_WRITE_LOG48 0x3f

#define	IDE_COMMAND_VERIFY 0x40

#define	IDE_COMMAND_VERIFY48 0x42

#define	IDE_COMMAND_READ_LOG_DMA48 0x47

#define	IDE_COMMAND_WRITE_LOG_DMA48 0x57

#define	IDE_COMMAND_TRUSTED_RCV 0x5c

#define	IDE_COMMAND_TRUSTED_RCV_DMA 0x5d

#define	IDE_COMMAND_TRUSTED_SEND 0x5e

#define	IDE_COMMAND_TRUSTED_SEND_DMA 0x5f

#define	IDE_COMMAND_SEEK 0x70

#define	IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91

#define	IDE_COMMAND_ATAPI_PACKET 0xA0

#define	IDE_COMMAND_ATAPI_IDENTIFY 0xA1

#define	IDE_COMMAND_READ_MULTIPLE 0xC4

#define	IDE_COMMAND_WRITE_MULTIPLE 0xC5

#define	IDE_COMMAND_SET_MULTIPLE 0xC6

#define	IDE_COMMAND_READ_DMA_Q 0xC7

#define	IDE_COMMAND_READ_DMA 0xC8

#define	IDE_COMMAND_WRITE_DMA 0xCA

#define	IDE_COMMAND_WRITE_DMA_Q 0xCC

#define	IDE_COMMAND_WRITE_MUL_FUA48 0xCE

#define	IDE_COMMAND_GET_MEDIA_STATUS 0xDA

#define	IDE_COMMAND_DOOR_LOCK 0xDE

#define	IDE_COMMAND_DOOR_UNLOCK 0xDF

#define	IDE_COMMAND_STANDBY_IMMED 0xE0

#define	IDE_COMMAND_IDLE_IMMED 0xE1

#define	IDE_COMMAND_STANDBY 0xE2

#define	IDE_COMMAND_IDLE 0xE3

#define	IDE_COMMAND_READ_PM 0xE4

#define	IDE_COMMAND_SLEEP 0xE6

#define	IDE_COMMAND_FLUSH_CACHE 0xE7

#define	IDE_COMMAND_WRITE_PM 0xE8

#define	IDE_COMMAND_IDENTIFY 0xEC

#define	IDE_COMMAND_MEDIA_EJECT 0xED

#define	IDE_COMMAND_FLUSH_CACHE48 0xEA

#define	IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF

#define	IDE_COMMAND_SET_FEATURES

#define	IDE_COMMAND_READ_NATIVE_SIZE 0xF8

#define	IDE_COMMAND_SET_NATIVE_SIZE 0xF9

#define	SCSIOP_ATA_PASSTHROUGH 0xCC

#define	IDE_STATUS_SUCCESS 0x00

#define	IDE_STATUS_ERROR 0x01

#define	IDE_STATUS_INDEX 0x02

#define	IDE_STATUS_CORRECTED_ERROR 0x04

#define	IDE_STATUS_DRQ 0x08

#define	IDE_STATUS_DSC 0x10

#define	IDE_STATUS_DMA 0x20 /* DMA ready */

#define	IDE_STATUS_DWF 0x20 /* drive write fault */

#define	IDE_STATUS_DRDY 0x40

#define	IDE_STATUS_IDLE 0x50

#define	IDE_STATUS_BUSY 0x80

#define	IDE_STATUS_WRONG 0xff

#define	IDE_STATUS_MASK 0xff

#define	IDE_DRIVE_SELECT 0xA0

#define	IDE_DRIVE_1 0x00

#define	IDE_DRIVE_2 0x10

#define	IDE_DRIVE_SELECT_1 (IDE_DRIVE_SELECT \| IDE_DRIVE_1)

#define	IDE_DRIVE_SELECT_2 (IDE_DRIVE_SELECT \| IDE_DRIVE_2)

#define	IDE_DRIVE_MASK (IDE_DRIVE_SELECT_1 \| IDE_DRIVE_SELECT_2)

#define	IDE_USE_LBA 0x40

#define	IDE_DC_DISABLE_INTERRUPTS 0x02

#define	IDE_DC_RESET_CONTROLLER 0x04

#define	IDE_DC_A_4BIT 0x80

#define	IDE_DC_USE_HOB 0x80

#define	IDE_DC_REENABLE_CONTROLLER 0x00

#define	IDE_ERROR_ICRC 0x80

#define	IDE_ERROR_BAD_BLOCK 0x80

#define	IDE_ERROR_DATA_ERROR 0x40

#define	IDE_ERROR_MEDIA_CHANGE 0x20

#define	IDE_ERROR_ID_NOT_FOUND 0x10

#define	IDE_ERROR_MEDIA_CHANGE_REQ 0x08

#define	IDE_ERROR_COMMAND_ABORTED 0x04

#define	IDE_ERROR_END_OF_MEDIA 0x02

#define	IDE_ERROR_NO_MEDIA 0x02

#define	IDE_ERROR_ILLEGAL_LENGTH 0x01

#define	IDX_ATAPI_IO1 IDX_IO1

#define	IDX_ATAPI_IO1_SZ sizeof(ATAPI_REGISTERS_1)

#define	IDX_ATAPI_IO1_i_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_i_Error (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_i_InterruptReason (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_i_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_i_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_i_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_i_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_i_Status (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_Feature (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_Unused0 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1)

#define	IDX_ATAPI_IO1_o_Command (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1)

#define	ATAPI_IR_COD 0x01

#define	ATAPI_IR_COD_Data 0x0

#define	ATAPI_IR_COD_Cmd 0x1

#define	ATAPI_IR_IO 0x02

#define	ATAPI_IR_IO_toDev 0x00

#define	ATAPI_IR_IO_toHost 0x02

#define	ATAPI_IR_Mask 0x03

#define	ATA_F_DMA 0x01 /* enable DMA */

#define	ATA_F_OVL 0x02 /* enable overlap */

#define	ATA_F_DMAREAD 0x04 /* DMA Packet (ATAPI) read */

#define	ATA_C_F_SETXFER 0x03 /* set transfer mode */

#define	ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */

#define	ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */

#define	ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */

#define	ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */

#define	ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */

#define	ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */

#define	ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */

#define	ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */

#define	ATA_C_F_ENAB_MEDIASTAT 0x95 /* enable media status */

#define	ATA_C_F_DIS_MEDIASTAT 0x31 /* disable media status */

#define	ATA_C_F_ENAB_APM 0x05 /* enable advanced power management */

#define	ATA_C_F_DIS_APM 0x85 /* disable advanced power management */

#define	ATA_C_F_APM_CNT_MAX_PERF 0xfe /* maximum performance */

#define	ATA_C_F_APM_CNT_MIN_NO_STANDBY 0x80 /* min. power w/o standby */

#define	ATA_C_F_APM_CNT_MIN_STANDBY 0x01 /* min. power with standby */

#define	ATA_C_F_ENAB_ACOUSTIC 0x42 /* enable acoustic management */

#define	ATA_C_F_DIS_ACOUSTIC 0xc2 /* disable acoustic management */

#define	ATA_C_F_AAM_CNT_MAX_PERF 0xfe /* maximum performance */

#define	ATA_C_F_AAM_CNT_MAX_POWER_SAVE 0x80 /* min. power */

#define	READ_LOG_SECTOR 0xD5

#define	WRITE_LOG_SECTOR 0xD6

#define	WRITE_THRESHOLDS 0xD7

#define	AUTO_OFFLINE 0xDB

#define	ATA_I_CMD 0x01 /* cmd (1) \| data (0) */

#define	ATA_I_IN 0x02 /* read (1) \| write (0) */

#define	ATA_I_RELEASE 0x04 /* released bus (1) */

#define	ATA_I_TAGMASK 0xf8 /* tag mask */

#define	ATAPI_PSIZE_12 0 /* 12 bytes */

#define	ATAPI_PSIZE_16 1 /* 16 bytes */

#define	ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */

#define	ATAPI_DRQT_INTR 1 /* intr 10 ms delay */

#define	ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */

#define	ATAPI_TYPE_DIRECT 0 /* disk/floppy */

#define	ATAPI_TYPE_TAPE 1 /* streaming tape */

#define	ATAPI_TYPE_CDROM 5 /* CD-ROM device */

#define	ATAPI_TYPE_OPTICAL 7 /* optical disk */

#define	ATAPI_PROTO_ATAPI 2

#define	ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */

#define	ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */

#define	ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */

#define	AdvancedPIOModes_3 1

#define	AdvancedPIOModes_4 2

#define	AdvancedPIOModes_5 4

#define	ATA_SATA_GEN1 0x0002

#define	ATA_SATA_GEN2 0x0004

#define	ATA_SATA_GEN3 0x0008

#define	ATA_SUPPORT_NCQ 0x0100

#define	ATA_SUPPORT_IFPWRMNGTRCV 0x0200

#define	ATA_SUPPORT_PHY_EVENT_COUNTER 0x0400

#define	ATA_SUPPORT_NCQ_UNLOAD 0x0800

#define	ATA_SUPPORT_NCQ_PRI_INFO 0x1000

#define	ATA_SUPPORT_NONZERO 0x0002

#define	ATA_SUPPORT_AUTOACTIVATE 0x0004

#define	ATA_SUPPORT_IFPWRMNGT 0x0008

#define	ATA_SUPPORT_INORDERDATA 0x0010

#define	ATA_VER_MJ_ATA4 0x0010

#define	ATA_VER_MJ_ATA5 0x0020

#define	ATA_VER_MJ_ATA6 0x0040

#define	ATA_VER_MJ_ATA7 0x0080

#define	ATA_VER_MJ_ATA8_ASC 0x0100

#define	IDENTIFY_CABLE_ID_VALID 0x01

#define	ATA_ChecksumValid 0xA5

#define	IDENTIFY_DATA2 IDENTIFY_DATA

#define	PIDENTIFY_DATA2 PIDENTIFY_DATA

#define	IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)

#define	IDENTIFY_DMA_CYCLES_MODE_0 0x00

#define	IDENTIFY_DMA_CYCLES_MODE_1 0x01

#define	IDENTIFY_DMA_CYCLES_MODE_2 0x02

#define	GetStatus(chan, Status) Status = AtapiReadPort1(chan, IDX_IO2_AltStatus);

#define	GetBaseStatus(chan, pStatus) pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status);

#define	WriteCommand(chan, _Command) AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);

#define	ReadBuffer(chan, Buffer, Count, timing)

#define	WriteBuffer(chan, Buffer, Count, timing)

#define	ReadBuffer2(chan, Buffer, Count, timing)

#define	WriteBuffer2(chan, Buffer, Count, timing)

#define	IS_RDP(OperationCode)

#define	AtapiCopyMemory RtlCopyMemory

#define	AtapiStringCmp(s1, s2, n) _strnicmp(s1, s2, n)

#define	INTERRUPT_REASON_IGNORE 0

#define	INTERRUPT_REASON_OUR 1

#define	INTERRUPT_REASON_UNEXPECTED 2

#define	UNIATA_FIND_DEV_UNHIDE 0x01

#define	CHAN_NOT_SPECIFIED (0xffffffffL)

#define	CHAN_NOT_SPECIFIED_CHECK_CABLE (0xfffffffeL)

#define	DEVNUM_NOT_SPECIFIED (0xffffffffL)

#define	IOMODE_NOT_SPECIFIED (0xffffffffL)

#define	ATA_AT_HOME_HDD 0x01

#define	ATA_AT_HOME_ATAPI 0x02

#define	ATA_AT_HOME_XXX 0x04

#define	ATA_AT_HOME_NOBODY 0x00

#define	ATA_CMD_FLAG_LBAIOsupp 0x01

#define	ATA_CMD_FLAG_48supp 0x02

#define	ATA_CMD_FLAG_48 0x04

#define	ATA_CMD_FLAG_DMA 0x08

#define	ATA_CMD_FLAG_FUA 0x10

#define	ATA_CMD_FLAG_In 0x40

#define	ATA_CMD_FLAG_Out 0x80

#define	UniAta_need_lba48(command, lba, count, supp48)

#define	UniAtaClearAtaReq(AtaReq)

#define	ATAPI_DEVICE(chan, dev) ((chan->lun[dev]->DeviceFlags & DFLAGS_ATAPI_DEVICE) ? TRUE : FALSE)

#define	PrintNtConsole(x) {;}

#define	IDENT_MODE_MAX FALSE

#define	IDENT_MODE_ACTIVE TRUE

Typedefs
typedef union _IDE_REGISTERS_1	IDE_REGISTERS_1

typedef union _IDE_REGISTERS_1 *	PIDE_REGISTERS_1

typedef union _IDE_REGISTERS_2	IDE_REGISTERS_2

typedef union _IDE_REGISTERS_2 *	PIDE_REGISTERS_2

typedef struct _MODE_SENSE_10	MODE_SENSE_10

typedef struct _MODE_SENSE_10 *	PMODE_SENSE_10

typedef struct _MODE_SELECT_10	MODE_SELECT_10

typedef struct _MODE_SELECT_10 *	PMODE_SELECT_10

typedef struct _MODE_PARAMETER_HEADER_10	MODE_PARAMETER_HEADER_10

typedef struct _MODE_PARAMETER_HEADER_10 *	PMODE_PARAMETER_HEADER_10

typedef union _ATAPI_REGISTERS_1	ATAPI_REGISTERS_1

typedef union _ATAPI_REGISTERS_1 *	PATAPI_REGISTERS_1

typedef struct _IDENTIFY_DATA	IDENTIFY_DATA

typedef struct _IDENTIFY_DATA *	PIDENTIFY_DATA

typedef struct _TRIM_DATA	TRIM_DATA

typedef struct _TRIM_DATA *	PTRIM_DATA

Functions
UCHAR DDKFASTAPI	SelectDrive (IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)

UCHAR DDKFASTAPI	WaitOnBusy (IN struct _HW_CHANNEL *chan)

UCHAR DDKFASTAPI	WaitOnBusyLong (IN struct _HW_CHANNEL *chan)

UCHAR DDKFASTAPI	WaitOnBaseBusy (IN struct _HW_CHANNEL *chan)

UCHAR DDKFASTAPI	WaitOnBaseBusyLong (IN struct _HW_CHANNEL *chan)

UCHAR DDKFASTAPI	WaitForDrq (IN struct _HW_CHANNEL *chan)

UCHAR DDKFASTAPI	WaitShortForDrq (IN struct _HW_CHANNEL *chan)

VOID DDKFASTAPI	AtapiSoftReset (IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)

VOID DDKFASTAPI	AtapiHardReset (IN struct _HW_CHANNEL *chan, IN BOOLEAN DisableInterrupts, IN ULONG Delay)

PSCSI_REQUEST_BLOCK NTAPI	BuildMechanismStatusSrb (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)

PSCSI_REQUEST_BLOCK NTAPI	BuildRequestSenseSrb (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)

VOID NTAPI	AtapiHwInitializeChanger (IN PVOID HwDeviceExtension, IN ULONG TargetId, IN PMECHANICAL_STATUS_INFORMATION_HEADER MechanismStatus)

ULONG NTAPI	AtapiSendCommand (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb, IN ULONG CmdAction)

ULONG NTAPI	IdeSendCommand (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb, IN ULONG CmdAction)

VOID NTAPI	AtapiHexToString (ULONG Value, PCHAR *Buffer)

BOOLEAN NTAPI	AtapiInterrupt (IN PVOID HwDeviceExtension)

BOOLEAN NTAPI	AtapiInterrupt__ (IN PVOID HwDeviceExtension, IN UCHAR c)

UCHAR NTAPI	AtapiCheckInterrupt__ (IN PVOID HwDeviceExtension, IN UCHAR c)

BOOLEAN NTAPI	AtapiHwInitialize (IN PVOID HwDeviceExtension)

ULONG NTAPI	IdeBuildSenseBuffer (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)

VOID NTAPI	IdeMediaStatus (BOOLEAN EnableMSN, IN PVOID HwDeviceExtension, IN ULONG lChannel, IN ULONG DeviceNumber)

ULONG NTAPI	AtapiFindIsaController (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)

ULONG NTAPI	AtapiReadArgumentString (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)

ULONG NTAPI	AtapiParseArgumentString (IN PCCH String, IN PCCH KeyWord)

BOOLEAN NTAPI	IssueIdentify (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG Channel, IN UCHAR Command, IN BOOLEAN NoSetup)

BOOLEAN NTAPI	SetDriveParameters (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG Channel)

ULONG NTAPI	CheckDevice (IN PVOID HwDeviceExtension, IN ULONG Channel, IN ULONG deviceNumber, IN BOOLEAN ResetBus)

BOOLEAN NTAPI	FindDevices (IN PVOID HwDeviceExtension, IN ULONG Flags, IN ULONG Channel)

BOOLEAN NTAPI	AtapiResetController (IN PVOID HwDeviceExtension, IN ULONG PathId)

BOOLEAN NTAPI	AtapiStartIo (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb)

BOOLEAN NTAPI	AtapiStartIo__ (IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb, IN BOOLEAN TopLevel)

UCHAR NTAPI	AtaCommand48 (IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN ULONG DeviceNumber, IN ULONG Channel, IN UCHAR command, IN ULONGLONG lba, IN USHORT count, IN USHORT feature, IN ULONG flags)

UCHAR NTAPI	AtaCommand (IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN ULONG DeviceNumber, IN ULONG Channel, IN UCHAR command, IN USHORT cylinder, IN UCHAR head, IN UCHAR sector, IN UCHAR count, IN UCHAR feature, IN ULONG flags)

LONG NTAPI	AtaPioMode (PIDENTIFY_DATA2 ident)

LONG NTAPI	AtaWmode (PIDENTIFY_DATA2 ident)

LONG NTAPI	AtaUmode (PIDENTIFY_DATA2 ident)

VOID NTAPI	AtapiDpcDispatch (IN PKDPC Dpc, IN PVOID DeferredContext, IN PVOID SystemArgument1, IN PVOID SystemArgument2)

LONG NTAPI	AtaPio2Mode (LONG pio)

VOID NTAPI	AtapiEnableInterrupts (IN PVOID HwDeviceExtension, IN ULONG c)

VOID NTAPI	AtapiDisableInterrupts (IN PVOID HwDeviceExtension, IN ULONG c)

VOID	UniataExpectChannelInterrupt (IN struct _HW_CHANNEL *chan, IN BOOLEAN Expecting)

ULONG NTAPI	AtapiRegCheckDevValue (IN PVOID HwDeviceExtension, IN ULONG chan, IN ULONG dev, IN PCWSTR Name, IN ULONG Default)

ULONG NTAPI	AtapiRegCheckParameterValue (IN PVOID HwDeviceExtension, IN PCWSTR PathSuffix, IN PCWSTR Name, IN ULONG Default)

VOID _cdecl	_PrintNtConsole (PCCH DebugMessage,...)

VOID NTAPI	UniataInitMapBM (IN struct _HW_DEVICE_EXTENSION deviceExtension, IN struct _IDE_BUSMASTER_REGISTERS BaseIoAddressBM_0, IN BOOLEAN MemIo)

VOID NTAPI	UniataInitMapBase (IN struct _HW_CHANNEL *chan, IN PIDE_REGISTERS_1 BaseIoAddress1, IN PIDE_REGISTERS_2 BaseIoAddress2)

VOID NTAPI	UniataInitSyncBaseIO (IN struct _HW_CHANNEL *chan)

VOID	UniataInitIoRes (IN struct _HW_CHANNEL *chan, IN ULONG idx, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)

VOID	UniataInitIoResEx (IN struct _IORES *IoRes, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)

UCHAR DDKFASTAPI	UniataIsIdle (IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN UCHAR Status)

VOID NTAPI	UniataDumpATARegs (IN struct _HW_CHANNEL *chan)

ULONG NTAPI	EncodeVendorStr (OUT PWCHAR Buffer, IN PUCHAR Str, IN ULONG Length)

ULONGLONG NTAPI	UniAtaCalculateLBARegsBack (struct _HW_LU_EXTENSION *LunExt, ULONGLONG lba)

ULONG NTAPI	UniataAnybodyHome (IN PVOID HwDeviceExtension, IN ULONG Channel, IN ULONG deviceNumber)

__inline BOOLEAN	ata_is_sata (PIDENTIFY_DATA ident)

__inline LONG	ata_cur_mode_from_ident (PIDENTIFY_DATA ident, BOOLEAN Active)

Variables
ULONG	g_LogToDisplay

UCHAR const	AtaCommands48 [256]

UCHAR const	AtaCommandFlags [256]

Macro Definition Documentation

◆ AdvancedPIOModes_3

#define AdvancedPIOModes_3 1

Definition at line 726 of file atapi.h.

◆ AdvancedPIOModes_4

#define AdvancedPIOModes_4 2

Definition at line 727 of file atapi.h.

◆ AdvancedPIOModes_5

#define AdvancedPIOModes_5 4

Definition at line 728 of file atapi.h.

◆ ATA_AT_HOME_ATAPI

#define ATA_AT_HOME_ATAPI 0x02

Definition at line 1593 of file atapi.h.

◆ ATA_AT_HOME_HDD

#define ATA_AT_HOME_HDD 0x01

Definition at line 1592 of file atapi.h.

◆ ATA_AT_HOME_NOBODY

#define ATA_AT_HOME_NOBODY 0x00

Definition at line 1595 of file atapi.h.

◆ ATA_AT_HOME_XXX

#define ATA_AT_HOME_XXX 0x04

Definition at line 1594 of file atapi.h.

◆ ATA_BT_DUALPORTMULTI

#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */

Definition at line 642 of file atapi.h.

◆ ATA_BT_DUALPORTMULTICACHE

#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */

Definition at line 643 of file atapi.h.

◆ ATA_BT_SINGLEPORTSECTOR

#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */

Definition at line 641 of file atapi.h.

◆ ATA_C_F_AAM_CNT_MAX_PERF

#define ATA_C_F_AAM_CNT_MAX_PERF 0xfe /* maximum performance */

Definition at line 586 of file atapi.h.

◆ ATA_C_F_AAM_CNT_MAX_POWER_SAVE

#define ATA_C_F_AAM_CNT_MAX_POWER_SAVE 0x80 /* min. power */

Definition at line 587 of file atapi.h.

◆ ATA_C_F_APM_CNT_MAX_PERF

#define ATA_C_F_APM_CNT_MAX_PERF 0xfe /* maximum performance */

Definition at line 580 of file atapi.h.

◆ ATA_C_F_APM_CNT_MIN_NO_STANDBY

#define ATA_C_F_APM_CNT_MIN_NO_STANDBY 0x80 /* min. power w/o standby */

Definition at line 581 of file atapi.h.

◆ ATA_C_F_APM_CNT_MIN_STANDBY

#define ATA_C_F_APM_CNT_MIN_STANDBY 0x01 /* min. power with standby */

Definition at line 582 of file atapi.h.

◆ ATA_C_F_DIS_ACOUSTIC

#define ATA_C_F_DIS_ACOUSTIC 0xc2 /* disable acoustic management */

Definition at line 585 of file atapi.h.

◆ ATA_C_F_DIS_APM

#define ATA_C_F_DIS_APM 0x85 /* disable advanced power management */

Definition at line 579 of file atapi.h.

◆ ATA_C_F_DIS_MEDIASTAT

#define ATA_C_F_DIS_MEDIASTAT 0x31 /* disable media status */

Definition at line 576 of file atapi.h.

◆ ATA_C_F_DIS_RCACHE

#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */

Definition at line 567 of file atapi.h.

◆ ATA_C_F_DIS_RELIRQ

#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */

Definition at line 570 of file atapi.h.

◆ ATA_C_F_DIS_SRVIRQ

#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */

Definition at line 573 of file atapi.h.

◆ ATA_C_F_DIS_WCACHE

#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */

Definition at line 564 of file atapi.h.

◆ ATA_C_F_ENAB_ACOUSTIC

#define ATA_C_F_ENAB_ACOUSTIC 0x42 /* enable acoustic management */

Definition at line 584 of file atapi.h.

◆ ATA_C_F_ENAB_APM

#define ATA_C_F_ENAB_APM 0x05 /* enable advanced power management */

Definition at line 578 of file atapi.h.

◆ ATA_C_F_ENAB_MEDIASTAT

#define ATA_C_F_ENAB_MEDIASTAT 0x95 /* enable media status */

Definition at line 575 of file atapi.h.

◆ ATA_C_F_ENAB_RCACHE

#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */

Definition at line 566 of file atapi.h.

◆ ATA_C_F_ENAB_RELIRQ

#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */

Definition at line 569 of file atapi.h.

◆ ATA_C_F_ENAB_SRVIRQ

#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */

Definition at line 572 of file atapi.h.

◆ ATA_C_F_ENAB_WCACHE

#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */

Definition at line 563 of file atapi.h.

◆ ATA_C_F_SETXFER

#define ATA_C_F_SETXFER 0x03 /* set transfer mode */

Definition at line 561 of file atapi.h.

◆ ATA_ChecksumValid

#define ATA_ChecksumValid 0xA5

Definition at line 978 of file atapi.h.

◆ ATA_CMD_FLAG_48

#define ATA_CMD_FLAG_48 0x04

Definition at line 1599 of file atapi.h.

◆ ATA_CMD_FLAG_48supp

#define ATA_CMD_FLAG_48supp 0x02

Definition at line 1598 of file atapi.h.

◆ ATA_CMD_FLAG_DMA

#define ATA_CMD_FLAG_DMA 0x08

Definition at line 1600 of file atapi.h.

◆ ATA_CMD_FLAG_FUA

#define ATA_CMD_FLAG_FUA 0x10

Definition at line 1601 of file atapi.h.

◆ ATA_CMD_FLAG_In

#define ATA_CMD_FLAG_In 0x40

Definition at line 1602 of file atapi.h.

◆ ATA_CMD_FLAG_LBAIOsupp

#define ATA_CMD_FLAG_LBAIOsupp 0x01

Definition at line 1597 of file atapi.h.

◆ ATA_CMD_FLAG_Out

#define ATA_CMD_FLAG_Out 0x80

Definition at line 1603 of file atapi.h.

◆ ATA_DMA

#define ATA_DMA 0x10

Definition at line 316 of file atapi.h.

◆ ATA_F_DMA

#define ATA_F_DMA 0x01 /* enable DMA */

Definition at line 557 of file atapi.h.

◆ ATA_F_DMAREAD

#define ATA_F_DMAREAD 0x04 /* DMA Packet (ATAPI) read */

Definition at line 559 of file atapi.h.

◆ ATA_F_OVL

#define ATA_F_OVL 0x02 /* enable overlap */

Definition at line 558 of file atapi.h.

◆ ATA_I_CMD

#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */

Definition at line 601 of file atapi.h.

◆ ATA_I_IN

#define ATA_I_IN 0x02 /* read (1) | write (0) */

Definition at line 602 of file atapi.h.

◆ ATA_I_RELEASE

#define ATA_I_RELEASE 0x04 /* released bus (1) */

Definition at line 603 of file atapi.h.

◆ ATA_I_TAGMASK

#define ATA_I_TAGMASK 0xf8 /* tag mask */

Definition at line 604 of file atapi.h.

◆ ATA_MODE_NOT_SPEC

#define ATA_MODE_NOT_SPEC ((ULONG)(-1)) /*0x82*/

Definition at line 341 of file atapi.h.

◆ ATA_PIO

#define ATA_PIO 0x00

Definition at line 306 of file atapi.h.

◆ ATA_PIO0

#define ATA_PIO0 0x08

Definition at line 309 of file atapi.h.

◆ ATA_PIO1

#define ATA_PIO1 0x09

Definition at line 310 of file atapi.h.

◆ ATA_PIO2

#define ATA_PIO2 0x0a

Definition at line 311 of file atapi.h.

◆ ATA_PIO3

#define ATA_PIO3 0x0b

Definition at line 312 of file atapi.h.

◆ ATA_PIO4

#define ATA_PIO4 0x0c

Definition at line 313 of file atapi.h.

◆ ATA_PIO5

#define ATA_PIO5 0x0d

Definition at line 314 of file atapi.h.

◆ ATA_PIO_NRDY

#define ATA_PIO_NRDY 0x01

Definition at line 307 of file atapi.h.

◆ ATA_SA150

#define ATA_SA150 0x47 /*0x80*/

Definition at line 337 of file atapi.h.

◆ ATA_SA300

#define ATA_SA300 0x48 /*0x81*/

Definition at line 338 of file atapi.h.

◆ ATA_SA600

#define ATA_SA600 0x49 /*0x82*/

Definition at line 339 of file atapi.h.

◆ ATA_SATA_GEN1

#define ATA_SATA_GEN1 0x0002

Definition at line 757 of file atapi.h.

◆ ATA_SATA_GEN2

#define ATA_SATA_GEN2 0x0004

Definition at line 758 of file atapi.h.

◆ ATA_SATA_GEN3

#define ATA_SATA_GEN3 0x0008

Definition at line 759 of file atapi.h.

◆ ATA_SDMA

#define ATA_SDMA 0x10

Definition at line 317 of file atapi.h.

◆ ATA_SDMA0

#define ATA_SDMA0 0x10

Definition at line 318 of file atapi.h.

◆ ATA_SDMA1

#define ATA_SDMA1 0x11

Definition at line 319 of file atapi.h.

◆ ATA_SDMA2

#define ATA_SDMA2 0x12

Definition at line 320 of file atapi.h.

◆ ATA_SUPPORT_AUTOACTIVATE

#define ATA_SUPPORT_AUTOACTIVATE 0x0004

Definition at line 770 of file atapi.h.

◆ ATA_SUPPORT_IFPWRMNGT

#define ATA_SUPPORT_IFPWRMNGT 0x0008

Definition at line 771 of file atapi.h.

◆ ATA_SUPPORT_IFPWRMNGTRCV

#define ATA_SUPPORT_IFPWRMNGTRCV 0x0200

Definition at line 761 of file atapi.h.

◆ ATA_SUPPORT_INORDERDATA

#define ATA_SUPPORT_INORDERDATA 0x0010

Definition at line 772 of file atapi.h.

◆ ATA_SUPPORT_NCQ

#define ATA_SUPPORT_NCQ 0x0100

Definition at line 760 of file atapi.h.

◆ ATA_SUPPORT_NCQ_PRI_INFO

#define ATA_SUPPORT_NCQ_PRI_INFO 0x1000

Definition at line 764 of file atapi.h.

◆ ATA_SUPPORT_NCQ_UNLOAD

#define ATA_SUPPORT_NCQ_UNLOAD 0x0800

Definition at line 763 of file atapi.h.

◆ ATA_SUPPORT_NONZERO

#define ATA_SUPPORT_NONZERO 0x0002

Definition at line 769 of file atapi.h.

◆ ATA_SUPPORT_PHY_EVENT_COUNTER

#define ATA_SUPPORT_PHY_EVENT_COUNTER 0x0400

Definition at line 762 of file atapi.h.

◆ ATA_UDMA

#define ATA_UDMA 0x40

Definition at line 327 of file atapi.h.

◆ ATA_UDMA0

#define ATA_UDMA0 0x40

Definition at line 328 of file atapi.h.

◆ ATA_UDMA1

#define ATA_UDMA1 0x41

Definition at line 329 of file atapi.h.

◆ ATA_UDMA2

#define ATA_UDMA2 0x42

Definition at line 330 of file atapi.h.

◆ ATA_UDMA3

#define ATA_UDMA3 0x43

Definition at line 331 of file atapi.h.

◆ ATA_UDMA4

#define ATA_UDMA4 0x44

Definition at line 332 of file atapi.h.

◆ ATA_UDMA5

#define ATA_UDMA5 0x45

Definition at line 333 of file atapi.h.

◆ ATA_UDMA6

#define ATA_UDMA6 0x46

Definition at line 334 of file atapi.h.

◆ ATA_VER_MJ_ATA4

#define ATA_VER_MJ_ATA4 0x0010

Definition at line 778 of file atapi.h.

◆ ATA_VER_MJ_ATA5

#define ATA_VER_MJ_ATA5 0x0020

Definition at line 779 of file atapi.h.

◆ ATA_VER_MJ_ATA6

#define ATA_VER_MJ_ATA6 0x0040

Definition at line 780 of file atapi.h.

◆ ATA_VER_MJ_ATA7

#define ATA_VER_MJ_ATA7 0x0080

Definition at line 781 of file atapi.h.

◆ ATA_VER_MJ_ATA8_ASC

#define ATA_VER_MJ_ATA8_ASC 0x0100

Definition at line 782 of file atapi.h.

◆ ATA_WDMA

#define ATA_WDMA 0x20

Definition at line 322 of file atapi.h.

◆ ATA_WDMA0

#define ATA_WDMA0 0x20

Definition at line 323 of file atapi.h.

◆ ATA_WDMA1

#define ATA_WDMA1 0x21

Definition at line 324 of file atapi.h.

◆ ATA_WDMA2

#define ATA_WDMA2 0x22

Definition at line 325 of file atapi.h.

◆ ATAPI_DEVICE

#define ATAPI_DEVICE	(	chan,
		dev
	)	((chan->lun[dev]->DeviceFlags & DFLAGS_ATAPI_DEVICE) ? TRUE : FALSE)

Definition at line 1624 of file atapi.h.

◆ ATAPI_DRQT_ACCEL

#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */

Definition at line 617 of file atapi.h.

◆ ATAPI_DRQT_INTR

#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */

Definition at line 616 of file atapi.h.

◆ ATAPI_DRQT_MPROC

#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */

Definition at line 615 of file atapi.h.

◆ ATAPI_FORMAT_UNIT

#define ATAPI_FORMAT_UNIT 0x24

Definition at line 270 of file atapi.h.

◆ ATAPI_IR_COD

#define ATAPI_IR_COD 0x01

Definition at line 543 of file atapi.h.

◆ ATAPI_IR_COD_Cmd

#define ATAPI_IR_COD_Cmd 0x1

Definition at line 545 of file atapi.h.

◆ ATAPI_IR_COD_Data

#define ATAPI_IR_COD_Data 0x0

Definition at line 544 of file atapi.h.

◆ ATAPI_IR_IO

#define ATAPI_IR_IO 0x02

Definition at line 547 of file atapi.h.

◆ ATAPI_IR_IO_toDev

#define ATAPI_IR_IO_toDev 0x00

Definition at line 548 of file atapi.h.

◆ ATAPI_IR_IO_toHost

#define ATAPI_IR_IO_toHost 0x02

Definition at line 549 of file atapi.h.

◆ ATAPI_IR_Mask

#define ATAPI_IR_Mask 0x03

Definition at line 551 of file atapi.h.

◆ ATAPI_MODE_SELECT

#define ATAPI_MODE_SELECT 0x55

Definition at line 269 of file atapi.h.

◆ ATAPI_MODE_SENSE

#define ATAPI_MODE_SENSE 0x5A

Definition at line 268 of file atapi.h.

◆ ATAPI_PROTO_ATAPI

#define ATAPI_PROTO_ATAPI 2

Definition at line 627 of file atapi.h.

◆ ATAPI_PSIZE_12

#define ATAPI_PSIZE_12 0 /* 12 bytes */

Definition at line 611 of file atapi.h.

◆ ATAPI_PSIZE_16

#define ATAPI_PSIZE_16 1 /* 16 bytes */

Definition at line 612 of file atapi.h.

◆ ATAPI_TYPE_CDROM

#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */

Definition at line 623 of file atapi.h.

◆ ATAPI_TYPE_DIRECT

#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */

Definition at line 621 of file atapi.h.

◆ ATAPI_TYPE_OPTICAL

#define ATAPI_TYPE_OPTICAL 7 /* optical disk */

Definition at line 624 of file atapi.h.

◆ ATAPI_TYPE_TAPE

#define ATAPI_TYPE_TAPE 1 /* streaming tape */

Definition at line 622 of file atapi.h.

◆ AtapiCopyMemory

#define AtapiCopyMemory RtlCopyMemory

Definition at line 1247 of file atapi.h.

◆ AtapiStallExecution

#define AtapiStallExecution ( dt ) ScsiPortStallExecution(dt)

Definition at line 158 of file atapi.h.

◆ AtapiStringCmp

#define AtapiStringCmp	(	s1,
		s2,
		n
	)	_strnicmp(s1, s2, n)

Definition at line 1256 of file atapi.h.

◆ AUTO_OFFLINE

#define AUTO_OFFLINE 0xDB

Definition at line 594 of file atapi.h.

◆ CHAN_NOT_SPECIFIED

#define CHAN_NOT_SPECIFIED (0xffffffffL)

Definition at line 1481 of file atapi.h.

◆ CHAN_NOT_SPECIFIED_CHECK_CABLE

#define CHAN_NOT_SPECIFIED_CHECK_CABLE (0xfffffffeL)

Definition at line 1482 of file atapi.h.

◆ Connect_DbgPrint

#define Connect_DbgPrint ( ) {;}

Definition at line 156 of file atapi.h.

◆ DEVNUM_NOT_SPECIFIED

#define DEVNUM_NOT_SPECIFIED (0xffffffffL)

Definition at line 1483 of file atapi.h.

◆ DFLAGS_ATAPI_CHANGER

#define DFLAGS_ATAPI_CHANGER 0x0040

Definition at line 244 of file atapi.h.

◆ DFLAGS_ATAPI_DEVICE

#define DFLAGS_ATAPI_DEVICE 0x0002

Definition at line 237 of file atapi.h.

◆ DFLAGS_CHANGER_INITED

#define DFLAGS_CHANGER_INITED 0x0100

Definition at line 246 of file atapi.h.

◆ DFLAGS_DEVICE_PRESENT

#define DFLAGS_DEVICE_PRESENT 0x0001

Definition at line 236 of file atapi.h.

◆ DFLAGS_DWORDIO_ENABLED

#define DFLAGS_DWORDIO_ENABLED 0x0400

Definition at line 248 of file atapi.h.

◆ DFLAGS_HIDDEN

#define DFLAGS_HIDDEN 0x8000

Definition at line 253 of file atapi.h.

◆ DFLAGS_INT_DRQ

#define DFLAGS_INT_DRQ 0x0008

Definition at line 239 of file atapi.h.

◆ DFLAGS_LBA32plus

#define DFLAGS_LBA32plus 0x20000

Definition at line 256 of file atapi.h.

◆ DFLAGS_LBA_ENABLED

#define DFLAGS_LBA_ENABLED 0x0200

Definition at line 247 of file atapi.h.

◆ DFLAGS_MANUAL_CHS

#define DFLAGS_MANUAL_CHS 0x10000

Definition at line 255 of file atapi.h.

◆ DFLAGS_MEDIA_STATUS_ENABLED

#define DFLAGS_MEDIA_STATUS_ENABLED 0x0020

Definition at line 243 of file atapi.h.

◆ DFLAGS_ORIG_GEOMETRY

#define DFLAGS_ORIG_GEOMETRY 0x2000

Definition at line 251 of file atapi.h.

◆ DFLAGS_RCACHE_ENABLED

#define DFLAGS_RCACHE_ENABLED 0x1000

Definition at line 250 of file atapi.h.

◆ DFLAGS_REINIT_DMA

#define DFLAGS_REINIT_DMA 0x4000

Definition at line 252 of file atapi.h.

◆ DFLAGS_REMOVABLE_DRIVE

#define DFLAGS_REMOVABLE_DRIVE 0x0010

Definition at line 241 of file atapi.h.

◆ DFLAGS_SANYO_ATAPI_CHANGER

#define DFLAGS_SANYO_ATAPI_CHANGER 0x0080

Definition at line 245 of file atapi.h.

◆ DFLAGS_TAPE_DEVICE

#define DFLAGS_TAPE_DEVICE 0x0004

Definition at line 238 of file atapi.h.

◆ DFLAGS_WCACHE_ENABLED

#define DFLAGS_WCACHE_ENABLED 0x0800

Definition at line 249 of file atapi.h.

◆ GetBaseStatus

#define GetBaseStatus	(	chan,
		pStatus
	)	pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status);

Definition at line 1092 of file atapi.h.

◆ GetStatus

#define GetStatus	(	chan,
		Status
	)	Status = AtapiReadPort1(chan, IDX_IO2_AltStatus);

Definition at line 1089 of file atapi.h.

◆ IDE_COMMAND_ATAPI_IDENTIFY

#define IDE_COMMAND_ATAPI_IDENTIFY 0xA1

Definition at line 383 of file atapi.h.

◆ IDE_COMMAND_ATAPI_PACKET

#define IDE_COMMAND_ATAPI_PACKET 0xA0

Definition at line 382 of file atapi.h.

◆ IDE_COMMAND_ATAPI_RESET

#define IDE_COMMAND_ATAPI_RESET 0x08

Definition at line 348 of file atapi.h.

◆ IDE_COMMAND_DATA_SET_MGMT

#define IDE_COMMAND_DATA_SET_MGMT 0x06

Definition at line 347 of file atapi.h.

◆ IDE_COMMAND_DOOR_LOCK

#define IDE_COMMAND_DOOR_LOCK 0xDE

Definition at line 393 of file atapi.h.

◆ IDE_COMMAND_DOOR_UNLOCK

#define IDE_COMMAND_DOOR_UNLOCK 0xDF

Definition at line 394 of file atapi.h.

◆ IDE_COMMAND_ENABLE_MEDIA_STATUS

#define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF

Definition at line 406 of file atapi.h.

◆ IDE_COMMAND_FLUSH_CACHE

#define IDE_COMMAND_FLUSH_CACHE 0xE7

Definition at line 401 of file atapi.h.

◆ IDE_COMMAND_FLUSH_CACHE48

#define IDE_COMMAND_FLUSH_CACHE48 0xEA

Definition at line 405 of file atapi.h.

◆ IDE_COMMAND_GET_MEDIA_STATUS

#define IDE_COMMAND_GET_MEDIA_STATUS 0xDA

Definition at line 392 of file atapi.h.

◆ IDE_COMMAND_IDENTIFY

#define IDE_COMMAND_IDENTIFY 0xEC

Definition at line 403 of file atapi.h.

◆ IDE_COMMAND_IDLE

#define IDE_COMMAND_IDLE 0xE3

Definition at line 398 of file atapi.h.

◆ IDE_COMMAND_IDLE_IMMED

#define IDE_COMMAND_IDLE_IMMED 0xE1

Definition at line 396 of file atapi.h.

◆ IDE_COMMAND_MEDIA_EJECT

#define IDE_COMMAND_MEDIA_EJECT 0xED

Definition at line 404 of file atapi.h.

◆ IDE_COMMAND_READ

#define IDE_COMMAND_READ 0x20

Definition at line 350 of file atapi.h.

◆ IDE_COMMAND_READ48

#define IDE_COMMAND_READ48 0x24

Definition at line 352 of file atapi.h.

◆ IDE_COMMAND_READ_DMA

#define IDE_COMMAND_READ_DMA 0xC8

Definition at line 388 of file atapi.h.

◆ IDE_COMMAND_READ_DMA48

#define IDE_COMMAND_READ_DMA48 0x25

Definition at line 353 of file atapi.h.

◆ IDE_COMMAND_READ_DMA_Q

#define IDE_COMMAND_READ_DMA_Q 0xC7

Definition at line 387 of file atapi.h.

◆ IDE_COMMAND_READ_DMA_Q48

#define IDE_COMMAND_READ_DMA_Q48 0x26

Definition at line 354 of file atapi.h.

◆ IDE_COMMAND_READ_LOG48

#define IDE_COMMAND_READ_LOG48 0x2f

Definition at line 359 of file atapi.h.

◆ IDE_COMMAND_READ_LOG_DMA48

#define IDE_COMMAND_READ_LOG_DMA48 0x47

Definition at line 374 of file atapi.h.

◆ IDE_COMMAND_READ_MUL48

#define IDE_COMMAND_READ_MUL48 0x29

Definition at line 356 of file atapi.h.

◆ IDE_COMMAND_READ_MULTIPLE

#define IDE_COMMAND_READ_MULTIPLE 0xC4

Definition at line 384 of file atapi.h.

◆ IDE_COMMAND_READ_NATIVE_SIZE

#define IDE_COMMAND_READ_NATIVE_SIZE 0xF8

Definition at line 408 of file atapi.h.

◆ IDE_COMMAND_READ_NATIVE_SIZE48

#define IDE_COMMAND_READ_NATIVE_SIZE48 0x27

Definition at line 355 of file atapi.h.

◆ IDE_COMMAND_READ_NO_RETR

#define IDE_COMMAND_READ_NO_RETR 0x21

Definition at line 351 of file atapi.h.

◆ IDE_COMMAND_READ_PM

#define IDE_COMMAND_READ_PM 0xE4

Definition at line 399 of file atapi.h.

◆ IDE_COMMAND_READ_STREAM48

#define IDE_COMMAND_READ_STREAM48 0x2B

Definition at line 358 of file atapi.h.

◆ IDE_COMMAND_READ_STREAM_DMA48

#define IDE_COMMAND_READ_STREAM_DMA48 0x2A

Definition at line 357 of file atapi.h.

◆ IDE_COMMAND_RECALIBRATE

#define IDE_COMMAND_RECALIBRATE 0x10

Definition at line 349 of file atapi.h.

◆ IDE_COMMAND_SEEK

#define IDE_COMMAND_SEEK 0x70

Definition at line 380 of file atapi.h.

◆ IDE_COMMAND_SET_DRIVE_PARAMETERS

#define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91

Definition at line 381 of file atapi.h.

◆ IDE_COMMAND_SET_FEATURES

#define IDE_COMMAND_SET_FEATURES

Value:

0xEF /* features command,

IDE_COMMAND_ENABLE_MEDIA_STATUS */

Definition at line 407 of file atapi.h.

◆ IDE_COMMAND_SET_MULTIPLE

#define IDE_COMMAND_SET_MULTIPLE 0xC6

Definition at line 386 of file atapi.h.

◆ IDE_COMMAND_SET_NATIVE_SIZE

#define IDE_COMMAND_SET_NATIVE_SIZE 0xF9

Definition at line 409 of file atapi.h.

◆ IDE_COMMAND_SET_NATIVE_SIZE48

#define IDE_COMMAND_SET_NATIVE_SIZE48 0x37

Definition at line 365 of file atapi.h.

◆ IDE_COMMAND_SLEEP

#define IDE_COMMAND_SLEEP 0xE6

Definition at line 400 of file atapi.h.

◆ IDE_COMMAND_STANDBY

#define IDE_COMMAND_STANDBY 0xE2

Definition at line 397 of file atapi.h.

◆ IDE_COMMAND_STANDBY_IMMED

#define IDE_COMMAND_STANDBY_IMMED 0xE0

Definition at line 395 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_RCV

#define IDE_COMMAND_TRUSTED_RCV 0x5c

Definition at line 376 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_RCV_DMA

#define IDE_COMMAND_TRUSTED_RCV_DMA 0x5d

Definition at line 377 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_SEND

#define IDE_COMMAND_TRUSTED_SEND 0x5e

Definition at line 378 of file atapi.h.

◆ IDE_COMMAND_TRUSTED_SEND_DMA

#define IDE_COMMAND_TRUSTED_SEND_DMA 0x5f

Definition at line 379 of file atapi.h.

◆ IDE_COMMAND_VERIFY

#define IDE_COMMAND_VERIFY 0x40

Definition at line 372 of file atapi.h.

◆ IDE_COMMAND_VERIFY48

#define IDE_COMMAND_VERIFY48 0x42

Definition at line 373 of file atapi.h.

◆ IDE_COMMAND_WRITE

#define IDE_COMMAND_WRITE 0x30

Definition at line 360 of file atapi.h.

◆ IDE_COMMAND_WRITE48

#define IDE_COMMAND_WRITE48 0x34

Definition at line 362 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA

#define IDE_COMMAND_WRITE_DMA 0xCA

Definition at line 389 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA48

#define IDE_COMMAND_WRITE_DMA48 0x35

Definition at line 363 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA_Q

#define IDE_COMMAND_WRITE_DMA_Q 0xCC

Definition at line 390 of file atapi.h.

◆ IDE_COMMAND_WRITE_DMA_Q48

#define IDE_COMMAND_WRITE_DMA_Q48 0x36

Definition at line 364 of file atapi.h.

◆ IDE_COMMAND_WRITE_FUA_DMA48

#define IDE_COMMAND_WRITE_FUA_DMA48 0x3d

Definition at line 369 of file atapi.h.

◆ IDE_COMMAND_WRITE_FUA_DMA_Q48

#define IDE_COMMAND_WRITE_FUA_DMA_Q48 0x3e

Definition at line 370 of file atapi.h.

◆ IDE_COMMAND_WRITE_LOG48

#define IDE_COMMAND_WRITE_LOG48 0x3f

Definition at line 371 of file atapi.h.

◆ IDE_COMMAND_WRITE_LOG_DMA48

#define IDE_COMMAND_WRITE_LOG_DMA48 0x57

Definition at line 375 of file atapi.h.

◆ IDE_COMMAND_WRITE_MUL48

#define IDE_COMMAND_WRITE_MUL48 0x39

Definition at line 366 of file atapi.h.

◆ IDE_COMMAND_WRITE_MUL_FUA48

#define IDE_COMMAND_WRITE_MUL_FUA48 0xCE

Definition at line 391 of file atapi.h.

◆ IDE_COMMAND_WRITE_MULTIPLE

#define IDE_COMMAND_WRITE_MULTIPLE 0xC5

Definition at line 385 of file atapi.h.

◆ IDE_COMMAND_WRITE_NO_RETR

#define IDE_COMMAND_WRITE_NO_RETR 0x31

Definition at line 361 of file atapi.h.

◆ IDE_COMMAND_WRITE_PM

#define IDE_COMMAND_WRITE_PM 0xE8

Definition at line 402 of file atapi.h.

◆ IDE_COMMAND_WRITE_STREAM48

#define IDE_COMMAND_WRITE_STREAM48 0x3b

Definition at line 368 of file atapi.h.

◆ IDE_COMMAND_WRITE_STREAM_DMA48

#define IDE_COMMAND_WRITE_STREAM_DMA48 0x3a

Definition at line 367 of file atapi.h.

◆ IDE_DC_A_4BIT

#define IDE_DC_A_4BIT 0x80

Definition at line 453 of file atapi.h.

◆ IDE_DC_DISABLE_INTERRUPTS

#define IDE_DC_DISABLE_INTERRUPTS 0x02

Definition at line 451 of file atapi.h.

◆ IDE_DC_REENABLE_CONTROLLER

#define IDE_DC_REENABLE_CONTROLLER 0x00

Definition at line 455 of file atapi.h.

◆ IDE_DC_RESET_CONTROLLER

#define IDE_DC_RESET_CONTROLLER 0x04

Definition at line 452 of file atapi.h.

◆ IDE_DC_USE_HOB

#define IDE_DC_USE_HOB 0x80

Definition at line 454 of file atapi.h.

◆ IDE_DRIVE_1

#define IDE_DRIVE_1 0x00

Definition at line 439 of file atapi.h.

◆ IDE_DRIVE_2

#define IDE_DRIVE_2 0x10

Definition at line 440 of file atapi.h.

◆ IDE_DRIVE_MASK

#define IDE_DRIVE_MASK (IDE_DRIVE_SELECT_1 | IDE_DRIVE_SELECT_2)

Definition at line 443 of file atapi.h.

◆ IDE_DRIVE_SELECT

#define IDE_DRIVE_SELECT 0xA0

Definition at line 438 of file atapi.h.

◆ IDE_DRIVE_SELECT_1

#define IDE_DRIVE_SELECT_1 (IDE_DRIVE_SELECT | IDE_DRIVE_1)

Definition at line 441 of file atapi.h.

◆ IDE_DRIVE_SELECT_2

#define IDE_DRIVE_SELECT_2 (IDE_DRIVE_SELECT | IDE_DRIVE_2)

Definition at line 442 of file atapi.h.

◆ IDE_ERROR_BAD_BLOCK

#define IDE_ERROR_BAD_BLOCK 0x80

Definition at line 461 of file atapi.h.

◆ IDE_ERROR_COMMAND_ABORTED

#define IDE_ERROR_COMMAND_ABORTED 0x04

Definition at line 466 of file atapi.h.

◆ IDE_ERROR_DATA_ERROR

#define IDE_ERROR_DATA_ERROR 0x40

Definition at line 462 of file atapi.h.

◆ IDE_ERROR_END_OF_MEDIA

#define IDE_ERROR_END_OF_MEDIA 0x02

Definition at line 467 of file atapi.h.

◆ IDE_ERROR_ICRC

#define IDE_ERROR_ICRC 0x80

Definition at line 460 of file atapi.h.

◆ IDE_ERROR_ID_NOT_FOUND

#define IDE_ERROR_ID_NOT_FOUND 0x10

Definition at line 464 of file atapi.h.

◆ IDE_ERROR_ILLEGAL_LENGTH

#define IDE_ERROR_ILLEGAL_LENGTH 0x01

Definition at line 469 of file atapi.h.

◆ IDE_ERROR_MEDIA_CHANGE

#define IDE_ERROR_MEDIA_CHANGE 0x20

Definition at line 463 of file atapi.h.

◆ IDE_ERROR_MEDIA_CHANGE_REQ

#define IDE_ERROR_MEDIA_CHANGE_REQ 0x08

Definition at line 465 of file atapi.h.

◆ IDE_ERROR_NO_MEDIA

#define IDE_ERROR_NO_MEDIA 0x02

Definition at line 468 of file atapi.h.

◆ IDE_STATUS_BUSY

#define IDE_STATUS_BUSY 0x80

Definition at line 428 of file atapi.h.

◆ IDE_STATUS_CORRECTED_ERROR

#define IDE_STATUS_CORRECTED_ERROR 0x04

Definition at line 420 of file atapi.h.

◆ IDE_STATUS_DMA

#define IDE_STATUS_DMA 0x20 /* DMA ready */

Definition at line 424 of file atapi.h.

◆ IDE_STATUS_DRDY

#define IDE_STATUS_DRDY 0x40

Definition at line 426 of file atapi.h.

◆ IDE_STATUS_DRQ

#define IDE_STATUS_DRQ 0x08

Definition at line 421 of file atapi.h.

◆ IDE_STATUS_DSC

#define IDE_STATUS_DSC 0x10

Definition at line 422 of file atapi.h.

◆ IDE_STATUS_DWF

#define IDE_STATUS_DWF 0x20 /* drive write fault */

Definition at line 425 of file atapi.h.

◆ IDE_STATUS_ERROR

#define IDE_STATUS_ERROR 0x01

Definition at line 418 of file atapi.h.

◆ IDE_STATUS_IDLE

#define IDE_STATUS_IDLE 0x50

Definition at line 427 of file atapi.h.

◆ IDE_STATUS_INDEX

#define IDE_STATUS_INDEX 0x02

Definition at line 419 of file atapi.h.

◆ IDE_STATUS_MASK

#define IDE_STATUS_MASK 0xff

Definition at line 431 of file atapi.h.

◆ IDE_STATUS_SUCCESS

#define IDE_STATUS_SUCCESS 0x00

Definition at line 417 of file atapi.h.

◆ IDE_STATUS_WRONG

#define IDE_STATUS_WRONG 0xff

Definition at line 430 of file atapi.h.

◆ IDE_USE_LBA

#define IDE_USE_LBA 0x40

Definition at line 445 of file atapi.h.

◆ IDENT_MODE_ACTIVE

#define IDENT_MODE_ACTIVE TRUE

Definition at line 1644 of file atapi.h.

◆ IDENT_MODE_MAX

#define IDENT_MODE_MAX FALSE

Definition at line 1643 of file atapi.h.

◆ IDENTIFY_CABLE_ID_VALID

#define IDENTIFY_CABLE_ID_VALID 0x01

Definition at line 844 of file atapi.h.

◆ IDENTIFY_DATA2

#define IDENTIFY_DATA2 IDENTIFY_DATA

Definition at line 989 of file atapi.h.

◆ IDENTIFY_DATA_SIZE

#define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)

Definition at line 1033 of file atapi.h.

◆ IDENTIFY_DMA_CYCLES_MODE_0

#define IDENTIFY_DMA_CYCLES_MODE_0 0x00

Definition at line 1037 of file atapi.h.

◆ IDENTIFY_DMA_CYCLES_MODE_1

#define IDENTIFY_DMA_CYCLES_MODE_1 0x01

Definition at line 1038 of file atapi.h.

◆ IDENTIFY_DMA_CYCLES_MODE_2

#define IDENTIFY_DMA_CYCLES_MODE_2 0x02

Definition at line 1039 of file atapi.h.

◆ IDX_ATAPI_IO1

#define IDX_ATAPI_IO1 IDX_IO1

Definition at line 502 of file atapi.h.

◆ IDX_ATAPI_IO1_i_ByteCountHigh

#define IDX_ATAPI_IO1_i_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1)

Definition at line 510 of file atapi.h.

◆ IDX_ATAPI_IO1_i_ByteCountLow

#define IDX_ATAPI_IO1_i_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1)

Definition at line 509 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Data

#define IDX_ATAPI_IO1_i_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1)

Definition at line 505 of file atapi.h.

◆ IDX_ATAPI_IO1_i_DriveSelect

#define IDX_ATAPI_IO1_i_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1)

Definition at line 511 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Error

#define IDX_ATAPI_IO1_i_Error (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1)

Definition at line 506 of file atapi.h.

◆ IDX_ATAPI_IO1_i_InterruptReason

#define IDX_ATAPI_IO1_i_InterruptReason (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1)

Definition at line 507 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Status

#define IDX_ATAPI_IO1_i_Status (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1)

Definition at line 512 of file atapi.h.

◆ IDX_ATAPI_IO1_i_Unused1

#define IDX_ATAPI_IO1_i_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1)

Definition at line 508 of file atapi.h.

◆ IDX_ATAPI_IO1_o_ByteCountHigh

#define IDX_ATAPI_IO1_o_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1)

Definition at line 519 of file atapi.h.

◆ IDX_ATAPI_IO1_o_ByteCountLow

#define IDX_ATAPI_IO1_o_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1)

Definition at line 518 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Command

#define IDX_ATAPI_IO1_o_Command (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1)

Definition at line 521 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Data

#define IDX_ATAPI_IO1_o_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1)

Definition at line 514 of file atapi.h.

◆ IDX_ATAPI_IO1_o_DriveSelect

#define IDX_ATAPI_IO1_o_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1)

Definition at line 520 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Feature

#define IDX_ATAPI_IO1_o_Feature (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1)

Definition at line 515 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Unused0

#define IDX_ATAPI_IO1_o_Unused0 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1)

Definition at line 516 of file atapi.h.

◆ IDX_ATAPI_IO1_o_Unused1

#define IDX_ATAPI_IO1_o_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1)

Definition at line 517 of file atapi.h.

◆ IDX_ATAPI_IO1_SZ

#define IDX_ATAPI_IO1_SZ sizeof(ATAPI_REGISTERS_1)

Definition at line 503 of file atapi.h.

◆ IDX_IO1 [1/2]

#define IDX_IO1 0

Definition at line 194 of file atapi.h.

◆ IDX_IO1 [2/2]

#define IDX_IO1 0

Definition at line 194 of file atapi.h.

◆ IDX_IO1_i_BlockCount

#define IDX_IO1_i_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1)

Definition at line 198 of file atapi.h.

◆ IDX_IO1_i_BlockNumber

#define IDX_IO1_i_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1)

Definition at line 199 of file atapi.h.

◆ IDX_IO1_i_CylinderHigh

#define IDX_IO1_i_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1)

Definition at line 201 of file atapi.h.

◆ IDX_IO1_i_CylinderLow

#define IDX_IO1_i_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1)

Definition at line 200 of file atapi.h.

◆ IDX_IO1_i_Data

#define IDX_IO1_i_Data (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1)

Definition at line 196 of file atapi.h.

◆ IDX_IO1_i_DriveSelect

#define IDX_IO1_i_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1)

Definition at line 202 of file atapi.h.

◆ IDX_IO1_i_Error

#define IDX_IO1_i_Error (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1)

Definition at line 197 of file atapi.h.

◆ IDX_IO1_i_Status

#define IDX_IO1_i_Status (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1)

Definition at line 203 of file atapi.h.

◆ IDX_IO1_o

#define IDX_IO1_o IDX_IO1_SZ

Definition at line 205 of file atapi.h.

◆ IDX_IO1_o_BlockCount

#define IDX_IO1_o_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o)

Definition at line 210 of file atapi.h.

◆ IDX_IO1_o_BlockNumber

#define IDX_IO1_o_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o)

Definition at line 211 of file atapi.h.

◆ IDX_IO1_o_Command

#define IDX_IO1_o_Command (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o)

Definition at line 215 of file atapi.h.

◆ IDX_IO1_o_CylinderHigh

#define IDX_IO1_o_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o)

Definition at line 213 of file atapi.h.

◆ IDX_IO1_o_CylinderLow

#define IDX_IO1_o_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o)

Definition at line 212 of file atapi.h.

◆ IDX_IO1_o_Data

#define IDX_IO1_o_Data (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o)

Definition at line 208 of file atapi.h.

◆ IDX_IO1_o_DriveSelect

#define IDX_IO1_o_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o)

Definition at line 214 of file atapi.h.

◆ IDX_IO1_o_Feature

#define IDX_IO1_o_Feature (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o)

Definition at line 209 of file atapi.h.

◆ IDX_IO1_o_SZ

#define IDX_IO1_o_SZ sizeof(IDE_REGISTERS_1)

Definition at line 206 of file atapi.h.

◆ IDX_IO1_SZ [1/2]

#define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)

Definition at line 195 of file atapi.h.

◆ IDX_IO1_SZ [2/2]

#define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)

Definition at line 195 of file atapi.h.

◆ IDX_IO2

#define IDX_IO2 (IDX_IO1_o+IDX_IO1_o_SZ)

Definition at line 222 of file atapi.h.

◆ IDX_IO2_AltStatus

#define IDX_IO2_AltStatus (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2)

Definition at line 225 of file atapi.h.

◆ IDX_IO2_o

#define IDX_IO2_o (IDX_IO2+IDX_IO2_SZ)

Definition at line 228 of file atapi.h.

◆ IDX_IO2_o_Control

#define IDX_IO2_o_Control (FIELD_OFFSET(IDE_REGISTERS_2, Control)+IDX_IO2_o)

Definition at line 231 of file atapi.h.

◆ IDX_IO2_o_SZ

#define IDX_IO2_o_SZ sizeof(IDE_REGISTERS_2)

Definition at line 229 of file atapi.h.

◆ IDX_IO2_SZ

#define IDX_IO2_SZ sizeof(IDE_REGISTERS_2)

Definition at line 223 of file atapi.h.

◆ INTERRUPT_REASON_IGNORE

#define INTERRUPT_REASON_IGNORE 0

Definition at line 1278 of file atapi.h.

◆ INTERRUPT_REASON_OUR

#define INTERRUPT_REASON_OUR 1

Definition at line 1279 of file atapi.h.

◆ INTERRUPT_REASON_UNEXPECTED

#define INTERRUPT_REASON_UNEXPECTED 2

Definition at line 1280 of file atapi.h.

◆ IOMODE_NOT_SPECIFIED

#define IOMODE_NOT_SPECIFIED (0xffffffffL)

Definition at line 1484 of file atapi.h.

◆ IS_RDP

#define IS_RDP ( OperationCode )

Value:

    ((OperationCode == SCSIOP_ERASE)||\
    (OperationCode == SCSIOP_LOAD_UNLOAD)||\
    (OperationCode == SCSIOP_LOCATE)||\
    (OperationCode == SCSIOP_REWIND) ||\
    (OperationCode == SCSIOP_SPACE)||\
    (OperationCode == SCSIOP_SEEK)||\
/*    (OperationCode == SCSIOP_FORMAT_UNIT)||\
    (OperationCode == SCSIOP_BLANK)||*/ \
    (OperationCode == SCSIOP_WRITE_FILEMARKS))

Definition at line 1197 of file atapi.h.

◆ KdPrint

#define KdPrint ( _x_ ) {;}

Definition at line 155 of file atapi.h.

◆ KdPrint2

#define KdPrint2 ( _x_ ) {;}

Definition at line 154 of file atapi.h.

◆ KdPrint3

#define KdPrint3 ( _x_ ) {;}

Definition at line 153 of file atapi.h.

◆ MAX_ERRORS

#define MAX_ERRORS 4

Definition at line 262 of file atapi.h.

◆ PIDENTIFY_DATA2

#define PIDENTIFY_DATA2 PIDENTIFY_DATA

Definition at line 990 of file atapi.h.

◆ PRINT_PREFIX

#define PRINT_PREFIX "UniATA: "

Definition at line 150 of file atapi.h.

◆ PrintNtConsole

#define PrintNtConsole ( x ) {;}

Definition at line 1629 of file atapi.h.

◆ READ_LOG_SECTOR

#define READ_LOG_SECTOR 0xD5

Definition at line 591 of file atapi.h.

◆ ReadBuffer

#define ReadBuffer	(	chan,
		Buffer,
		Count,
		timing
	)

Value:

    AtapiReadBuffer2(chan, IDX_IO1_i_Data, \
                                 Buffer, \
                                 Count, \
                                 timing);

Definition at line 1105 of file atapi.h.

◆ ReadBuffer2

#define ReadBuffer2	(	chan,
		Buffer,
		Count,
		timing
	)

Value:

    AtapiReadBuffer4(chan, IDX_IO1_i_Data, \
                             Buffer, \
                                 Count, \
                                 timing);

Definition at line 1117 of file atapi.h.

◆ SCSIOP_ATA_PASSTHROUGH

#define SCSIOP_ATA_PASSTHROUGH 0xCC

Definition at line 411 of file atapi.h.

◆ UNIATA_FIND_DEV_UNHIDE

#define UNIATA_FIND_DEV_UNHIDE 0x01

Definition at line 1360 of file atapi.h.

◆ UniAta_need_lba48

#define UniAta_need_lba48	(	command,
		lba,
		count,
		supp48
	)

Value:

( ((AtaCommandFlags[command] & ATA_CMD_FLAG_LBAIOsupp) && (supp48) && (((lba+count) >= ATA_MAX_IOLBA28) || (count > 256)) ) || \

(lba > ATA_MAX_LBA28) || (count > 255) )

ATA_MAX_LBA28

#define ATA_MAX_LBA28

Definition: bsmaster.h:95

ATA_MAX_IOLBA28

#define ATA_MAX_IOLBA28

Definition: bsmaster.h:94

count

GLuint GLuint GLsizei count

Definition: gl.h:1545

command

Definition: tnmain.cpp:425

lba

#define lba

AtaCommandFlags

UCHAR const AtaCommandFlags[256]

Definition: atacmd_map.h:25

ATA_CMD_FLAG_LBAIOsupp

#define ATA_CMD_FLAG_LBAIOsupp

Definition: atapi.h:1597

Definition at line 1609 of file atapi.h.

◆ UniAtaClearAtaReq

#define UniAtaClearAtaReq ( AtaReq )

Value:

{  \
        RtlZeroMemory((PCHAR)(AtaReq), FIELD_OFFSET(ATA_REQ, ata)); \
}

Definition at line 1615 of file atapi.h.

◆ WRITE_LOG_SECTOR

#define WRITE_LOG_SECTOR 0xD6

Definition at line 592 of file atapi.h.

◆ WRITE_THRESHOLDS

#define WRITE_THRESHOLDS 0xD7

Definition at line 593 of file atapi.h.

◆ WriteBuffer

#define WriteBuffer	(	chan,
		Buffer,
		Count,
		timing
	)

Value:

    AtapiWriteBuffer2(chan, IDX_IO1_o_Data, \
                                  Buffer, \
                                 Count, \
                                 timing);

Definition at line 1111 of file atapi.h.

◆ WriteBuffer2

#define WriteBuffer2	(	chan,
		Buffer,
		Count,
		timing
	)

Value:

    AtapiWriteBuffer4(chan, IDX_IO1_o_Data, \
                              Buffer, \
                                 Count, \
                                 timing);

Definition at line 1123 of file atapi.h.

◆ WriteCommand

#define WriteCommand	(	chan,
		_Command
	)	AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);

Definition at line 1095 of file atapi.h.

Typedef Documentation

◆ ATAPI_REGISTERS_1

typedef union _ATAPI_REGISTERS_1 ATAPI_REGISTERS_1

◆ IDE_REGISTERS_1

typedef union _IDE_REGISTERS_1 IDE_REGISTERS_1

◆ IDE_REGISTERS_2

typedef union _IDE_REGISTERS_2 IDE_REGISTERS_2

◆ IDENTIFY_DATA

typedef struct _IDENTIFY_DATA IDENTIFY_DATA

◆ MODE_PARAMETER_HEADER_10

typedef struct _MODE_PARAMETER_HEADER_10 MODE_PARAMETER_HEADER_10

◆ MODE_SELECT_10

typedef struct _MODE_SELECT_10 MODE_SELECT_10

◆ MODE_SENSE_10

typedef struct _MODE_SENSE_10 MODE_SENSE_10

◆ PATAPI_REGISTERS_1

typedef union _ATAPI_REGISTERS_1 * PATAPI_REGISTERS_1

◆ PIDE_REGISTERS_1

typedef union _IDE_REGISTERS_1 * PIDE_REGISTERS_1

◆ PIDE_REGISTERS_2

typedef union _IDE_REGISTERS_2 * PIDE_REGISTERS_2

◆ PIDENTIFY_DATA

typedef struct _IDENTIFY_DATA * PIDENTIFY_DATA

◆ PMODE_PARAMETER_HEADER_10

typedef struct _MODE_PARAMETER_HEADER_10 * PMODE_PARAMETER_HEADER_10

◆ PMODE_SELECT_10

typedef struct _MODE_SELECT_10 * PMODE_SELECT_10

◆ PMODE_SENSE_10

typedef struct _MODE_SENSE_10 * PMODE_SENSE_10

◆ PTRIM_DATA

typedef struct _TRIM_DATA * PTRIM_DATA

◆ TRIM_DATA

typedef struct _TRIM_DATA TRIM_DATA

Function Documentation

◆ _PrintNtConsole()

VOID _cdecl _PrintNtConsole	(	PCCH	DebugMessage,
			...
	)

Definition at line 11689 of file id_ata.cpp.

{
    //int len;
    UCHAR dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE];
//    UNICODE_STRING msgBuff;
    va_list ap;
    va_start(ap, DebugMessage);
 
    /*len =*/ _vsnprintf((PCHAR)&dbg_print_tmp_buff[0], DEBUG_MSG_BUFFER_SIZE-1, DebugMessage, ap);
 
    dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE-1] = 0;
 
    //DbgPrint(((PCHAR)&(dbg_print_tmp_buff[0]))); // already done in KdPrint macro
    HalDisplayString(dbg_print_tmp_buff);
 
#ifdef _DEBUG
    if(g_LogToDisplay > 1) {
        AtapiStallExecution(g_LogToDisplay*1000);
    }
#endif // _DEBUG
 
    va_end(ap);
 
} // end PrintNtConsole()

Referenced by DriverEntry().

◆ ata_cur_mode_from_ident()

__inline LONG ata_cur_mode_from_ident	(	PIDENTIFY_DATA	ident,
		BOOLEAN	Active
	)

Definition at line 1648 of file atapi.h.

{
    USHORT mode;
    if(ata_is_sata(ident)) {
        if(ident->SataCapabilities & ATA_SATA_GEN3) {
            return ATA_SA600;
        } else
        if(ident->SataCapabilities & ATA_SATA_GEN2) {
            return ATA_SA300;
        } else
        if(ident->SataCapabilities & ATA_SATA_GEN1) {
            return ATA_SA150;
        }
        return ATA_SA150;
    }
 
    if (ident->UdmaModesValid) {
        mode = Active ? ident->UltraDMAActive : ident->UltraDMASupport;
        if (mode & 0x40)
            return ATA_UDMA0+6;
        if (mode & 0x20)
            return ATA_UDMA0+5;
        if (mode & 0x10)
            return ATA_UDMA0+4;
        if (mode & 0x08)
            return ATA_UDMA0+3;
        if (mode & 0x04)
            return ATA_UDMA0+2;
        if (mode & 0x02)
            return ATA_UDMA0+1;
        if (mode & 0x01)
            return ATA_UDMA0+0;
    }
 
    mode = Active ? ident->MultiWordDMAActive : ident->MultiWordDMASupport;
    if (ident->MultiWordDMAActive & 0x04)
        return ATA_WDMA0+2;
    if (ident->MultiWordDMAActive & 0x02)
        return ATA_WDMA0+1;
    if (ident->MultiWordDMAActive & 0x01)
        return ATA_WDMA0+0;
 
    mode = Active ? ident->SingleWordDMAActive : ident->SingleWordDMASupport;
    if (ident->SingleWordDMAActive & 0x04)
        return ATA_SDMA0+2;
    if (ident->SingleWordDMAActive & 0x02)
        return ATA_SDMA0+1;
    if (ident->SingleWordDMAActive & 0x01)
        return ATA_SDMA0+0;
 
    if (ident->PioTimingsValid) {
        mode = ident->AdvancedPIOModes;
        if (mode & AdvancedPIOModes_5)
            return ATA_PIO0+5;
        if (mode & AdvancedPIOModes_4)
            return ATA_PIO0+4;
        if (mode & AdvancedPIOModes_3)
            return ATA_PIO0+3;
    }
    mode = ident->PioCycleTimingMode;
    if (ident->PioCycleTimingMode == 2)
        return ATA_PIO0+2;
    if (ident->PioCycleTimingMode == 1)
        return ATA_PIO0+1;
    if (ident->PioCycleTimingMode == 0)
        return ATA_PIO0+0;
 

Referenced by ata_check_unit(), and IssueIdentify().

◆ ata_is_sata()

__inline BOOLEAN ata_is_sata ( PIDENTIFY_DATA ident )

Definition at line 1636 of file atapi.h.

1641{

Referenced by ata_cur_mode_from_ident(), and AtapiDmaInit().

◆ AtaCommand()

UCHAR NTAPI AtaCommand	(	IN struct _HW_DEVICE_EXTENSION *	deviceExtension,
		IN ULONG	DeviceNumber,
		IN ULONG	Channel,
		IN UCHAR	command,
		IN USHORT	cylinder,
		IN UCHAR	head,
		IN UCHAR	sector,
		IN UCHAR	count,
		IN UCHAR	feature,
		IN ULONG	flags
	)

Referenced by AtaSetTransferMode().

◆ AtaCommand48()

UCHAR NTAPI AtaCommand48	(	IN struct _HW_DEVICE_EXTENSION *	deviceExtension,
		IN ULONG	DeviceNumber,
		IN ULONG	Channel,
		IN UCHAR	command,
		IN ULONGLONG	lba,
		IN USHORT	count,
		IN USHORT	feature,
		IN ULONG	flags
	)

◆ AtapiCheckInterrupt__()

UCHAR NTAPI AtapiCheckInterrupt__	(	IN PVOID	HwDeviceExtension,
		IN UCHAR	c
	)

clear interrupt and get status *‍/

Definition at line 4512 of file id_ata.cpp.

{
    PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
    PHW_CHANNEL chan = &(deviceExtension->chan[c]);
    PHW_LU_EXTENSION LunExt;
 
    ULONG VendorID  = deviceExtension->DevID & 0xffff;
    ULONG ChipType  = deviceExtension->HwFlags & CHIPTYPE_MASK;
 
    ULONG status;
    ULONG pr_status = 0;
    UCHAR dma_status = 0;
    UCHAR reg8 = 0;
    ULONG reg32 = 0;
    UCHAR statusByte = 0;
    ULONG slotNumber = deviceExtension->slotNumber;
    ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
    ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
    UCHAR Channel;
    UCHAR lChannel;
    BOOLEAN DmaTransfer = FALSE;
    BOOLEAN OurInterrupt = FALSE;
    BOOLEAN StatusValid = FALSE;
//    ULONG k;
    UCHAR interruptReason;
    BOOLEAN EarlyIntr = FALSE;
    BOOLEAN SingleBlockIntr = FALSE;
 
    KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__:\n"));
 
    lChannel = c;
    Channel = (UCHAR)(deviceExtension->Channel + lChannel);
    LunExt = chan->lun[chan->cur_cdev];
 
    //KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__ chan %#x:\n", chan));
    //KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__ (%d/%d):\n", Channel, chan->cur_cdev));
 
    if((ChipFlags & UNIATA_AHCI) &&
        UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
 
        if(!UniataAhciChanImplemented(deviceExtension, lChannel)) {
            return OurInterrupt;
        }
 
        OurInterrupt = UniataAhciStatus(HwDeviceExtension, lChannel, DEVNUM_NOT_SPECIFIED);
        if((OurInterrupt == INTERRUPT_REASON_UNEXPECTED) &&
           (LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE)) {
            UniataAhciWaitCommandReady(chan, 2 /* ms */ );
            statusByte = (UCHAR)UniataAhciWaitReady(chan, 0 /* immediate */);
            if(!(statusByte & (IDE_STATUS_BUSY)) ) {
                KdPrint2((PRINT_PREFIX "ATAPI special case READY\n"));
                //deviceExtension->ExpectingInterrupt++; // will be updated in ISR on ReturnEnableInterrupts
                OurInterrupt = INTERRUPT_REASON_OUR;
            } else
            if((statusByte & (IDE_STATUS_BUSY | IDE_STATUS_DRDY)) == (IDE_STATUS_BUSY | IDE_STATUS_DRDY) ) {
                KdPrint2((PRINT_PREFIX "ATAPI special case pre ERR-READY\n"));
                OurInterrupt = INTERRUPT_REASON_OUR;
            } else
            if(statusByte & IDE_STATUS_ERROR) {
                KdPrint2((PRINT_PREFIX "ATAPI special case ERR-READY\n"));
                OurInterrupt = INTERRUPT_REASON_OUR;
            } else {
                KdPrint2((PRINT_PREFIX "ATAPI special case ? %x\n", statusByte));
                OurInterrupt = INTERRUPT_REASON_OUR;
            }
        }
        return OurInterrupt;
    }
 
    if(chan->ChannelCtrlFlags & CTRFLAGS_DMA_ACTIVE) {
        DmaTransfer = TRUE;
        KdPrint2((PRINT_PREFIX "  cntrlr %#x:%#x, lch %#x DmaTransfer = TRUE\n", deviceExtension->DevIndex,
            deviceExtension->Channel + c, c));
    } else {
        KdPrint2((PRINT_PREFIX "  cntrlr %#x:%#x, lch %#x DmaTransfer = FALSE\n", deviceExtension->DevIndex,
            deviceExtension->Channel + c, c));
        dma_status = GetDmaStatus(deviceExtension, lChannel);
        KdPrint2((PRINT_PREFIX "  DMA status %#x\n", dma_status));
    }
 
    // do controller-specific interrupt servicing staff
    if(deviceExtension->UnknownDev) {
        KdPrint2((PRINT_PREFIX "  UnknownDev\n"));
        goto check_unknown;
    }
 
    // Attention !
    // We can catch (BM_STATUS_ACTIVE + BM_STATUS_INTR) when operation is actually completed
    // Such behavior was observed with Intel ICH-xxx chips
    // This condition shall also be treated as 'our interrupt' because of BM_STATUS_INTR flag
 
    switch(VendorID) {
 
    case ATA_PROMISE_ID: {
        switch(ChipType) {
        case PROLD:
        case PRNEW:
            status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1c);
            if (!DmaTransfer)
                break;
            if (!(status &
                  ((Channel) ? 0x00004000 : 0x00000400))) {
                KdPrint2((PRINT_PREFIX "  Promise old/new unexpected\n"));
                return INTERRUPT_REASON_IGNORE;
            }
            break;
        case PRTX:
            AtapiWritePort1(chan, IDX_BM_DeviceSpecific0, 0x0b);
            status = AtapiReadPort1(chan, IDX_BM_DeviceSpecific1);
            if (!DmaTransfer)
                break;
            if(!(status & 0x20)) {
                KdPrint2((PRINT_PREFIX "  Promise tx unexpected\n"));
                return INTERRUPT_REASON_IGNORE;
            }
            break;
        case PRMIO: {
            ULONG stat_reg = (ChipFlags & PRG2) ? 0x60 : 0x6c;
            status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x40);
            AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x40, status);
 
            if(status & (1 << (Channel+1))) {
                // our
            } else {
                KdPrint2((PRINT_PREFIX "  Promise mio unexpected\n"));
                return INTERRUPT_REASON_IGNORE;
            }
 
            if(!(ChipFlags & UNIATA_SATA))
                break;
 
            pr_status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),stat_reg);
            AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),stat_reg, (pr_status & (0x11 << Channel)));
            if(pr_status & (0x11 << Channel)) {
                // TODO: reset channel
                KdPrint2((PRINT_PREFIX "  Promise mio unexpected + reset req\n"));
                UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH, 0);
            }
            if(!(status & (0x01 << Channel))) {
                // Connect event
                KdPrint2((PRINT_PREFIX "  Promise mio unexpected attach\n"));
                UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH, 0);
            }
            if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
            } else {
                return INTERRUPT_REASON_IGNORE;
            }
 
            AtapiWritePort4(chan, IDX_BM_DeviceSpecific0, 0x00000001);
            break; }
        }
        break; }
    case ATA_NVIDIA_ID: {
        if(!(ChipFlags & UNIATA_SATA) || (ChipFlags & NVGEN))
            break;
 
        KdPrint2((PRINT_PREFIX "NVIDIA\n"));
 
        ULONG offs = (ChipFlags & NV4OFF) ? 0x0440 : 0x0010;
        ULONG shift = Channel * ((ChipFlags & NVQ) ? 4 : 16);
 
        /* get and clear interrupt status */
        if(ChipFlags & NVQ) {
            pr_status = AtapiReadPortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs);
            AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, (0x0fUL << shift) | 0x00f000f0);
        } else {
            pr_status = AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs);
            AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, (0x0f << shift));
        }
        KdPrint2((PRINT_PREFIX "  pr_status %x, shift %x\n", pr_status, shift));
 
        /* check for and handle connect events */
        if(((pr_status & (0x0cUL << shift)) == (0x04UL << shift)) ) {
            UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_ATTACH, 0);
        }
        /* check for and handle disconnect events */
        if((pr_status & (0x08UL << shift)) &&
            !((pr_status & (0x04UL << shift) &&
            UniataSataReadPort4(chan, IDX_SATA_SStatus, 0))) ) {
            UniataSataEvent(deviceExtension, lChannel, UNIATA_SATA_EVENT_DETACH, 0);
        }
        /* do we have any device action ? */
        if(!(pr_status & (0x01UL << shift))) {
            KdPrint2((PRINT_PREFIX "  nVidia unexpected\n"));
            if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
            } else {
                return INTERRUPT_REASON_IGNORE;
            }
        }
 
        break; }
    case ATA_ATI_ID:
        KdPrint2((PRINT_PREFIX "ATI\n"));
        if(ChipType == SIIMIO) {
            // fall to SiI
        } else {
            break;
        }
    case ATA_SILICON_IMAGE_ID:
 
        if(ChipType == SIIMIO) {
 
            reg32 = AtapiReadPort4(chan, IDX_BM_DeviceSpecific0);
            KdPrint2((PRINT_PREFIX "  Sii DS0 %x\n", reg32));
            if(reg32 == 0xffffffff) {
                KdPrint2((PRINT_PREFIX "  Sii mio unexpected\n"));
                return INTERRUPT_REASON_IGNORE;
            }
            if(!(reg32 & (BM_DS0_SII_DMA_SATA_IRQ | BM_DS0_SII_DMA_COMPLETE | BM_DS0_SII_IRQ | BM_DS0_SII_DMA_ENABLE | BM_DS0_SII_DMA_ERROR))) {
                KdPrint2((PRINT_PREFIX "  Sii mio unexpected (2)\n"));
                return INTERRUPT_REASON_IGNORE;
            }
 
            if(ChipFlags & UNIATA_SATA) {
                if(reg32 & (BM_DS0_SII_DMA_SATA_IRQ | BM_DS0_SII_IRQ)) {
 
                    /* SIEN doesn't mask SATA IRQs on some 3112s.  Those
                    * controllers continue to assert IRQ as long as
                    * SError bits are pending.  Clear SError immediately.
                    */
                    if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                        OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
                    }
                }
            }
 
            if (!DmaTransfer)
                break;
            if (!((dma_status = GetDmaStatus(deviceExtension, lChannel)) & BM_STATUS_INTR)) {
                KdPrint2((PRINT_PREFIX "  Sii mio unexpected (3)\n"));
                return OurInterrupt;
            }
            AtapiWritePort1(chan, IDX_BM_Status, dma_status & ~BM_STATUS_ERR);
            goto skip_dma_stat_check;
 
        } else {
            if(!(deviceExtension->HwFlags & SIIINTR))
                break;
            GetPciConfig1(0x71, reg8);
            KdPrint2((PRINT_PREFIX "  0x71 = %#x\n", reg8));
            if (!(reg8 &
                  (Channel ? 0x08 : 0x04))) {
                return INTERRUPT_REASON_IGNORE;
            }
            if (!DmaTransfer) {
                KdPrint2((PRINT_PREFIX "  cmd our\n"));
                OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
            }
            SetPciConfig1(0x71, (Channel ? 0x08 : 0x04));
        }
        break;
 
    case ATA_ACARD_ID:
        if (!DmaTransfer)
            break;
        //dma_status = GetDmaStatus(deviceExtension, lChannel);
        if (!((dma_status = GetDmaStatus(deviceExtension, lChannel)) & BM_STATUS_INTR)) {
            KdPrint2((PRINT_PREFIX "  Acard unexpected\n"));
            return INTERRUPT_REASON_IGNORE;
        }
        AtapiWritePort1(chan, IDX_BM_Status, dma_status | BM_STATUS_INTR);
        AtapiStallExecution(1);
        AtapiWritePort1(chan, IDX_BM_Command,
            AtapiReadPort1(chan, IDX_BM_Command) & ~BM_COMMAND_START_STOP);
        goto skip_dma_stat_check;
    case ATA_INTEL_ID:
        if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
            if(ChipFlags & UNIATA_AHCI) {
                // Do nothing here
            } else
            if(ChipFlags & UNIATA_SATA) {
                if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                    OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
                }
                if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
                    if(UniataSataClearErr(chan->DeviceExtension, chan->lChannel, UNIATA_SATA_IGNORE_CONNECT, 1)) {
                        OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
                    }
                }
            }
        }
        break;
    default:
        if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
            if(ChipFlags & UNIATA_AHCI) {
                // Do nothing here
            } else
            if(ChipFlags & UNIATA_SATA) {
                if(UniataSataClearErr(HwDeviceExtension, c, UNIATA_SATA_DO_CONNECT, 0)) {
                    OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
                }
            }
        }
    }
check_unknown:
    KdPrint2((PRINT_PREFIX "  perform generic check\n"));
    if (DmaTransfer) {
        if (!((dma_status = GetDmaStatus(deviceExtension, lChannel)) & BM_STATUS_INTR)) {
            KdPrint2((PRINT_PREFIX "  DmaTransfer + !BM_STATUS_INTR (%x)\n", dma_status));
            if(dma_status & BM_STATUS_ERR) {
                KdPrint2((PRINT_PREFIX "  DmaTransfer + BM_STATUS_ERR -> our\n"));
                OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
            } else {
                KdPrint2((PRINT_PREFIX "  getting status...\n"));
                GetStatus(chan, statusByte);
                StatusValid = 1;
                KdPrint2((PRINT_PREFIX "  status %#x\n", statusByte));
                if(statusByte & IDE_STATUS_ERROR) {
                    KdPrint2((PRINT_PREFIX "  IDE_STATUS_ERROR -> our\n", statusByte));
                    OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
                } else
                if ((statusByte & IDE_STATUS_DSC) &&
                    (LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) &&
                    (dma_status == BM_STATUS_ACTIVE)) {
                    KdPrint2((PRINT_PREFIX "  special case DMA + ATAPI + IDE_STATUS_DSC -> our\n", statusByte));
                    // some devices interrupts on each block transfer even in DMA mode
                    if(LunExt->TransferMode >= ATA_SDMA && LunExt->TransferMode <= ATA_WDMA2) {
                        KdPrint2((PRINT_PREFIX "  wait for completion\n"));
                        //GetBaseStatus(chan, statusByte);
                        //return INTERRUPT_REASON_IGNORE;
                        SingleBlockIntr = TRUE;
                    }
                } else {
                    return INTERRUPT_REASON_IGNORE;
                }
            }
        }
    } else {
        if(dma_status & BM_STATUS_INTR) {
            // bullshit, we have DMA interrupt, but had never initiate DMA operation
            KdPrint2((PRINT_PREFIX "  clear unexpected DMA intr\n"));
            AtapiDmaDone(deviceExtension, DEVNUM_NOT_SPECIFIED ,lChannel, NULL);
            // catch it !
            OurInterrupt = INTERRUPT_REASON_UNEXPECTED;
        }
    }
skip_dma_stat_check:
    if(!(ChipFlags & UNIATA_SATA) && chan->ExpectingInterrupt) {
        AtapiStallExecution(1);
    }
 
    /* if drive is busy it didn't interrupt */
    /* the exception is DCS + BSY state of ATAPI devices */
    if(!StatusValid) {
        KdPrint2((PRINT_PREFIX "  getting status...\n"));
        GetStatus(chan, statusByte);
    }
    if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
        KdPrint3((PRINT_PREFIX "  ATAPI status %#x\n", statusByte));
    } else {
        KdPrint2((PRINT_PREFIX "  IDE status %#x\n", statusByte));
    }
    if (statusByte == IDE_STATUS_WRONG) {
        // interrupt from empty controller ?
    } else
    if (statusByte & IDE_STATUS_BUSY) {
        if(!chan->ExpectingInterrupt) {
            KdPrint3((PRINT_PREFIX "  unexpected intr + BUSY\n"));
            return OurInterrupt;
        }
 
        if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
            KdPrint2((PRINT_PREFIX "  ATAPI additional check\n"));
        } else {
            KdPrint2((PRINT_PREFIX "  expecting intr + BUSY (3), non ATAPI\n"));
            return INTERRUPT_REASON_IGNORE;
        }
        if((statusByte & ~(IDE_STATUS_DRQ | IDE_STATUS_INDEX)) !=
           (IDE_STATUS_BUSY | IDE_STATUS_DRDY | IDE_STATUS_DSC)) {
            KdPrint3((PRINT_PREFIX "  unexpected status, seems it is not our\n"));
            return INTERRUPT_REASON_IGNORE;
        }
        if(!(LunExt->DeviceFlags & DFLAGS_INT_DRQ) && (statusByte & IDE_STATUS_DRQ)) {
            KdPrint3((PRINT_PREFIX "  unexpected DRQ, seems it is not our\n"));
            return INTERRUPT_REASON_IGNORE;
        }
 
        EarlyIntr = TRUE;
 
        if(dma_status & BM_STATUS_INTR) {
            KdPrint3((PRINT_PREFIX "  our interrupt with BSY set, try wait in ISR or post to DPC\n"));
            /* clear interrupt and get status */
            GetBaseStatus(chan, statusByte);
            if(!(dma_status & BM_STATUS_ACTIVE)) {
                AtapiDmaDone(deviceExtension, DEVNUM_NOT_SPECIFIED ,lChannel, NULL);
            }
            KdPrint3((PRINT_PREFIX "  base status %#x (+BM_STATUS_INTR)\n", statusByte));
            return INTERRUPT_REASON_OUR;
        }
 
        if(g_WaitBusyInISR) {
            GetStatus(chan, statusByte);
            KdPrint2((PRINT_PREFIX "  status re-check %#x\n", statusByte));
            reg8 = AtapiReadPort1(chan, IDX_IO1_i_Error);
            KdPrint2((PRINT_PREFIX "  Error reg (%#x)\n", reg8));
            if (!(statusByte & IDE_STATUS_BUSY)) {
                KdPrint2((PRINT_PREFIX "  expecting intr + cleared BUSY\n"));
            }
            if (statusByte & IDE_STATUS_BUSY) {
                KdPrint2((PRINT_PREFIX "  still BUSY, seems it is not our\n"));
                return INTERRUPT_REASON_IGNORE;
            }
        }
 
    }
 
    /* clear interrupt and get status */
    GetBaseStatus(chan, statusByte);
    KdPrint2((PRINT_PREFIX "  base status %#x\n", statusByte));
    if (statusByte == IDE_STATUS_WRONG) {
        // interrupt from empty controller ?
    } else
    if(!(statusByte & (IDE_STATUS_DRQ | IDE_STATUS_DRDY))) {
        KdPrint2((PRINT_PREFIX "  no DRQ/DRDY set\n"));
        return OurInterrupt;
    }
 
#ifndef UNIATA_PIO_ONLY
    if(DmaTransfer) {
        if(!SingleBlockIntr && (!EarlyIntr || g_WaitBusyInISR)) {
            dma_status = AtapiDmaDone(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, lChannel, NULL/*srb*/);
        } else {
            PSCSI_REQUEST_BLOCK srb = UniataGetCurRequest(chan);
            PATA_REQ AtaReq = srb ? (PATA_REQ)(srb->SrbExtension) : NULL;
 
            //ASSERT(AtaReq);
 
            if(SingleBlockIntr) {
                KdPrint2((PRINT_PREFIX "  set REQ_STATE_ATAPI_EXPECTING_DATA_INTR2.\n"));
            } else {
                KdPrint2((PRINT_PREFIX "  set REQ_STATE_EARLY_INTR.\n"));
            }
            if(AtaReq) {
                AtaReq->ReqState = SingleBlockIntr ? REQ_STATE_ATAPI_EXPECTING_DATA_INTR2 : REQ_STATE_EARLY_INTR;
            }
        }
    }
#endif //
 
    if (!(chan->ExpectingInterrupt)) {
 
        KdPrint2((PRINT_PREFIX "  Unexpected interrupt.\n"));
 
        if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
            KdPrint2((PRINT_PREFIX "  ATAPI additional check\n"));
        } else {
            KdPrint2((PRINT_PREFIX "  OurInterrupt = %d\n", OurInterrupt));
            return OurInterrupt;
        }
        interruptReason = (AtapiReadPort1(chan, IDX_ATAPI_IO1_i_InterruptReason) & ATAPI_IR_Mask);
        KdPrint3((PRINT_PREFIX "AtapiCheckInterrupt__: ATAPI int reason %x\n", interruptReason));
        return OurInterrupt;
    }
    //ASSERT(!chan->queue_depth || chan->cur_req);
 
    KdPrint2((PRINT_PREFIX "AtapiCheckInterrupt__: exit with TRUE\n"));
    return INTERRUPT_REASON_OUR;
 
} // end AtapiCheckInterrupt__()

Referenced by AtapiInterrupt(), AtapiInterrupt2(), and IdeSendCommand().

◆ AtapiDisableInterrupts()

VOID NTAPI AtapiDisableInterrupts	(	IN PVOID	HwDeviceExtension,
		IN ULONG	c
	)

Definition at line 4457 of file id_ata.cpp.

{
    PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
    PHW_CHANNEL chan;
    if(c >= deviceExtension->NumberChannels) {
        KdPrint2((PRINT_PREFIX "AtapiDisableInterrupts_%d: WRONG CHANNEL\n",c));
        return;
    }
    chan = &(deviceExtension->chan[c]);
    KdPrint2((PRINT_PREFIX "AtapiDisableInterrupts_%d: %d\n",c, chan->DisableIntr));
    // mark channel as busy
    if(InterlockedIncrement(&chan->DisableIntr)) {
        if(deviceExtension->HwFlags & UNIATA_AHCI) {
            UniataAhciWriteChannelPort4(chan, IDX_AHCI_P_IE, 0);
        } else {
            //SelectDrive(chan, 0);
            AtapiWritePort1(chan, IDX_IO2_o_Control,
                                   IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
            //if(chan->NumberLuns) {
            //    SelectDrive(chan, 1);
            //    AtapiWritePort1(chan, IDX_IO2_o_Control,
            //                           IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
            //    SelectDrive(chan, chan->cur_cdev);
            //}
        }
        chan->ChannelCtrlFlags |= CTRFLAGS_INTR_DISABLED;
    }
 
    return;
} // end AtapiDisableInterrupts()

Referenced by AtapiAdapterControl(), AtapiHwInitialize__(), AtapiInterrupt(), AtapiInterrupt__(), AtapiResetController__(), AtapiSendCommand(), AtapiStartIo__(), AtaSetTransferMode(), FindDevices(), IdeSendCommand(), IssueIdentify(), and UniataUserDeviceReset().

◆ AtapiDpcDispatch()

VOID NTAPI AtapiDpcDispatch	(	IN PKDPC	Dpc,
		IN PVOID	DeferredContext,
		IN PVOID	SystemArgument1,
		IN PVOID	SystemArgument2
	)

◆ AtapiEnableInterrupts()

VOID NTAPI AtapiEnableInterrupts	(	IN PVOID	HwDeviceExtension,
		IN ULONG	c
	)

Definition at line 4397 of file id_ata.cpp.

{
    PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
    PHW_CHANNEL chan;
    //UCHAR statusByte;
 
    if(c >= deviceExtension->NumberChannels) {
        KdPrint2((PRINT_PREFIX "AtapiEnableInterrupts_%d: WRONG CHANNEL\n",c));
        return;
    }
    if((deviceExtension->HwFlags & UNIATA_AHCI) &&
       !UniataAhciChanImplemented(deviceExtension, c)) {
        KdPrint2((PRINT_PREFIX "AtapiEnableInterrupts_%d: not imp. CHANNEL\n",c));
        return;
    }
 
    chan = &(deviceExtension->chan[c]);
    KdPrint2((PRINT_PREFIX "AtapiEnableInterrupts_%d: %d\n",c, chan->DisableIntr));
    if(!InterlockedDecrement(&chan->DisableIntr)) {
        if(deviceExtension->HwFlags & UNIATA_AHCI) {
            UniataAhciWriteChannelPort4(chan, IDX_AHCI_P_IE,
                (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
                 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_INF | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
                 ((/*ch->pm_level == */0) ? ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC : 0) |
                 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | /* DEBUG */
                 ATA_AHCI_P_IX_DI |
                 ATA_AHCI_P_IX_DP | ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB |
                 ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)
                );
        } else {
            //SelectDrive(chan, 0);
            //GetBaseStatus(chan, statusByte);
            AtapiWritePort1(chan, IDX_IO2_o_Control,
                                   0 | IDE_DC_A_4BIT );
            //if(chan->NumberLuns) {
            //    SelectDrive(chan, 1);
            //    GetBaseStatus(chan, statusByte);
            //    AtapiWritePort1(chan, IDX_IO2_o_Control,
            //                           IDE_DC_A_4BIT );
            //    SelectDrive(chan, chan->cur_cdev);
            //}
        }
        chan->ChannelCtrlFlags &= ~CTRFLAGS_INTR_DISABLED;
    } else {
        if(deviceExtension->HwFlags & UNIATA_AHCI) {
            // keep interrupts disabled
            UniataAhciWriteChannelPort4(chan, IDX_AHCI_P_IE, 0);
        } else {
            AtapiWritePort1(chan, IDX_IO2_o_Control,
                               IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
        }
    }
    return;
} // end AtapiEnableInterrupts()

Referenced by AtapiAdapterControl(), AtapiCallBack__(), AtapiEnableInterrupts__(), AtapiHwInitialize__(), AtapiInterrupt(), AtapiInterrupt__(), AtapiResetController__(), AtapiSendCommand(), AtapiStartIo__(), AtaSetTransferMode(), FindDevices(), IdeSendCommand(), IssueIdentify(), and UniataUserDeviceReset().

◆ AtapiFindIsaController()

ULONG NTAPI AtapiFindIsaController	(	IN PVOID	HwDeviceExtension,
		IN PVOID	Context,
		IN PVOID	BusInformation,
		IN PCHAR	ArgumentString,
		IN OUT PPORT_CONFIGURATION_INFORMATION	ConfigInfo,
		OUT PBOOLEAN	Again
	)

Definition at line 2243 of file id_probe.cpp.

{
    PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
    PHW_CHANNEL          chan;
    PULONG               adapterCount    = (PULONG)Context;
    PUCHAR               ioSpace = NULL;
    ULONG                i;
    ULONG                irq=0;
    ULONG                portBase=0;
    ULONG                retryCount;
//    BOOLEAN              atapiOnly;
    UCHAR                statusByte, statusByte2;
    BOOLEAN              preConfig = FALSE;
    //
    PIDE_REGISTERS_1 BaseIoAddress1;
    PIDE_REGISTERS_2 BaseIoAddress2 = NULL;
 
    // The following table specifies the ports to be checked when searching for
    // an IDE controller.  A zero entry terminates the search.
    static CONST ULONG AdapterAddresses[5] = {IO_WD1, IO_WD2, IO_WD1-8, IO_WD2-8, 0};
//    CONST UCHAR Channels[5] = {0, 1, 0, 1, 0};
 
    // The following table specifies interrupt levels corresponding to the
    // port addresses in the previous table.
    static CONST ULONG InterruptLevels[5] = {14, 15, 11, 10, 0};
 
    KdPrint2((PRINT_PREFIX "AtapiFindIsaController (ISA):\n"));
 
    if (!deviceExtension) {
        return SP_RETURN_ERROR;
    }
    RtlZeroMemory(deviceExtension, sizeof(HW_DEVICE_EXTENSION));
 
    KdPrint2((PRINT_PREFIX "  assume max PIO4\n"));
    deviceExtension->MaxTransferMode = ATA_PIO4;
    deviceExtension->NumberChannels = 1;
    deviceExtension->NumberLuns = IDE_MAX_LUN_PER_CHAN; // default
 
    if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
        goto exit_error;
    }
 
    chan = &(deviceExtension->chan[0]);
    AtapiSetupLunPtrs(chan, deviceExtension, 0);
 
    deviceExtension->AdapterInterfaceType =
    deviceExtension->OrigAdapterInterfaceType
                                        = ConfigInfo->AdapterInterfaceType;
 
#ifndef UNIATA_CORE
 
    /* do extra chipset specific setups */
    AtapiReadChipConfig(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, CHAN_NOT_SPECIFIED);
    AtapiChipInit(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, CHAN_NOT_SPECIFIED);
 
    // Check to see if this is a special configuration environment.
    portBase = irq = 0;
    if (ArgumentString) {
 
        irq = AtapiParseArgumentString(ArgumentString, "Interrupt");
        if (irq ) {
 
            // Both parameters must be present to proceed
            portBase = AtapiParseArgumentString(ArgumentString, "BaseAddress");
            if (!portBase) {
 
                // Try a default search for the part.
                irq = 0;
            }
        }
    }
 
#endif //UNIATA_CORE
/*
    for(i=0; i<2; i++) {
        if((*ConfigInfo->AccessRanges)[i].RangeStart) {
            KdPrint2((PRINT_PREFIX "  IoRange[%d], start %#x, len %#x, mem %#x\n",
                i,
                ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[i].RangeStart),
                (*ConfigInfo->AccessRanges)[i].RangeLength,
                (*ConfigInfo->AccessRanges)[i].RangeInMemory
                ));
        }
    }
*/
//    if((*ConfigInfo->AccessRanges)[0].RangeStart) {
        portBase = ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[0].RangeStart);
//    }
    if(portBase) {
        if(!AtapiCheckIOInterference(ConfigInfo, portBase)) {
            ioSpace =  (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
                                             ConfigInfo->AdapterInterfaceType,
                                             ConfigInfo->SystemIoBusNumber,
                                             (*ConfigInfo->AccessRanges)[0].RangeStart,
                                             (*ConfigInfo->AccessRanges)[0].RangeLength,
                                             (BOOLEAN) !((*ConfigInfo->AccessRanges)[0].RangeInMemory));
        } else {
            // do not touch resources, just fail later inside loop on next call to
            // AtapiCheckIOInterference()
        }
        *Again = FALSE;
        // Since we have pre-configured information we only need to go through this loop once
        preConfig = TRUE;
        KdPrint2((PRINT_PREFIX "  preconfig, portBase=%x, len=%x\n", portBase, (*ConfigInfo->AccessRanges)[0].RangeLength));
    }
 
    // Scan through the adapter address looking for adapters.
#ifndef UNIATA_CORE
    while (AdapterAddresses[*adapterCount] != 0) {
#else
    do {
#endif //UNIATA_CORE
 
        retryCount = 4;
        deviceExtension->DevIndex = (*adapterCount); // this is used inside AtapiRegCheckDevValue()
        KdPrint2((PRINT_PREFIX "AtapiFindIsaController: adapterCount=%d\n", *adapterCount));
 
        for (i = 0; i < deviceExtension->NumberLuns; i++) {
            // Zero device fields to ensure that if earlier devices were found,
            // but not claimed, the fields are cleared.
            deviceExtension->lun[i].DeviceFlags &= ~(DFLAGS_ATAPI_DEVICE | DFLAGS_DEVICE_PRESENT | DFLAGS_TAPE_DEVICE);
        }
        // Get the system physical address for this IO range.
 
        // Check if configInfo has the default information
        // if not, we go and find ourselves
        if (preConfig == FALSE) {
 
            ULONG portBase_reg = 0;
            ULONG irq_reg = 0;
 
            if (!portBase) {
                portBase = AdapterAddresses[*adapterCount];
                KdPrint2((PRINT_PREFIX "portBase[%d]=%x\n", *adapterCount, portBase));
            } else {
                KdPrint2((PRINT_PREFIX "portBase=%x\n", portBase));
            }
 
            portBase_reg = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"PortBase", 0);
            irq_reg      = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"Irq", 0);
            if(portBase_reg && irq_reg) {
                KdPrint2((PRINT_PREFIX "use registry settings portBase=%x, irq=%d\n", portBase_reg, irq_reg));
                portBase = portBase_reg;
                irq = irq_reg;
            }
            // check if Primary/Secondary Master IDE claimed
            if(AtapiCheckIOInterference(ConfigInfo, portBase)) {
                goto next_adapter;
            }
            ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
                                            ConfigInfo->AdapterInterfaceType,
                                            ConfigInfo->SystemIoBusNumber,
                                            ScsiPortConvertUlongToPhysicalAddress(portBase),
                                            ATA_IOSIZE,
                                            TRUE);
 
        } else {
            KdPrint2((PRINT_PREFIX "preconfig portBase=%x\n", portBase));
            // Check if Primary/Secondary Master IDE claimed
            // We can also get here from preConfig branc with conflicting portBase
            //   (and thus, w/o ioSpace allocated)
            if(AtapiCheckIOInterference(ConfigInfo, portBase)) {
                goto not_found;
            }
        }
        BaseIoAddress1 = (PIDE_REGISTERS_1)ioSpace;
next_adapter:
        // Update the adapter count.
        (*adapterCount)++;
 
        // Check if ioSpace accessible.
        if (!ioSpace) {
            KdPrint2((PRINT_PREFIX "AtapiFindIsaController: !ioSpace\n"));
            portBase = 0;
            continue;
        }
 
        // Get the system physical address for the second IO range.
        if (BaseIoAddress1) {
            if(preConfig &&
               !ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[1].RangeStart)) {
                KdPrint2((PRINT_PREFIX "AtapiFindIsaController: PCMCIA ?\n"));
                ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
                                                ConfigInfo->AdapterInterfaceType,
                                                ConfigInfo->SystemIoBusNumber,
                                                ScsiPortConvertUlongToPhysicalAddress((ULONGIO_PTR)BaseIoAddress1 + 0x0E),
                                                ATA_ALTIOSIZE,
                                                TRUE);
            } else {
                ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
                                                ConfigInfo->AdapterInterfaceType,
                                                ConfigInfo->SystemIoBusNumber,
                                                ScsiPortConvertUlongToPhysicalAddress((ULONGIO_PTR)BaseIoAddress1 + ATA_ALTOFFSET),
                                                ATA_ALTIOSIZE,
                                                TRUE);
            }
        }
        BaseIoAddress2 = (PIDE_REGISTERS_2)ioSpace;
        KdPrint2((PRINT_PREFIX "  BaseIoAddress1=%x\n", BaseIoAddress1));
        KdPrint2((PRINT_PREFIX "  BaseIoAddress2=%x\n", BaseIoAddress2));
        if(!irq) {
            KdPrint2((PRINT_PREFIX "  expected InterruptLevel=%x\n", InterruptLevels[*adapterCount - 1]));
        }
 
        UniataInitMapBase(chan, BaseIoAddress1, BaseIoAddress2);
        UniataInitMapBM(deviceExtension, 0, FALSE);
 
#ifdef _DEBUG
        UniataDumpATARegs(chan);
#endif
 
        // Select master.
        SelectDrive(chan, 0);
 
        statusByte = AtapiReadPort1(chan, IDX_IO1_i_Status);
        statusByte2 = AtapiReadPort1(chan, IDX_IO2_AltStatus);
        if((statusByte ^ statusByte2) & ~IDE_STATUS_INDEX) {
            KdPrint2((PRINT_PREFIX "AtapiFindIsaController: Status %x vs AltStatus %x missmatch, abort init ?\n", statusByte, statusByte2));
 
            if(BaseIoAddress2) {
                ScsiPortFreeDeviceBase(HwDeviceExtension,
                                       (PCHAR)BaseIoAddress2);
                BaseIoAddress2 = NULL;
            }
            BaseIoAddress2 = (PIDE_REGISTERS_2)((ULONGIO_PTR)BaseIoAddress1 + 0x0E);
            KdPrint2((PRINT_PREFIX "  try BaseIoAddress2=%x\n", BaseIoAddress2));
            ioSpace = (PUCHAR)ScsiPortGetDeviceBase(HwDeviceExtension,
                                            ConfigInfo->AdapterInterfaceType,
                                            ConfigInfo->SystemIoBusNumber,
                                            ScsiPortConvertUlongToPhysicalAddress((ULONGIO_PTR)BaseIoAddress2),
                                            ATA_ALTIOSIZE,
                                            TRUE);
            if(!ioSpace) {
                BaseIoAddress2 = NULL;
                KdPrint2((PRINT_PREFIX "    abort (0)\n"));
                goto not_found;
            }
            UniataInitMapBase(chan, BaseIoAddress1, BaseIoAddress2);
            statusByte = AtapiReadPort1(chan, IDX_IO1_i_Status);
            statusByte2 = AtapiReadPort1(chan, IDX_IO2_AltStatus);
            if((statusByte ^ statusByte2) & ~IDE_STATUS_INDEX) {
                KdPrint2((PRINT_PREFIX "    abort: Status %x vs AltStatus %x missmatch\n", statusByte, statusByte2));
                goto not_found;
            }
        }
 
retryIdentifier:
 
        // Select master.
        SelectDrive(chan, 0);
 
        // Check if card at this address.
        AtapiWritePort1(chan, IDX_IO1_o_CylinderLow, 0xAA);
        statusByte = AtapiReadPort1(chan, IDX_IO1_i_CylinderLow);
 
        // Check if indentifier can be read back.
        if (AtapiReadPort1(chan, IDX_IO1_i_CylinderLow) != 0xAA ||
            statusByte == IDE_STATUS_WRONG) {
 
            KdPrint2((PRINT_PREFIX "AtapiFindIsaController: Identifier read back from Master (%#x)\n",
                        statusByte));
 
            statusByte = AtapiReadPort1(chan, IDX_IO2_AltStatus);
 
            if (statusByte != IDE_STATUS_WRONG && (statusByte & IDE_STATUS_BUSY)) {
 
                i = 0;
 
                // Could be the TEAC in a thinkpad. Their dos driver puts it in a sleep-mode that
                // warm boots don't clear.
                do {
                    AtapiStallExecution(1000);
                    statusByte = AtapiReadPort1(chan, IDX_ATAPI_IO1_i_Status);
                    KdPrint2((PRINT_PREFIX
                                "AtapiFindIsaController: First access to status %#x\n",
                                statusByte));
                } while ((statusByte & IDE_STATUS_BUSY) && ++i < 10);
 
                if (retryCount-- && (!(statusByte & IDE_STATUS_BUSY))) {
                    goto retryIdentifier;
                }
            }
 
            // Select slave.
            SelectDrive(chan, 1);
            statusByte = AtapiReadPort1(chan, IDX_IO2_AltStatus);
 
            // See if slave is present.
            AtapiWritePort1(chan, IDX_IO1_o_CylinderLow, 0xAA);
 
            if (AtapiReadPort1(chan, IDX_IO1_i_CylinderLow) != 0xAA ||
                statusByte == IDE_STATUS_WRONG) {
 
                KdPrint2((PRINT_PREFIX
                            "AtapiFindIsaController: Identifier read back from Slave (%#x)\n",
                            statusByte));
                goto not_found;
            }
        }
 
        // Fill in the access array information only if default params are not in there.
        if (preConfig == FALSE) {
 
            // An adapter has been found request another call, only if we didn't get preconfigured info.
            *Again = TRUE;
 
            if (portBase) {
                (*ConfigInfo->AccessRanges)[0].RangeStart = ScsiPortConvertUlongToPhysicalAddress(portBase);
            } else {
                (*ConfigInfo->AccessRanges)[0].RangeStart =
                    ScsiPortConvertUlongToPhysicalAddress(AdapterAddresses[*adapterCount - 1]);
            }
 
            (*ConfigInfo->AccessRanges)[0].RangeLength = ATA_IOSIZE;
            (*ConfigInfo->AccessRanges)[0].RangeInMemory = FALSE;
 
            if(BaseIoAddress2) {
                if(hasPCI) {
                    (*ConfigInfo->AccessRanges)[1].RangeStart = ScsiPortConvertUlongToPhysicalAddress((ULONG_PTR)BaseIoAddress2);
                    (*ConfigInfo->AccessRanges)[1].RangeLength = ATA_ALTIOSIZE;
                    (*ConfigInfo->AccessRanges)[1].RangeInMemory = FALSE;
                } else {
                    // NT4 and NT3.51 on ISA-only hardware definitly fail floppy.sys load
                    // when this range is claimed by other driver.
                    // However, floppy should use only 0x3f0-3f5,3f7
                    if((ULONGIO_PTR)BaseIoAddress2 >= 0x3f0 && (ULONGIO_PTR)BaseIoAddress2 <= 0x3f7) {
                        KdPrint2((PRINT_PREFIX "!!! Possible AltStatus vs Floppy IO range interference !!!\n"));
                    }
                    KdPrint2((PRINT_PREFIX "Do not expose to OS on old ISA\n"));
                    (*ConfigInfo->AccessRanges)[1].RangeStart = ScsiPortConvertUlongToPhysicalAddress(0);
                    (*ConfigInfo->AccessRanges)[1].RangeLength = 0;
                }
            }
 
            // Indicate the interrupt level corresponding to this IO range.
            if (irq) {
                ConfigInfo->BusInterruptLevel = irq;
            } else {
                ConfigInfo->BusInterruptLevel = InterruptLevels[*adapterCount - 1];
            }
 
            if (ConfigInfo->AdapterInterfaceType == MicroChannel) {
                ConfigInfo->InterruptMode = LevelSensitive;
            } else {
                ConfigInfo->InterruptMode = Latched;
            }
        }
 
        ConfigInfo->NumberOfBuses = 1;
        ConfigInfo->MaximumNumberOfTargets = IDE_MAX_LUN_PER_CHAN;
 
        // Indicate maximum transfer length is 64k.
        ConfigInfo->MaximumTransferLength = 0x10000;
        deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength;
 
        KdPrint2((PRINT_PREFIX "de %#x, Channel ???\n", deviceExtension));
        //PrintNtConsole("de %#x, Channel %#x, nchan %#x\n",deviceExtension, channel, deviceExtension->NumberChannels);
 
        KdPrint2((PRINT_PREFIX "chan = %#x\n", chan));
        //PrintNtConsole("chan = %#x, c=%#x\n", chan, c);
/*
        // should be already set up in AtapiSetupLunPtrs(chan, deviceExtension, 0);
 
        chan->DeviceExtension = deviceExtension;
        chan->lChannel        = 0;
        chan->lun[0] = &(deviceExtension->lun[0]);
        chan->lun[1] = &(deviceExtension->lun[1]);*/
 
        /* do extra channel-specific setups */
        AtapiReadChipConfig(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, 0);
        AtapiChipInit(HwDeviceExtension, DEVNUM_NOT_SPECIFIED, 0);
 
        KdPrint2((PRINT_PREFIX
                   "AtapiFindIsaController: Found IDE at %#x\n",
                   BaseIoAddress1));
 
        // For Daytona, the atdisk driver gets the first shot at the
        // primary and secondary controllers.
        if (preConfig == FALSE) {
 
            if (*adapterCount - 1 < 2) {
 
                // Determine whether this driver is being initialized by the
                // system or as a crash dump driver.
                if (g_Dump) {
#ifndef UNIATA_CORE
                    deviceExtension->DriverMustPoll = TRUE;
#endif //UNIATA_CORE
                } else {
                    deviceExtension->DriverMustPoll = FALSE;
                }
 
            } else {
                //atapiOnly = FALSE;
            }
 
        } else {
 
            //atapiOnly = FALSE;
            deviceExtension->DriverMustPoll = FALSE;
 
        }// preConfig check
 
        // Save the Interrupe Mode for later use
        deviceExtension->InterruptMode = ConfigInfo->InterruptMode;
        deviceExtension->BusInterruptLevel = ConfigInfo->BusInterruptLevel;
        deviceExtension->BusInterruptVector = ConfigInfo->BusInterruptVector;
 
        KdPrint2((PRINT_PREFIX
                   "AtapiFindIsaController: look for devices\n"));
        // Search for devices on this controller.
        if (FindDevices(HwDeviceExtension,
                        0,
                        0 /* Channel */)) {
 
            KdPrint2((PRINT_PREFIX
                       "AtapiFindIsaController: detected\n"));
            // Claim primary or secondary ATA IO range.
            if (portBase) {
                switch (portBase) {
                case IO_WD2:
                    ConfigInfo->AtdiskSecondaryClaimed = TRUE;
                    chan->PrimaryAddress = FALSE;
                    break;
                case IO_WD1:
                    ConfigInfo->AtdiskPrimaryClaimed = TRUE;
                    chan->PrimaryAddress = TRUE;
                    break;
                default:
                    break;
                }
            } else {
                if (*adapterCount == 1) {
                    ConfigInfo->AtdiskPrimaryClaimed = TRUE;
                    chan->PrimaryAddress = TRUE;
                } else if (*adapterCount == 2) {
                    ConfigInfo->AtdiskSecondaryClaimed = TRUE;
                    chan->PrimaryAddress = FALSE;
                }
            }
 
            if(deviceExtension->AdapterInterfaceType == Isa) {
                IsaCount++;
            } else
            if(deviceExtension->AdapterInterfaceType == MicroChannel) {
                MCACount++;
            }
 
            ConfigInfo->NumberOfBuses++; // add virtual channel for communication port
            KdPrint2((PRINT_PREFIX
                       "AtapiFindIsaController: return SP_RETURN_FOUND\n"));
            return(SP_RETURN_FOUND);
        } else {
not_found:
            // No controller at this base address.
            if(BaseIoAddress1) {
                ScsiPortFreeDeviceBase(HwDeviceExtension,
                                       (PCHAR)BaseIoAddress1);
                BaseIoAddress1 = NULL;
            }
            if(BaseIoAddress2) {
                ScsiPortFreeDeviceBase(HwDeviceExtension,
                                       (PCHAR)BaseIoAddress2);
                BaseIoAddress2 = NULL;
            }
            for(i=0; i<2; i++) {
                KdPrint2((PRINT_PREFIX
                           "AtapiFindIsaController: cleanup AccessRanges %d\n", i));
                (*ConfigInfo->AccessRanges)[i].RangeStart = ScsiPortConvertUlongToPhysicalAddress(0);
                (*ConfigInfo->AccessRanges)[i].RangeLength = 0;
                (*ConfigInfo->AccessRanges)[i].RangeInMemory = FALSE;
            }
            irq = 0;
            portBase = 0;
        }
#ifndef UNIATA_CORE
    }
#else
    } while(FALSE);
#endif //UNIATA_CORE
 
    // The entire table has been searched and no adapters have been found.
    // There is no need to call again and the device base can now be freed.
    // Clear the adapter count for the next bus.
    *Again = FALSE;
    *(adapterCount) = 0;
 
    KdPrint2((PRINT_PREFIX
               "AtapiFindIsaController: return SP_RETURN_NOT_FOUND\n"));
    UniataFreeLunExt(deviceExtension);
    return(SP_RETURN_NOT_FOUND);
 
exit_error:
    UniataFreeLunExt(deviceExtension);
    return SP_RETURN_ERROR;
 
} // end AtapiFindIsaController()

Referenced by DriverEntry().

◆ AtapiHardReset()

VOID DDKFASTAPI AtapiHardReset	(	IN struct _HW_CHANNEL *	chan,
		IN BOOLEAN	DisableInterrupts,
		IN ULONG	Delay
	)

Definition at line 948 of file id_ata.cpp.

{
    KdPrint2((PRINT_PREFIX "AtapiHardReset: %d, dis=%d\n", Delay, DisableInterrupts));
    AtapiWritePort1(chan, IDX_IO2_o_Control, IDE_DC_RESET_CONTROLLER |
                              (DisableInterrupts ? IDE_DC_DISABLE_INTERRUPTS : 0));
    chan->last_devsel = -1;
    AtapiStallExecution(Delay);
    AtapiWritePort1(chan, IDX_IO2_o_Control, IDE_DC_REENABLE_CONTROLLER);
} // end AtapiHardReset()

Referenced by AtapiResetController__(), CheckDevice(), and FindDevices().

◆ AtapiHexToString()

VOID NTAPI AtapiHexToString	(	ULONG	Value,
		PCHAR *	Buffer
	)

◆ AtapiHwInitialize()

BOOLEAN NTAPI AtapiHwInitialize ( IN PVOID HwDeviceExtension )

Definition at line 1282 of file atapi.c.

{
    PHW_DEVICE_EXTENSION deviceExtension = HwDeviceExtension;
    PIDE_REGISTERS_1     baseIoAddress;
    ULONG i;
    UCHAR statusByte, errorByte;
 
 
    for (i = 0; i < 4; i++) {
        if (deviceExtension->DeviceFlags[i] & DFLAGS_DEVICE_PRESENT) {
 
            if (!(deviceExtension->DeviceFlags[i] & DFLAGS_ATAPI_DEVICE)) {
 
                //
                // Enable media status notification
                //
 
                baseIoAddress = deviceExtension->BaseIoAddress1[i >> 1];
 
                IdeMediaStatus(TRUE,HwDeviceExtension,i);
 
                //
                // If supported, setup Multi-block transfers.
                //
                if (deviceExtension->MaximumBlockXfer[i]) {
 
                    //
                    // Select the device.
                    //
 
                    ScsiPortWritePortUchar(&baseIoAddress->DriveSelect,
                                           (UCHAR)(((i & 0x1) << 4) | 0xA0));
 
                    //
                    // Setup sector count to reflect the # of blocks.
                    //
 
                    ScsiPortWritePortUchar(&baseIoAddress->BlockCount,
                                           deviceExtension->MaximumBlockXfer[i]);
 
                    //
                    // Issue the command.
                    //
 
                    ScsiPortWritePortUchar(&baseIoAddress->Command,
                                           IDE_COMMAND_SET_MULTIPLE);
 
                    //
                    // Wait for busy to drop.
                    //
 
                    WaitOnBaseBusy(baseIoAddress,statusByte);
 
                    //
                    // Check for errors. Reset the value to 0 (disable MultiBlock) if the
                    // command was aborted.
                    //
 
                    if (statusByte & IDE_STATUS_ERROR) {
 
                        //
                        // Read the error register.
                        //
 
                        errorByte = ScsiPortReadPortUchar((PUCHAR)baseIoAddress + 1);
 
                        DebugPrint((1,
                                    "AtapiHwInitialize: Error setting multiple mode. Status %x, error byte %x\n",
                                    statusByte,
                                    errorByte));
                        //
                        // Adjust the devExt. value, if necessary.
                        //
 
                        deviceExtension->MaximumBlockXfer[i] = 0;
 
                    } else {
                        DebugPrint((2,
                                    "AtapiHwInitialize: Using Multiblock on Device %d. Blocks / int - %d\n",
                                    i,
                                    deviceExtension->MaximumBlockXfer[i]));
                    }
                }
            } else if (!(deviceExtension->DeviceFlags[i] & DFLAGS_CHANGER_INITED)){
 
                ULONG j;
                UCHAR vendorId[26];
 
                //
                // Attempt to identify any special-case devices - psuedo-atapi changers, atapi changers, etc.
                //
 
                for (j = 0; j < 13; j += 2) {
 
                    //
                    // Build a buffer based on the identify data.
                    //
 
                    vendorId[j] = ((PUCHAR)deviceExtension->IdentifyData[i].ModelNumber)[j + 1];
                    vendorId[j+1] = ((PUCHAR)deviceExtension->IdentifyData[i].ModelNumber)[j];
                }
 
                if (!AtapiStringCmp ((PCHAR)vendorId, "CD-ROM  CDR", 11)) {
 
                    //
                    // Inquiry string for older model had a '-', newer is '_'
                    //
 
                    if (vendorId[12] == 'C') {
 
                        //
                        // Torisan changer. Set the bit. This will be used in several places
                        // acting like 1) a multi-lun device and 2) building the 'special' TUR's.
                        //
 
                        deviceExtension->DeviceFlags[i] |= (DFLAGS_CHANGER_INITED | DFLAGS_SANYO_ATAPI_CHANGER);
                        deviceExtension->DiscsPresent[i] = 3;
                    }
                }
            }
 
            //
            // We need to get our device ready for action before
            // returning from this function
            //
            // According to the atapi spec 2.5 or 2.6, an atapi device
            // clears its status BSY bit when it is ready for atapi commands.
            // However, some devices (Panasonic SQ-TC500N) are still
            // not ready even when the status BSY is clear.  They don't react
            // to atapi commands.
            //
            // Since there is really no other indication that tells us
            // the drive is really ready for action.  We are going to check BSY
            // is clear and then just wait for an arbitrary amount of time!
            //
            if (deviceExtension->DeviceFlags[i] & DFLAGS_ATAPI_DEVICE) {
                //PIDE_REGISTERS_1     baseIoAddress1 = deviceExtension->BaseIoAddress1[i >> 1];
                PIDE_REGISTERS_2     baseIoAddress2 = deviceExtension->BaseIoAddress2[i >> 1];
                ULONG waitCount;
 
                // have to get out of the loop sometime!
                // 10000 * 100us = 1000,000us = 1000ms = 1s
                waitCount = 10000;
                GetStatus(baseIoAddress2, statusByte);
                while ((statusByte & IDE_STATUS_BUSY) && waitCount) {
                    //
                    // Wait for Busy to drop.
                    //
                    ScsiPortStallExecution(100);
                    GetStatus(baseIoAddress2, statusByte);
                    waitCount--;
                }
 
                // 5000 * 100us = 500,000us = 500ms = 0.5s
                waitCount = 5000;
                do {
                    ScsiPortStallExecution(100);
                } while (waitCount--);
            }
        }
    }
 
    return TRUE;
 
} // end AtapiHwInitialize()

Referenced by AtapiResetController(), and DriverEntry().

◆ AtapiHwInitializeChanger()

VOID NTAPI AtapiHwInitializeChanger	(	IN PVOID	HwDeviceExtension,
		IN ULONG	TargetId,
		IN PMECHANICAL_STATUS_INFORMATION_HEADER	MechanismStatus
	)

Definition at line 1469 of file atapi.c.

{
    PHW_DEVICE_EXTENSION deviceExtension = HwDeviceExtension;
 
    if (MechanismStatus) {
        deviceExtension->DiscsPresent[TargetId] = MechanismStatus->NumberAvailableSlots;
        if (deviceExtension->DiscsPresent[TargetId] > 1) {
            deviceExtension->DeviceFlags[TargetId] |= DFLAGS_ATAPI_CHANGER;
        }
    }
    return;
}

Referenced by AtapiInterrupt(), and AtapiSendCommand().

◆ AtapiInterrupt()

BOOLEAN NTAPI AtapiInterrupt ( IN PVOID HwDeviceExtension )

Definition at line 3484 of file atapi.c.

{
    PHW_DEVICE_EXTENSION deviceExtension = HwDeviceExtension;
    PSCSI_REQUEST_BLOCK srb              = deviceExtension->CurrentSrb;
    PATAPI_REGISTERS_1 baseIoAddress1;
    PATAPI_REGISTERS_2 baseIoAddress2;
    ULONG wordCount = 0, wordsThisInterrupt = 256;
    ULONG status;
    ULONG i;
    UCHAR statusByte,interruptReason;
    BOOLEAN atapiDev = FALSE;
 
    if (srb) {
        baseIoAddress1 =    (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[srb->TargetId >> 1];
        baseIoAddress2 =    (PATAPI_REGISTERS_2)deviceExtension->BaseIoAddress2[srb->TargetId >> 1];
    } else {
        DebugPrint((2,
                    "AtapiInterrupt: CurrentSrb is NULL\n"));
        //
        // We can only support one ATAPI IDE master on Carolina, so find
        // the base address that is non NULL and clear its interrupt before
        // returning.
        //
 
#ifdef _PPC_
 
        if ((PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[0] != NULL) {
           baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[0];
        } else {
           baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[1];
        }
 
        GetBaseStatus(baseIoAddress1, statusByte);
#else
 
        if (deviceExtension->InterruptMode == LevelSensitive) {
            if (deviceExtension->BaseIoAddress1[0] != NULL) {
               baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[0];
               GetBaseStatus(baseIoAddress1, statusByte);
            }
            if (deviceExtension->BaseIoAddress1[1] != NULL) {
               baseIoAddress1 = (PATAPI_REGISTERS_1)deviceExtension->BaseIoAddress1[1];
               GetBaseStatus(baseIoAddress1, statusByte);
            }
        }
#endif
        return FALSE;
    }
 
    if (!(deviceExtension->ExpectingInterrupt)) {
 
        DebugPrint((3,
                    "AtapiInterrupt: Unexpected interrupt.\n"));
        return FALSE;
    }
 
    //
    // Clear interrupt by reading status.
    //
 
    GetBaseStatus(baseIoAddress1, statusByte);
 
    DebugPrint((3,
                "AtapiInterrupt: Entered with status (%x)\n",
                statusByte));
 
 
    if (statusByte & IDE_STATUS_BUSY) {
        if (deviceExtension->DriverMustPoll) {
 
            //
            // Crashdump is polling and we got caught with busy asserted.
            // Just go away, and we will be polled again shortly.
            //
 
            DebugPrint((3,
                        "AtapiInterrupt: Hit BUSY while polling during crashdump.\n"));
 
            return TRUE;
        }
 
        //
        // Ensure BUSY is non-asserted.
        //
 
        for (i = 0; i < 10; i++) {
 
            GetBaseStatus(baseIoAddress1, statusByte);
            if (!(statusByte & IDE_STATUS_BUSY)) {
                break;
            }
            ScsiPortStallExecution(5000);
        }
 
        if (i == 10) {
 
            DebugPrint((2,
                        "AtapiInterrupt: BUSY on entry. Status %x, Base IO %x\n",
                        statusByte,
                        baseIoAddress1));
 
            ScsiPortNotification(RequestTimerCall,
                                 HwDeviceExtension,
                                 AtapiCallBack,
                                 500);
            return TRUE;
        }
    }
 
 
    //
    // Check for error conditions.
    //
 
    if (statusByte & IDE_STATUS_ERROR) {
 
        if (srb->Cdb[0] != SCSIOP_REQUEST_SENSE) {
 
            //
            // Fail this request.
            //
 
            status = SRB_STATUS_ERROR;
            goto CompleteRequest;
        }
    }
 
    //
    // check reason for this interrupt.
    //
 
    if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
 
        interruptReason = (ScsiPortReadPortUchar(&baseIoAddress1->InterruptReason) & 0x3);
        atapiDev = TRUE;
        wordsThisInterrupt = 256;
 
    } else {
 
        if (statusByte & IDE_STATUS_DRQ) {
 
            if (deviceExtension->MaximumBlockXfer[srb->TargetId]) {
                wordsThisInterrupt = 256 * deviceExtension->MaximumBlockXfer[srb->TargetId];
 
            }
 
            if (srb->SrbFlags & SRB_FLAGS_DATA_IN) {
 
                interruptReason =  0x2;
 
            } else if (srb->SrbFlags & SRB_FLAGS_DATA_OUT) {
                interruptReason = 0x0;
 
            } else {
                status = SRB_STATUS_ERROR;
                goto CompleteRequest;
            }
 
        } else if (statusByte & IDE_STATUS_BUSY) {
 
            return FALSE;
 
        } else {
 
            if (deviceExtension->WordsLeft) {
 
                ULONG k;
 
                //
                // Funky behaviour seen with PCI IDE (not all, just one).
                // The ISR hits with DRQ low, but comes up later.
                //
 
                for (k = 0; k < 5000; k++) {
                    GetStatus(baseIoAddress2,statusByte);
                    if (!(statusByte & IDE_STATUS_DRQ)) {
                        ScsiPortStallExecution(100);
                    } else {
                        break;
                    }
                }
 
                if (k == 5000) {
 
                    //
                    // reset the controller.
                    //
 
                    DebugPrint((1,
                                "AtapiInterrupt: Resetting due to DRQ not up. Status %x, Base IO %x\n",
                                statusByte,
                                baseIoAddress1));
 
                    AtapiResetController(HwDeviceExtension,srb->PathId);
                    return TRUE;
                } else {
 
                    interruptReason = (srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x2 : 0x0;
                }
 
            } else {
 
                //
                // Command complete - verify, write, or the SMART enable/disable.
                //
                // Also get_media_status
 
                interruptReason = 0x3;
            }
        }
    }
 
    if (interruptReason == 0x1 && (statusByte & IDE_STATUS_DRQ)) {
 
        //
        // Write the packet.
        //
 
        DebugPrint((2,
                    "AtapiInterrupt: Writing Atapi packet.\n"));
 
        //
        // Send CDB to device.
        //
 
        WriteBuffer(baseIoAddress1,
                    (PUSHORT)srb->Cdb,
                    6);
 
        return TRUE;
 
    } else if (interruptReason == 0x0 && (statusByte & IDE_STATUS_DRQ)) {
 
        //
        // Write the data.
        //
 
        if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
 
            //
            // Pick up bytes to transfer and convert to words.
            //
 
            wordCount =
                ScsiPortReadPortUchar(&baseIoAddress1->ByteCountLow);
 
            wordCount |=
                ScsiPortReadPortUchar(&baseIoAddress1->ByteCountHigh) << 8;
 
            //
            // Covert bytes to words.
            //
 
            wordCount >>= 1;
 
            if (wordCount != deviceExtension->WordsLeft) {
                DebugPrint((3,
                           "AtapiInterrupt: %d words requested; %d words xferred\n",
                           deviceExtension->WordsLeft,
                           wordCount));
            }
 
            //
            // Verify this makes sense.
            //
 
            if (wordCount > deviceExtension->WordsLeft) {
                wordCount = deviceExtension->WordsLeft;
            }
 
        } else {
 
            //
            // IDE path. Check if words left is at least 256.
            //
 
            if (deviceExtension->WordsLeft < wordsThisInterrupt) {
 
               //
               // Transfer only words requested.
               //
 
               wordCount = deviceExtension->WordsLeft;
 
            } else {
 
               //
               // Transfer next block.
               //
 
               wordCount = wordsThisInterrupt;
            }
        }
 
        //
        // Ensure that this is a write command.
        //
 
        if (srb->SrbFlags & SRB_FLAGS_DATA_OUT) {
 
           DebugPrint((3,
                      "AtapiInterrupt: Write interrupt\n"));
 
           WaitOnBusy(baseIoAddress2,statusByte);
 
           if (atapiDev || !deviceExtension->DWordIO) {
 
               WriteBuffer(baseIoAddress1,
                           deviceExtension->DataBuffer,
                           wordCount);
           } else {
 
               PIDE_REGISTERS_3 address3 = (PIDE_REGISTERS_3)baseIoAddress1;
 
               WriteBuffer2(address3,
                           (PULONG)(deviceExtension->DataBuffer),
                           wordCount / 2);
           }
        } else {
 
            DebugPrint((1,
                        "AtapiInterrupt: Int reason %x, but srb is for a write %x.\n",
                        interruptReason,
                        srb));
 
            //
            // Fail this request.
            //
 
            status = SRB_STATUS_ERROR;
            goto CompleteRequest;
        }
 
 
        //
        // Advance data buffer pointer and bytes left.
        //
 
        deviceExtension->DataBuffer += wordCount;
        deviceExtension->WordsLeft -= wordCount;
 
        return TRUE;
 
    } else if (interruptReason == 0x2 && (statusByte & IDE_STATUS_DRQ)) {
 
 
        if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
 
            //
            // Pick up bytes to transfer and convert to words.
            //
 
            wordCount =
                ScsiPortReadPortUchar(&baseIoAddress1->ByteCountLow);
 
            wordCount |=
                ScsiPortReadPortUchar(&baseIoAddress1->ByteCountHigh) << 8;
 
            //
            // Covert bytes to words.
            //
 
            wordCount >>= 1;
 
            if (wordCount != deviceExtension->WordsLeft) {
                DebugPrint((3,
                           "AtapiInterrupt: %d words requested; %d words xferred\n",
                           deviceExtension->WordsLeft,
                           wordCount));
            }
 
            //
            // Verify this makes sense.
            //
 
            if (wordCount > deviceExtension->WordsLeft) {
                wordCount = deviceExtension->WordsLeft;
            }
 
        } else {
 
            //
            // Check if words left is at least 256.
            //
 
            if (deviceExtension->WordsLeft < wordsThisInterrupt) {
 
               //
               // Transfer only words requested.
               //
 
               wordCount = deviceExtension->WordsLeft;
 
            } else {
 
               //
               // Transfer next block.
               //
 
               wordCount = wordsThisInterrupt;
            }
        }
 
        //
        // Ensure that this is a read command.
        //
 
        if (srb->SrbFlags & SRB_FLAGS_DATA_IN) {
 
           DebugPrint((3,
                      "AtapiInterrupt: Read interrupt\n"));
 
           WaitOnBusy(baseIoAddress2,statusByte);
 
           if (atapiDev || !deviceExtension->DWordIO) {
               ReadBuffer(baseIoAddress1,
                         deviceExtension->DataBuffer,
                         wordCount);
 
           } else {
               PIDE_REGISTERS_3 address3 = (PIDE_REGISTERS_3)baseIoAddress1;
 
               ReadBuffer2(address3,
                          (PULONG)(deviceExtension->DataBuffer),
                          wordCount / 2);
           }
        } else {
 
            DebugPrint((1,
                        "AtapiInterrupt: Int reason %x, but srb is for a read %x.\n",
                        interruptReason,
                        srb));
 
            //
            // Fail this request.
            //
 
            status = SRB_STATUS_ERROR;
            goto CompleteRequest;
        }
 
        //
        // Translate ATAPI data back to SCSI data if needed
        //
 
        if (srb->Cdb[0] == ATAPI_MODE_SENSE &&
            deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
 
            //
            //convert and adjust the wordCount
            //
 
            wordCount -= Atapi2Scsi(srb, (char *)deviceExtension->DataBuffer,
                                     wordCount << 1);
        }
        //
        // Advance data buffer pointer and bytes left.
        //
 
        deviceExtension->DataBuffer += wordCount;
        deviceExtension->WordsLeft -= wordCount;
 
        //
        // Check for read command complete.
        //
 
        if (deviceExtension->WordsLeft == 0) {
 
            if (deviceExtension->DeviceFlags[srb->TargetId] & DFLAGS_ATAPI_DEVICE) {
 
                //
                // Work around to make many atapi devices return correct sector size
                // of 2048. Also certain devices will have sector count == 0x00, check
                // for that also.
                //
 
                if ((srb->Cdb[0] == 0x25) &&
                    ((deviceExtension->IdentifyData[srb->TargetId].GeneralConfiguration >> 8) & 0x1f) == 0x05) {
 
                    deviceExtension->DataBuffer -= wordCount;
                    if (deviceExtension->DataBuffer[0] == 0x00) {
 
                        *((ULONG *) &(deviceExtension->DataBuffer[0])) = 0xFFFFFF7F;
 
                    }
 
                    *((ULONG *) &(deviceExtension->DataBuffer[2])) = 0x00080000;
                    deviceExtension->DataBuffer += wordCount;
                }
            } else {
 
                //
                // Completion for IDE drives.
                //
 
 
                if (deviceExtension->WordsLeft) {
 
                    status = SRB_STATUS_DATA_OVERRUN;
 
                } else {
 
                    status = SRB_STATUS_SUCCESS;
 
                }
 
                goto CompleteRequest;
 
            }
        }
 
        return TRUE;
 
    } else if (interruptReason == 0x3  && !(statusByte & IDE_STATUS_DRQ)) {
 
        //
        // Command complete.
        //
 
        if (deviceExtension->WordsLeft) {
 
            status = SRB_STATUS_DATA_OVERRUN;
 
        } else {
 
            status = SRB_STATUS_SUCCESS;
 
        }
 
CompleteRequest:
 
        //
        // Check and see if we are processing our secret (mechanism status/request sense) srb
        //
        if (deviceExtension->OriginalSrb) {
 
            ULONG srbStatus;
 
            if (srb->Cdb[0] == SCSIOP_MECHANISM_STATUS) {
 
                if (status == SRB_STATUS_SUCCESS) {
                    // Bingo!!
                    AtapiHwInitializeChanger (HwDeviceExtension,
                                              srb->TargetId,
                                              (PMECHANICAL_STATUS_INFORMATION_HEADER) srb->DataBuffer);
 
                    // Get ready to issue the original srb
                    srb = deviceExtension->CurrentSrb = deviceExtension->OriginalSrb;
                    deviceExtension->OriginalSrb = NULL;
 
                } else {
                    // failed!  Get the sense key and maybe try again
                    srb = deviceExtension->CurrentSrb = BuildRequestSenseSrb (
                                                          HwDeviceExtension,
                                                          deviceExtension->OriginalSrb->PathId,
                                                          deviceExtension->OriginalSrb->TargetId);
                }
 
                srbStatus = AtapiSendCommand(HwDeviceExtension, deviceExtension->CurrentSrb);
                if (srbStatus == SRB_STATUS_PENDING) {
                    return TRUE;
                }
 
            } else { // srb->Cdb[0] == SCSIOP_REQUEST_SENSE)
 
                PSENSE_DATA senseData = (PSENSE_DATA) srb->DataBuffer;
 
                if (status == SRB_STATUS_DATA_OVERRUN) {
                    // Check to see if we at least get minimum number of bytes
                    if ((srb->DataTransferLength - deviceExtension->WordsLeft) >
                        (FIELD_OFFSET (SENSE_DATA, AdditionalSenseLength) + sizeof(senseData->AdditionalSenseLength))) {
                        status = SRB_STATUS_SUCCESS;
                    }
                }
 
                if (status == SRB_STATUS_SUCCESS) {
                    if ((senseData->SenseKey != SCSI_SENSE_ILLEGAL_REQUEST) &&
                        deviceExtension->MechStatusRetryCount) {
 
                        // The sense key doesn't say the last request is illegal, so try again
                        deviceExtension->MechStatusRetryCount--;
                        srb = deviceExtension->CurrentSrb = BuildMechanismStatusSrb (
                                                              HwDeviceExtension,
                                                              deviceExtension->OriginalSrb->PathId,
                                                              deviceExtension->OriginalSrb->TargetId);
                    } else {
 
                        // last request was illegal.  No point trying again
 
                        AtapiHwInitializeChanger (HwDeviceExtension,
                                                  srb->TargetId,
                                                  (PMECHANICAL_STATUS_INFORMATION_HEADER) NULL);
 
                        // Get ready to issue the original srb
                        srb = deviceExtension->CurrentSrb = deviceExtension->OriginalSrb;
                        deviceExtension->OriginalSrb = NULL;
                    }
 
                    srbStatus = AtapiSendCommand(HwDeviceExtension, deviceExtension->CurrentSrb);
                    if (srbStatus == SRB_STATUS_PENDING) {
                        return TRUE;
                    }
                }
            }
 
            // If we get here, it means AtapiSendCommand() has failed
            // Can't recover.  Pretend the original srb has failed and complete it.
 
            if (deviceExtension->OriginalSrb) {
                AtapiHwInitializeChanger (HwDeviceExtension,
                                          srb->TargetId,
         

Classes

Macros

Typedefs

Functions

Variables

Macro Definition Documentation

◆ AdvancedPIOModes_3

◆ AdvancedPIOModes_4

◆ AdvancedPIOModes_5

◆ ATA_AT_HOME_ATAPI

◆ ATA_AT_HOME_HDD

◆ ATA_AT_HOME_NOBODY

◆ ATA_AT_HOME_XXX

◆ ATA_BT_DUALPORTMULTI

◆ ATA_BT_DUALPORTMULTICACHE

◆ ATA_BT_SINGLEPORTSECTOR

◆ ATA_C_F_AAM_CNT_MAX_PERF

◆ ATA_C_F_AAM_CNT_MAX_POWER_SAVE

◆ ATA_C_F_APM_CNT_MAX_PERF

◆ ATA_C_F_APM_CNT_MIN_NO_STANDBY

◆ ATA_C_F_APM_CNT_MIN_STANDBY

◆ ATA_C_F_DIS_ACOUSTIC

◆ ATA_C_F_DIS_APM

◆ ATA_C_F_DIS_MEDIASTAT

◆ ATA_C_F_DIS_RCACHE

◆ ATA_C_F_DIS_RELIRQ

◆ ATA_C_F_DIS_SRVIRQ

◆ ATA_C_F_DIS_WCACHE

◆ ATA_C_F_ENAB_ACOUSTIC

◆ ATA_C_F_ENAB_APM

◆ ATA_C_F_ENAB_MEDIASTAT

◆ ATA_C_F_ENAB_RCACHE

◆ ATA_C_F_ENAB_RELIRQ

◆ ATA_C_F_ENAB_SRVIRQ

◆ ATA_C_F_ENAB_WCACHE

◆ ATA_C_F_SETXFER

◆ ATA_ChecksumValid

◆ ATA_CMD_FLAG_48

◆ ATA_CMD_FLAG_48supp

◆ ATA_CMD_FLAG_DMA

◆ ATA_CMD_FLAG_FUA

◆ ATA_CMD_FLAG_In

◆ ATA_CMD_FLAG_LBAIOsupp

◆ ATA_CMD_FLAG_Out

◆ ATA_DMA

◆ ATA_F_DMA

◆ ATA_F_DMAREAD

◆ ATA_F_OVL

◆ ATA_I_CMD

◆ ATA_I_IN

◆ ATA_I_RELEASE

◆ ATA_I_TAGMASK

◆ ATA_MODE_NOT_SPEC

◆ ATA_PIO

◆ ATA_PIO0

◆ ATA_PIO1

◆ ATA_PIO2

◆ ATA_PIO3

◆ ATA_PIO4

◆ ATA_PIO5

◆ ATA_PIO_NRDY

◆ ATA_SA150

◆ ATA_SA300

◆ ATA_SA600

◆ ATA_SATA_GEN1

◆ ATA_SATA_GEN2

◆ ATA_SATA_GEN3

◆ ATA_SDMA

◆ ATA_SDMA0

◆ ATA_SDMA1

◆ ATA_SDMA2

◆ ATA_SUPPORT_AUTOACTIVATE

◆ ATA_SUPPORT_IFPWRMNGT

◆ ATA_SUPPORT_IFPWRMNGTRCV

◆ ATA_SUPPORT_INORDERDATA

◆ ATA_SUPPORT_NCQ

◆ ATA_SUPPORT_NCQ_PRI_INFO

◆ ATA_SUPPORT_NCQ_UNLOAD

◆ ATA_SUPPORT_NONZERO

◆ ATA_SUPPORT_PHY_EVENT_COUNTER