110 *(
volatile char*)
data;
257 ULONG dma_count, dma_base, dma_baseu;
258 ULONG dma_count0, dma_base0;
275 AtaReq->
ata.dma_base = 0;
305 AtaReq->
ahci.ahci_base64 = 0;
311 KdPrint2((
PRINT_PREFIX "AtapiDmaSetup: SRB built-in PRD above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
312 if(!deviceExtension->
Host64) {
318 if(!dma_base || !
i || ((
LONG)(dma_base) == -1)) {
322 AtaReq->
ata.dma_base = dma_base;
326 if(dma_baseu && dma_count) {
327 KdPrint2((
PRINT_PREFIX "AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x cnt=%x\n", dma_baseu, dma_base, dma_count));
328 if(!deviceExtension->
Host64) {
337 if(!dma_count || ((
LONG)(dma_base) == -1)) {
349 dma_count0 = dma_count;
350 dma_base0 = dma_base;
356 if(dma_base0+dma_count0 == dma_base &&
357 dma_count0+dma_count <= max_frag) {
360 if(dma_base & seg_align) {
365 dma_base = dma_base0;
366 dma_count += dma_count0;
370 AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].base = dma_base;
371 AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].baseu = dma_baseu;
372 AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].Reserved1 = 0;
373 *((
PULONG)&(AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].DBC_ULONG)) = ((dma_count-1) & 0x3fffff);
381 dma_count0 = dma_count;
382 dma_base0 = dma_base;
384 if (
i >= max_entries) {
392 if(dma_baseu && dma_count) {
393 KdPrint2((
PRINT_PREFIX "AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x, cnt=%x\n", dma_baseu, dma_base, dma_count));
394 if(!deviceExtension->
Host64) {
396 KdPrint2((
PRINT_PREFIX "AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
403 if(!dma_count || !dma_base || ((
LONG)(dma_base) == -1)) {
405 AtaReq->
ahci.ahci_base64 = 0;
418 if(dma_base0+dma_count0 == dma_base &&
419 dma_count0+dma_count <= max_frag) {
421 if(dma_base & seg_align) {
426 dma_base = dma_base0;
427 dma_count += dma_count0;
431 AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].base = dma_base;
432 AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].baseu = dma_baseu;
433 AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].Reserved1 = 0;
436 *((
PULONG)&(AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i].DBC_ULONG)) = ((dma_count-1) & 0x3fffff);
441 &AtaReq->
ahci.ahci_cmd_ptr->prd_tab, &(AtaReq->
ahci.ahci_cmd_ptr->prd_tab[
i]) ));
468 PVOID HwDeviceExtension,
546 Srb->DataTransferLength);
562 if(!AtaReq->
ata.dma_base) {
581 Srb->DataTransferLength);
600 ULONG VendorID = deviceExtension->
DevID & 0xffff;
609 if(!AtaReq->
ata.dma_base) {
639 if(ChipType ==
PRNEW) {
697 ULONG VendorID = deviceExtension->
DevID & 0xffff;
709 if(ChipType ==
PRNEW) {
773 "AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device %d\n", LunExt->Lun));
777 if(!AtaReq->ahci.ahci_base64) {
779 "AtapiDmaReinit: no AHCI PRD, fatal on Device %d\n", LunExt->Lun));
783 if(!AtaReq->ata.dma_base) {
785 "AtapiDmaReinit: no PRD, fall to PIO on Device %d\n", LunExt->Lun));
791 (LunExt->TransferMode >
ATA_PIO5) ) {
793 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d for LBA48\n", LunExt->Lun));
800 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d\n", LunExt->Lun));
807 (LunExt->TransferMode >
ATA_PIO5) && (LunExt->TransferMode !=
ATA_PIO0+apiomode)
810 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x)\n", LunExt->Lun, LunExt->TransferMode,
ATA_PIO0+apiomode));
811 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
816 if(LunExt->LimitedTransferMode < LunExt->TransferMode) {
818 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x) (2)\n", LunExt->Lun, LunExt->TransferMode, LunExt->LimitedTransferMode));
819 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
820 LunExt->LimitedTransferMode-
ATA_PIO0,
827 "AtapiDmaReinit: set MAX mode on Device %d\n", LunExt->Lun));
828 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
838 (LunExt->LimitedTransferMode >
839 LunExt->TransferMode) ||
844 "AtapiDmaReinit: restore IO mode on Device %d, last dev %d\n", LunExt->Lun, LunExt->chan->last_cdev));
848 "AtapiDmaReinit: LimitedTransferMode == TransferMode = %x (%x), Device %d, last dev %d\n", LunExt->TransferMode, LunExt->DeviceFlags, LunExt->Lun, LunExt->chan->last_cdev));
862 if(LunExt->IdentifyData.SupportDma ||
863 (LunExt->IdentifyData.AtapiDMA.DMASupport && (LunExt->DeviceFlags &
DFLAGS_ATAPI_DEVICE))) {
865 "AtapiDmaInit__: Set (U)DMA on Device %d\n", LunExt->Lun));
878 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
884 "AtapiDmaInit__: Set PIO on Device %d\n", LunExt->Lun));
885 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
901 "AtaSetTransferMode: Set %#x on Device %d/%d\n",
mode, lChannel,
DeviceNumber));
941 if( (apiomode > 0) &&
950 KdPrint3((
PRINT_PREFIX " assume that drive doesn't support mode swithing using PIO%d\n", apiomode));
959 LunExt->PhyTransferMode =
max(LunExt->PhyTransferMode, LunExt->TransferMode);
961 LunExt->PhyTransferMode = LunExt->TransferMode;
965 LunExt->PhyTransferMode =
max(LunExt->LimitedTransferMode, LunExt->TransferMode);
967 LunExt->PhyTransferMode = LunExt->TransferMode;
998 ULONG VendorID = deviceExtension->
DevID & 0xffff;
1004 LONG statusByte = 0;
1014 wdmamode = udmamode = -1;
1029 wdmamode = udmamode = -1;
1033 wdmamode = udmamode = -1;
1053 wdmamode = udmamode = -1;
1057 wdmamode = udmamode = -1;
1098 udmamode =
min(udmamode, 6);
1107 udmamode =
min(udmamode, 6);
1129 goto try_generic_dma;
1152 static const USHORT reg4a = 0xa6;
1157 static const USHORT reg4x2 = 0x0301;
1159 for(
i=udmamode;
i>=0;
i--) {
1169 if (wdmamode >= 2 && apiomode >= 4) {
1176 static const UCHAR reg4x = 0x31;
1178 for(
i=udmamode;
i>=0;
i--) {
1188 if (wdmamode >= 2 && apiomode >= 4) {
1200 static const UCHAR ali_udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
1201 static const ULONG ali_pio[] =
1202 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1203 0x00310001, 0x00440001};
1205 if ((ChipFlags &
ALIOLD) &&
1206 (udmamode >= 0 || wdmamode >= 0)) {
1212 udmamode = wdmamode = -1;
1216 for(
i=udmamode;
i>=0;
i--) {
1221 word54 &= ~(0x000f000f << (
dev * 4));
1222 word54 |= (((ali_udma[
i]<<16) | 5) << (
dev * 4));
1231 if (wdmamode >= 2 && apiomode >= 4) {
1240 for(
i=apiomode;
i>=0;
i--) {
1261 if((ChipFlags &
VIABAR) &&
1268 static const UCHAR via_modes[6][7] = {
1269 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 },
1270 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 },
1271 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 },
1272 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 },
1273 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 },
1274 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }};
1275 static const UCHAR via_pio[] =
1276 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
1277 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1287 reg_val = &via_modes[ChipType][0];
1294 for(
i = udmamode;
i>=0;
i--) {
1301 if(!(ChipFlags &
VIABAR)) {
1303 for(
i = wdmamode;
i>=0;
i--) {
1312 if((apiomode >= 0) && (ChipType !=
VIA133)) {
1331 ULONG cyr_piotiming[] =
1332 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1333 ULONG cyr_wdmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1334 ULONG cyr_udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1337 for(
i=udmamode;
i>=0;
i--) {
1343 for(
i=wdmamode;
i>=0;
i--) {
1355 UCHAR cyr_piotiming_old[] =
1359 for(
i=wdmamode;
i>=0;
i--) {
1365 timing = (6-apiomode) | (cyr_piotiming_old[
i]);
1392 for(
i=udmamode;
i>=0;
i--) {
1397 for(
i=wdmamode;
i>=0;
i--) {
1414 ULONG nat_piotiming[] =
1415 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1416 0x00803020, 0x20102010, 0x00100010,
1417 0x00100010, 0x00100010, 0x00100010 };
1418 ULONG nat_dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1419 ULONG nat_udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1423 for(
i=udmamode;
i>=0;
i--) {
1430 for(
i=wdmamode;
i>=0;
i--) {
1451 if (wdmamode >= 2 && apiomode >= 4) {
1463 for(
i=udmamode;
i>=0;
i--) {
1468 for(
i=wdmamode;
i>=0;
i--) {
1474 if (wdmamode >= 0 && apiomode >= 4) {
1486 if (wdmamode >= 2 && apiomode >= 4) {
1497 for(
i=udmamode;
i>=0;
i--) {
1504 for(
i=wdmamode;
i>=0;
i--) {
1511 if (wdmamode >= 0 && apiomode >= 4) {
1537 UCHAR intel_timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1538 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1539 UCHAR intel_utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
1540 const UCHAR needed_pio[3] = {
1548 for(
i=wdmamode;
i>=0;
i--) {
1561 if (apiomode < needed_pio[wdmamode]) {
1581 reg4x |= intel_timings[
idx] << 8;
1591 for(
i=udmamode;
i>=0;
i--) {
1594 tim &= ~(0x7 << 16);
1604 for(
i=wdmamode;
i>=0;
i--) {
1606 tim &= ~(0x1 << 31);
1623 tim |= (apiomode & 0x7);
1644 for(
i=udmamode;
i>=0;
i--) {
1655 (((
USHORT)(intel_utimings[
i])) << (
dev<<2) ) );
1659 reg54 &= ~(0x1001 <<
dev);
1661 reg54 |= (0x1 <<
dev);
1665 reg54 |= (0x1000 <<
dev);
1685 for(
i=wdmamode;
i>=0;
i--) {
1707 reg40 &= ~0x00ff00ff;
1708 reg40 |= 0x40774077;
1710 mask40 = 0x000000ff;
1713 mask40 = 0x00003300;
1714 new40 = ((
USHORT)(intel_timings[
idx]) << 8);
1717 new44 = ((intel_timings[
idx] & 0x30) >> 2) |
1718 (intel_timings[
idx] & 0x03);
1739 UCHAR sel66 = Channel ? 0x08: 0x02;
1741 if(ChipType <
PRTX) {
1747 for(
i=udmamode;
i>=0;
i--) {
1749 if(ChipType ==
PRNEW) {
1766 if(ChipType ==
PRNEW) {
1771 for(
i=wdmamode;
i>=0;
i--) {
1785 goto l_ATA_SILICON_IMAGE_ID;
1797 static const ULONG sw_dma_modes[] = { 0x70, 0x21, 0x20 };
1798 static const ULONG sw_pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1799 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1806 for(
i=udmamode;
i>=0;
i--) {
1809 reg56 &= ~(0xf << (
dev * 4));
1815 reg44 = (reg44 & ~(0xff << bit_offset)) |
1816 (sw_dma_modes[2] << bit_offset);
1820 reg40 = (reg40 & ~(0xff << bit_offset)) |
1821 (sw_pio_modes[8+
i] << bit_offset);
1827 for(
i=wdmamode;
i>=0;
i--) {
1833 reg44 = (reg44 & ~(0xff << bit_offset)) |
1834 (sw_dma_modes[wdmamode] << bit_offset);
1838 reg40 = (reg40 & ~(0xff << bit_offset)) |
1839 (sw_pio_modes[5+
i] << bit_offset);
1852 reg4a = (reg4a & ~(0xf << (
dev*4))) |
1853 (apiomode << (
dev*4));
1859 reg40 = (reg40 & ~(0xff << bit_offset)) |
1860 (sw_pio_modes[apiomode] << bit_offset);
1865 l_ATA_SILICON_IMAGE_ID:
1871 static const UCHAR sil_modes[7] =
1872 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1873 static const USHORT sil_wdma_modes[3] =
1874 { 0x2208, 0x10c2, 0x10c1 };
1875 static const USHORT sil_pio_modes[6] =
1876 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1, 0x10c1 };
1880 UCHAR mreg = Channel ? 0x84 : 0x80;
1888 for(
i = udmamode;
i>=0;
i--) {
1897 for(
i = wdmamode;
i>=0;
i--) {
1914 static const UCHAR cmd_modes[2][6] = {
1915 { 0x31, 0x21, 0x011, 0x25, 0x15, 0x05 },
1916 { 0xc2, 0x82, 0x042, 0x8a, 0x4a, 0x0a } };
1917 static const UCHAR cmd_wdma_modes[] = { 0x87, 0x32, 0x3f };
1918 static const UCHAR cmd_pio_modes[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1921 udmamode =
min(udmamode, 5);
1923 for(
i = udmamode;
i>=0;
i--) {
1937 for(
i = wdmamode;
i>=0;
i--) {
1960 static const ULONG sis_modes_new133[] =
1961 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
1962 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
1963 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
1964 static const ULONG sis_modes_old133[] =
1965 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1966 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
1967 static const ULONG sis_modes_old[] =
1968 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 0x0301,
1969 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
1970 static const ULONG sis_modes_new100[] =
1971 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1972 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
1981 sis_modes = (
PULONG)(&sis_modes_new133[0]);
1984 reg = (reg57 & 0x40 ? 0x70 : 0x40) + (
dev * 4);
1987 sis_modes = (
PULONG)(&sis_modes_old133[0]);
1992 sis_modes = (
PULONG)(&sis_modes_new100[0]);
1999 sis_modes = (
PULONG)(&sis_modes_old[0]);
2006 for(
i=udmamode;
i>=0;
i--) {
2018 for(
i=wdmamode;
i>=0;
i--) {
2038 if (wdmamode >= 0 &&
2049 int a_speed = 3 << (
dev * 4);
2050 int u_flag = 1 <<
dev;
2070 for(
i=udmamode;
i>=0;
i--) {
2076 goto setup_drive_ite;
2080 for(
i=wdmamode;
i>=0;
i--) {
2112 drive_enables |= 0x4000;
2114 drive_enables &= (0xc000 | (0x06 << (
DeviceNumber*4)));
2123 static const UCHAR udmatiming[] =
2124 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2125 static const UCHAR chtiming[] =
2126 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2130 for(
i=udmamode;
i>=0;
i--) {
2138 for(
i=wdmamode;
i>=0;
i--) {
2143 if(reg54 < chtiming[
i+5]) {
2152 if(reg54 < chtiming[apiomode]) {
2159 static const UCHAR udmatiming[] =
2160 { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
2161 static const UCHAR timings[] =
2162 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
2163 0x23, 0x23, 0x23, 0x23, 0x23, 0x02, 0x02 };
2172 USHORT mask40=0, new40=0;
2173 UCHAR mask44=0, new44=0;
2180 if(!(reg54 & (0x10 <<
dev))) {
2182 udmamode =
min(udmamode, 2);
2185 for(
i=udmamode;
i>=0;
i--) {
2189 (
a & ~(0x3 << (
dev*4))) |
2190 (udmatiming[
i] << (
dev*4)) );
2198 for(
i=wdmamode; !
ok &&
i>=0;
i--) {
2209 timing = timings[apiomode];
2217 reg54 |= (0x1 <<
dev);
2219 reg54 &= ~(0x1 <<
dev);
2222 reg54 |= (0x1000 <<
dev);
2224 reg54 &= ~(0x1000 <<
dev);
2232 reg40 |= (isAtapi ? 0x04 : 0x00);
2236 reg40 |= (isAtapi ? 0x40 : 0x00);
2238 new44 = ((
timing & 0x30) >> 2) |
2250 if (wdmamode >= 0 &&
2273 for(
i=udmamode;
i>=0;
i--) {
2278 for(
i=wdmamode;
i>=0;
i--) {
2303 if ((udmamode >= 0 || wdmamode >= 0) &&
2318 if ((wdmamode >= 0 && apiomode >= 4) && deviceExtension->BaseIoAddressBM[lChannel]) {
2344 ULONG reg20 = 0x0000e132;
2345 ULONG reg24 = 0x00017771;
2351 case ATA_PIO0: reg20 = 0x0000e132;
break;
2352 case ATA_PIO1: reg20 = 0x00018121;
break;
2353 case ATA_PIO2: reg20 = 0x00024020;
break;
2354 case ATA_PIO3: reg20 = 0x00032010;
break;
2356 case ATA_PIO5: reg20 = 0x00040010;
break;
2357 case ATA_WDMA2: reg24 = 0x00002020;
break;
2358 case ATA_UDMA2: reg24 = 0x00911030;
break;
2372 PVOID HwDeviceExtension = (
PVOID)deviceExtension;
2373 ULONG slotNumber = deviceExtension->slotNumber;
2374 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
2440 UCHAR r_bp, r_cp, r_ap;
2443 static UCHAR udma_timing[6][2] = {
2451 static UCHAR mdma_timing[3][2] = {
2456 static USHORT pio_timing[5] = {
2457 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
2474 r_bp |= udma_timing[
i][0];
2475 r_cp |= udma_timing[
i][1];
2479 r_bp |= mdma_timing[
i][0];
2480 r_cp |= mdma_timing[
i][1];
2492 r_ap |= (
UCHAR)(pio_timing[
i] >> 8);
2493 r_bp |= (
UCHAR)(pio_timing[
i] & 0xFF);
2517 PVOID HwDeviceExtension = (
PVOID)deviceExtension;
2518 ULONG slotNumber = deviceExtension->slotNumber;
2519 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
2548 default:
timing = 0x0d029d5e;
2570 default:
timing = 0x0d029d5e;
2591 default:
timing = 0x06514e57;
2610 default:
timing = 0x01208585;
2629 default:
timing = 0x0120a7a7;
2642 default:
timing = 0x0120d9d9;
2652 #define FIT(v,min,max) (((v)>(max)?(max):(v))<(min)?(min):(v)) 2662 PVOID HwDeviceExtension = (
PVOID)deviceExtension;
2663 ULONG slotNumber = deviceExtension->slotNumber;
2664 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
2668 deviceExtension->MaxTransferMode <
ATA_UDMA6) {
2683 case ATA_PIO0:
setup = 70; active = 165; recover = 150; cycle = 600;
break;
2684 case ATA_PIO1:
setup = 50; active = 125; recover = 100; cycle = 383;
break;
2685 case ATA_PIO2:
setup = 30; active = 100; recover = 90; cycle = 240;
break;
2686 case ATA_PIO3:
setup = 30; active = 80; recover = 70; cycle = 180;
break;
2687 case ATA_PIO4:
setup = 25; active = 70; recover = 25; cycle = 120;
break;
2688 case ATA_PIO5:
setup = 20; active = 50; recover = 30; cycle = 100;
break;
2692 active = (active -1)/(
T+1);
2693 recover = (recover-1)/(
T+1);
2694 cycle = (cycle -1)/(
T+1);
2696 if (active + recover < cycle) {
2697 active += (cycle - (active + recover)) / 2;
2698 recover = cycle - active;
2703 t = (
t & ~(3 << ((3 -
dev) << 1))) | (
FIT(
setup - 1, 0, 3) << ((3 -
dev) << 1));
#define ChangePciConfig2(offs, _op)
IDENTIFY_DATA2 IdentifyData
struct _ATA_REQ::@1120::@1122::@1126::@1128 ata
UCHAR NTAPI AtapiDmaDone(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
NTSYSAPI VOID NTAPI RtlCopyMemory(VOID UNALIGNED *Destination, CONST VOID UNALIGNED *Source, ULONG Length)
static const CHAR retry_Wdma[MAX_RETRIES+1]
UCHAR DDKFASTAPI UniataIsIdle(IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN UCHAR Status)
#define GetStatus(BaseIoAddress, Status)
#define GetDmaStatus(de, c)
#define ChangePciConfig1(offs, _op)
#define ATA_SILICON_IMAGE_ID
VOID NTAPI AtapiDmaStart(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
LONG NTAPI AtaWmode(PIDENTIFY_DATA2 ident)
INTERFACE_TYPE OrigAdapterInterfaceType
ULONG NTAPI hpt_cable80(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel)
GLuint GLuint GLsizei count
BOOLEAN NTAPI AtapiDmaSetup(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb, IN PUCHAR data, IN ULONG count)
struct _ATA_REQ::@1120::@1122::@1126::@1129 ahci
VOID NTAPI cyrix_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
UCHAR DDKFASTAPI SelectDrive(IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)
BOOLEAN NTAPI AtapiDmaPioSync(PVOID HwDeviceExtension, PSCSI_REQUEST_BLOCK Srb, PUCHAR data, ULONG count)
#define BM_STATUS_DRIVE_1_DMA
#define DFLAGS_ATAPI_DEVICE
#define BM_STATUS_DRIVE_0_DMA
#define SRB_FLAGS_DATA_IN
VOID NTAPI AtapiDmaInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN SCHAR apiomode, IN SCHAR wdmamode, IN SCHAR udmamode)
VOID NTAPI MmFreeContiguousMemory(IN PVOID BaseAddress)
static const ULONG valid_udma[7]
VOID NTAPI AtapiDmaAlloc(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN ULONG lChannel)
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock
#define ATA_SERVERWORKS_ID
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
__inline BOOLEAN ata_is_sata(PIDENTIFY_DATA ident)
#define SetPciConfig1(offs, op)
#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru)
LONG NTAPI AtaUmode(PIDENTIFY_DATA2 ident)
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock0
BOOLEAN NTAPI AtapiDmaDBSync(PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
static const CHAR retry_Udma[MAX_RETRIES+1]
LONG NTAPI AtaPioMode(PIDENTIFY_DATA2 ident)
struct BM_DMA_ENTRY BM_DMA_ENTRY
#define SetPciConfig2(offs, op)
__inline BOOLEAN UniataIsSATARangeAvailable(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG lChannel)
#define REQ_FLAG_FORCE_DOWNRATE
#define DFLAGS_MANUAL_CHS
ULONGLONG AHCI_CTL_PhAddr
#define ChangePciConfig4(offs, _op)
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
VOID NTAPI AtapiDisableInterrupts(IN PVOID HwDeviceExtension, IN ULONG c)
#define SetPciConfig4(offs, op)
#define GetPciConfig4(offs, op)
SCSI_PHYSICAL_ADDRESS NTAPI ScsiPortConvertUlongToPhysicalAddress(IN ULONG_PTR UlongAddress)
GLint GLenum GLsizei GLsizei GLsizei GLint GLsizei const GLvoid * data
VOID NTAPI promise_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel) ?(CompletionRoutine !=NULL) :TRUE)
GLenum const GLvoid * addr
#define memcpy(s1, s2, n)
BOOLEAN NTAPI AtapiDmaDBPreSync(IN PVOID HwDeviceExtension, PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
#define REQ_FLAG_DMA_DBUF
BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES]
ULONG DmaSegmentAlignmentMask
UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
#define HBAFLAGS_DMA_DISABLED_LBA48
VOID NTAPI AtapiEnableInterrupts(IN PVOID HwDeviceExtension, IN ULONG c)
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
#define CTRFLAGS_DMA_ACTIVE
VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
struct _IDE_AHCI_CHANNEL_CTL_BLOCK * PIDE_AHCI_CHANNEL_CTL_BLOCK
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
#define DFLAGS_REINIT_DMA
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
#define REQ_FLAG_DMA_OPERATION
PVOID NTAPI MmAllocateContiguousMemory(IN SIZE_T NumberOfBytes, IN PHYSICAL_ADDRESS HighestAcceptableAddress)
#define GetPciConfig2(offs, op)
#define AHCI_CLB_ALIGNEMENT_MASK
#define REQ_FLAG_DMA_DBUF_PRD
BOOLEAN NTAPI AtaSetTransferMode(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PHW_LU_EXTENSION LunExt, IN ULONG mode)
#define GetPciConfig1(offs, op)
void setup(char *serport, int baud)
UCHAR LimitedTransferMode
#define AtapiStallExecution(dt)
VOID NTAPI via82c_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
UCHAR NTAPI AtaCommand(IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN ULONG DeviceNumber, IN ULONG Channel, IN UCHAR command, IN USHORT cylinder, IN UCHAR head, IN UCHAR sector, IN UCHAR count, IN UCHAR feature, IN ULONG flags)
PHYSICAL_ADDRESS NTAPI MmGetPhysicalAddress(IN PVOID Address)
VOID NTAPI AtapiDmaReinit(IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt, IN PATA_REQ AtaReq)
#define IDENTIFY_CABLE_ID_VALID
ULONG NTAPI AtapiVirtToPhysAddr_(IN PVOID HwDeviceExtension, IN PSCSI_REQUEST_BLOCK Srb, IN PUCHAR data, OUT PULONG count, OUT PULONG ph_addru)
#define REQ_FLAG_FORCE_DOWNRATE_LBA48
PVOID NTAPI ScsiPortGetVirtualAddress(IN PVOID HwDeviceExtension, IN SCSI_PHYSICAL_ADDRESS PhysicalAddress)
ULONG MaximumDmaTransferLength
GLboolean GLboolean GLboolean GLboolean a
_In_ PCHAR _In_ ULONG DeviceNumber
IN PSCSI_REQUEST_BLOCK Srb
#define IDE_COMMAND_SET_FEATURES
VOID NTAPI hpt_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
union _ATA_REQ * PATA_REQ
#define BM_COMMAND_START_STOP
#define ATA_AHCI_DMA_ENTRIES
VOID NTAPI AtapiDmaInit__(IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt)
#define UNIATA_CHAN_TIMINGS
#define ATAPI_DEVICE(chan, dev)
#define ATA_WAIT_BASE_READY
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]