998 ULONG VendorID = deviceExtension->
DevID & 0xffff;
1004 LONG statusByte = 0;
1014 wdmamode = udmamode = -1;
1029 wdmamode = udmamode = -1;
1033 wdmamode = udmamode = -1;
1053 wdmamode = udmamode = -1;
1057 wdmamode = udmamode = -1;
1098 udmamode =
min(udmamode, 6);
1107 udmamode =
min(udmamode, 6);
1129 goto try_generic_dma;
1152 static const USHORT reg4a = 0xa6;
1157 static const USHORT reg4x2 = 0x0301;
1159 for(
i=udmamode;
i>=0;
i--) {
1169 if (wdmamode >= 2 && apiomode >= 4) {
1176 static const UCHAR reg4x = 0x31;
1178 for(
i=udmamode;
i>=0;
i--) {
1188 if (wdmamode >= 2 && apiomode >= 4) {
1200 static const UCHAR ali_udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
1201 static const ULONG ali_pio[] =
1202 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1203 0x00310001, 0x00440001};
1205 if ((ChipFlags &
ALIOLD) &&
1206 (udmamode >= 0 || wdmamode >= 0)) {
1212 udmamode = wdmamode = -1;
1216 for(
i=udmamode;
i>=0;
i--) {
1221 word54 &= ~(0x000f000f << (
dev * 4));
1222 word54 |= (((ali_udma[
i]<<16) | 5) << (
dev * 4));
1231 if (wdmamode >= 2 && apiomode >= 4) {
1240 for(
i=apiomode;
i>=0;
i--) {
1261 if((ChipFlags &
VIABAR) &&
1268 static const UCHAR via_modes[6][7] = {
1269 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 },
1270 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 },
1271 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 },
1272 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 },
1273 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 },
1274 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }};
1275 static const UCHAR via_pio[] =
1276 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
1277 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1287 reg_val = &via_modes[ChipType][0];
1294 for(
i = udmamode;
i>=0;
i--) {
1301 if(!(ChipFlags &
VIABAR)) {
1303 for(
i = wdmamode;
i>=0;
i--) {
1312 if((apiomode >= 0) && (ChipType !=
VIA133)) {
1332 static const ULONG cyr_piotiming[] =
1333 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1334 static const ULONG cyr_wdmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1335 static const ULONG cyr_udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1337 ULONG cyr_piotiming[] =
1338 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1339 ULONG cyr_wdmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1340 ULONG cyr_udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1344 for(
i=udmamode;
i>=0;
i--) {
1350 for(
i=wdmamode;
i>=0;
i--) {
1363 static const UCHAR cyr_piotiming_old[] = { 11, 6, 3, 2, 1 };
1365 UCHAR cyr_piotiming_old[] =
1370 for(
i=wdmamode;
i>=0;
i--) {
1376 timing = (6-apiomode) | (cyr_piotiming_old[
i]);
1403 for(
i=udmamode;
i>=0;
i--) {
1408 for(
i=wdmamode;
i>=0;
i--) {
1426 static const ULONG nat_piotiming[] =
1427 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 0x00803020,
1428 0x20102010, 0x00100010, 0x00100010, 0x00100010, 0x00100010 };
1429 static const ULONG nat_dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1430 static const ULONG nat_udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1432 ULONG nat_piotiming[] =
1433 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1434 0x00803020, 0x20102010, 0x00100010,
1435 0x00100010, 0x00100010, 0x00100010 };
1436 ULONG nat_dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1437 ULONG nat_udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1442 for(
i=udmamode;
i>=0;
i--) {
1449 for(
i=wdmamode;
i>=0;
i--) {
1470 if (wdmamode >= 2 && apiomode >= 4) {
1482 for(
i=udmamode;
i>=0;
i--) {
1487 for(
i=wdmamode;
i>=0;
i--) {
1493 if (wdmamode >= 0 && apiomode >= 4) {
1505 if (wdmamode >= 2 && apiomode >= 4) {
1516 for(
i=udmamode;
i>=0;
i--) {
1523 for(
i=wdmamode;
i>=0;
i--) {
1530 if (wdmamode >= 0 && apiomode >= 4) {
1557 static const UCHAR intel_timings[] =
1558 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1559 static const UCHAR intel_utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
1561 UCHAR intel_timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1562 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1563 UCHAR intel_utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
1565 const UCHAR needed_pio[3] = {
1573 for(
i=wdmamode;
i>=0;
i--) {
1586 if (apiomode < needed_pio[wdmamode]) {
1606 reg4x |= intel_timings[
idx] << 8;
1616 for(
i=udmamode;
i>=0;
i--) {
1619 tim &= ~(0x7 << 16);
1629 for(
i=wdmamode;
i>=0;
i--) {
1631 tim &= ~(0x1 << 31);
1648 tim |= (apiomode & 0x7);
1669 for(
i=udmamode;
i>=0;
i--) {
1680 (((
USHORT)(intel_utimings[
i])) << (
dev<<2) ) );
1684 reg54 &= ~(0x1001 <<
dev);
1686 reg54 |= (0x1 <<
dev);
1690 reg54 |= (0x1000 <<
dev);
1710 for(
i=wdmamode;
i>=0;
i--) {
1732 reg40 &= ~0x00ff00ff;
1733 reg40 |= 0x40774077;
1735 mask40 = 0x000000ff;
1738 mask40 = 0x00003300;
1739 new40 = ((
USHORT)(intel_timings[
idx]) << 8);
1742 new44 = ((intel_timings[
idx] & 0x30) >> 2) |
1743 (intel_timings[
idx] & 0x03);
1764 UCHAR sel66 = Channel ? 0x08: 0x02;
1766 if(ChipType <
PRTX) {
1772 for(
i=udmamode;
i>=0;
i--) {
1774 if(ChipType ==
PRNEW) {
1791 if(ChipType ==
PRNEW) {
1796 for(
i=wdmamode;
i>=0;
i--) {
1810 goto l_ATA_SILICON_IMAGE_ID;
1822 static const ULONG sw_dma_modes[] = { 0x70, 0x21, 0x20 };
1823 static const ULONG sw_pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1824 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1831 for(
i=udmamode;
i>=0;
i--) {
1834 reg56 &= ~(0xf << (
dev * 4));
1840 reg44 = (reg44 & ~(0xff << bit_offset)) |
1841 (sw_dma_modes[2] << bit_offset);
1845 reg40 = (reg40 & ~(0xff << bit_offset)) |
1846 (sw_pio_modes[8+
i] << bit_offset);
1852 for(
i=wdmamode;
i>=0;
i--) {
1858 reg44 = (reg44 & ~(0xff << bit_offset)) |
1859 (sw_dma_modes[wdmamode] << bit_offset);
1863 reg40 = (reg40 & ~(0xff << bit_offset)) |
1864 (sw_pio_modes[5+
i] << bit_offset);
1877 reg4a = (reg4a & ~(0xf << (
dev*4))) |
1878 (apiomode << (
dev*4));
1884 reg40 = (reg40 & ~(0xff << bit_offset)) |
1885 (sw_pio_modes[apiomode] << bit_offset);
1890 l_ATA_SILICON_IMAGE_ID:
1896 static const UCHAR sil_modes[7] =
1897 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1898 static const USHORT sil_wdma_modes[3] =
1899 { 0x2208, 0x10c2, 0x10c1 };
1900 static const USHORT sil_pio_modes[6] =
1901 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1, 0x10c1 };
1905 UCHAR mreg = Channel ? 0x84 : 0x80;
1913 for(
i = udmamode;
i>=0;
i--) {
1922 for(
i = wdmamode;
i>=0;
i--) {
1939 static const UCHAR cmd_modes[2][6] = {
1940 { 0x31, 0x21, 0x011, 0x25, 0x15, 0x05 },
1941 { 0xc2, 0x82, 0x042, 0x8a, 0x4a, 0x0a } };
1942 static const UCHAR cmd_wdma_modes[] = { 0x87, 0x32, 0x3f };
1943 static const UCHAR cmd_pio_modes[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1946 udmamode =
min(udmamode, 5);
1948 for(
i = udmamode;
i>=0;
i--) {
1962 for(
i = wdmamode;
i>=0;
i--) {
1985 static const ULONG sis_modes_new133[] =
1986 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
1987 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
1988 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
1989 static const ULONG sis_modes_old133[] =
1990 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1991 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
1992 static const ULONG sis_modes_old[] =
1993 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 0x0301,
1994 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
1995 static const ULONG sis_modes_new100[] =
1996 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1997 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
2006 sis_modes = (
PULONG)(&sis_modes_new133[0]);
2009 reg = (reg57 & 0x40 ? 0x70 : 0x40) + (
dev * 4);
2012 sis_modes = (
PULONG)(&sis_modes_old133[0]);
2017 sis_modes = (
PULONG)(&sis_modes_new100[0]);
2024 sis_modes = (
PULONG)(&sis_modes_old[0]);
2031 for(
i=udmamode;
i>=0;
i--) {
2043 for(
i=wdmamode;
i>=0;
i--) {
2063 if (wdmamode >= 0 &&
2074 int a_speed = 3 << (
dev * 4);
2075 int u_flag = 1 <<
dev;
2095 for(
i=udmamode;
i>=0;
i--) {
2101 goto setup_drive_ite;
2105 for(
i=wdmamode;
i>=0;
i--) {
2137 drive_enables |= 0x4000;
2139 drive_enables &= (0xc000 | (0x06 << (
DeviceNumber*4)));
2148 static const UCHAR udmatiming[] =
2149 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2150 static const UCHAR chtiming[] =
2151 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2155 for(
i=udmamode;
i>=0;
i--) {
2163 for(
i=wdmamode;
i>=0;
i--) {
2168 if(reg54 < chtiming[
i+5]) {
2177 if(reg54 < chtiming[apiomode]) {
2184 static const UCHAR udmatiming[] =
2185 { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
2186 static const UCHAR timings[] =
2187 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
2188 0x23, 0x23, 0x23, 0x23, 0x23, 0x02, 0x02 };
2197 USHORT mask40=0, new40=0;
2198 UCHAR mask44=0, new44=0;
2205 if(!(reg54 & (0x10 <<
dev))) {
2207 udmamode =
min(udmamode, 2);
2210 for(
i=udmamode;
i>=0;
i--) {
2214 (
a & ~(0x3 << (
dev*4))) |
2215 (udmatiming[
i] << (
dev*4)) );
2223 for(
i=wdmamode; !
ok &&
i>=0;
i--) {
2234 timing = timings[apiomode];
2242 reg54 |= (0x1 <<
dev);
2244 reg54 &= ~(0x1 <<
dev);
2247 reg54 |= (0x1000 <<
dev);
2249 reg54 &= ~(0x1000 <<
dev);
2257 reg40 |= (isAtapi ? 0x04 : 0x00);
2261 reg40 |= (isAtapi ? 0x40 : 0x00);
2263 new44 = ((
timing & 0x30) >> 2) |
2275 if (wdmamode >= 0 &&
2298 for(
i=udmamode;
i>=0;
i--) {
2303 for(
i=wdmamode;
i>=0;
i--) {
2328 if ((udmamode >= 0 || wdmamode >= 0) &&
2343 if ((wdmamode >= 0 && apiomode >= 4) && deviceExtension->BaseIoAddressBM[lChannel]) {
#define ChangePciConfig2(offs, _op)
IDENTIFY_DATA2 IdentifyData
VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
UCHAR DDKFASTAPI UniataIsIdle(IN struct _HW_DEVICE_EXTENSION *deviceExtension, IN UCHAR Status)
#define GetDmaStatus(de, c)
#define ChangePciConfig1(offs, _op)
#define ATA_SILICON_IMAGE_ID
return pRequest GetStatus()
UCHAR DDKFASTAPI SelectDrive(IN struct _HW_CHANNEL *chan, IN ULONG DeviceNumber)
#define BM_STATUS_DRIVE_1_DMA
#define BM_STATUS_DRIVE_0_DMA
#define ATA_SERVERWORKS_ID
__inline BOOLEAN ata_is_sata(PIDENTIFY_DATA ident)
#define SetPciConfig1(offs, op)
#define SetPciConfig2(offs, op)
__inline BOOLEAN UniataIsSATARangeAvailable(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG lChannel)
#define ChangePciConfig4(offs, _op)
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
#define SetPciConfig4(offs, op)
#define GetPciConfig4(offs, op)
VOID NTAPI promise_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
static const unsigned char reg_size[]
UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
#define DFLAGS_REINIT_DMA
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
#define GetPciConfig2(offs, op)
BOOLEAN NTAPI AtaSetTransferMode(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PHW_LU_EXTENSION LunExt, IN ULONG mode)
#define GetPciConfig1(offs, op)
UCHAR LimitedTransferMode
VOID NTAPI via82c_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
#define IDENTIFY_CABLE_ID_VALID
GLboolean GLboolean GLboolean GLboolean a
_In_ PCHAR _In_ ULONG DeviceNumber
VOID NTAPI hpt_timing(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG dev, IN CHAR mode)
#define ATAPI_DEVICE(chan, dev)
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]