ReactOS  0.4.14-dev-606-g14ebc0b
bsmaster.h File Reference
#include "config.h"
#include "tools.h"
#include "bm_devs_decl.h"
#include "uata_ctl.h"
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Classes

struct  _BUSMASTER_CTX
 
struct  BM_DMA_ENTRY
 
struct  _IDE_BUSMASTER_REGISTERS
 
struct  _IDE_AHCI_REGISTERS
 
union  _SATA_SSTATUS_REG
 
union  _SATA_SCONTROL_REG
 
union  _SATA_SERROR_REG
 
struct  _IDE_SATA_REGISTERS
 
union  _AHCI_IS_REG
 
struct  _IDE_AHCI_PORT_REGISTERS
 
struct  _IDE_AHCI_PRD_ENTRY
 
struct  _AHCI_ATA_H2D_FIS
 
struct  _IDE_AHCI_CMD
 
struct  _IDE_AHCI_CMD_LIST
 
struct  _IDE_AHCI_RCV_FIS
 
struct  _IDE_AHCI_CHANNEL_CTL_BLOCK
 
union  _ATA_REQ
 
struct  _IORES
 
struct  _HW_CHANNEL
 
struct  _HW_LU_EXTENSION
 
struct  _HW_DEVICE_EXTENSION
 
struct  _ISR2_DEVICE_EXTENSION
 

Macros

#define ATA_IDLE   0x0
 
#define ATA_IMMEDIATE   0x1
 
#define ATA_WAIT_INTR   0x2
 
#define ATA_WAIT_READY   0x3
 
#define ATA_ACTIVE   0x4
 
#define ATA_ACTIVE_ATA   0x5
 
#define ATA_ACTIVE_ATAPI   0x6
 
#define ATA_REINITING   0x7
 
#define ATA_WAIT_BASE_READY   0x8
 
#define ATA_WAIT_IDLE   0x9
 
#define MAX_RETRIES   6
 
#define RETRY_UDMA2   1
 
#define RETRY_WDMA   2
 
#define RETRY_PIO   3
 
#define IO_WD1   0x1F0 /* Primary Fixed Disk Controller */
 
#define IO_WD2   0x170 /* Secondary Fixed Disk Controller */
 
#define IP_PC98_BANK   0x432
 
#define IO_FLOPPY_INT   0x3F6 /* AltStatus inside Floppy I/O range */
 
#define PCI_ADDRESS_IOMASK   0xfffffff0
 
#define ATA_BM_OFFSET1   0x08
 
#define ATA_IOSIZE   0x08
 
#define ATA_ALTOFFSET   0x206 /* alternate registers offset */
 
#define ATA_PCCARD_ALTOFFSET   0x0e /* do for PCCARD devices */
 
#define ATA_ALTIOSIZE   0x01 /* alternate registers size */
 
#define ATA_BMIOSIZE   0x20
 
#define ATA_PC98_BANKIOSIZE   0x01
 
#define ATA_MAX_IOLBA28   DEF_U64(0x0fffff80)
 
#define ATA_MAX_LBA28   DEF_U64(0x0fffffff)
 
#define ATA_MAX_IOLBA32   DEF_U64(0xffffff80)
 
#define ATA_MAX_LBA32   DEF_U64(0xffffffff)
 
#define ATA_DMA_ENTRIES   256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
 
#define ATA_DMA_EOT   0x80000000
 
#define DEV_BSIZE   512
 
#define ATAPI_MAGIC_LSB   0x14
 
#define ATAPI_MAGIC_MSB   0xeb
 
#define AHCI_MAX_PORT   32
 
#define SATA_MAX_PM_UNITS   16
 
#define PCI_DEV_CLASS_STORAGE   0x01
 
#define PCI_DEV_SUBCLASS_IDE   0x01
 
#define PCI_DEV_SUBCLASS_RAID   0x04
 
#define PCI_DEV_SUBCLASS_ATA   0x05
 
#define PCI_DEV_SUBCLASS_SATA   0x06
 
#define PCI_DEV_PROGIF_AHCI_1_0   0x01
 
#define BM_STATUS_ACTIVE   0x01
 
#define BM_STATUS_ERR   0x02
 
#define BM_STATUS_INTR   0x04
 
#define BM_STATUS_MASK   0x07
 
#define BM_STATUS_DRIVE_0_DMA   0x20
 
#define BM_STATUS_DRIVE_1_DMA   0x40
 
#define BM_STATUS_SIMPLEX_ONLY   0x80
 
#define BM_COMMAND_START_STOP   0x01
 
#define BM_COMMAND_WRITE   0x00
 
#define BM_COMMAND_READ   0x08
 
#define BM_DS0_SII_DMA_ENABLE   (1 << 0) /* DMA run switch */
 
#define BM_DS0_SII_IRQ   (1 << 3) /* ??? */
 
#define BM_DS0_SII_DMA_SATA_IRQ   (1 << 4) /* OR of all SATA IRQs */
 
#define BM_DS0_SII_DMA_ERROR   (1 << 17) /* PCI bus error */
 
#define BM_DS0_SII_DMA_COMPLETE   (1 << 18) /* cmd complete / IRQ pending */
 
#define IDX_BM_IO   (IDX_IO2_o+IDX_IO2_o_SZ)
 
#define IDX_BM_IO_SZ   5
 
#define IDX_BM_Command   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
 
#define IDX_BM_DeviceSpecific0   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
 
#define IDX_BM_Status   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
 
#define IDX_BM_DeviceSpecific1   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
 
#define IDX_BM_PRD_Table   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
 
#define AHCI_CAP_NOP_MASK   0x0000001f
 
#define AHCI_CAP_CCC   0x00000080
 
#define AHCI_CAP_NCS_MASK   0x00001f00
 
#define AHCI_CAP_PMD   0x00008000
 
#define AHCI_CAP_SPM   0x00020000
 
#define AHCI_CAP_SAM   0x00040000
 
#define AHCI_CAP_ISS_MASK   0x00f00000
 
#define AHCI_CAP_SCLO   0x01000000
 
#define AHCI_CAP_SNTF   0x20000000
 
#define AHCI_CAP_NCQ   0x40000000
 
#define AHCI_CAP_S64A   0x80000000
 
#define AHCI_GHC   0x04
 
#define AHCI_GHC_HR   0x00000001
 
#define AHCI_GHC_IE   0x00000002
 
#define AHCI_GHC_AE   0x80000000
 
#define AHCI_CAP2_BOH   0x00000001
 
#define AHCI_CAP2_NVMP   0x00000002
 
#define AHCI_CAP2_APST   0x00000004
 
#define AHCI_BOHC_BB   0x00000001
 
#define AHCI_BOHC_OOC   0x00000002
 
#define AHCI_BOHC_SOOE   0x00000004
 
#define AHCI_BOHC_OOS   0x00000008
 
#define AHCI_BOHC_BOS   0x00000010
 
#define IDX_AHCI_CAP   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
 
#define IDX_AHCI_GHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
 
#define IDX_AHCI_IS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
 
#define IDX_AHCI_VS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
 
#define IDX_AHCI_PI   (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
 
#define IDX_AHCI_CAP2   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))
 
#define IDX_AHCI_BOHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))
 
#define SStatus_DET_NoDev   0x00
 
#define SStatus_DET_Dev_NoPhy   0x01
 
#define SStatus_DET_Dev_Ok   0x03
 
#define SStatus_DET_Offline   0x04
 
#define SStatus_SPD_NoDev   0x00
 
#define SStatus_SPD_Gen1   0x01
 
#define SStatus_SPD_Gen2   0x02
 
#define SStatus_SPD_Gen3   0x03
 
#define SStatus_IPM_NoDev   0x00
 
#define SStatus_IPM_Active   0x01
 
#define SStatus_IPM_Partial   0x02
 
#define SStatus_IPM_Slumber   0x06
 
#define ATA_SS_DET_MASK   0x0000000f
 
#define ATA_SS_DET_NO_DEVICE   0x00000000
 
#define ATA_SS_DET_DEV_PRESENT   0x00000001
 
#define ATA_SS_DET_PHY_ONLINE   0x00000003
 
#define ATA_SS_DET_PHY_OFFLINE   0x00000004
 
#define ATA_SS_SPD_MASK   0x000000f0
 
#define ATA_SS_SPD_NO_SPEED   0x00000000
 
#define ATA_SS_SPD_GEN1   0x00000010
 
#define ATA_SS_SPD_GEN2   0x00000020
 
#define ATA_SS_IPM_MASK   0x00000f00
 
#define ATA_SS_IPM_NO_DEVICE   0x00000000
 
#define ATA_SS_IPM_ACTIVE   0x00000100
 
#define ATA_SS_IPM_PARTIAL   0x00000200
 
#define ATA_SS_IPM_SLUMBER   0x00000600
 
#define SControl_DET_DoNothing   0x00
 
#define SControl_DET_Idle   0x00
 
#define SControl_DET_Init   0x01
 
#define SControl_DET_Disable   0x04
 
#define SControl_SPD_NoRestrict   0x00
 
#define SControl_SPD_LimGen1   0x01
 
#define SControl_SPD_LimGen2   0x02
 
#define SControl_SPD_LimGen3   0x03
 
#define SControl_IPM_NoRestrict   0x00
 
#define SControl_IPM_NoPartial   0x01
 
#define SControl_IPM_NoSlumber   0x02
 
#define SControl_IPM_NoPartialSlumber   0x03
 
#define ATA_SC_DET_MASK   0x0000000f
 
#define ATA_SC_DET_IDLE   0x00000000
 
#define ATA_SC_DET_RESET   0x00000001
 
#define ATA_SC_DET_DISABLE   0x00000004
 
#define ATA_SC_SPD_MASK   0x000000f0
 
#define ATA_SC_SPD_NO_SPEED   0x00000000
 
#define ATA_SC_SPD_SPEED_GEN1   0x00000010
 
#define ATA_SC_SPD_SPEED_GEN2   0x00000020
 
#define ATA_SC_SPD_SPEED_GEN3   0x00000040
 
#define ATA_SC_IPM_MASK   0x00000f00
 
#define ATA_SC_IPM_NONE   0x00000000
 
#define ATA_SC_IPM_DIS_PARTIAL   0x00000100
 
#define ATA_SC_IPM_DIS_SLUMBER   0x00000200
 
#define ATA_SE_DATA_CORRECTED   0x00000001
 
#define ATA_SE_COMM_CORRECTED   0x00000002
 
#define ATA_SE_DATA_ERR   0x00000100
 
#define ATA_SE_COMM_ERR   0x00000200
 
#define ATA_SE_PROT_ERR   0x00000400
 
#define ATA_SE_HOST_ERR   0x00000800
 
#define ATA_SE_PHY_CHANGED   0x00010000
 
#define ATA_SE_PHY_IERROR   0x00020000
 
#define ATA_SE_COMM_WAKE   0x00040000
 
#define ATA_SE_DECODE_ERR   0x00080000
 
#define ATA_SE_PARITY_ERR   0x00100000
 
#define ATA_SE_CRC_ERR   0x00200000
 
#define ATA_SE_HANDSHAKE_ERR   0x00400000
 
#define ATA_SE_LINKSEQ_ERR   0x00800000
 
#define ATA_SE_TRANSPORT_ERR   0x01000000
 
#define ATA_SE_UNKNOWN_FIS   0x02000000
 
#define IDX_SATA_IO   (IDX_BM_IO+IDX_BM_IO_SZ)
 
#define IDX_SATA_IO_SZ   5
 
#define IDX_SATA_SStatus   (0+IDX_SATA_IO)
 
#define IDX_SATA_SError   (1+IDX_SATA_IO)
 
#define IDX_SATA_SControl   (2+IDX_SATA_IO)
 
#define IDX_SATA_SActive   (3+IDX_SATA_IO)
 
#define IDX_SATA_SNTF_PMN   (4+IDX_SATA_IO)
 
#define IDX_INDEXED_IO   (IDX_SATA_IO+IDX_SATA_IO_SZ)
 
#define IDX_INDEXED_IO_SZ   2
 
#define IDX_INDEXED_ADDR   (0+IDX_INDEXED_IO)
 
#define IDX_INDEXED_DATA   (1+IDX_INDEXED_IO)
 
#define IDX_MAX_REG   (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
 
#define ATA_AHCI_P_IX_DHR   0x00000001
 
#define ATA_AHCI_P_IX_PS   0x00000002
 
#define ATA_AHCI_P_IX_DS   0x00000004
 
#define ATA_AHCI_P_IX_SDB   0x00000008
 
#define ATA_AHCI_P_IX_UF   0x00000010
 
#define ATA_AHCI_P_IX_DP   0x00000020
 
#define ATA_AHCI_P_IX_PC   0x00000040
 
#define ATA_AHCI_P_IX_DI   0x00000080
 
#define ATA_AHCI_P_IX_PRC   0x00400000
 
#define ATA_AHCI_P_IX_IPM   0x00800000
 
#define ATA_AHCI_P_IX_OF   0x01000000
 
#define ATA_AHCI_P_IX_INF   0x04000000
 
#define ATA_AHCI_P_IX_IF   0x08000000
 
#define ATA_AHCI_P_IX_HBD   0x10000000
 
#define ATA_AHCI_P_IX_HBF   0x20000000
 
#define ATA_AHCI_P_IX_TFE   0x40000000
 
#define ATA_AHCI_P_IX_CPD   0x80000000
 
#define AHCI_CLB_ALIGNEMENT_MASK   ((ULONGLONG)(1024-1))
 
#define AHCI_FIS_ALIGNEMENT_MASK   ((ULONGLONG)(256-1))
 
#define AHCI_CMD_ALIGNEMENT_MASK   ((ULONGLONG)(128-1))
 
#define SATA_CMD_ICC_Idle   0x00
 
#define SATA_CMD_ICC_NoOp   0x00
 
#define SATA_CMD_ICC_Active   0x01
 
#define SATA_CMD_ICC_Partial   0x02
 
#define SATA_CMD_ICC_Slumber   0x06
 
#define IDX_AHCI_P_CLB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
 
#define IDX_AHCI_P_FB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
 
#define IDX_AHCI_P_IS   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
 
#define IDX_AHCI_P_IE   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))
 
#define IDX_AHCI_P_CI   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
 
#define IDX_AHCI_P_TFD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
 
#define IDX_AHCI_P_SIG   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
 
#define IDX_AHCI_P_CMD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
 
#define IDX_AHCI_P_SStatus   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))
 
#define IDX_AHCI_P_SControl   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))
 
#define IDX_AHCI_P_SError   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))
 
#define IDX_AHCI_P_ACT   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
 
#define IDX_AHCI_P_SNTF   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
 
#define ATA_AHCI_P_CMD_ST   0x00000001
 
#define ATA_AHCI_P_CMD_SUD   0x00000002
 
#define ATA_AHCI_P_CMD_POD   0x00000004
 
#define ATA_AHCI_P_CMD_CLO   0x00000008
 
#define ATA_AHCI_P_CMD_FRE   0x00000010
 
#define ATA_AHCI_P_CMD_CCS_MASK   0x00001f00
 
#define ATA_AHCI_P_CMD_ISS   0x00002000
 
#define ATA_AHCI_P_CMD_FR   0x00004000
 
#define ATA_AHCI_P_CMD_CR   0x00008000
 
#define ATA_AHCI_P_CMD_CPS   0x00010000
 
#define ATA_AHCI_P_CMD_PMA   0x00020000
 
#define ATA_AHCI_P_CMD_HPCP   0x00040000
 
#define ATA_AHCI_P_CMD_ISP   0x00080000
 
#define ATA_AHCI_P_CMD_CPD   0x00100000
 
#define ATA_AHCI_P_CMD_ESP   0x00200000
 
#define ATA_AHCI_P_CMD_ATAPI   0x01000000
 
#define ATA_AHCI_P_CMD_DLAE   0x02000000
 
#define ATA_AHCI_P_CMD_ALPE   0x04000000
 
#define ATA_AHCI_P_CMD_ASP   0x08000000
 
#define ATA_AHCI_P_CMD_ICC_MASK   0xf0000000
 
#define ATA_AHCI_P_CMD_NOOP   0x00000000
 
#define ATA_AHCI_P_CMD_ACTIVE   0x10000000
 
#define ATA_AHCI_P_CMD_PARTIAL   0x20000000
 
#define ATA_AHCI_P_CMD_SLUMBER   0x60000000
 
#define ATA_AHCI_DMA_ENTRIES   (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
 
#define ATA_AHCI_MAX_TAGS   32
 
#define AHCI_FIS_TYPE_ATA_H2D   0x27
 
#define AHCI_FIS_TYPE_ATA_D2H   0x34
 
#define AHCI_FIS_TYPE_DMA_D2H   0x39
 
#define AHCI_FIS_TYPE_DMA_BiDi   0x41
 
#define AHCI_FIS_TYPE_DATA_BiDi   0x46
 
#define AHCI_FIS_TYPE_BIST_BiDi   0x58
 
#define AHCI_FIS_TYPE_PIO_D2H   0x5f
 
#define AHCI_FIS_TYPE_DEV_BITS_D2H   0xA1
 
#define IDX_AHCI_o_Command   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))
 
#define IDX_AHCI_o_Feature   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))
 
#define IDX_AHCI_o_BlockNumber   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))
 
#define IDX_AHCI_o_CylinderLow   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))
 
#define IDX_AHCI_o_CylinderHigh   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))
 
#define IDX_AHCI_o_DriveSelect   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))
 
#define IDX_AHCI_o_BlockCount   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))
 
#define IDX_AHCI_o_Control   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))
 
#define IDX_AHCI_o_FeatureExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))
 
#define IDX_AHCI_o_BlockNumberExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))
 
#define IDX_AHCI_o_CylinderLowExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))
 
#define IDX_AHCI_o_CylinderHighExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))
 
#define IDX_AHCI_o_BlockCountExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))
 
#define AHCI_FIS_COMM_PM   (0x80 | AHCI_DEV_SEL_PM)
 
#define AHCI_DEV_SEL_1   0x00
 
#define AHCI_DEV_SEL_2   0x01
 
#define AHCI_DEV_SEL_PM   0x0f
 
#define ATA_AHCI_CMD_ATAPI   0x0020
 
#define ATA_AHCI_CMD_WRITE   0x0040
 
#define ATA_AHCI_CMD_PREFETCH   0x0080
 
#define ATA_AHCI_CMD_RESET   0x0100
 
#define ATA_AHCI_CMD_BIST   0x0200
 
#define ATA_AHCI_CMD_CLR_BUSY   0x0400
 
#define IsBusMaster(pciData)
 
#define PCI_IDE_PROGIF_NATIVE_1   0x01
 
#define PCI_IDE_PROGIF_NATIVE_2   0x04
 
#define PCI_IDE_PROGIF_NATIVE_ALL   0x05
 
#define IsMasterDev(pciData)
 
#define MIN_REQ_TTL   4
 
#define REQ_FLAG_FORCE_DOWNRATE   0x01
 
#define REQ_FLAG_DMA_OPERATION   0x02
 
#define REQ_FLAG_REORDERABLE_CMD   0x04
 
#define REQ_FLAG_RW_MASK   0x08
 
#define REQ_FLAG_READ   0x08
 
#define REQ_FLAG_WRITE   0x00
 
#define REQ_FLAG_FORCE_DOWNRATE_LBA48   0x10
 
#define REQ_FLAG_DMA_DBUF   0x20
 
#define REQ_FLAG_DMA_DBUF_PRD   0x40
 
#define REQ_FLAG_LBA48   0x80
 
#define REQ_STATE_NONE   0x00
 
#define REQ_STATE_QUEUED   0x10
 
#define REQ_STATE_PREPARE_TO_TRANSFER   0x20
 
#define REQ_STATE_PREPARE_TO_NEXT   0x21
 
#define REQ_STATE_READY_TO_TRANSFER   0x30
 
#define REQ_STATE_EXPECTING_INTR   0x40
 
#define REQ_STATE_ATAPI_EXPECTING_CMD_INTR   0x41
 
#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR   0x42
 
#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2   0x43
 
#define REQ_STATE_ATAPI_DO_NOTHING_INTR   0x44
 
#define REQ_STATE_EARLY_INTR   0x48
 
#define REQ_STATE_PROCESSING_INTR   0x50
 
#define REQ_STATE_DPC_INTR_REQ   0x51
 
#define REQ_STATE_DPC_RESET_REQ   0x52
 
#define REQ_STATE_DPC_COMPLETE_REQ   0x53
 
#define REQ_STATE_DPC_WAIT_BUSY0   0x57
 
#define REQ_STATE_DPC_WAIT_BUSY1   0x58
 
#define REQ_STATE_DPC_WAIT_BUSY   0x59
 
#define REQ_STATE_DPC_WAIT_DRQ   0x5a
 
#define REQ_STATE_DPC_WAIT_DRQ0   0x5b
 
#define REQ_STATE_DPC_WAIT_DRQ_ERR   0x5c
 
#define REQ_STATE_TRANSFER_COMPLETE   0x7f
 
#define CMD_ACTION_PREPARE   0x01
 
#define CMD_ACTION_EXEC   0x02
 
#define CMD_ACTION_ALL   (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
 
#define REORDER_COST_MAX   ((DEF_I64(0x1) << 60) - 1)
 
#define REORDER_COST_TTL   (REORDER_COST_MAX - 1)
 
#define REORDER_COST_INTERSECT   (REORDER_COST_MAX - 2)
 
#define REORDER_COST_DENIED   (REORDER_COST_MAX - 3)
 
#define REORDER_COST_RESELECT   (REORDER_COST_MAX/4)
 
#define REORDER_COST_SWITCH_RW_CD   (REORDER_COST_MAX/8)
 
#define REORDER_MCOST_SWITCH_RW_CD   (0)
 
#define REORDER_MCOST_SEEK_BACK_CD   (16)
 
#define REORDER_COST_SWITCH_RW_HDD   (0)
 
#define REORDER_MCOST_SWITCH_RW_HDD   (4)
 
#define REORDER_MCOST_SEEK_BACK_HDD   (2)
 
#define CHECK_INTR_ACTIVE   0x03
 
#define CHECK_INTR_DETECTED   0x02
 
#define CHECK_INTR_CHECK   0x01
 
#define CHECK_INTR_IDLE   0x00
 
#define CTRFLAGS_DMA_ACTIVE   0x0001
 
#define CTRFLAGS_DMA_RO   0x0002
 
#define CTRFLAGS_DMA_OPERATION   0x0004
 
#define CTRFLAGS_INTR_DISABLED   0x0008
 
#define CTRFLAGS_DPC_REQ   0x0010
 
#define CTRFLAGS_ENABLE_INTR_REQ   0x0020
 
#define CTRFLAGS_LBA48   0x0040
 
#define CTRFLAGS_DSC_BSY   0x0080
 
#define CTRFLAGS_NO_SLAVE   0x0100
 
#define CTRFLAGS_AHCI_PM   0x0400
 
#define CTRFLAGS_AHCI_PM2   0x0800
 
#define CTRFLAGS_PERMANENT   (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
 
#define GEOM_AUTO   0xffffffff
 
#define GEOM_STD   0x0000
 
#define GEOM_UNIATA   0x0001
 
#define GEOM_ORIG   0x0002
 
#define GEOM_MANUAL   0x0003
 
#define DPC_STATE_NONE   0x00
 
#define DPC_STATE_ISR   0x10
 
#define DPC_STATE_DPC   0x20
 
#define DPC_STATE_TIMER   0x30
 
#define DPC_STATE_COMPLETE   0x40
 
#define HBAFLAGS_DMA_DISABLED   0x01
 
#define HBAFLAGS_DMA_DISABLED_LBA48   0x02
 
#define UNIATA_ALLOCATE_NEW_LUNS   0x00
 
#define PCIBUSNUM_NOT_SPECIFIED   (0xffffffffL)
 
#define PCISLOTNUM_NOT_SPECIFIED   (0xffffffffL)
 
#define GetPciConfig1(offs, op)
 
#define SetPciConfig1(offs, op)
 
#define ChangePciConfig1(offs, _op)
 
#define GetPciConfig2(offs, op)
 
#define SetPciConfig2(offs, op)
 
#define ChangePciConfig2(offs, _op)
 
#define GetPciConfig4(offs, op)
 
#define SetPciConfig4(offs, op)
 
#define ChangePciConfig4(offs, _op)
 
#define DMA_MODE_NONE   0x00
 
#define DMA_MODE_BM   0x01
 
#define DMA_MODE_AHCI   0x02
 
#define GetDmaStatus(de, c)   (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
 
#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru)   AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
 
#define GET_CHANNEL(Srb)   (Srb->PathId)
 
#define GET_CDEV(Srb)   (Srb->TargetId)
 
#define VM_AUTO   0x00
 
#define VM_NONE   0x01
 
#define VM_VBOX   0x02
 
#define VM_VMWARE   0x03
 
#define VM_QEMU   0x04
 
#define VM_BOCHS   0x05
 
#define VM_PCEM   0x06
 
#define VM_MAX_KNOWN   VM_PCEM
 

Typedefs

typedef struct _BUSMASTER_CTX BUSMASTER_CTX
 
typedef struct _BUSMASTER_CTXPBUSMASTER_CTX
 
typedef struct BM_DMA_ENTRY BM_DMA_ENTRY
 
typedef struct BM_DMA_ENTRYPBM_DMA_ENTRY
 
typedef struct _IDE_BUSMASTER_REGISTERS IDE_BUSMASTER_REGISTERS
 
typedef struct _IDE_BUSMASTER_REGISTERSPIDE_BUSMASTER_REGISTERS
 
typedef struct _IDE_AHCI_REGISTERS IDE_AHCI_REGISTERS
 
typedef struct _IDE_AHCI_REGISTERSPIDE_AHCI_REGISTERS
 
typedef union _SATA_SSTATUS_REG SATA_SSTATUS_REG
 
typedef union _SATA_SSTATUS_REGPSATA_SSTATUS_REG
 
typedef union _SATA_SCONTROL_REG SATA_SCONTROL_REG
 
typedef union _SATA_SCONTROL_REGPSATA_SCONTROL_REG
 
typedef union _SATA_SERROR_REG SATA_SERROR_REG
 
typedef union _SATA_SERROR_REGPSATA_SERROR_REG
 
typedef struct _IDE_SATA_REGISTERS IDE_SATA_REGISTERS
 
typedef struct _IDE_SATA_REGISTERSPIDE_SATA_REGISTERS
 
typedef union _AHCI_IS_REG AHCI_IS_REG
 
typedef union _AHCI_IS_REGPAHCI_IS_REG
 
typedef struct _IDE_AHCI_PORT_REGISTERS IDE_AHCI_PORT_REGISTERS
 
typedef struct _IDE_AHCI_PORT_REGISTERSPIDE_AHCI_PORT_REGISTERS
 
typedef struct _IDE_AHCI_PRD_ENTRY IDE_AHCI_PRD_ENTRY
 
typedef struct _IDE_AHCI_PRD_ENTRYPIDE_AHCI_PRD_ENTRY
 
typedef struct _AHCI_ATA_H2D_FIS AHCI_ATA_H2D_FIS
 
typedef struct _AHCI_ATA_H2D_FISPAHCI_ATA_H2D_FIS
 
typedef struct _IDE_AHCI_CMD IDE_AHCI_CMD
 
typedef struct _IDE_AHCI_CMDPIDE_AHCI_CMD
 
typedef struct _IDE_AHCI_CMD_LIST IDE_AHCI_CMD_LIST
 
typedef struct _IDE_AHCI_CMD_LISTPIDE_AHCI_CMD_LIST
 
typedef struct _IDE_AHCI_RCV_FIS IDE_AHCI_RCV_FIS
 
typedef struct _IDE_AHCI_RCV_FISPIDE_AHCI_RCV_FIS
 
typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCK IDE_AHCI_CHANNEL_CTL_BLOCK
 
typedef struct _IDE_AHCI_CHANNEL_CTL_BLOCKPIDE_AHCI_CHANNEL_CTL_BLOCK
 
typedef union _ATA_REQ ATA_REQ
 
typedef union _ATA_REQPATA_REQ
 
typedef struct _IORES IORES
 
typedef struct _IORESPIORES
 
typedef struct _HW_CHANNEL HW_CHANNEL
 
typedef struct _HW_CHANNELPHW_CHANNEL
 
typedef struct _HW_LU_EXTENSION HW_LU_EXTENSION
 
typedef struct _HW_LU_EXTENSIONPHW_LU_EXTENSION
 
typedef struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION
 
typedef struct _HW_DEVICE_EXTENSIONPHW_DEVICE_EXTENSION
 
typedef struct _ISR2_DEVICE_EXTENSION ISR2_DEVICE_EXTENSION
 
typedef struct _ISR2_DEVICE_EXTENSIONPISR2_DEVICE_EXTENSION
 
typedef ISR2_DEVICE_EXTENSION PCIIDE_DEVICE_EXTENSION
 
typedef PISR2_DEVICE_EXTENSION PPCIIDE_DEVICE_EXTENSION
 

Functions

VOID NTAPI UniataEnumBusMasterController (IN PVOID DriverObject, PVOID Argument2)
 
ULONG NTAPI UniataFindCompatBusMasterController1 (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
ULONG NTAPI UniataFindCompatBusMasterController2 (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
BOOLEAN NTAPI UniataAllocateLunExt (PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
 
VOID NTAPI UniataFreeLunExt (PHW_DEVICE_EXTENSION deviceExtension)
 
ULONG NTAPI UniataFindBusMasterController (IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
 
NTSTATUS NTAPI UniataClaimLegacyPCIIDE (ULONG i)
 
NTSTATUS NTAPI UniataConnectIntr2 (IN PVOID HwDeviceExtension)
 
NTSTATUS NTAPI UniataDisconnectIntr2 (IN PVOID HwDeviceExtension)
 
ULONG NTAPI ScsiPortGetBusDataByOffset (IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
 
ULONG NTAPI AtapiFindListedDev (PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG lim, IN PVOID HwDeviceExtension, IN ULONG BusNumber, IN ULONG SlotNumber, OUT PCI_SLOT_NUMBER *_slotData)
 
ULONG NTAPI AtapiFindDev (IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN ULONG dev_id, IN ULONG RevID)
 
VOID NTAPI AtapiDmaAlloc (IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN ULONG lChannel)
 
BOOLEAN NTAPI AtapiDmaSetup (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb, IN PUCHAR data, IN ULONG count)
 
BOOLEAN NTAPI AtapiDmaPioSync (PVOID HwDeviceExtension, PSCSI_REQUEST_BLOCK Srb, PUCHAR data, ULONG count)
 
BOOLEAN NTAPI AtapiDmaDBSync (PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
 
BOOLEAN NTAPI AtapiDmaDBPreSync (IN PVOID HwDeviceExtension, PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
 
VOID NTAPI AtapiDmaStart (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
 
UCHAR NTAPI AtapiDmaDone (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
 
VOID NTAPI AtapiDmaReinit (IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt, IN PATA_REQ AtaReq)
 
VOID NTAPI AtapiDmaInit__ (IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt)
 
VOID NTAPI AtapiDmaInit (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN SCHAR apiomode, IN SCHAR wdmamode, IN SCHAR udmamode)
 
BOOLEAN NTAPI AtapiInterrupt2 (IN PKINTERRUPT Interrupt, IN PVOID HwDeviceExtension)
 
BOOLEAN NTAPI UniataChipDetectChannels (IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo)
 
NTSTATUS NTAPI UniataChipDetect (IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN BOOLEAN *simplexOnly)
 
BOOLEAN NTAPI AtapiChipInit (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG c)
 
ULONGIO_PTR NTAPI AtapiGetIoRange (IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
 
USHORT NTAPI UniataEnableIoPCI (IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
 
VOID DDKFASTAPI AtapiWritePort4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
 
VOID DDKFASTAPI AtapiWritePort2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
 
VOID DDKFASTAPI AtapiWritePort1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
 
VOID DDKFASTAPI AtapiWritePortEx4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
 
VOID DDKFASTAPI AtapiWritePortEx1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
 
ULONG DDKFASTAPI AtapiReadPort4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
 
USHORT DDKFASTAPI AtapiReadPort2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
 
UCHAR DDKFASTAPI AtapiReadPort1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
 
ULONG DDKFASTAPI AtapiReadPortEx4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
 
UCHAR DDKFASTAPI AtapiReadPortEx1 (IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
 
VOID DDKFASTAPI AtapiWriteBuffer4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID DDKFASTAPI AtapiWriteBuffer2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID DDKFASTAPI AtapiReadBuffer4 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID DDKFASTAPI AtapiReadBuffer2 (IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
 
VOID NTAPI AtapiSetupLunPtrs (IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
 
BOOLEAN NTAPI AtapiReadChipConfig (IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
 
VOID NTAPI UniataForgetDevice (PHW_LU_EXTENSION LunExt)
 

Variables

UCHAR pciBuffer [256]
 
PBUSMASTER_CONTROLLER_INFORMATION BMList
 
ULONG BMListLen
 
ULONG IsaCount
 
ULONG MCACount
 
UNICODE_STRING SavedRegPath
 
PDRIVER_OBJECT SavedDriverObject
 
ULONG SkipRaids
 
ULONG ForceSimplex
 
BOOLEAN g_opt_AtapiDmaRawRead
 
BOOLEAN hasPCI
 
BOOLEAN InDriverEntry
 
BOOLEAN g_Dump
 
BOOLEAN g_opt_Verbose
 
ULONG g_opt_VirtualMachine
 
ULONG g_opt_WaitBusyResetCount
 
ULONG CPU_num
 
BOOLEAN WinVer_WDM_Model
 

Macro Definition Documentation

◆ AHCI_BOHC_BB

#define AHCI_BOHC_BB   0x00000001

Definition at line 259 of file bsmaster.h.

◆ AHCI_BOHC_BOS

#define AHCI_BOHC_BOS   0x00000010

Definition at line 263 of file bsmaster.h.

◆ AHCI_BOHC_OOC

#define AHCI_BOHC_OOC   0x00000002

Definition at line 260 of file bsmaster.h.

◆ AHCI_BOHC_OOS

#define AHCI_BOHC_OOS   0x00000008

Definition at line 262 of file bsmaster.h.

◆ AHCI_BOHC_SOOE

#define AHCI_BOHC_SOOE   0x00000004

Definition at line 261 of file bsmaster.h.

◆ AHCI_CAP2_APST

#define AHCI_CAP2_APST   0x00000004

Definition at line 247 of file bsmaster.h.

◆ AHCI_CAP2_BOH

#define AHCI_CAP2_BOH   0x00000001

Definition at line 245 of file bsmaster.h.

◆ AHCI_CAP2_NVMP

#define AHCI_CAP2_NVMP   0x00000002

Definition at line 246 of file bsmaster.h.

◆ AHCI_CAP_CCC

#define AHCI_CAP_CCC   0x00000080

Definition at line 201 of file bsmaster.h.

◆ AHCI_CAP_ISS_MASK

#define AHCI_CAP_ISS_MASK   0x00f00000

Definition at line 206 of file bsmaster.h.

◆ AHCI_CAP_NCQ

#define AHCI_CAP_NCQ   0x40000000

Definition at line 209 of file bsmaster.h.

◆ AHCI_CAP_NCS_MASK

#define AHCI_CAP_NCS_MASK   0x00001f00

Definition at line 202 of file bsmaster.h.

◆ AHCI_CAP_NOP_MASK

#define AHCI_CAP_NOP_MASK   0x0000001f

Definition at line 200 of file bsmaster.h.

◆ AHCI_CAP_PMD

#define AHCI_CAP_PMD   0x00008000

Definition at line 203 of file bsmaster.h.

◆ AHCI_CAP_S64A

#define AHCI_CAP_S64A   0x80000000

Definition at line 210 of file bsmaster.h.

◆ AHCI_CAP_SAM

#define AHCI_CAP_SAM   0x00040000

Definition at line 205 of file bsmaster.h.

◆ AHCI_CAP_SCLO

#define AHCI_CAP_SCLO   0x01000000

Definition at line 207 of file bsmaster.h.

◆ AHCI_CAP_SNTF

#define AHCI_CAP_SNTF   0x20000000

Definition at line 208 of file bsmaster.h.

◆ AHCI_CAP_SPM

#define AHCI_CAP_SPM   0x00020000

Definition at line 204 of file bsmaster.h.

◆ AHCI_CLB_ALIGNEMENT_MASK

#define AHCI_CLB_ALIGNEMENT_MASK   ((ULONGLONG)(1024-1))

Definition at line 518 of file bsmaster.h.

◆ AHCI_CMD_ALIGNEMENT_MASK

#define AHCI_CMD_ALIGNEMENT_MASK   ((ULONGLONG)(128-1))

Definition at line 520 of file bsmaster.h.

◆ AHCI_DEV_SEL_1

#define AHCI_DEV_SEL_1   0x00

Definition at line 801 of file bsmaster.h.

◆ AHCI_DEV_SEL_2

#define AHCI_DEV_SEL_2   0x01

Definition at line 802 of file bsmaster.h.

◆ AHCI_DEV_SEL_PM

#define AHCI_DEV_SEL_PM   0x0f

Definition at line 803 of file bsmaster.h.

◆ AHCI_FIS_ALIGNEMENT_MASK

#define AHCI_FIS_ALIGNEMENT_MASK   ((ULONGLONG)(256-1))

Definition at line 519 of file bsmaster.h.

◆ AHCI_FIS_COMM_PM

#define AHCI_FIS_COMM_PM   (0x80 | AHCI_DEV_SEL_PM)

Definition at line 799 of file bsmaster.h.

◆ AHCI_FIS_TYPE_ATA_D2H

#define AHCI_FIS_TYPE_ATA_D2H   0x34

Definition at line 753 of file bsmaster.h.

◆ AHCI_FIS_TYPE_ATA_H2D

#define AHCI_FIS_TYPE_ATA_H2D   0x27

Definition at line 752 of file bsmaster.h.

◆ AHCI_FIS_TYPE_BIST_BiDi

#define AHCI_FIS_TYPE_BIST_BiDi   0x58

Definition at line 757 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DATA_BiDi

#define AHCI_FIS_TYPE_DATA_BiDi   0x46

Definition at line 756 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DEV_BITS_D2H

#define AHCI_FIS_TYPE_DEV_BITS_D2H   0xA1

Definition at line 759 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DMA_BiDi

#define AHCI_FIS_TYPE_DMA_BiDi   0x41

Definition at line 755 of file bsmaster.h.

◆ AHCI_FIS_TYPE_DMA_D2H

#define AHCI_FIS_TYPE_DMA_D2H   0x39

Definition at line 754 of file bsmaster.h.

◆ AHCI_FIS_TYPE_PIO_D2H

#define AHCI_FIS_TYPE_PIO_D2H   0x5f

Definition at line 758 of file bsmaster.h.

◆ AHCI_GHC

#define AHCI_GHC   0x04

Definition at line 220 of file bsmaster.h.

◆ AHCI_GHC_AE

#define AHCI_GHC_AE   0x80000000

Definition at line 223 of file bsmaster.h.

◆ AHCI_GHC_HR

#define AHCI_GHC_HR   0x00000001

Definition at line 221 of file bsmaster.h.

◆ AHCI_GHC_IE

#define AHCI_GHC_IE   0x00000002

Definition at line 222 of file bsmaster.h.

◆ AHCI_MAX_PORT

#define AHCI_MAX_PORT   32

Definition at line 108 of file bsmaster.h.

◆ ATA_ACTIVE

#define ATA_ACTIVE   0x4

Definition at line 58 of file bsmaster.h.

◆ ATA_ACTIVE_ATA

#define ATA_ACTIVE_ATA   0x5

Definition at line 59 of file bsmaster.h.

◆ ATA_ACTIVE_ATAPI

#define ATA_ACTIVE_ATAPI   0x6

Definition at line 60 of file bsmaster.h.

◆ ATA_AHCI_CMD_ATAPI

#define ATA_AHCI_CMD_ATAPI   0x0020

Definition at line 815 of file bsmaster.h.

◆ ATA_AHCI_CMD_BIST

#define ATA_AHCI_CMD_BIST   0x0200

Definition at line 819 of file bsmaster.h.

◆ ATA_AHCI_CMD_CLR_BUSY

#define ATA_AHCI_CMD_CLR_BUSY   0x0400

Definition at line 820 of file bsmaster.h.

◆ ATA_AHCI_CMD_PREFETCH

#define ATA_AHCI_CMD_PREFETCH   0x0080

Definition at line 817 of file bsmaster.h.

◆ ATA_AHCI_CMD_RESET

#define ATA_AHCI_CMD_RESET   0x0100

Definition at line 818 of file bsmaster.h.

◆ ATA_AHCI_CMD_WRITE

#define ATA_AHCI_CMD_WRITE   0x0040

Definition at line 816 of file bsmaster.h.

◆ ATA_AHCI_DMA_ENTRIES

#define ATA_AHCI_DMA_ENTRIES   (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */

Definition at line 749 of file bsmaster.h.

◆ ATA_AHCI_MAX_TAGS

#define ATA_AHCI_MAX_TAGS   32

Definition at line 750 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ACTIVE

#define ATA_AHCI_P_CMD_ACTIVE   0x10000000

Definition at line 719 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ALPE

#define ATA_AHCI_P_CMD_ALPE   0x04000000

Definition at line 715 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ASP

#define ATA_AHCI_P_CMD_ASP   0x08000000

Definition at line 716 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ATAPI

#define ATA_AHCI_P_CMD_ATAPI   0x01000000

Definition at line 713 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CCS_MASK

#define ATA_AHCI_P_CMD_CCS_MASK   0x00001f00

Definition at line 703 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CLO

#define ATA_AHCI_P_CMD_CLO   0x00000008

Definition at line 701 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CPD

#define ATA_AHCI_P_CMD_CPD   0x00100000

Definition at line 711 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CPS

#define ATA_AHCI_P_CMD_CPS   0x00010000

Definition at line 707 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_CR

#define ATA_AHCI_P_CMD_CR   0x00008000

Definition at line 706 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_DLAE

#define ATA_AHCI_P_CMD_DLAE   0x02000000

Definition at line 714 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ESP

#define ATA_AHCI_P_CMD_ESP   0x00200000

Definition at line 712 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_FR

#define ATA_AHCI_P_CMD_FR   0x00004000

Definition at line 705 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_FRE

#define ATA_AHCI_P_CMD_FRE   0x00000010

Definition at line 702 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_HPCP

#define ATA_AHCI_P_CMD_HPCP   0x00040000

Definition at line 709 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ICC_MASK

#define ATA_AHCI_P_CMD_ICC_MASK   0xf0000000

Definition at line 717 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ISP

#define ATA_AHCI_P_CMD_ISP   0x00080000

Definition at line 710 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ISS

#define ATA_AHCI_P_CMD_ISS   0x00002000

Definition at line 704 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_NOOP

#define ATA_AHCI_P_CMD_NOOP   0x00000000

Definition at line 718 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_PARTIAL

#define ATA_AHCI_P_CMD_PARTIAL   0x20000000

Definition at line 720 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_PMA

#define ATA_AHCI_P_CMD_PMA   0x00020000

Definition at line 708 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_POD

#define ATA_AHCI_P_CMD_POD   0x00000004

Definition at line 700 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_SLUMBER

#define ATA_AHCI_P_CMD_SLUMBER   0x60000000

Definition at line 721 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_ST

#define ATA_AHCI_P_CMD_ST   0x00000001

Definition at line 698 of file bsmaster.h.

◆ ATA_AHCI_P_CMD_SUD

#define ATA_AHCI_P_CMD_SUD   0x00000002

Definition at line 699 of file bsmaster.h.

◆ ATA_AHCI_P_IX_CPD

#define ATA_AHCI_P_IX_CPD   0x80000000

Definition at line 516 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DHR

#define ATA_AHCI_P_IX_DHR   0x00000001

Definition at line 499 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DI

#define ATA_AHCI_P_IX_DI   0x00000080

Definition at line 506 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DP

#define ATA_AHCI_P_IX_DP   0x00000020

Definition at line 504 of file bsmaster.h.

◆ ATA_AHCI_P_IX_DS

#define ATA_AHCI_P_IX_DS   0x00000004

Definition at line 501 of file bsmaster.h.

◆ ATA_AHCI_P_IX_HBD

#define ATA_AHCI_P_IX_HBD   0x10000000

Definition at line 513 of file bsmaster.h.

◆ ATA_AHCI_P_IX_HBF

#define ATA_AHCI_P_IX_HBF   0x20000000

Definition at line 514 of file bsmaster.h.

◆ ATA_AHCI_P_IX_IF

#define ATA_AHCI_P_IX_IF   0x08000000

Definition at line 512 of file bsmaster.h.

◆ ATA_AHCI_P_IX_INF

#define ATA_AHCI_P_IX_INF   0x04000000

Definition at line 511 of file bsmaster.h.

◆ ATA_AHCI_P_IX_IPM

#define ATA_AHCI_P_IX_IPM   0x00800000

Definition at line 509 of file bsmaster.h.

◆ ATA_AHCI_P_IX_OF

#define ATA_AHCI_P_IX_OF   0x01000000

Definition at line 510 of file bsmaster.h.

◆ ATA_AHCI_P_IX_PC

#define ATA_AHCI_P_IX_PC   0x00000040

Definition at line 505 of file bsmaster.h.

◆ ATA_AHCI_P_IX_PRC

#define ATA_AHCI_P_IX_PRC   0x00400000

Definition at line 508 of file bsmaster.h.

◆ ATA_AHCI_P_IX_PS

#define ATA_AHCI_P_IX_PS   0x00000002

Definition at line 500 of file bsmaster.h.

◆ ATA_AHCI_P_IX_SDB

#define ATA_AHCI_P_IX_SDB   0x00000008

Definition at line 502 of file bsmaster.h.

◆ ATA_AHCI_P_IX_TFE

#define ATA_AHCI_P_IX_TFE   0x40000000

Definition at line 515 of file bsmaster.h.

◆ ATA_AHCI_P_IX_UF

#define ATA_AHCI_P_IX_UF   0x00000010

Definition at line 503 of file bsmaster.h.

◆ ATA_ALTIOSIZE

#define ATA_ALTIOSIZE   0x01 /* alternate registers size */

Definition at line 89 of file bsmaster.h.

◆ ATA_ALTOFFSET

#define ATA_ALTOFFSET   0x206 /* alternate registers offset */

Definition at line 87 of file bsmaster.h.

◆ ATA_BM_OFFSET1

#define ATA_BM_OFFSET1   0x08

Definition at line 85 of file bsmaster.h.

◆ ATA_BMIOSIZE

#define ATA_BMIOSIZE   0x20

Definition at line 90 of file bsmaster.h.

◆ ATA_DMA_ENTRIES

#define ATA_DMA_ENTRIES   256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/

Definition at line 100 of file bsmaster.h.

◆ ATA_DMA_EOT

#define ATA_DMA_EOT   0x80000000

Definition at line 101 of file bsmaster.h.

◆ ATA_IDLE

#define ATA_IDLE   0x0

Definition at line 54 of file bsmaster.h.

◆ ATA_IMMEDIATE

#define ATA_IMMEDIATE   0x1

Definition at line 55 of file bsmaster.h.

◆ ATA_IOSIZE

#define ATA_IOSIZE   0x08

Definition at line 86 of file bsmaster.h.

◆ ATA_MAX_IOLBA28

#define ATA_MAX_IOLBA28   DEF_U64(0x0fffff80)

Definition at line 94 of file bsmaster.h.

◆ ATA_MAX_IOLBA32

#define ATA_MAX_IOLBA32   DEF_U64(0xffffff80)

Definition at line 97 of file bsmaster.h.

◆ ATA_MAX_LBA28

#define ATA_MAX_LBA28   DEF_U64(0x0fffffff)

Definition at line 95 of file bsmaster.h.

◆ ATA_MAX_LBA32

#define ATA_MAX_LBA32   DEF_U64(0xffffffff)

Definition at line 98 of file bsmaster.h.

◆ ATA_PC98_BANKIOSIZE

#define ATA_PC98_BANKIOSIZE   0x01

Definition at line 91 of file bsmaster.h.

◆ ATA_PCCARD_ALTOFFSET

#define ATA_PCCARD_ALTOFFSET   0x0e /* do for PCCARD devices */

Definition at line 88 of file bsmaster.h.

◆ ATA_REINITING

#define ATA_REINITING   0x7

Definition at line 61 of file bsmaster.h.

◆ ATA_SC_DET_DISABLE

#define ATA_SC_DET_DISABLE   0x00000004

Definition at line 361 of file bsmaster.h.

◆ ATA_SC_DET_IDLE

#define ATA_SC_DET_IDLE   0x00000000

Definition at line 359 of file bsmaster.h.

◆ ATA_SC_DET_MASK

#define ATA_SC_DET_MASK   0x0000000f

Definition at line 358 of file bsmaster.h.

◆ ATA_SC_DET_RESET

#define ATA_SC_DET_RESET   0x00000001

Definition at line 360 of file bsmaster.h.

◆ ATA_SC_IPM_DIS_PARTIAL

#define ATA_SC_IPM_DIS_PARTIAL   0x00000100

Definition at line 371 of file bsmaster.h.

◆ ATA_SC_IPM_DIS_SLUMBER

#define ATA_SC_IPM_DIS_SLUMBER   0x00000200

Definition at line 372 of file bsmaster.h.

◆ ATA_SC_IPM_MASK

#define ATA_SC_IPM_MASK   0x00000f00

Definition at line 369 of file bsmaster.h.

◆ ATA_SC_IPM_NONE

#define ATA_SC_IPM_NONE   0x00000000

Definition at line 370 of file bsmaster.h.

◆ ATA_SC_SPD_MASK

#define ATA_SC_SPD_MASK   0x000000f0

Definition at line 363 of file bsmaster.h.

◆ ATA_SC_SPD_NO_SPEED

#define ATA_SC_SPD_NO_SPEED   0x00000000

Definition at line 364 of file bsmaster.h.

◆ ATA_SC_SPD_SPEED_GEN1

#define ATA_SC_SPD_SPEED_GEN1   0x00000010

Definition at line 365 of file bsmaster.h.

◆ ATA_SC_SPD_SPEED_GEN2

#define ATA_SC_SPD_SPEED_GEN2   0x00000020

Definition at line 366 of file bsmaster.h.

◆ ATA_SC_SPD_SPEED_GEN3

#define ATA_SC_SPD_SPEED_GEN3   0x00000040

Definition at line 367 of file bsmaster.h.

◆ ATA_SE_COMM_CORRECTED

#define ATA_SE_COMM_CORRECTED   0x00000002

Definition at line 410 of file bsmaster.h.

◆ ATA_SE_COMM_ERR

#define ATA_SE_COMM_ERR   0x00000200

Definition at line 412 of file bsmaster.h.

◆ ATA_SE_COMM_WAKE

#define ATA_SE_COMM_WAKE   0x00040000

Definition at line 417 of file bsmaster.h.

◆ ATA_SE_CRC_ERR

#define ATA_SE_CRC_ERR   0x00200000

Definition at line 420 of file bsmaster.h.

◆ ATA_SE_DATA_CORRECTED

#define ATA_SE_DATA_CORRECTED   0x00000001

Definition at line 409 of file bsmaster.h.

◆ ATA_SE_DATA_ERR

#define ATA_SE_DATA_ERR   0x00000100

Definition at line 411 of file bsmaster.h.

◆ ATA_SE_DECODE_ERR

#define ATA_SE_DECODE_ERR   0x00080000

Definition at line 418 of file bsmaster.h.

◆ ATA_SE_HANDSHAKE_ERR

#define ATA_SE_HANDSHAKE_ERR   0x00400000

Definition at line 421 of file bsmaster.h.

◆ ATA_SE_HOST_ERR

#define ATA_SE_HOST_ERR   0x00000800

Definition at line 414 of file bsmaster.h.

◆ ATA_SE_LINKSEQ_ERR

#define ATA_SE_LINKSEQ_ERR   0x00800000

Definition at line 422 of file bsmaster.h.

◆ ATA_SE_PARITY_ERR

#define ATA_SE_PARITY_ERR   0x00100000

Definition at line 419 of file bsmaster.h.

◆ ATA_SE_PHY_CHANGED

#define ATA_SE_PHY_CHANGED   0x00010000

Definition at line 415 of file bsmaster.h.

◆ ATA_SE_PHY_IERROR

#define ATA_SE_PHY_IERROR   0x00020000

Definition at line 416 of file bsmaster.h.

◆ ATA_SE_PROT_ERR

#define ATA_SE_PROT_ERR   0x00000400

Definition at line 413 of file bsmaster.h.

◆ ATA_SE_TRANSPORT_ERR

#define ATA_SE_TRANSPORT_ERR   0x01000000

Definition at line 423 of file bsmaster.h.

◆ ATA_SE_UNKNOWN_FIS

#define ATA_SE_UNKNOWN_FIS   0x02000000

Definition at line 424 of file bsmaster.h.

◆ ATA_SS_DET_DEV_PRESENT

#define ATA_SS_DET_DEV_PRESENT   0x00000001

Definition at line 311 of file bsmaster.h.

◆ ATA_SS_DET_MASK

#define ATA_SS_DET_MASK   0x0000000f

Definition at line 309 of file bsmaster.h.

◆ ATA_SS_DET_NO_DEVICE

#define ATA_SS_DET_NO_DEVICE   0x00000000

Definition at line 310 of file bsmaster.h.

◆ ATA_SS_DET_PHY_OFFLINE

#define ATA_SS_DET_PHY_OFFLINE   0x00000004

Definition at line 313 of file bsmaster.h.

◆ ATA_SS_DET_PHY_ONLINE

#define ATA_SS_DET_PHY_ONLINE   0x00000003

Definition at line 312 of file bsmaster.h.

◆ ATA_SS_IPM_ACTIVE

#define ATA_SS_IPM_ACTIVE   0x00000100

Definition at line 322 of file bsmaster.h.

◆ ATA_SS_IPM_MASK

#define ATA_SS_IPM_MASK   0x00000f00

Definition at line 320 of file bsmaster.h.

◆ ATA_SS_IPM_NO_DEVICE

#define ATA_SS_IPM_NO_DEVICE   0x00000000

Definition at line 321 of file bsmaster.h.

◆ ATA_SS_IPM_PARTIAL

#define ATA_SS_IPM_PARTIAL   0x00000200

Definition at line 323 of file bsmaster.h.

◆ ATA_SS_IPM_SLUMBER

#define ATA_SS_IPM_SLUMBER   0x00000600

Definition at line 324 of file bsmaster.h.

◆ ATA_SS_SPD_GEN1

#define ATA_SS_SPD_GEN1   0x00000010

Definition at line 317 of file bsmaster.h.

◆ ATA_SS_SPD_GEN2

#define ATA_SS_SPD_GEN2   0x00000020

Definition at line 318 of file bsmaster.h.

◆ ATA_SS_SPD_MASK

#define ATA_SS_SPD_MASK   0x000000f0

Definition at line 315 of file bsmaster.h.

◆ ATA_SS_SPD_NO_SPEED

#define ATA_SS_SPD_NO_SPEED   0x00000000

Definition at line 316 of file bsmaster.h.

◆ ATA_WAIT_BASE_READY

#define ATA_WAIT_BASE_READY   0x8

Definition at line 62 of file bsmaster.h.

◆ ATA_WAIT_IDLE

#define ATA_WAIT_IDLE   0x9

Definition at line 63 of file bsmaster.h.

◆ ATA_WAIT_INTR

#define ATA_WAIT_INTR   0x2

Definition at line 56 of file bsmaster.h.

◆ ATA_WAIT_READY

#define ATA_WAIT_READY   0x3

Definition at line 57 of file bsmaster.h.

◆ ATAPI_MAGIC_LSB

#define ATAPI_MAGIC_LSB   0x14

Definition at line 105 of file bsmaster.h.

◆ ATAPI_MAGIC_MSB

#define ATAPI_MAGIC_MSB   0xeb

Definition at line 106 of file bsmaster.h.

◆ AtapiVirtToPhysAddr

#define AtapiVirtToPhysAddr (   hwde,
  srb,
  phaddr,
  plen,
  phaddru 
)    AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);

Definition at line 1716 of file bsmaster.h.

◆ BM_COMMAND_READ

#define BM_COMMAND_READ   0x08

Definition at line 154 of file bsmaster.h.

◆ BM_COMMAND_START_STOP

#define BM_COMMAND_START_STOP   0x01

Definition at line 150 of file bsmaster.h.

◆ BM_COMMAND_WRITE

#define BM_COMMAND_WRITE   0x00

Definition at line 153 of file bsmaster.h.

◆ BM_DS0_SII_DMA_COMPLETE

#define BM_DS0_SII_DMA_COMPLETE   (1 << 18) /* cmd complete / IRQ pending */

Definition at line 160 of file bsmaster.h.

◆ BM_DS0_SII_DMA_ENABLE

#define BM_DS0_SII_DMA_ENABLE   (1 << 0) /* DMA run switch */

Definition at line 156 of file bsmaster.h.

◆ BM_DS0_SII_DMA_ERROR

#define BM_DS0_SII_DMA_ERROR   (1 << 17) /* PCI bus error */

Definition at line 159 of file bsmaster.h.

◆ BM_DS0_SII_DMA_SATA_IRQ

#define BM_DS0_SII_DMA_SATA_IRQ   (1 << 4) /* OR of all SATA IRQs */

Definition at line 158 of file bsmaster.h.

◆ BM_DS0_SII_IRQ

#define BM_DS0_SII_IRQ   (1 << 3) /* ??? */

Definition at line 157 of file bsmaster.h.

◆ BM_STATUS_ACTIVE

#define BM_STATUS_ACTIVE   0x01

Definition at line 142 of file bsmaster.h.

◆ BM_STATUS_DRIVE_0_DMA

#define BM_STATUS_DRIVE_0_DMA   0x20

Definition at line 146 of file bsmaster.h.

◆ BM_STATUS_DRIVE_1_DMA

#define BM_STATUS_DRIVE_1_DMA   0x40

Definition at line 147 of file bsmaster.h.

◆ BM_STATUS_ERR

#define BM_STATUS_ERR   0x02

Definition at line 143 of file bsmaster.h.

◆ BM_STATUS_INTR

#define BM_STATUS_INTR   0x04

Definition at line 144 of file bsmaster.h.

◆ BM_STATUS_MASK

#define BM_STATUS_MASK   0x07

Definition at line 145 of file bsmaster.h.

◆ BM_STATUS_SIMPLEX_ONLY

#define BM_STATUS_SIMPLEX_ONLY   0x80

Definition at line 148 of file bsmaster.h.

◆ ChangePciConfig1

#define ChangePciConfig1 (   offs,
  _op 
)
Value:
{ \
UCHAR a = 0; \
GetPciConfig1(offs, a); \
a = (UCHAR)(_op); \
SetPciConfig1(offs, a); \
}
unsigned char UCHAR
Definition: xmlstorage.h:181
GLboolean GLboolean GLboolean GLboolean a
Definition: glext.h:6204

Definition at line 1641 of file bsmaster.h.

◆ ChangePciConfig2

#define ChangePciConfig2 (   offs,
  _op 
)
Value:
{ \
USHORT a = 0; \
GetPciConfig2(offs, a); \
a = (USHORT)(_op); \
SetPciConfig2(offs, a); \
}
unsigned short USHORT
Definition: pedump.c:61
GLboolean GLboolean GLboolean GLboolean a
Definition: glext.h:6204

Definition at line 1670 of file bsmaster.h.

◆ ChangePciConfig4

#define ChangePciConfig4 (   offs,
  _op 
)
Value:
{ \
ULONG a = 0; \
GetPciConfig4(offs, a); \
a = _op; \
SetPciConfig4(offs, a); \
}
GLboolean GLboolean GLboolean GLboolean a
Definition: glext.h:6204

Definition at line 1699 of file bsmaster.h.

◆ CHECK_INTR_ACTIVE

#define CHECK_INTR_ACTIVE   0x03

Definition at line 1066 of file bsmaster.h.

◆ CHECK_INTR_CHECK

#define CHECK_INTR_CHECK   0x01

Definition at line 1068 of file bsmaster.h.

◆ CHECK_INTR_DETECTED

#define CHECK_INTR_DETECTED   0x02

Definition at line 1067 of file bsmaster.h.

◆ CHECK_INTR_IDLE

#define CHECK_INTR_IDLE   0x00

Definition at line 1069 of file bsmaster.h.

◆ CMD_ACTION_ALL

#define CMD_ACTION_ALL   (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)

Definition at line 976 of file bsmaster.h.

◆ CMD_ACTION_EXEC

#define CMD_ACTION_EXEC   0x02

Definition at line 975 of file bsmaster.h.

◆ CMD_ACTION_PREPARE

#define CMD_ACTION_PREPARE   0x01

Definition at line 974 of file bsmaster.h.

◆ CTRFLAGS_AHCI_PM

#define CTRFLAGS_AHCI_PM   0x0400

Definition at line 1143 of file bsmaster.h.

◆ CTRFLAGS_AHCI_PM2

#define CTRFLAGS_AHCI_PM2   0x0800

Definition at line 1144 of file bsmaster.h.

◆ CTRFLAGS_DMA_ACTIVE

#define CTRFLAGS_DMA_ACTIVE   0x0001

Definition at line 1131 of file bsmaster.h.

◆ CTRFLAGS_DMA_OPERATION

#define CTRFLAGS_DMA_OPERATION   0x0004

Definition at line 1133 of file bsmaster.h.

◆ CTRFLAGS_DMA_RO

#define CTRFLAGS_DMA_RO   0x0002

Definition at line 1132 of file bsmaster.h.

◆ CTRFLAGS_DPC_REQ

#define CTRFLAGS_DPC_REQ   0x0010

Definition at line 1135 of file bsmaster.h.

◆ CTRFLAGS_DSC_BSY

#define CTRFLAGS_DSC_BSY   0x0080

Definition at line 1138 of file bsmaster.h.

◆ CTRFLAGS_ENABLE_INTR_REQ

#define CTRFLAGS_ENABLE_INTR_REQ   0x0020

Definition at line 1136 of file bsmaster.h.

◆ CTRFLAGS_INTR_DISABLED

#define CTRFLAGS_INTR_DISABLED   0x0008

Definition at line 1134 of file bsmaster.h.

◆ CTRFLAGS_LBA48

#define CTRFLAGS_LBA48   0x0040

Definition at line 1137 of file bsmaster.h.

◆ CTRFLAGS_NO_SLAVE

#define CTRFLAGS_NO_SLAVE   0x0100

Definition at line 1139 of file bsmaster.h.

◆ CTRFLAGS_PERMANENT

#define CTRFLAGS_PERMANENT   (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)

Definition at line 1146 of file bsmaster.h.

◆ DEV_BSIZE

#define DEV_BSIZE   512

Definition at line 103 of file bsmaster.h.

◆ DMA_MODE_AHCI

#define DMA_MODE_AHCI   0x02

Definition at line 1708 of file bsmaster.h.

◆ DMA_MODE_BM

#define DMA_MODE_BM   0x01

Definition at line 1707 of file bsmaster.h.

◆ DMA_MODE_NONE

#define DMA_MODE_NONE   0x00

Definition at line 1706 of file bsmaster.h.

◆ DPC_STATE_COMPLETE

#define DPC_STATE_COMPLETE   0x40

Definition at line 1158 of file bsmaster.h.

◆ DPC_STATE_DPC

#define DPC_STATE_DPC   0x20

Definition at line 1156 of file bsmaster.h.

◆ DPC_STATE_ISR

#define DPC_STATE_ISR   0x10

Definition at line 1155 of file bsmaster.h.

◆ DPC_STATE_NONE

#define DPC_STATE_NONE   0x00

Definition at line 1154 of file bsmaster.h.

◆ DPC_STATE_TIMER

#define DPC_STATE_TIMER   0x30

Definition at line 1157 of file bsmaster.h.

◆ GEOM_AUTO

#define GEOM_AUTO   0xffffffff

Definition at line 1148 of file bsmaster.h.

◆ GEOM_MANUAL

#define GEOM_MANUAL   0x0003

Definition at line 1152 of file bsmaster.h.

◆ GEOM_ORIG

#define GEOM_ORIG   0x0002

Definition at line 1151 of file bsmaster.h.

◆ GEOM_STD

#define GEOM_STD   0x0000

Definition at line 1149 of file bsmaster.h.

◆ GEOM_UNIATA

#define GEOM_UNIATA   0x0001

Definition at line 1150 of file bsmaster.h.

◆ GET_CDEV

#define GET_CDEV (   Srb)    (Srb->TargetId)

Definition at line 1850 of file bsmaster.h.

◆ GET_CHANNEL

#define GET_CHANNEL (   Srb)    (Srb->PathId)

Definition at line 1847 of file bsmaster.h.

◆ GetDmaStatus

#define GetDmaStatus (   de,
  c 
)    (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)

Definition at line 1711 of file bsmaster.h.

◆ GetPciConfig1

#define GetPciConfig1 (   offs,
  op 
)
Value:
{ \
ScsiPortGetBusDataByOffset(HwDeviceExtension, \
SystemIoBusNumber, \
slotNumber, \
&op, \
offs, \
1); \
}
UINT op
Definition: effect.c:223

Definition at line 1620 of file bsmaster.h.

◆ GetPciConfig2

#define GetPciConfig2 (   offs,
  op 
)
Value:
{ \
ScsiPortGetBusDataByOffset(HwDeviceExtension, \
SystemIoBusNumber, \
slotNumber, \
&op, \
offs, \
2); \
}
UINT op
Definition: effect.c:223

Definition at line 1649 of file bsmaster.h.

◆ GetPciConfig4

#define GetPciConfig4 (   offs,
  op 
)
Value:
{ \
ScsiPortGetBusDataByOffset(HwDeviceExtension, \
SystemIoBusNumber, \
slotNumber, \
&op, \
offs, \
4); \
}
UINT op
Definition: effect.c:223

Definition at line 1678 of file bsmaster.h.

◆ HBAFLAGS_DMA_DISABLED

#define HBAFLAGS_DMA_DISABLED   0x01

Definition at line 1358 of file bsmaster.h.

◆ HBAFLAGS_DMA_DISABLED_LBA48

#define HBAFLAGS_DMA_DISABLED_LBA48   0x02

Definition at line 1359 of file bsmaster.h.

◆ IDX_AHCI_BOHC

#define IDX_AHCI_BOHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))

Definition at line 276 of file bsmaster.h.

◆ IDX_AHCI_CAP

#define IDX_AHCI_CAP   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))

Definition at line 270 of file bsmaster.h.

◆ IDX_AHCI_CAP2

#define IDX_AHCI_CAP2   (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))

Definition at line 275 of file bsmaster.h.

◆ IDX_AHCI_GHC

#define IDX_AHCI_GHC   (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))

Definition at line 271 of file bsmaster.h.

◆ IDX_AHCI_IS

#define IDX_AHCI_IS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))

Definition at line 272 of file bsmaster.h.

◆ IDX_AHCI_o_BlockCount

#define IDX_AHCI_o_BlockCount   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))

Definition at line 791 of file bsmaster.h.

◆ IDX_AHCI_o_BlockCountExp

#define IDX_AHCI_o_BlockCountExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))

Definition at line 797 of file bsmaster.h.

◆ IDX_AHCI_o_BlockNumber

#define IDX_AHCI_o_BlockNumber   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))

Definition at line 787 of file bsmaster.h.

◆ IDX_AHCI_o_BlockNumberExp

#define IDX_AHCI_o_BlockNumberExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))

Definition at line 794 of file bsmaster.h.

◆ IDX_AHCI_o_Command

#define IDX_AHCI_o_Command   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))

Definition at line 785 of file bsmaster.h.

◆ IDX_AHCI_o_Control

#define IDX_AHCI_o_Control   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))

Definition at line 792 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderHigh

#define IDX_AHCI_o_CylinderHigh   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))

Definition at line 789 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderHighExp

#define IDX_AHCI_o_CylinderHighExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))

Definition at line 796 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderLow

#define IDX_AHCI_o_CylinderLow   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))

Definition at line 788 of file bsmaster.h.

◆ IDX_AHCI_o_CylinderLowExp

#define IDX_AHCI_o_CylinderLowExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))

Definition at line 795 of file bsmaster.h.

◆ IDX_AHCI_o_DriveSelect

#define IDX_AHCI_o_DriveSelect   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))

Definition at line 790 of file bsmaster.h.

◆ IDX_AHCI_o_Feature

#define IDX_AHCI_o_Feature   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))

Definition at line 786 of file bsmaster.h.

◆ IDX_AHCI_o_FeatureExp

#define IDX_AHCI_o_FeatureExp   (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))

Definition at line 793 of file bsmaster.h.

◆ IDX_AHCI_P_ACT

#define IDX_AHCI_P_ACT   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))

Definition at line 693 of file bsmaster.h.

◆ IDX_AHCI_P_CI

#define IDX_AHCI_P_CI   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))

Definition at line 686 of file bsmaster.h.

◆ IDX_AHCI_P_CLB

#define IDX_AHCI_P_CLB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))

Definition at line 682 of file bsmaster.h.

◆ IDX_AHCI_P_CMD

#define IDX_AHCI_P_CMD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))

Definition at line 689 of file bsmaster.h.

◆ IDX_AHCI_P_FB

#define IDX_AHCI_P_FB   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))

Definition at line 683 of file bsmaster.h.

◆ IDX_AHCI_P_IE

#define IDX_AHCI_P_IE   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))

Definition at line 685 of file bsmaster.h.

◆ IDX_AHCI_P_IS

#define IDX_AHCI_P_IS   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))

Definition at line 684 of file bsmaster.h.

◆ IDX_AHCI_P_SControl

#define IDX_AHCI_P_SControl   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))

Definition at line 691 of file bsmaster.h.

◆ IDX_AHCI_P_SError

#define IDX_AHCI_P_SError   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))

Definition at line 692 of file bsmaster.h.

◆ IDX_AHCI_P_SIG

#define IDX_AHCI_P_SIG   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))

Definition at line 688 of file bsmaster.h.

◆ IDX_AHCI_P_SNTF

#define IDX_AHCI_P_SNTF   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))

Definition at line 695 of file bsmaster.h.

◆ IDX_AHCI_P_SStatus

#define IDX_AHCI_P_SStatus   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))

Definition at line 690 of file bsmaster.h.

◆ IDX_AHCI_P_TFD

#define IDX_AHCI_P_TFD   (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))

Definition at line 687 of file bsmaster.h.

◆ IDX_AHCI_PI

#define IDX_AHCI_PI   (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))

Definition at line 274 of file bsmaster.h.

◆ IDX_AHCI_VS

#define IDX_AHCI_VS   (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))

Definition at line 273 of file bsmaster.h.

◆ IDX_BM_Command

Definition at line 167 of file bsmaster.h.

◆ IDX_BM_DeviceSpecific0

#define IDX_BM_DeviceSpecific0   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)

Definition at line 168 of file bsmaster.h.

◆ IDX_BM_DeviceSpecific1

#define IDX_BM_DeviceSpecific1   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)

Definition at line 170 of file bsmaster.h.

◆ IDX_BM_IO

#define IDX_BM_IO   (IDX_IO2_o+IDX_IO2_o_SZ)

Definition at line 163 of file bsmaster.h.

◆ IDX_BM_IO_SZ

#define IDX_BM_IO_SZ   5

Definition at line 165 of file bsmaster.h.

◆ IDX_BM_PRD_Table

#define IDX_BM_PRD_Table   (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)

Definition at line 171 of file bsmaster.h.

◆ IDX_BM_Status

Definition at line 169 of file bsmaster.h.

◆ IDX_INDEXED_ADDR

#define IDX_INDEXED_ADDR   (0+IDX_INDEXED_IO)

Definition at line 466 of file bsmaster.h.

◆ IDX_INDEXED_DATA

#define IDX_INDEXED_DATA   (1+IDX_INDEXED_IO)

Definition at line 467 of file bsmaster.h.

◆ IDX_INDEXED_IO

#define IDX_INDEXED_IO   (IDX_SATA_IO+IDX_SATA_IO_SZ)

Definition at line 463 of file bsmaster.h.

◆ IDX_INDEXED_IO_SZ

#define IDX_INDEXED_IO_SZ   2

Definition at line 464 of file bsmaster.h.

◆ IDX_MAX_REG

Definition at line 469 of file bsmaster.h.

◆ IDX_SATA_IO

#define IDX_SATA_IO   (IDX_BM_IO+IDX_BM_IO_SZ)

Definition at line 453 of file bsmaster.h.

◆ IDX_SATA_IO_SZ

#define IDX_SATA_IO_SZ   5

Definition at line 455 of file bsmaster.h.

◆ IDX_SATA_SActive

#define IDX_SATA_SActive   (3+IDX_SATA_IO)

Definition at line 460 of file bsmaster.h.

◆ IDX_SATA_SControl

#define IDX_SATA_SControl   (2+IDX_SATA_IO)

Definition at line 459 of file bsmaster.h.

◆ IDX_SATA_SError

#define IDX_SATA_SError   (1+IDX_SATA_IO)

Definition at line 458 of file bsmaster.h.

◆ IDX_SATA_SNTF_PMN

#define IDX_SATA_SNTF_PMN   (4+IDX_SATA_IO)

Definition at line 461 of file bsmaster.h.

◆ IDX_SATA_SStatus

#define IDX_SATA_SStatus   (0+IDX_SATA_IO)

Definition at line 457 of file bsmaster.h.

◆ IO_FLOPPY_INT

#define IO_FLOPPY_INT   0x3F6 /* AltStatus inside Floppy I/O range */

Definition at line 81 of file bsmaster.h.

◆ IO_WD1

#define IO_WD1   0x1F0 /* Primary Fixed Disk Controller */

Definition at line 78 of file bsmaster.h.

◆ IO_WD2

#define IO_WD2   0x170 /* Secondary Fixed Disk Controller */

Definition at line 79 of file bsmaster.h.

◆ IP_PC98_BANK

#define IP_PC98_BANK   0x432

Definition at line 80 of file bsmaster.h.

◆ IsBusMaster

#define IsBusMaster (   pciData)
Value:
( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \
(PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/))
Definition: shell.h:41
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3262

Definition at line 853 of file bsmaster.h.

◆ IsMasterDev

#define IsMasterDev (   pciData)
Value:
( ((pciData)->ProgIf & 0x80) && \
#define PCI_IDE_PROGIF_NATIVE_ALL
Definition: bsmaster.h:859

Definition at line 861 of file bsmaster.h.

◆ MAX_RETRIES

#define MAX_RETRIES   6

Definition at line 72 of file bsmaster.h.

◆ MIN_REQ_TTL

#define MIN_REQ_TTL   4

Definition at line 866 of file bsmaster.h.

◆ PCI_ADDRESS_IOMASK

#define PCI_ADDRESS_IOMASK   0xfffffff0

Definition at line 83 of file bsmaster.h.

◆ PCI_DEV_CLASS_STORAGE

#define PCI_DEV_CLASS_STORAGE   0x01

Definition at line 117 of file bsmaster.h.

◆ PCI_DEV_PROGIF_AHCI_1_0

#define PCI_DEV_PROGIF_AHCI_1_0   0x01

Definition at line 124 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_ATA

#define PCI_DEV_SUBCLASS_ATA   0x05

Definition at line 121 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_IDE

#define PCI_DEV_SUBCLASS_IDE   0x01

Definition at line 119 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_RAID

#define PCI_DEV_SUBCLASS_RAID   0x04

Definition at line 120 of file bsmaster.h.

◆ PCI_DEV_SUBCLASS_SATA

#define PCI_DEV_SUBCLASS_SATA   0x06

Definition at line 122 of file bsmaster.h.

◆ PCI_IDE_PROGIF_NATIVE_1

#define PCI_IDE_PROGIF_NATIVE_1   0x01

Definition at line 857 of file bsmaster.h.

◆ PCI_IDE_PROGIF_NATIVE_2

#define PCI_IDE_PROGIF_NATIVE_2   0x04

Definition at line 858 of file bsmaster.h.

◆ PCI_IDE_PROGIF_NATIVE_ALL

#define PCI_IDE_PROGIF_NATIVE_ALL   0x05

Definition at line 859 of file bsmaster.h.

◆ PCIBUSNUM_NOT_SPECIFIED

#define PCIBUSNUM_NOT_SPECIFIED   (0xffffffffL)

Definition at line 1451 of file bsmaster.h.

◆ PCISLOTNUM_NOT_SPECIFIED

#define PCISLOTNUM_NOT_SPECIFIED   (0xffffffffL)

Definition at line 1452 of file bsmaster.h.

◆ REORDER_COST_DENIED

#define REORDER_COST_DENIED   (REORDER_COST_MAX - 3)

Definition at line 982 of file bsmaster.h.

◆ REORDER_COST_INTERSECT

#define REORDER_COST_INTERSECT   (REORDER_COST_MAX - 2)

Definition at line 981 of file bsmaster.h.

◆ REORDER_COST_MAX

#define REORDER_COST_MAX   ((DEF_I64(0x1) << 60) - 1)

Definition at line 979 of file bsmaster.h.

◆ REORDER_COST_RESELECT

#define REORDER_COST_RESELECT   (REORDER_COST_MAX/4)

Definition at line 983 of file bsmaster.h.

◆ REORDER_COST_SWITCH_RW_CD

#define REORDER_COST_SWITCH_RW_CD   (REORDER_COST_MAX/8)

Definition at line 985 of file bsmaster.h.

◆ REORDER_COST_SWITCH_RW_HDD

#define REORDER_COST_SWITCH_RW_HDD   (0)

Definition at line 989 of file bsmaster.h.

◆ REORDER_COST_TTL

#define REORDER_COST_TTL   (REORDER_COST_MAX - 1)

Definition at line 980 of file bsmaster.h.

◆ REORDER_MCOST_SEEK_BACK_CD

#define REORDER_MCOST_SEEK_BACK_CD   (16)

Definition at line 987 of file bsmaster.h.

◆ REORDER_MCOST_SEEK_BACK_HDD

#define REORDER_MCOST_SEEK_BACK_HDD   (2)

Definition at line 991 of file bsmaster.h.

◆ REORDER_MCOST_SWITCH_RW_CD

#define REORDER_MCOST_SWITCH_RW_CD   (0)

Definition at line 986 of file bsmaster.h.

◆ REORDER_MCOST_SWITCH_RW_HDD

#define REORDER_MCOST_SWITCH_RW_HDD   (4)

Definition at line 990 of file bsmaster.h.

◆ REQ_FLAG_DMA_DBUF

#define REQ_FLAG_DMA_DBUF   0x20

Definition at line 938 of file bsmaster.h.

◆ REQ_FLAG_DMA_DBUF_PRD

#define REQ_FLAG_DMA_DBUF_PRD   0x40

Definition at line 939 of file bsmaster.h.

◆ REQ_FLAG_DMA_OPERATION

#define REQ_FLAG_DMA_OPERATION   0x02

Definition at line 932 of file bsmaster.h.

◆ REQ_FLAG_FORCE_DOWNRATE

#define REQ_FLAG_FORCE_DOWNRATE   0x01

Definition at line 931 of file bsmaster.h.

◆ REQ_FLAG_FORCE_DOWNRATE_LBA48

#define REQ_FLAG_FORCE_DOWNRATE_LBA48   0x10

Definition at line 937 of file bsmaster.h.

◆ REQ_FLAG_LBA48

#define REQ_FLAG_LBA48   0x80

Definition at line 940 of file bsmaster.h.

◆ REQ_FLAG_READ

#define REQ_FLAG_READ   0x08

Definition at line 935 of file bsmaster.h.

◆ REQ_FLAG_REORDERABLE_CMD

#define REQ_FLAG_REORDERABLE_CMD   0x04

Definition at line 933 of file bsmaster.h.

◆ REQ_FLAG_RW_MASK

#define REQ_FLAG_RW_MASK   0x08

Definition at line 934 of file bsmaster.h.

◆ REQ_FLAG_WRITE

#define REQ_FLAG_WRITE   0x00

Definition at line 936 of file bsmaster.h.

◆ REQ_STATE_ATAPI_DO_NOTHING_INTR

#define REQ_STATE_ATAPI_DO_NOTHING_INTR   0x44

Definition at line 954 of file bsmaster.h.

◆ REQ_STATE_ATAPI_EXPECTING_CMD_INTR

#define REQ_STATE_ATAPI_EXPECTING_CMD_INTR   0x41

Definition at line 951 of file bsmaster.h.

◆ REQ_STATE_ATAPI_EXPECTING_DATA_INTR

#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR   0x42

Definition at line 952 of file bsmaster.h.

◆ REQ_STATE_ATAPI_EXPECTING_DATA_INTR2

#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2   0x43

Definition at line 953 of file bsmaster.h.

◆ REQ_STATE_DPC_COMPLETE_REQ

#define REQ_STATE_DPC_COMPLETE_REQ   0x53

Definition at line 962 of file bsmaster.h.

◆ REQ_STATE_DPC_INTR_REQ

#define REQ_STATE_DPC_INTR_REQ   0x51

Definition at line 960 of file bsmaster.h.

◆ REQ_STATE_DPC_RESET_REQ

#define REQ_STATE_DPC_RESET_REQ   0x52

Definition at line 961 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_BUSY

#define REQ_STATE_DPC_WAIT_BUSY   0x59

Definition at line 966 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_BUSY0

#define REQ_STATE_DPC_WAIT_BUSY0   0x57

Definition at line 964 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_BUSY1

#define REQ_STATE_DPC_WAIT_BUSY1   0x58

Definition at line 965 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_DRQ

#define REQ_STATE_DPC_WAIT_DRQ   0x5a

Definition at line 967 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_DRQ0

#define REQ_STATE_DPC_WAIT_DRQ0   0x5b

Definition at line 968 of file bsmaster.h.

◆ REQ_STATE_DPC_WAIT_DRQ_ERR

#define REQ_STATE_DPC_WAIT_DRQ_ERR   0x5c

Definition at line 969 of file bsmaster.h.

◆ REQ_STATE_EARLY_INTR

#define REQ_STATE_EARLY_INTR   0x48

Definition at line 956 of file bsmaster.h.

◆ REQ_STATE_EXPECTING_INTR

#define REQ_STATE_EXPECTING_INTR   0x40

Definition at line 950 of file bsmaster.h.

◆ REQ_STATE_NONE

#define REQ_STATE_NONE   0x00

Definition at line 943 of file bsmaster.h.

◆ REQ_STATE_PREPARE_TO_NEXT

#define REQ_STATE_PREPARE_TO_NEXT   0x21

Definition at line 947 of file bsmaster.h.

◆ REQ_STATE_PREPARE_TO_TRANSFER

#define REQ_STATE_PREPARE_TO_TRANSFER   0x20

Definition at line 946 of file bsmaster.h.

◆ REQ_STATE_PROCESSING_INTR

#define REQ_STATE_PROCESSING_INTR   0x50

Definition at line 958 of file bsmaster.h.

◆ REQ_STATE_QUEUED

#define REQ_STATE_QUEUED   0x10

Definition at line 944 of file bsmaster.h.

◆ REQ_STATE_READY_TO_TRANSFER

#define REQ_STATE_READY_TO_TRANSFER   0x30

Definition at line 948 of file bsmaster.h.

◆ REQ_STATE_TRANSFER_COMPLETE

#define REQ_STATE_TRANSFER_COMPLETE   0x7f

Definition at line 971 of file bsmaster.h.

◆ RETRY_PIO

#define RETRY_PIO   3

Definition at line 75 of file bsmaster.h.

◆ RETRY_UDMA2

#define RETRY_UDMA2   1

Definition at line 73 of file bsmaster.h.

◆ RETRY_WDMA

#define RETRY_WDMA   2

Definition at line 74 of file bsmaster.h.

◆ SATA_CMD_ICC_Active

#define SATA_CMD_ICC_Active   0x01

Definition at line 602 of file bsmaster.h.

◆ SATA_CMD_ICC_Idle

#define SATA_CMD_ICC_Idle   0x00

Definition at line 600 of file bsmaster.h.

◆ SATA_CMD_ICC_NoOp

#define SATA_CMD_ICC_NoOp   0x00

Definition at line 601 of file bsmaster.h.

◆ SATA_CMD_ICC_Partial

#define SATA_CMD_ICC_Partial   0x02

Definition at line 603 of file bsmaster.h.

◆ SATA_CMD_ICC_Slumber

#define SATA_CMD_ICC_Slumber   0x06

Definition at line 604 of file bsmaster.h.

◆ SATA_MAX_PM_UNITS

#define SATA_MAX_PM_UNITS   16

Definition at line 110 of file bsmaster.h.

◆ SControl_DET_Disable

#define SControl_DET_Disable   0x04

Definition at line 334 of file bsmaster.h.

◆ SControl_DET_DoNothing

#define SControl_DET_DoNothing   0x00

Definition at line 331 of file bsmaster.h.

◆ SControl_DET_Idle

#define SControl_DET_Idle   0x00

Definition at line 332 of file bsmaster.h.

◆ SControl_DET_Init

#define SControl_DET_Init   0x01

Definition at line 333 of file bsmaster.h.

◆ SControl_IPM_NoPartial

#define SControl_IPM_NoPartial   0x01

Definition at line 346 of file bsmaster.h.

◆ SControl_IPM_NoPartialSlumber

#define SControl_IPM_NoPartialSlumber   0x03

Definition at line 348 of file bsmaster.h.

◆ SControl_IPM_NoRestrict

#define SControl_IPM_NoRestrict   0x00

Definition at line 345 of file bsmaster.h.

◆ SControl_IPM_NoSlumber

#define SControl_IPM_NoSlumber   0x02

Definition at line 347 of file bsmaster.h.

◆ SControl_SPD_LimGen1

#define SControl_SPD_LimGen1   0x01

Definition at line 339 of file bsmaster.h.

◆ SControl_SPD_LimGen2

#define SControl_SPD_LimGen2   0x02

Definition at line 340 of file bsmaster.h.

◆ SControl_SPD_LimGen3

#define SControl_SPD_LimGen3   0x03

Definition at line 341 of file bsmaster.h.

◆ SControl_SPD_NoRestrict

#define SControl_SPD_NoRestrict   0x00

Definition at line 338 of file bsmaster.h.

◆ SetPciConfig1

#define SetPciConfig1 (   offs,
  op 
)
Value:
{ \
UCHAR _a = op; \
ScsiPortSetBusDataByOffset(HwDeviceExtension, \
SystemIoBusNumber, \
slotNumber, \
&_a, \
offs, \
1); \
}
UINT op
Definition: effect.c:223

Definition at line 1630 of file bsmaster.h.

◆ SetPciConfig2

#define SetPciConfig2 (   offs,
  op 
)
Value:
{ \
USHORT _a = op; \
ScsiPortSetBusDataByOffset(HwDeviceExtension, \
SystemIoBusNumber, \
slotNumber, \
&_a, \
offs, \
2); \
}
UINT op
Definition: effect.c:223

Definition at line 1659 of file bsmaster.h.

◆ SetPciConfig4

#define SetPciConfig4 (   offs,
  op 
)
Value:
{ \
ULONG _a = op; \
ScsiPortSetBusDataByOffset(HwDeviceExtension, \
SystemIoBusNumber, \
slotNumber, \
&_a, \
offs, \
4); \
}
UINT op
Definition: effect.c:223

Definition at line 1688 of file bsmaster.h.

◆ SStatus_DET_Dev_NoPhy

#define SStatus_DET_Dev_NoPhy   0x01

Definition at line 285 of file bsmaster.h.

◆ SStatus_DET_Dev_Ok

#define SStatus_DET_Dev_Ok   0x03

Definition at line 286 of file bsmaster.h.

◆ SStatus_DET_NoDev

#define SStatus_DET_NoDev   0x00

Definition at line 284 of file bsmaster.h.

◆ SStatus_DET_Offline

#define SStatus_DET_Offline   0x04

Definition at line 287 of file bsmaster.h.

◆ SStatus_IPM_Active

#define SStatus_IPM_Active   0x01

Definition at line 299 of file bsmaster.h.

◆ SStatus_IPM_NoDev

#define SStatus_IPM_NoDev   0x00

Definition at line 298 of file bsmaster.h.

◆ SStatus_IPM_Partial

#define SStatus_IPM_Partial   0x02

Definition at line 300 of file bsmaster.h.

◆ SStatus_IPM_Slumber

#define SStatus_IPM_Slumber   0x06

Definition at line 301 of file bsmaster.h.

◆ SStatus_SPD_Gen1

#define SStatus_SPD_Gen1   0x01

Definition at line 292 of file bsmaster.h.

◆ SStatus_SPD_Gen2

#define SStatus_SPD_Gen2   0x02

Definition at line 293 of file bsmaster.h.

◆ SStatus_SPD_Gen3

#define SStatus_SPD_Gen3   0x03

Definition at line 294 of file bsmaster.h.

◆ SStatus_SPD_NoDev

#define SStatus_SPD_NoDev   0x00

Definition at line 291 of file bsmaster.h.

◆ UNIATA_ALLOCATE_NEW_LUNS

#define UNIATA_ALLOCATE_NEW_LUNS   0x00

Definition at line 1398 of file bsmaster.h.

◆ VM_AUTO

#define VM_AUTO   0x00

Definition at line 1901 of file bsmaster.h.

◆ VM_BOCHS

#define VM_BOCHS   0x05

Definition at line 1906 of file bsmaster.h.

◆ VM_MAX_KNOWN

#define VM_MAX_KNOWN   VM_PCEM

Definition at line 1909 of file bsmaster.h.

◆ VM_NONE

#define VM_NONE   0x01

Definition at line 1902 of file bsmaster.h.

◆ VM_PCEM

#define VM_PCEM   0x06

Definition at line 1907 of file bsmaster.h.

◆ VM_QEMU

#define VM_QEMU   0x04

Definition at line 1905 of file bsmaster.h.

◆ VM_VBOX

#define VM_VBOX   0x02

Definition at line 1903 of file bsmaster.h.

◆ VM_VMWARE

#define VM_VMWARE   0x03

Definition at line 1904 of file bsmaster.h.

Typedef Documentation

◆ AHCI_ATA_H2D_FIS

◆ AHCI_IS_REG

typedef union _AHCI_IS_REG AHCI_IS_REG

◆ ATA_REQ

typedef union _ATA_REQ ATA_REQ

◆ BM_DMA_ENTRY

◆ BUSMASTER_CTX

◆ HW_CHANNEL

◆ HW_DEVICE_EXTENSION

◆ HW_LU_EXTENSION

◆ IDE_AHCI_CHANNEL_CTL_BLOCK

◆ IDE_AHCI_CMD

◆ IDE_AHCI_CMD_LIST

◆ IDE_AHCI_PORT_REGISTERS

◆ IDE_AHCI_PRD_ENTRY

◆ IDE_AHCI_RCV_FIS

◆ IDE_AHCI_REGISTERS

◆ IDE_BUSMASTER_REGISTERS

◆ IDE_SATA_REGISTERS

◆ IORES

typedef struct _IORES IORES

◆ ISR2_DEVICE_EXTENSION

◆ PAHCI_ATA_H2D_FIS

◆ PAHCI_IS_REG

typedef union _AHCI_IS_REG * PAHCI_IS_REG

◆ PATA_REQ

typedef union _ATA_REQ * PATA_REQ

◆ PBM_DMA_ENTRY

◆ PBUSMASTER_CTX

◆ PCIIDE_DEVICE_EXTENSION

Definition at line 1355 of file bsmaster.h.

◆ PHW_CHANNEL

◆ PHW_DEVICE_EXTENSION

◆ PHW_LU_EXTENSION

◆ PIDE_AHCI_CHANNEL_CTL_BLOCK

◆ PIDE_AHCI_CMD

◆ PIDE_AHCI_CMD_LIST

◆ PIDE_AHCI_PORT_REGISTERS

◆ PIDE_AHCI_PRD_ENTRY

◆ PIDE_AHCI_RCV_FIS

◆ PIDE_AHCI_REGISTERS

◆ PIDE_BUSMASTER_REGISTERS

◆ PIDE_SATA_REGISTERS

◆ PIORES

typedef struct _IORES * PIORES

◆ PISR2_DEVICE_EXTENSION

◆ PPCIIDE_DEVICE_EXTENSION

Definition at line 1356 of file bsmaster.h.

◆ PSATA_SCONTROL_REG

◆ PSATA_SERROR_REG

◆ PSATA_SSTATUS_REG

◆ SATA_SCONTROL_REG

◆ SATA_SERROR_REG

◆ SATA_SSTATUS_REG

Function Documentation

◆ AtapiChipInit()

BOOLEAN NTAPI AtapiChipInit ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  c 
)

Definition at line 1879 of file id_init.cpp.

1884 {
1885  PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1886  ULONG slotNumber = deviceExtension->slotNumber;
1887  ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1888  ULONG VendorID = deviceExtension->DevID & 0xffff;
1889  ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
1890  ULONG RevID = deviceExtension->RevID;
1891 // ULONG i;
1892 // BUSMASTER_CONTROLLER_INFORMATION_BASE* DevTypeInfo;
1893  ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1894  ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
1895  PHW_CHANNEL chan;
1896  UCHAR tmp8;
1897  USHORT tmp16;
1898  ULONG tmp32;
1899  ULONG c; // logical channel (for Compatible Mode controllers)
1900  BOOLEAN CheckCable = FALSE;
1902  //ULONG BaseIoAddress;
1903 
1904  switch(channel) {
1906  CheckCable = TRUE;
1907  /* FALLTHROUGH */
1908  case CHAN_NOT_SPECIFIED:
1910  GlobalInit = TRUE;
1911  break;
1912  default:
1913  //c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1914  c = channel;
1915  channel += deviceExtension->Channel;
1916  }
1917 
1918  KdPrint2((PRINT_PREFIX "AtapiChipInit: dev %#x, ph chan %d, c %d\n", DeviceNumber, channel, c));
1919 
1920  KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags));
1921  KdPrint2((PRINT_PREFIX "VendorID/DeviceID/Rev %#x/%#x/%#x\n", VendorID, DeviceID, RevID));
1922 
1923  if(deviceExtension->UnknownDev) {
1924  KdPrint2((PRINT_PREFIX " Unknown chip\n" ));
1925  //return TRUE;
1926  VendorID = 0xffffffff;
1927  }
1928 
1929 
1930  if(ChipFlags & UNIATA_AHCI) {
1931  /* if BAR(5) is IO it should point to SATA interface registers */
1932  if(!deviceExtension->BaseIoAHCI_0.Addr) {
1933  KdPrint2((PRINT_PREFIX " !BaseIoAHCI_0, exiting\n" ));
1934  return FALSE;
1935  }
1936  if(c == CHAN_NOT_SPECIFIED) {
1937  return UniataAhciInit(HwDeviceExtension);
1938  } else
1939  if(c<deviceExtension->NumberChannels) {
1940  KdPrint2((PRINT_PREFIX " AHCI single channel init\n" ));
1941  UniataAhciReset(HwDeviceExtension, c);
1942  return TRUE;
1943  } else {
1944  KdPrint2((PRINT_PREFIX " AHCI non-existent channel\n" ));
1945  return FALSE;
1946  }
1947  }
1948 
1949  if((WinVer_Id() > WinVer_NT) &&
1950  GlobalInit &&
1951  deviceExtension->MasterDev) {
1952  PCI_COMMON_CONFIG pciData;
1953  ULONG busDataRead;
1954 
1955  KdPrint2((PRINT_PREFIX " re-enable IO resources of MasterDev\n" ));
1956 
1957  busDataRead = HalGetBusData
1958  //ScsiPortGetBusData
1959  (
1960  //HwDeviceExtension,
1961  PCIConfiguration, SystemIoBusNumber, slotNumber,
1962  &pciData, PCI_COMMON_HDR_LENGTH);
1963  if(busDataRead == PCI_COMMON_HDR_LENGTH) {
1964  UniataEnableIoPCI(SystemIoBusNumber, slotNumber, &pciData);
1965  } else {
1966  KdPrint2((PRINT_PREFIX " re-enable IO resources of MasterDev FAILED\n" ));
1967  }
1968  }
1969 
1970  switch(VendorID) {
1971 // case ATA_ACARD_ID:
1972 // break;
1973  case ATA_ACER_LABS_ID:
1974  if(ChipFlags & UNIATA_SATA) {
1975  if(c == CHAN_NOT_SPECIFIED) {
1976  for(c=0; c<deviceExtension->NumberChannels; c++) {
1977  chan = &deviceExtension->chan[c];
1979  /* the southbridge might need the data corruption fix */
1980  if(RevID == 0xc2 || RevID == 0xc3) {
1981  AtapiAliSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
1982  SystemIoBusNumber, slotNumber, c);
1983  }
1984  }
1985  /* enable PCI interrupt */
1987  }
1988  } else
1989  if(ChipFlags & ALINEW) {
1990  if(c == CHAN_NOT_SPECIFIED) {
1991  /* use device interrupt as byte count end */
1992  ChangePciConfig1(0x4a, (a | 0x20));
1993  /* enable cable detection and UDMA support on newer chips, rev < 0xc7 */
1994  if(RevID < 0xc7) {
1995  ChangePciConfig1(0x4b, (a | 0x09));
1996  }
1997 
1998  /* enable ATAPI UDMA mode */
1999  ChangePciConfig1(0x53, (a | (RevID >= 0xc7 ? 0x03 : 0x01)));
2000 
2001  } else {
2002  // check 80-pin cable
2003  generic_cable80(deviceExtension, channel, 0x4a, 0);
2004  }
2005  } else {
2006  if(c == CHAN_NOT_SPECIFIED) {
2007  /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
2008  ChangePciConfig1(0x53, (a | 0x03));
2009  } else {
2010  // ATAPI DMA R/O
2011  deviceExtension->chan[c].ChannelCtrlFlags |= CTRFLAGS_DMA_RO;
2012  }
2013  }
2014  break;
2015  case ATA_AMD_ID:
2016  if(c == CHAN_NOT_SPECIFIED) {
2017  /* set prefetch, postwrite */
2018  if(ChipFlags & AMDBUG) {
2019  ChangePciConfig1(0x41, (a & 0x0f));
2020  } else {
2021  ChangePciConfig1(0x41, (a | 0xf0));
2022  }
2023  }
2024  if(deviceExtension->MaxTransferMode < ATA_UDMA2)
2025  break;
2026  // check 80-pin cable
2027  if(!(ChipFlags & UNIATA_NO80CHK)) {
2028  if(c == CHAN_NOT_SPECIFIED) {
2029  // do nothing
2030  } else {
2031  generic_cable80(deviceExtension, channel, 0x42, 0);
2032  }
2033  }
2034  break;
2035  case ATA_HIGHPOINT_ID:
2036 
2037  if(c == CHAN_NOT_SPECIFIED) {
2038 
2039  if(ChipFlags & HPTOLD) {
2040  /* turn off interrupt prediction */
2041  ChangePciConfig1(0x51, (a & ~0x80));
2042  } else {
2043  /* turn off interrupt prediction */
2044  ChangePciConfig1(0x51, (a & ~0x03));
2045  ChangePciConfig1(0x55, (a & ~0x03));
2046  /* turn on interrupts */
2047  ChangePciConfig1(0x5a, (a & ~0x10));
2048  /* set clocks etc */
2049  if(ChipType < HPT372) {
2050  SetPciConfig1(0x5b, 0x22);
2051  } else {
2052  ChangePciConfig1(0x5b, ((a & 0x01) | 0x20));
2053  }
2054  }
2055 
2056  } else {
2057  // check 80-pin cable
2058  chan = &deviceExtension->chan[c];
2059  if(!hpt_cable80(deviceExtension, channel)) {
2060  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2061  }
2062  }
2063  break;
2064  case ATA_INTEL_ID: {
2065  BOOLEAN IsPata;
2066  USHORT reg54;
2067  if(ChipFlags & UNIATA_SATA) {
2068 
2069  KdPrint2((PRINT_PREFIX "Intel SATA\n"));
2070  if(ChipFlags & UNIATA_AHCI) {
2071  KdPrint2((PRINT_PREFIX "Do nothing for AHCI\n"));
2072  /* enable PCI interrupt */
2074  break;
2075  }
2076  if(c == CHAN_NOT_SPECIFIED) {
2077  KdPrint2((PRINT_PREFIX "Base init\n"));
2078  /* force all ports active "the legacy way" */
2079  ChangePciConfig2(0x92, (a | 0x0f));
2080 
2081  if(deviceExtension->BaseIoAddressSATA_0.Addr && (ChipFlags & ICH7)) {
2082  /* Set SCRAE bit to enable registers access. */
2083  ChangePciConfig4(0x94, (a | (1 << 9)));
2084  /* Set Ports Implemented register bits. */
2085  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c,
2086  AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c) | 0x0f);
2087  }
2088  /* enable PCI interrupt */
2090 
2091  } else {
2092 
2093  KdPrint2((PRINT_PREFIX "channel init\n"));
2094 
2095  GetPciConfig1(0x90, tmp8);
2096  KdPrint2((PRINT_PREFIX "reg 90: %x, init lun map\n", tmp8));
2097 
2098  KdPrint2((PRINT_PREFIX "chan %d\n", c));
2099  chan = &deviceExtension->chan[c];
2100  IsPata = FALSE;
2101  if(ChipFlags & ICH5) {
2102  KdPrint2((PRINT_PREFIX "ICH5\n"));
2103  if ((tmp8 & 0x04) == 0) {
2105  chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ^ c;
2106  chan->lun[1]->SATA_lun_map = 0;
2107  } else if ((tmp8 & 0x02) == 0) {
2108  if(c == 0) {
2109  chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2110  chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2111  } else {
2112  IsPata = TRUE;
2113  //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2114  }
2115  } else if ((tmp8 & 0x02) != 0) {
2116  if(c == 1) {
2117  chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2118  chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2119  } else {
2120  IsPata = TRUE;
2121  //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2122  }
2123  }
2124  } else
2125  if(ChipFlags & I6CH2) {
2126  KdPrint2((PRINT_PREFIX "I6CH2\n"));
2128  chan->lun[0]->SATA_lun_map = c ? 0 : 1;
2129  chan->lun[1]->SATA_lun_map = 0;
2130  } else {
2131  KdPrint2((PRINT_PREFIX "other Intel\n"));
2132  switch(tmp8 & 0x03) {
2133  case 0:
2134  KdPrint2((PRINT_PREFIX "0 -> %d/%d\n", 0+c, 2+c));
2135  chan->lun[0]->SATA_lun_map = 0+c;
2136  chan->lun[1]->SATA_lun_map = 2+c;
2137  break;
2138  case 2:
2139  if(c==0) {
2140  KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 0, 2));
2141  chan->lun[0]->SATA_lun_map = 0;
2142  chan->lun[1]->SATA_lun_map = 2;
2143  } else {
2144  // PATA
2145  KdPrint2((PRINT_PREFIX "PATA\n"));
2146  IsPata = TRUE;
2147  }
2148  break;
2149  case 1:
2150  if(c==1) {
2151  KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 1, 3));
2152  chan->lun[0]->SATA_lun_map = 1;
2153  chan->lun[1]->SATA_lun_map = 3;
2154  } else {
2155  // PATA
2156  KdPrint2((PRINT_PREFIX "PATA\n"));
2157  IsPata = TRUE;
2158  }
2159  break;
2160  }
2161  }
2162 
2163  if(IsPata) {
2164  KdPrint2((PRINT_PREFIX "PATA part\n"));
2165  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2166  }
2167 
2168  if(ChipType == INTEL_IDX) {
2169  KdPrint2((PRINT_PREFIX "io indexed\n"));
2170  //for(c=0; c<deviceExtension->NumberChannels; c++) {
2171  chan = &deviceExtension->chan[c];
2172  UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
2173  if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
2174  UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 1);
2175  }
2176  //}
2177  }
2178  }
2179 
2180  break;
2181  }
2182  if(deviceExtension->MaxTransferMode <= ATA_UDMA2)
2183  break;
2184  // check 80-pin cable
2185  if(c == CHAN_NOT_SPECIFIED) {
2186  // do nothing
2187  } else {
2188  chan = &deviceExtension->chan[c];
2189  GetPciConfig2(0x54, reg54);
2190  KdPrint2((PRINT_PREFIX " intel 80-pin check (reg54=%x)\n", reg54));
2191  if(deviceExtension->HwFlags & UNIATA_NO80CHK) {
2192  KdPrint2((PRINT_PREFIX " No check (administrative)\n"));
2193  if(chan->Force80pin) {
2194  KdPrint2((PRINT_PREFIX "Force80pin\n"));
2195  }
2196  } else
2197  if(reg54 == 0x0000 || reg54 == 0xffff) {
2198  KdPrint2((PRINT_PREFIX " check failed (not supported)\n"));
2199  } else
2200  if( ((reg54 >> (channel*2)) & 30) == 0) {
2201  KdPrint2((PRINT_PREFIX " intel 40-pin\n"));
2202  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2203  }
2204  }
2205  break; }
2206  case ATA_NVIDIA_ID: {
2207  if(ChipFlags & UNIATA_SATA) {
2208  if(c == CHAN_NOT_SPECIFIED) {
2209  ULONG offs = (ChipFlags & NV4OFF) ? 0x0440 : 0x0010;
2210  /* enable control access */
2211  ChangePciConfig1(0x50, (a | 0x04));
2212  /* MCP55 seems to need some time to allow r_res2 read. */
2213  AtapiStallExecution(10);
2214  KdPrint2((PRINT_PREFIX "BaseIoAddressSATA_0=%x\n", deviceExtension->BaseIoAddressSATA_0.Addr));
2215  if(ChipFlags & NVQ) {
2216  KdPrint2((PRINT_PREFIX "Disable NCQ\n"));
2217  tmp32 = AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400);
2218  KdPrint2((PRINT_PREFIX "MODE=%#x\n", tmp32));
2219  if(tmp32 & ~0xfffffff9) {
2220  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400,
2221  tmp32 & 0xfffffff9);
2222  }
2223  ChipFlags &= ~NVQ;
2224  deviceExtension->HwFlags = ChipFlags;
2225  }
2226  if(ChipFlags & NVQ) {
2227  /* disable ECO 398 */
2228  ChangePciConfig1(0x7f, (a & ~(1 << 7)));
2229 
2230  KdPrint2((PRINT_PREFIX "Enable NCQ\n"));
2231  /* enable NCQ support */
2232  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400,
2233  tmp32 | ~0x00000006);
2234 
2235  /* clear interrupt status */
2236  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0x00ff00ff);
2237  /* enable device and PHY state change interrupts */
2238  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+4, 0x000d000d);
2239  } else {
2240  /* clear interrupt status */
2241  AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0xff);
2242  /* enable device and PHY state change interrupts */
2243  AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+1, 0xdd);
2244  }
2245  /* enable PCI interrupt */
2247  } else {
2248  //UniataSataPhyEnable(HwDeviceExtension, c);
2249  }
2250  } else {
2251  //UCHAR reg52;
2252 
2253  if(c == CHAN_NOT_SPECIFIED) {
2254  /* set prefetch, postwrite */
2255  ChangePciConfig1(0x51, (a & 0x0f));
2256  } else {
2257  // check 80-pin cable
2258  generic_cable80(deviceExtension, channel, 0x52, 1);
2259 /* chan = &deviceExtension->chan[c];
2260  GetPciConfig1(0x52, reg52);
2261  if( !((reg52 >> (channel*2)) & 0x01)) {
2262  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2263  }*/
2264  }
2265  }
2266  break; }
2267  case ATA_PROMISE_ID: {
2268  USHORT Reg50;
2269  switch(ChipType) {
2270  case PRNEW:
2271  /* setup clocks */
2272  if(c == CHAN_NOT_SPECIFIED) {
2273 // ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
2274  AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
2275  AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) | 0x0a );
2276  }
2277  /* FALLTHROUGH */
2278  case PROLD:
2279  /* enable burst mode */
2280 // ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
2281  if(c == CHAN_NOT_SPECIFIED) {
2282  AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f,
2283  AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f) | 0x01 );
2284  } else {
2285  // check 80-pin cable
2286  chan = &deviceExtension->chan[c];
2287  GetPciConfig2(0x50, Reg50);
2288  if(Reg50 & (1 << (channel+10))) {
2289  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2290  }
2291  }
2292  break;
2293  case PRTX:
2294  if(c == CHAN_NOT_SPECIFIED) {
2295  // do nothing
2296  } else {
2297  // check 80-pin cable
2298  chan = &deviceExtension->chan[c];
2300  if(AtapiReadPort1(chan, IDX_BM_DeviceSpecific1) & 0x04) {
2301  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2302  }
2303  }
2304  break;
2305  case PRMIO:
2306  if(c == CHAN_NOT_SPECIFIED) {
2307  /* clear SATA status and unmask interrupts */
2308  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),
2309  (ChipFlags & PRG2) ? 0x60 : 0x6c, 0x000000ff);
2310  if(ChipFlags & UNIATA_SATA) {
2311  /* enable "long burst length" on gen2 chips */
2312  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44,
2313  AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44) | 0x2000);
2314  }
2315  } else {
2316  chan = &deviceExtension->chan[c];
2318  (AtapiReadPort4(chan, IDX_BM_Command) & ~0x00000f8f) | channel );
2319  AtapiWritePort4(chan, IDX_BM_DeviceSpecific0, 0x00000001);
2320  // check 80-pin cable
2321  if(chan->MaxTransferMode < ATA_SA150 &&
2322  (AtapiReadPort4(chan, IDX_BM_Command) & 0x01000000)) {
2323  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2324  }
2325  }
2326  break;
2327  }
2328  break; }
2329  case ATA_SERVERWORKS_ID:
2330  if(c == CHAN_NOT_SPECIFIED) {
2331  if(ChipType == SWKS33) {
2332  AtapiRosbSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
2333  SystemIoBusNumber, slotNumber);
2334  } else {
2335  ChangePciConfig1(0x5a, ((a & ~0x40) | ((ChipType == SWKS100) ? 0x03 : 0x02)));
2336  }
2337  }
2338  break;
2339  case ATA_ATI_ID:
2340  if(ChipType == SIIMIO) {
2341  KdPrint2((PRINT_PREFIX "ATI New\n"));
2342  // fall to SiI
2343  } else {
2344  KdPrint2((PRINT_PREFIX "ATI\n"));
2345  break;
2346  }
2347  /* FALLTHROUGH */
2348  case ATA_SILICON_IMAGE_ID:
2349  /* if(ChipFlags & SIIENINTR) {
2350  SetPciConfig1(0x71, 0x01);
2351  }*/
2352  switch(ChipType) {
2353  case SIIMIO: {
2354 
2355  KdPrint2((PRINT_PREFIX "SII\n"));
2356  USHORT Reg79;
2357 
2358  if(c == CHAN_NOT_SPECIFIED) {
2359  if(ChipFlags & SIISETCLK) {
2360  KdPrint2((PRINT_PREFIX "SIISETCLK\n"));
2361  GetPciConfig1(0x8a, tmp8);
2362  if ((tmp8 & 0x30) != 0x10)
2363  ChangePciConfig1(0x8a, (a & 0xcf) | 0x10);
2364  GetPciConfig1(0x8a, tmp8);
2365  if ((tmp8 & 0x30) != 0x10) {
2366  KdPrint2((PRINT_PREFIX "Sil 0680 could not set ATA133 clock\n"));
2367  deviceExtension->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2368  }
2369  }
2370  }
2371  if(deviceExtension->MaxTransferMode < ATA_SA150) {
2372  // check 80-pin cable
2373  if(c == CHAN_NOT_SPECIFIED) {
2374  // do nothing
2375  } else {
2376  KdPrint2((PRINT_PREFIX "Check UDMA66 cable\n"));
2377  chan = &deviceExtension->chan[c];
2378  GetPciConfig2(0x79, Reg79);
2379  if(Reg79 & (channel ? 0x02 : 0x01)) {
2380  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2381  }
2382  }
2383  } else {
2384  ULONG unit01 = (c & 1);
2385  ULONG unit10 = (c & 2);
2386  /* enable/disable PHY state change interrupt */
2387  if(c == CHAN_NOT_SPECIFIED) {
2388  for(c=0; c<deviceExtension->NumberChannels; c++) {
2389  unit01 = (c & 1);
2390  unit10 = (c & 2);
2391  if(ChipFlags & SIINOSATAIRQ) {
2392  KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c));
2393  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0);
2394  }
2395  }
2396  } else {
2397  if(ChipFlags & SIINOSATAIRQ) {
2398  KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c));
2399  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0);
2400  } else {
2401  KdPrint2((PRINT_PREFIX "Enable SATA intr on c=%x\n", c));
2402  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
2403  }
2404  }
2405  }
2406  if(c == CHAN_NOT_SPECIFIED) {
2407  /* enable interrupt as BIOS might not */
2408  ChangePciConfig1(0x8a, (a & 0x3f));
2409  // Enable 3rd and 4th channels
2410  if (ChipFlags & SII4CH) {
2411  KdPrint2((PRINT_PREFIX "SII4CH\n"));
2412  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0200, 0x00000002);
2413  }
2414  } else {
2415  chan = &deviceExtension->chan[c];
2416  /* dont block interrupts */
2417  //ChangePciConfig4(0x48, (a & ~0x03c00000));
2418  /*tmp32 =*/ AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
2419  AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48, (1 << 22) << c);
2420  // flush
2421  /*tmp32 =*/ AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
2422 
2423  /* Initialize FIFO PCI bus arbitration */
2424  GetPciConfig1(offsetof(PCI_COMMON_CONFIG, CacheLineSize), tmp8);
2425  if(tmp8) {
2426  KdPrint2((PRINT_PREFIX "SII: CacheLine=%d\n", tmp8));
2427  tmp8 = (tmp8/8)+1;
2428  AtapiWritePort2(chan, IDX_BM_DeviceSpecific1, ((USHORT)tmp8) << 8 | tmp8);
2429  } else {
2430  KdPrint2((PRINT_PREFIX "SII: CacheLine=0 !!!\n"));
2431  }
2432  }
2433  break; }
2434 
2435  case SIICMD: {
2436 
2437  KdPrint2((PRINT_PREFIX "SII_CMD\n"));
2438  if(c == CHAN_NOT_SPECIFIED) {
2439  /* Setup interrupts. */
2440  SetPciConfig1(0x71, 0x01);
2441 
2442  /* GetPciConfig1(0x8a, tmp8);
2443  tmp8 &= ~(0x30);
2444  SetPciConfig1(0x71, tmp8);*/
2445 
2446  /* Use MEMORY READ LINE for reads.
2447  * NOTE: Although not mentioned in the PCI0646U specs,
2448  * these bits are write only and won't be read
2449  * back as set or not. The PCI0646U2 specs clarify
2450  * this point.
2451  */
2452  /* tmp8 |= 0x02;
2453  SetPciConfig1(0x71, tmp8);
2454  */
2455  /* Set reasonable active/recovery/address-setup values. */
2456  SetPciConfig1(0x53, 0x40);
2457  SetPciConfig1(0x54, 0x3f);
2458  SetPciConfig1(0x55, 0x40);
2459  SetPciConfig1(0x56, 0x3f);
2460  SetPciConfig1(0x57, 0x1c);
2461  SetPciConfig1(0x58, 0x3f);
2462  SetPciConfig1(0x5b, 0x3f);
2463  }
2464 
2465  break; }
2466  case ATI700:
2467  KdPrint2((PRINT_PREFIX "ATI700\n"));
2468  if(c == 0 && !(ChipFlags & UNIATA_AHCI)) {
2469  KdPrint2((PRINT_PREFIX "IXP700 PATA\n"));
2470  chan = &deviceExtension->chan[c];
2471  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2472  }
2473  break;
2474  } /* switch(ChipType) */
2475  break;
2476  case ATA_SIS_ID:
2477  if(c == CHAN_NOT_SPECIFIED) {
2478  switch(ChipType) {
2479  case SIS33:
2480  break;
2481  case SIS66:
2482  case SIS100OLD:
2483  ChangePciConfig1(0x52, (a & ~0x04));
2484  break;
2485  case SIS100NEW:
2486  case SIS133OLD:
2487  ChangePciConfig1(0x49, (a & ~0x01));
2488  break;
2489  case SIS133NEW:
2490  ChangePciConfig2(0x50, (a | 0x0008));
2491  ChangePciConfig2(0x52, (a | 0x0008));
2492  break;
2493  case SISSATA:
2494  ChangePciConfig2(0x04, (a & ~0x0400));
2495  break;
2496  }
2497  }
2498  if(deviceExtension->HwFlags & UNIATA_SATA) {
2499  // do nothing for SATA
2500  } else
2501  if(ChipType == SIS133NEW) {
2502  // check 80-pin cable
2503  if(c == CHAN_NOT_SPECIFIED) {
2504  // do nothing
2505  } else {
2506  chan = &deviceExtension->chan[c];
2507  GetPciConfig2(channel ? 0x52 : 0x50, tmp16);
2508  if(tmp16 & 0x8000) {
2509  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2510  }
2511  }
2512  } else {
2513  // check 80-pin cable
2514  if(c == CHAN_NOT_SPECIFIED) {
2515  // do nothing
2516  } else {
2517  chan = &deviceExtension->chan[c];
2518  GetPciConfig1(48, tmp8);
2519  if(tmp8 & (0x10 << channel)) {
2520  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2521  }
2522  }
2523  }
2524  break;
2525  case ATA_VIA_ID:
2526 
2527 /* if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI | VIASATA) {
2528  break;
2529  }*/
2530  if(c == CHAN_NOT_SPECIFIED) {
2531  /* prepare for ATA-66 on the 82C686a and 82C596b */
2532  if(ChipFlags & VIACLK) {
2533  ChangePciConfig4(0x50, (a | 0x030b030b));
2534  }
2535  // no init for SATA
2536  if(ChipFlags & (UNIATA_SATA | VIASATA)) {
2537  /* enable PCI interrupt */
2539 
2540  /*
2541  * vt6420/1 has problems talking to some drives. The following
2542  * is based on the fix from Joseph Chan <JosephChan@via.com.tw>.
2543  *
2544  * When host issues HOLD, device may send up to 20DW of data
2545  * before acknowledging it with HOLDA and the host should be
2546  * able to buffer them in FIFO. Unfortunately, some WD drives
2547  * send upto 40DW before acknowledging HOLD and, in the
2548  * default configuration, this ends up overflowing vt6421's
2549  * FIFO, making the controller abort the transaction with
2550  * R_ERR.
2551  *
2552  * Rx52[2] is the internal 128DW FIFO Flow control watermark
2553  * adjusting mechanism enable bit and the default value 0
2554  * means host will issue HOLD to device when the left FIFO
2555  * size goes below 32DW. Setting it to 1 makes the watermark
2556  * 64DW.
2557  *
2558  * http://www.reactos.org/bugzilla/show_bug.cgi?id=6500
2559  */
2560 
2561  if(DeviceID == 0x3149 || DeviceID == 0x3249) { //vt6420 or vt6421
2562  KdPrint2((PRINT_PREFIX "VIA 642x FIFO\n"));
2563  ChangePciConfig1(0x52, a | (1 << 2));
2564  }
2565 
2566  break;
2567  }
2568 
2569  /* the southbridge might need the data corruption fix */
2570  if(ChipFlags & VIABUG) {
2571  AtapiViaSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
2572  SystemIoBusNumber, slotNumber);
2573  }
2574  /* set prefetch, postwrite */
2575  if(ChipType != VIA133) {
2576  ChangePciConfig1(0x41, (a | 0xf0));
2577  }
2578 
2579  /* set fifo configuration half'n'half */
2580  ChangePciConfig1(0x43, ((a & ((ChipFlags & VIAPRQ) ? 0x80 : 0x90)) | 0x2a));
2581 
2582  /* set status register read retry */
2583  ChangePciConfig1(0x44, (a | 0x08));
2584 
2585  /* set DMA read & end-of-sector fifo flush */
2586  ChangePciConfig1(0x46, ((a & 0x0c) | 0xf0));
2587 
2588  /* set sector size */
2589  SetPciConfig2(0x60, DEV_BSIZE);
2590  SetPciConfig2(0x68, DEV_BSIZE);
2591  } else {
2592 
2593  chan = &deviceExtension->chan[c];
2594  // no init for SATA
2595  if(ChipFlags & (UNIATA_SATA | VIASATA)) {
2596  if((ChipFlags & VIABAR) && (c >= 2)) {
2597  // this is PATA channel
2598  chan->MaxTransferMode = ATA_UDMA5;
2599  break;
2600  }
2601  UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
2602  break;
2603  }
2604 /*
2605  // check 80-pin cable
2606  if(!via_cable80(deviceExtension, channel)) {
2607  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2608  }
2609 */
2610  }
2611 
2612  break;
2613 
2614  case ATA_ITE_ID:
2615  if(ChipType == ITE_33 || ChipType == ITE_133_NEW) {
2616  break;
2617  }
2618  if(ChipType == ITE_133) {
2619  if(c == CHAN_NOT_SPECIFIED) {
2620  /* set PCI mode and 66Mhz reference clock */
2621  ChangePciConfig1(0x50, a & ~0x83);
2622 
2623  /* set default active & recover timings */
2624  SetPciConfig1(0x54, 0x31);
2625  SetPciConfig1(0x56, 0x31);
2626  } else {
2627  // check 80-pin cable
2628  GetPciConfig2(0x40, tmp16);
2629  chan = &deviceExtension->chan[c];
2630  if(!(tmp16 & (channel ? 0x08 : 0x04))) {
2631  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2632  }
2633  }
2634  } else
2635  if(ChipType == ITE_133_NEW) {
2636  }
2637  break;
2638  case ATA_CYRIX_ID:
2639  KdPrint2((PRINT_PREFIX "Cyrix\n"));
2640  if(ChipType == CYRIX_OLD) {
2641  if(c == CHAN_NOT_SPECIFIED) {
2642  GetPciConfig1(0x60, tmp8);
2643  if(!(tmp8 & 0x40)) {
2644  KdPrint2((PRINT_PREFIX "Enable DMA\n"));
2645  tmp8 |= 0x40;
2646  SetPciConfig1(0x60, tmp8);
2647  }
2648  }
2649  }
2650  break;
2651  case ATA_JMICRON_ID:
2652  /* New JMicron PATA controllers */
2653  if(deviceExtension->DevID == ATA_JMB361 ||
2654  deviceExtension->DevID == ATA_JMB363 ||
2655  deviceExtension->DevID == ATA_JMB365 ||
2656  deviceExtension->DevID == ATA_JMB366 ||
2657  deviceExtension->DevID == ATA_JMB368) {
2658  KdPrint2((PRINT_PREFIX "JMicron\n"));
2659 
2660  ULONG c_swp = 0;
2661  ULONG reg40, reg80;
2662 
2663  GetPciConfig4(0x40, reg40);
2664  KdPrint2((PRINT_PREFIX "reg 40: %x\n", reg40));
2665 
2666  c_swp = (reg40 & (1<<22)) ? 1 : 0; // 1=swap, 0=keep
2667  KdPrint2((PRINT_PREFIX "c_swp: %x\n", c_swp));
2668 
2669  GetPciConfig4(0x80, reg80);
2670  KdPrint2((PRINT_PREFIX "reg 80: %x\n", reg80));
2671 
2672  if(c == CHAN_NOT_SPECIFIED) {
2673  UCHAR P1mode;
2674 
2675  P1mode = (reg80 & (1<<24)) ? ATA_UDMA6 : ATA_SA300;
2676  KdPrint2((PRINT_PREFIX "p1 mode: %x\n", P1mode));
2677 
2678  if(reg40 & (1 << 23)) {
2679  KdPrint2((PRINT_PREFIX "SATA+PATA0\n"));
2680  deviceExtension->chan[0 ^ c_swp].MaxTransferMode = P1mode;
2681  deviceExtension->chan[1 ^ c_swp].MaxTransferMode = ATA_UDMA6;
2682  deviceExtension->chan[1 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2683 
2684  } else {
2685  KdPrint2((PRINT_PREFIX "SATA+SATA\n"));
2686  deviceExtension->chan[0 ^ c_swp].MaxTransferMode = P1mode;
2687  //deviceExtension->chan[0 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2688  deviceExtension->chan[1 ^ c_swp].MaxTransferMode = ATA_SA300;
2689  deviceExtension->chan[1 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2690  }
2691 
2692  } else {
2693  /*
2694  deviceExtension->chan[0 ^ c_swp].lun[0]->SATA_lun_map =
2695  deviceExtension->chan[0 ^ c_swp].lun[0]->SATA_lun_map = 0;
2696  deviceExtension->chan[1 ^ c_swp].lun[0]->SATA_lun_map =
2697  deviceExtension->chan[1 ^ c_swp].lun[0]->SATA_lun_map = 1;
2698  */
2699  KdPrint2((PRINT_PREFIX "chan %d\n", c));
2700  chan = &deviceExtension->chan[c];
2701 
2702  UCHAR ph_channel = (UCHAR)(c ^ c_swp);
2703  //c_swp = chan->lun[0]->SATA_lun_map;
2704  if(chan->MaxTransferMode >= ATA_SA150) {
2705  KdPrint2((PRINT_PREFIX "SATA, map -> %x\n", ph_channel));
2706  } else {
2707  KdPrint2((PRINT_PREFIX "PATA, map -> %x\n", ph_channel));
2708  if(!ph_channel) {
2709  if(!(reg40 & (1<<5))) {
2710  KdPrint2((PRINT_PREFIX "disabled\n", ph_channel));
2711  } else
2712  if(!(reg40 & (1<<3))) {
2713  KdPrint2((PRINT_PREFIX "40-pin\n"));
2714  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2715  }
2716  } else {
2717  if(!(reg80 & (1<<21))) {
2718  KdPrint2((PRINT_PREFIX "disabled\n", ph_channel));
2719  } else
2720  if(!(reg80 & (1<<19))) {
2721  KdPrint2((PRINT_PREFIX "40-pin\n"));
2722  chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2723  }
2724  }
2725  }
2726  }
2727 
2728  }
2729  break;
2730  default:
2731  if(c != CHAN_NOT_SPECIFIED) {
2732  // We don't know how to check for 80-pin cable on unknown controllers.
2733  // Later we shall check bit in IDENTIFY structure, but it is not reliable way.
2734  // So, leave this flag to use as hint in error recovery procedures
2735  KdPrint2((PRINT_PREFIX "UNIATA_NO80CHK\n"));
2736  deviceExtension->HwFlags |= UNIATA_NO80CHK;
2737  }
2738  break;
2739  }
2740 
2741  // In all places separate channels are inited after common controller init
2742  // The only exception is probe. But there we may need info about 40/80 pin and MaxTransferRate
2743  // Do not check UNIATA_SATA here since we may have controller with mixed ports
2744  if(CheckCable && !(ChipFlags & (UNIATA_NO80CHK/* | UNIATA_SATA*/))) {
2745  for(c=0; c<deviceExtension->NumberChannels; c++) {
2746  AtapiChipInit(HwDeviceExtension, DeviceNumber, c);
2747  }
2748  }
2749 
2750  return TRUE;
2751 } // end AtapiChipInit()
VOID NTAPI AtapiViaSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber)
Definition: id_init.cpp:1368
#define ChangePciConfig2(offs, _op)
Definition: bsmaster.h:1670
static void GlobalInit()
Definition: treelist.c:438
#define ATA_JMICRON_ID
Definition: bm_devs_decl.h:318
#define ITE_33
Definition: bm_devs_decl.h:724
ULONG NTAPI hpt_cable80(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel)
Definition: id_init.cpp:1537
#define ATA_ATI_ID
Definition: bm_devs_decl.h:147
VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
#define TRUE
Definition: types.h:120
#define CHAN_NOT_SPECIFIED_CHECK_CABLE
Definition: atapi.h:1484
#define KdPrint2(_x_)
Definition: atapi.h:154
#define ATA_AMD_ID
Definition: bm_devs_decl.h:129
#define CHAN_NOT_SPECIFIED
Definition: atapi.h:1483
#define IDX_BM_Command
Definition: bsmaster.h:167
#define VIABAR
Definition: bm_devs_decl.h:711
#define ChangePciConfig1(offs, _op)
Definition: bsmaster.h:1641
#define ATA_SILICON_IMAGE_ID
Definition: bm_devs_decl.h:507
#define NVQ
Definition: bm_devs_decl.h:700
#define CHIPFLAG_MASK
Definition: bm_devs_decl.h:621
#define HPT372
Definition: bm_devs_decl.h:643
#define VIABUG
Definition: bm_devs_decl.h:713
#define CTRFLAGS_NO_SLAVE
Definition: bsmaster.h:1139
#define AMDBUG
Definition: bm_devs_decl.h:710
#define ITE_133
Definition: bm_devs_decl.h:725
ULONG ChannelCtrlFlags
Definition: bsmaster.h:1059
ULONG MaxTransferMode
Definition: bsmaster.h:1057
#define ATA_JMB368
Definition: bm_devs_decl.h:325
_In_ USHORT DeviceID
Definition: iotypes.h:860
#define PROLD
Definition: bm_devs_decl.h:647
#define PRNEW
Definition: bm_devs_decl.h:648
#define CHIPTYPE_MASK
Definition: bm_devs_decl.h:620
#define ICH7
Definition: bm_devs_decl.h:697
#define ATA_PROMISE_ID
Definition: bm_devs_decl.h:454
#define ICH5
Definition: bm_devs_decl.h:693
#define ATA_NVIDIA_ID
Definition: bm_devs_decl.h:355
#define ATA_SA300
Definition: atapi.h:338
PHW_CHANNEL chan
Definition: bsmaster.h:1257
Definition: shell.h:41
ULONG DDKFASTAPI AtapiReadPort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
#define VIAPRQ
Definition: bm_devs_decl.h:716
VOID NTAPI UniataSataWritePort4(IN PHW_CHANNEL chan, IN ULONG io_port_ndx, IN ULONG data, IN ULONG pm_port)
Definition: id_sata.cpp:357
#define SIS133OLD
Definition: bm_devs_decl.h:680
#define CTRFLAGS_DMA_RO
Definition: bsmaster.h:1132
#define ATA_SERVERWORKS_ID
Definition: bm_devs_decl.h:494
#define ATI700
Definition: bm_devs_decl.h:668
#define SetPciConfig1(offs, op)
Definition: bsmaster.h:1630
#define ATA_UDMA6
Definition: atapi.h:334
#define ATA_HIGHPOINT_ID
Definition: bm_devs_decl.h:177
#define NV4OFF
Definition: bm_devs_decl.h:699
#define ALINEW
Definition: bm_devs_decl.h:639
#define SIICMD
Definition: bm_devs_decl.h:666
#define ATA_SIS_ID
Definition: bm_devs_decl.h:521
unsigned char BOOLEAN
VOID NTAPI UniataAhciReset(IN PVOID HwDeviceExtension, IN ULONG lChannel)
Definition: id_sata.cpp:1925
smooth NULL
Definition: ftsmooth.c:416
#define offsetof(TYPE, MEMBER)
#define UNIATA_SATA
Definition: bm_devs_decl.h:627
#define IDX_SATA_SError
Definition: bsmaster.h:458
VOID NTAPI AtapiAliSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber, IN ULONG c)
Definition: id_init.cpp:1485
#define ATA_SA150
Definition: atapi.h:337
#define SetPciConfig2(offs, op)
Definition: bsmaster.h:1659
#define WinVer_NT
Definition: CrossNt.h:112
#define ATA_JMB363
Definition: bm_devs_decl.h:322
VOID NTAPI AtapiRosbSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber)
Definition: id_init.cpp:1433
#define SISSATA
Definition: bm_devs_decl.h:678
#define ChangePciConfig4(offs, _op)
Definition: bsmaster.h:1699
#define VIACLK
Definition: bm_devs_decl.h:712
#define DEV_BSIZE
Definition: bsmaster.h:103
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
BOOLEAN NTAPI UniataAhciInit(IN PVOID HwDeviceExtension)
Definition: id_sata.cpp:645
#define GetPciConfig4(offs, op)
Definition: bsmaster.h:1678
USHORT NTAPI UniataEnableIoPCI(IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
Definition: id_probe.cpp:95
#define SIS66
Definition: bm_devs_decl.h:683
#define ATA_INTEL_ID
Definition: bm_devs_decl.h:184
#define SIS133NEW
Definition: bm_devs_decl.h:679
const GLubyte * c
Definition: glext.h:8905
#define SIIMIO
Definition: bm_devs_decl.h:667
VOID DDKFASTAPI AtapiWritePort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
#define PRTX
Definition: bm_devs_decl.h:649
BOOLEAN NTAPI generic_cable80(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel, IN ULONG pci_reg, IN ULONG bit_offs)
Definition: id_init.cpp:1638
#define IDX_BM_DeviceSpecific0
Definition: bsmaster.h:168
#define SIS33
Definition: bm_devs_decl.h:684
#define I6CH2
Definition: bm_devs_decl.h:695
#define SIINOSATAIRQ
Definition: bm_devs_decl.h:675
unsigned char UCHAR
Definition: xmlstorage.h:181
#define IDX_BM_DeviceSpecific1
Definition: bsmaster.h:170
#define ATA_CYRIX_ID
Definition: bm_devs_decl.h:168
#define UNIATA_AHCI
Definition: bm_devs_decl.h:630
UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
#define SII4CH
Definition: bm_devs_decl.h:672
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
#define ATA_JMB365
Definition: bm_devs_decl.h:323
BOOLEAN Force80pin
Definition: bsmaster.h:1048
unsigned short USHORT
Definition: pedump.c:61
#define SIS100OLD
Definition: bm_devs_decl.h:682
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
#define ATA_JMB366
Definition: bm_devs_decl.h:324
#define PRG2
Definition: bm_devs_decl.h:656
#define SIISETCLK
Definition: bm_devs_decl.h:673
#define INTEL_IDX
Definition: bm_devs_decl.h:690
#define min(a, b)
Definition: monoChain.cc:55
#define ATA_JMB361
Definition: bm_devs_decl.h:320
#define SIS100NEW
Definition: bm_devs_decl.h:681
#define GetPciConfig2(offs, op)
Definition: bsmaster.h:1649
ULONG DDKFASTAPI AtapiReadPortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
#define PRINT_PREFIX
Definition: atapi.h:150
#define GetPciConfig1(offs, op)
Definition: bsmaster.h:1620
#define PRMIO
Definition: bm_devs_decl.h:650
#define AtapiStallExecution(dt)
Definition: atapi.h:158
#define ATA_UDMA2
Definition: atapi.h:330
#define ATA_VIA_ID
Definition: bm_devs_decl.h:571
#define ATA_ITE_ID
Definition: bm_devs_decl.h:604
#define VIA133
Definition: bm_devs_decl.h:707
#define c
Definition: ke_i.h:80
unsigned int ULONG
Definition: retypes.h:1
NTHALAPI ULONG NTAPI HalGetBusData(BUS_DATA_TYPE, ULONG, ULONG, PVOID, ULONG)
#define UNIATA_NO80CHK
Definition: bm_devs_decl.h:631
#define WinVer_Id()
Definition: CrossNt.h:109
#define CYRIX_OLD
Definition: bm_devs_decl.h:719
GLboolean GLboolean GLboolean GLboolean a
Definition: glext.h:6204
_In_ PCHAR _In_ ULONG DeviceNumber
Definition: classpnp.h:1036
#define SWKS33
Definition: bm_devs_decl.h:660
#define ITE_133_NEW
Definition: bm_devs_decl.h:726
#define ULONGIO_PTR
Definition: config.h:102
#define HPTOLD
Definition: bm_devs_decl.h:645
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]
Definition: bsmaster.h:1088
ULONG NumberChannels
Definition: atapi.c:68
BOOLEAN NTAPI AtapiChipInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
Definition: id_init.cpp:1879
#define ATA_UDMA5
Definition: atapi.h:333
#define ATA_ACER_LABS_ID
Definition: bm_devs_decl.h:120
#define SWKS100
Definition: bm_devs_decl.h:662
#define VIASATA
Definition: bm_devs_decl.h:717
ULONG Addr
Definition: bsmaster.h:1009
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3238

Referenced by AtapiAdapterControl(), AtapiFindIsaController(), AtapiHwInitialize(), AtapiHwInitialize__(), and UniataFindBusMasterController().

◆ AtapiDmaAlloc()

VOID NTAPI AtapiDmaAlloc ( IN PVOID  HwDeviceExtension,
IN PPORT_CONFIGURATION_INFORMATION  ConfigInfo,
IN ULONG  lChannel 
)

Definition at line 138 of file id_dma.cpp.

143 {
144 #ifdef USE_OWN_DMA
145  PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
146  PHW_CHANNEL chan = &(deviceExtension->chan[lChannel]);
147  ULONG c = lChannel;
148  ULONG i;
149  ULONG ph_addru;
150 
151  deviceExtension->chan[c].CopyDmaBuffer = FALSE;
152 
153  if(!deviceExtension->Host64 && (WinVer_Id() > WinVer_NT)) {
154  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: allocate tmp buffers below 4Gb\n"));
155  if(chan->DB_PRD) {
156  KdPrint2((PRINT_PREFIX " already initialized %x\n", chan->DB_PRD));
157  return;
158  }
159  chan->DB_PRD = MmAllocateContiguousMemory(sizeof(((PATA_REQ)NULL)->dma_tab), ph4gb);
160  if(chan->DB_PRD) {
161  chan->DB_PRD_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->DB_PRD), &i, &ph_addru);
162  if(!chan->DB_PRD_PhAddr || !i || ((LONG)(chan->DB_PRD_PhAddr) == -1)) {
163  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD BASE\n" ));
164  chan->DB_PRD = NULL;
165  chan->DB_PRD_PhAddr = 0;
166  return;
167  }
168  if(ph_addru) {
169  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD below 4Gb\n" ));
170  goto err_1;
171  }
172  }
174  if(chan->DB_IO) {
175  chan->DB_IO_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->DB_IO), &i, &ph_addru);
176  if(!chan->DB_IO_PhAddr || !i || ((LONG)(chan->DB_IO_PhAddr) == -1)) {
177  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB IO BASE\n" ));
178 err_1:
180  chan->DB_PRD = NULL;
181  chan->DB_PRD_PhAddr = 0;
182  chan->DB_IO = NULL;
183  chan->DB_IO_PhAddr = 0;
184  return;
185  }
186  if(ph_addru) {
187  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB IO below 4Gb\n" ));
189  goto err_1;
190  }
191  }
192  }
193 
194 
195  if(deviceExtension->HwFlags & UNIATA_AHCI) {
196  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: AHCI\n" ));
197  if(chan->AhciCtlBlock) {
198  KdPrint2((PRINT_PREFIX " already initialized %x\n", chan->AhciCtlBlock));
199  return;
200  }
201  // Need 1K-byte alignment
204  ph4gb);
205  if(chan->AhciCtlBlock0) {
206  union {
207  PUCHAR AhciCtlBlock;
208  ULONGLONG AhciCtlBlock64;
209  };
210  AhciCtlBlock64 = 0;
211  AhciCtlBlock = (PUCHAR)chan->AhciCtlBlock0;
212 
213  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP BASE %I64x\n", AhciCtlBlock64));
214 
215  AhciCtlBlock64 += AHCI_CLB_ALIGNEMENT_MASK;
216  AhciCtlBlock64 &= ~AHCI_CLB_ALIGNEMENT_MASK;
217 
218  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP BASE 1k-aligned %I64x\n", AhciCtlBlock64));
219 
220  chan->AhciCtlBlock = (PIDE_AHCI_CHANNEL_CTL_BLOCK)AhciCtlBlock;
221 
222  chan->AHCI_CTL_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->AhciCtlBlock), &i, &ph_addru);
223  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP Phys BASE %I64x\n", chan->AHCI_CTL_PhAddr));
224  if(!chan->AHCI_CTL_PhAddr || !i || ((LONG)(chan->AHCI_CTL_PhAddr) == -1)) {
225  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No AHCI CLP BASE\n" ));
226  chan->AhciCtlBlock = NULL;
227  chan->AHCI_CTL_PhAddr = 0;
228  return;
229  }
230  if(ph_addru) {
231  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No AHCI CLP below 4Gb\n" ));
233  chan->AhciCtlBlock = NULL;
234  chan->AHCI_CTL_PhAddr = 0;
235  return;
236  }
237  } else {
238  KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: Can't alloc AHCI CLP\n"));
239  }
240  }
241 #endif //USE_OWN_DMA
242  return;
243 } // end AtapiDmaAlloc()
#define KdPrint2(_x_)
Definition: atapi.h:154
unsigned char * PUCHAR
Definition: retypes.h:3
PHW_CHANNEL chan
Definition: bsmaster.h:1257
VOID NTAPI MmFreeContiguousMemory(IN PVOID BaseAddress)
Definition: contmem.c:653
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock
Definition: bsmaster.h:1103
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
long LONG
Definition: pedump.c:60
#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru)
Definition: bsmaster.h:1716
smooth NULL
Definition: ftsmooth.c:416
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock0
Definition: bsmaster.h:1102
#define WinVer_NT
Definition: CrossNt.h:112
ULONGLONG AHCI_CTL_PhAddr
Definition: bsmaster.h:1104
uint64_t ULONGLONG
Definition: typedefs.h:65
const GLubyte * c
Definition: glext.h:8905
BOOLEAN CopyDmaBuffer
Definition: bsmaster.h:1045
ULONG DB_IO_PhAddr
Definition: bsmaster.h:1097
PVOID DB_IO
Definition: bsmaster.h:1096
#define UNIATA_AHCI
Definition: bm_devs_decl.h:630
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
struct _IDE_AHCI_CHANNEL_CTL_BLOCK * PIDE_AHCI_CHANNEL_CTL_BLOCK
PHYSICAL_ADDRESS ph4gb
Definition: id_dma.cpp:56
ULONG DB_PRD_PhAddr
Definition: bsmaster.h:1095
PVOID NTAPI MmAllocateContiguousMemory(IN SIZE_T NumberOfBytes, IN PHYSICAL_ADDRESS HighestAcceptableAddress)
Definition: contmem.c:626
#define AHCI_CLB_ALIGNEMENT_MASK
Definition: bsmaster.h:518
#define PRINT_PREFIX
Definition: atapi.h:150
#define c
Definition: ke_i.h:80
unsigned int ULONG
Definition: retypes.h:1
#define WinVer_Id()
Definition: CrossNt.h:109
ULONG MaximumDmaTransferLength
Definition: bsmaster.h:1317
PVOID DB_PRD
Definition: bsmaster.h:1094

Referenced by UniataAhciInit(), and UniataFindBusMasterController().

◆ AtapiDmaDBPreSync()

BOOLEAN NTAPI AtapiDmaDBPreSync ( IN PVOID  HwDeviceExtension,
PHW_CHANNEL  chan,
PSCSI_REQUEST_BLOCK  Srb 
)

Definition at line 553 of file id_dma.cpp.

558 {
559  PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
560  PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension);
561 
562  if(!AtaReq->ata.dma_base) {
563  KdPrint2((PRINT_PREFIX "AtapiDmaDBPreSync: *** !AtaReq->ata.dma_base\n"));
564  return FALSE;
565  }
566 // GetStatus(chan, statusByte2);
567  if(AtaReq->Flags & REQ_FLAG_DMA_DBUF_PRD) {
568  KdPrint2((PRINT_PREFIX " DBUF_PRD\n"));
569  ASSERT(FALSE);
570  if(deviceExtension->HwFlags & UNIATA_AHCI) {
571  RtlCopyMemory(chan->DB_PRD, AtaReq->ahci.ahci_cmd_ptr, sizeof(AtaReq->ahci_cmd0));
572  } else {
573  RtlCopyMemory(chan->DB_PRD, &(AtaReq->dma_tab), sizeof(AtaReq->dma_tab));
574  }
575  }
576  if(!(Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
577  (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
578  KdPrint2((PRINT_PREFIX " DBUF (Write)\n"));
579  ASSERT(FALSE);
580  RtlCopyMemory(chan->DB_IO, AtaReq->DataBuffer,
581  Srb->DataTransferLength);
582  }
583  return TRUE;
584 } // end AtapiDmaDBPreSync()
struct _ATA_REQ::@1120::@1122::@1126::@1128 ata
#define TRUE
Definition: types.h:120
NTSYSAPI VOID NTAPI RtlCopyMemory(VOID UNALIGNED *Destination, CONST VOID UNALIGNED *Source, ULONG Length)
#define KdPrint2(_x_)
Definition: atapi.h:154
struct _ATA_REQ::@1120::@1122::@1126::@1129 ahci
IDE_AHCI_CMD ahci_cmd0
Definition: bsmaster.h:922
#define SRB_FLAGS_DATA_IN
Definition: srb.h:392
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel) ?(CompletionRoutine !=NULL) :TRUE)
PVOID DB_IO
Definition: bsmaster.h:1096
#define REQ_FLAG_DMA_DBUF
Definition: bsmaster.h:938
BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES]
Definition: bsmaster.h:921
#define UNIATA_AHCI
Definition: bm_devs_decl.h:630
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
UCHAR Flags
Definition: bsmaster.h:892
#define PRINT_PREFIX
Definition: atapi.h:150
#define REQ_FLAG_DMA_DBUF_PRD
Definition: bsmaster.h:939
IN PSCSI_REQUEST_BLOCK Srb
Definition: class2.h:49
union _ATA_REQ * PATA_REQ
PVOID DB_PRD
Definition: bsmaster.h:1094
PUSHORT DataBuffer
Definition: bsmaster.h:882

Referenced by AtapiInterrupt__(), AtapiSendCommand(), IdeReadWrite(), and IdeSendCommand().

◆ AtapiDmaDBSync()

BOOLEAN NTAPI AtapiDmaDBSync ( PHW_CHANNEL  chan,
PSCSI_REQUEST_BLOCK  Srb 
)

Definition at line 532 of file id_dma.cpp.

536 {
537  PATA_REQ AtaReq;
538 
539  AtaReq = (PATA_REQ)(Srb->SrbExtension);
540  if((Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
541  (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
542  KdPrint2((PRINT_PREFIX " AtapiDmaDBSync is issued.\n"));
543  ASSERT(FALSE);
544  KdPrint2((PRINT_PREFIX " DBUF (Read)\n"));
545  RtlCopyMemory(AtaReq->DataBuffer, chan->DB_IO,
546  Srb->DataTransferLength);
547  }
548  return TRUE;
549 } // end AtapiDmaDBSync()
#define TRUE
Definition: types.h:120
NTSYSAPI VOID NTAPI RtlCopyMemory(VOID UNALIGNED *Destination, CONST VOID UNALIGNED *Source, ULONG Length)
#define KdPrint2(_x_)
Definition: atapi.h:154
#define SRB_FLAGS_DATA_IN
Definition: srb.h:392
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel) ?(CompletionRoutine !=NULL) :TRUE)
PVOID DB_IO
Definition: bsmaster.h:1096
#define REQ_FLAG_DMA_DBUF
Definition: bsmaster.h:938
UCHAR Flags
Definition: bsmaster.h:892
#define PRINT_PREFIX
Definition: atapi.h:150
IN PSCSI_REQUEST_BLOCK Srb
Definition: class2.h:49
union _ATA_REQ * PATA_REQ
PUSHORT DataBuffer
Definition: bsmaster.h:882

Referenced by AtapiCallBack__(), AtapiInterrupt__(), and AtapiStartIo__().

◆ AtapiDmaDone()

UCHAR NTAPI AtapiDmaDone ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  lChannel,
IN PSCSI_REQUEST_BLOCK  Srb 
)

Definition at line 685 of file id_dma.cpp.

691 {
692  PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
693  //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
694  PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
695  UCHAR dma_status;
696 
697  ULONG VendorID = deviceExtension->DevID & 0xffff;
698  ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
699 
700  KdPrint2((PRINT_PREFIX "AtapiDmaDone: dev %d\n", DeviceNumber));
701 
702  if(deviceExtension->HwFlags & UNIATA_AHCI) {
703  KdPrint2((PRINT_PREFIX " ACHTUNG! should not be called for AHCI!\n"));
704  return IDE_STATUS_WRONG;
705  }
706 
707  switch(VendorID) {
708  case ATA_PROMISE_ID:
709  if(ChipType == PRNEW) {
710  ULONG Channel = deviceExtension->Channel + lChannel;
711 /*
712  AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
713  AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) &
714  ~(Channel ? 0x08 : 0x02));
715 */
716  if(chan->ChannelCtrlFlags & CTRFLAGS_LBA48) {
717  AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20),
718  0
719  );
720  }
721 /*
722  } else
723  if(deviceExtension->MemIo) {
724  // end transaction
725  AtapiWritePort4(chan,
726  IDX_BM_Command,
727  (AtapiReadPort4(chan,
728  IDX_BM_Command) & ~0x00000080) );
729  // clear flag
730  chan->ChannelCtrlFlags &= ~CTRFLAGS_DMA_ACTIVE;
731  return 0;
732 */
733  }
734  break;
735  }
736 
737  // get status
738  dma_status = AtapiReadPort1(chan, IDX_BM_Status) & BM_STATUS_MASK;
739  // end transaction
743  // clear interrupt and error status
745  // clear flag
747 
748  return dma_status;
749 
750 } // end AtapiDmaDone()
#define KdPrint2(_x_)
Definition: atapi.h:154
#define IDX_BM_Command
Definition: bsmaster.h:167
#define BM_STATUS_MASK
Definition: bsmaster.h:145
ULONG ChannelCtrlFlags
Definition: bsmaster.h:1059
#define PRNEW
Definition: bm_devs_decl.h:648
#define CHIPTYPE_MASK
Definition: bm_devs_decl.h:620
#define ATA_PROMISE_ID
Definition: bm_devs_decl.h:454
PHW_CHANNEL chan
Definition: bsmaster.h:1257
#define IDE_STATUS_WRONG
Definition: atapi.h:431
#define CTRFLAGS_LBA48
Definition: bsmaster.h:1137
#define BM_STATUS_INTR
Definition: bsmaster.h:144
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
#define IDX_BM_Status
Definition: bsmaster.h:169
unsigned char UCHAR
Definition: xmlstorage.h:181
#define UNIATA_AHCI
Definition: bm_devs_decl.h:630
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
#define CTRFLAGS_DMA_ACTIVE
Definition: bsmaster.h:1131
VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
#define PRINT_PREFIX
Definition: atapi.h:150
unsigned int ULONG
Definition: retypes.h:1
#define BM_STATUS_ERR
Definition: bsmaster.h:143
_In_ PCHAR _In_ ULONG DeviceNumber
Definition: classpnp.h:1036
#define BM_COMMAND_START_STOP
Definition: bsmaster.h:150
#define ULONGIO_PTR
Definition: config.h:102

Referenced by AtapiCheckInterrupt__(), AtapiInterrupt__(), AtapiResetController__(), AtapiSoftReset(), IdeSendCommand(), and UniataFindBusMasterController().

◆ AtapiDmaInit()

VOID NTAPI AtapiDmaInit ( IN PVOID  HwDeviceExtension,
IN ULONG  DeviceNumber,
IN ULONG  lChannel,
IN SCHAR  apiomode,
IN SCHAR  wdmamode,
IN SCHAR  udmamode 
)

Definition at line 975 of file id_dma.cpp.

984 {
985  PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
986  ULONG Channel = deviceExtension->Channel + lChannel;
987  PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
988  //LONG statusByte = 0;
989  ULONG dev = Channel*2 + DeviceNumber; // for non-SATA/AHCI only!
990  //ULONG ldev = lChannel*2 + DeviceNumber; // for non-SATA/AHCI only!
991  BOOLEAN isAtapi = ATAPI_DEVICE(chan, DeviceNumber);
992  ULONG slotNumber = deviceExtension->slotNumber;
993  ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
994  LONG i;
995  PHW_LU_EXTENSION LunExt = chan->lun[DeviceNumber];
996  UCHAR ModeByte;
997 
998  ULONG VendorID = deviceExtension->DevID & 0xffff;
999  //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
1000  //ULONG RevID = deviceExtension->RevID;
1001  ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1002  ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
1003 
1004  LONG statusByte = 0;
1005 
1006  //UCHAR *reg_val = NULL;
1007 
1008  LunExt->DeviceFlags &= ~DFLAGS_REINIT_DMA;
1009  /* set our most pessimistic default mode */
1010  LunExt->TransferMode = ATA_PIO;
1011 // if(!deviceExtension->BaseIoAddressBM[lChannel]) {
1012  if(!deviceExtension->BusMaster) {
1013  KdPrint2((PRINT_PREFIX " !deviceExtension->BusMaster: NO DMA\n"));
1014  wdmamode = udmamode = -1;
1015  }
1016 
1017  // Limit transfer mode (controller limitation)
1018  if((LONG)chan->MaxTransferMode >= ATA_UDMA) {
1019  KdPrint2((PRINT_PREFIX "AtapiDmaInit: chan->MaxTransferMode >= ATA_UDMA\n"));
1020  udmamode = min( udmamode, (CHAR)(chan->MaxTransferMode - ATA_UDMA));
1021  } else
1022  if((LONG)chan->MaxTransferMode >= ATA_WDMA) {
1023  KdPrint2((PRINT_PREFIX "AtapiDmaInit: chan->MaxTransferMode >= ATA_WDMA\n"));
1024  udmamode = -1;
1025  wdmamode = min( wdmamode, (CHAR)(chan->MaxTransferMode - ATA_WDMA));
1026  } else
1027  if((LONG)chan->MaxTransferMode >= ATA_PIO0) {
1028  KdPrint2((PRINT_PREFIX "AtapiDmaInit: NO DMA\n"));
1029  wdmamode = udmamode = -1;
1030  apiomode = min( apiomode, (CHAR)(chan->MaxTransferMode - ATA_PIO0));
1031  } else {
1032  KdPrint2((PRINT_PREFIX "AtapiDmaInit: PIO0\n"));
1033  wdmamode = udmamode = -1;
1034  apiomode = 0;
1035  }
1036  // Limit transfer mode (device limitation)
1037  KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->LimitedTransferMode %#x\n", LunExt->LimitedTransferMode));
1038  if((LONG)LunExt->LimitedTransferMode >= ATA_UDMA) {
1039  KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => %#x\n",
1040  min( udmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_UDMA))
1041  ));
1042  udmamode = min( udmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_UDMA));
1043  } else
1044  if((LONG)LunExt->LimitedTransferMode >= ATA_WDMA) {
1045  KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->MaxTransferMode >= ATA_WDMA => %#x\n",
1046  min( wdmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_WDMA))
1047  ));
1048  udmamode = -1;
1049  wdmamode = min( wdmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_WDMA));
1050  } else
1051  if((LONG)LunExt->LimitedTransferMode >= ATA_PIO0) {
1052  KdPrint2((PRINT_PREFIX "AtapiDmaInit: lun NO DMA\n"));
1053  wdmamode = udmamode = -1;
1054  apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO0));
1055  } else {
1056  KdPrint2((PRINT_PREFIX "AtapiDmaInit: lun PIO0\n"));
1057  wdmamode = udmamode = -1;
1058  apiomode = 0;
1059  }
1060 
1061  //if(!(ChipFlags & UNIATA_AHCI)) {
1062 
1063  // this is necessary for future PM support
1064  SelectDrive(chan, DeviceNumber);
1065  GetStatus(chan, statusByte);
1066  // we can see here IDE_STATUS_ERROR status after previous operation
1067  if(statusByte & IDE_STATUS_ERROR) {
1068  KdPrint2((PRINT_PREFIX "IDE_STATUS_ERROR detected on entry, statusByte = %#x\n", statusByte));
1069  //GetBaseStatus(chan, statusByte);
1070  }
1071  if(statusByte && UniataIsIdle(deviceExtension, statusByte & ~IDE_STATUS_ERROR) != IDE_STATUS_IDLE) {
1072  KdPrint2((PRINT_PREFIX "Can't setup transfer mode: statusByte = %#x\n", statusByte));
1073  return;
1074  }
1075  //}
1076 
1077  chan->last_cdev = DeviceNumber;
1078  if(UniataIsSATARangeAvailable(deviceExtension, lChannel) ||
1079  (ChipFlags & UNIATA_AHCI) || (chan->MaxTransferMode >= ATA_SA150)
1080  ) {
1081  //if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI)) {
1082  /****************/
1083  /* SATA Generic */
1084  /****************/
1085 
1086  KdPrint2((PRINT_PREFIX "SATA Generic\n"));
1087 
1088  if((udmamode >= 5) || (ChipFlags & UNIATA_AHCI) || ((udmamode >= 0) && (chan->MaxTransferMode >= ATA_SA150))) {
1089  /* some drives report UDMA6, some UDMA5 */
1090  /* ATAPI may not have SataCapabilities set in IDENTIFY DATA */
1091  if(ata_is_sata(&(LunExt->IdentifyData))) {
1092  //udmamode = min(udmamode, 6);
1093  KdPrint2((PRINT_PREFIX "LunExt->LimitedTransferMode %x, LunExt->OrigTransferMode %x\n",
1094  LunExt->LimitedTransferMode, LunExt->OrigTransferMode));
1095  if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, min(LunExt->LimitedTransferMode, LunExt->OrigTransferMode))) {
1096  return;
1097  }
1098  udmamode = min(udmamode, 6);
1099 
1100  } else {
1101  KdPrint2((PRINT_PREFIX "SATA -> PATA adapter ?\n"));
1102  if (udmamode > 2 && (!LunExt->IdentifyData.HwResCableId && (LunExt->IdentifyData.HwResValid == IDENTIFY_CABLE_ID_VALID) )) {
1103  KdPrint2((PRINT_PREFIX "AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1104  udmamode = 2;
1105  apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO0));
1106  } else {
1107  udmamode = min(udmamode, 6);
1108  }
1109  }
1110  }
1111  if(udmamode >= 0) {
1112  ModeByte = ATA_UDMA0 + udmamode;
1113  } else
1114  if(wdmamode >= 0) {
1115  ModeByte = ATA_WDMA0 + wdmamode;
1116  } else
1117  if(apiomode >= 0) {
1118  ModeByte = ATA_PIO0 + apiomode;
1119  } else {
1120  ModeByte = ATA_PIO;
1121  }
1122 
1123  AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ModeByte);
1124  return;
1125  }
1126 
1127  if(deviceExtension->UnknownDev) {
1128  KdPrint2((PRINT_PREFIX "Unknown chip, omit Vendor/Dev checks\n"));
1129  goto try_generic_dma;
1130  }
1131 
1132  if(udmamode > 2 && (!LunExt->IdentifyData.HwResCableId && (LunExt->IdentifyData.HwResValid == IDENTIFY_CABLE_ID_VALID)) ) {
1133  if(ata_is_sata(&(LunExt->IdentifyData))) {
1134  KdPrint2((PRINT_PREFIX "AtapiDmaInit: SATA beyond adapter or Controller compat mode\n"));
1135  } else {
1136  KdPrint2((PRINT_PREFIX "AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1137  udmamode = 2;
1138  apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO));
1139  }
1140  }
1141 
1142  KdPrint2((PRINT_PREFIX "Setup chip a:w:u=%d:%d:%d\n",
1143  apiomode,
1144  wdmamode,
1145  udmamode));
1146 
1147  switch(VendorID) {
1148  case ATA_ACARD_ID: {
1149  /*********/
1150  /* Acard */
1151  /*********/
1152  static const USHORT reg4a = 0xa6;
1153  UCHAR reg = 0x40 + (UCHAR)dev;
1154 
1155  if(ChipType == ATPOLD) {
1156  /* Old Acard 850 */
1157  static const USHORT reg4x2 = 0x0301;
1158 
1159  for(i=udmamode; i>=0; i--) {
1160  if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA + i)) {
1161 set_old_acard:
1162  ChangePciConfig1(0x54, a | (0x01 << dev) | ((i+1) << (dev*2)));
1163  SetPciConfig1(0x4a, reg4a);
1164  SetPciConfig2(reg, reg4x2);
1165  return;
1166  }
1167 
1168  }
1169  if (wdmamode >= 2 && apiomode >= 4) {
1170  if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1171  goto set_old_acard;
1172  }
1173  }
1174  } else {
1175  /* New Acard 86X */
1176  static const UCHAR reg4x = 0x31;
1177 
1178  for(i=udmamode; i>=0; i--) {
1179  if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA + i)) {
1180 set_new_acard:
1181  ChangePciConfig2(0x44, (a & ~(0x000f << (dev * 4))) | ((i+1) << (dev*4)));
1182  SetPciConfig1(0x4a, reg4a);