68 ULONG VendorID = deviceExtension->
DevID & 0xffff;
116 switch(deviceExtension->
DevID) {
125 if(ChipType !=
PRMIO) {
143 switch(deviceExtension->
DevID) {
157 switch(deviceExtension->
DevID) {
185 KdPrint((
"SATA controller %s (%s%s channel)\n",
186 (satacfg & 0x01) == 0 ?
"disabled" :
"enabled",
187 (satacfg & 0x08) == 0 ?
"" :
"combined mode, ",
188 (satacfg & 0x10) == 0 ?
"primary" :
"secondary"));
193 if ((satacfg & 0x09) == 0x01) {
256 if(deviceExtension->
DevID == 0x82131283) {
281 #endif // this code is removed from newer FreeBSD 291 ULONG tmp32, port_mask;
301 #endif // this code is unnecessary since port mapping is implemented 350 ULONG VendorID = deviceExtension->
DevID & 0xffff;
378 BaseIoAddressBM = pciData->u.type0.BaseAddresses[4] & ~0x07;
380 ConfigInfo->MaximumTransferLength =
DEV_BSIZE*256;
551 switch(deviceExtension->
DevID) {
613 deviceExtension->
HwFlags = tmp32;
617 deviceExtension->
HwFlags |= tmp32;
627 if(tmp32 != 0xffffffff) {
691 BaseIoAddress1 =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
693 BaseIoAddress2 =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
695 BaseIoAddressBM =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
700 chan = &deviceExtension->
chan[
c];
725 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
726 5, 0, ((ChipFlags &
NV4OFF) ? 0x400 : 0) + 0x40*2);
728 if(!BaseMemAddress) {
731 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
737 chan = &deviceExtension->
chan[
c];
749 if(ChipType !=
PRMIO) {
758 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
761 if(!BaseMemAddress) {
764 if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
771 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
774 if(!BaseMemAddress) {
777 if((*ConfigInfo->AccessRanges)[3].RangeInMemory) {
788 ((reg48 & 0x02) ? 1 : 0) +
798 chan = &deviceExtension->
chan[
c];
814 if((ChipFlags &
PRSATA) ||
815 ((ChipFlags &
PRCMBO) &&
c<2)) {
836 chan = &deviceExtension->
chan[0];
861 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
864 if(!BaseMemAddress) {
867 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
877 chan = &deviceExtension->
chan[
c];
919 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
922 if(!BaseMemAddress) {
925 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
934 chan = &deviceExtension->
chan[
c];
995 if(SiSSouthAdapters[
i].nDeviceId == 0x1182 ||
996 SiSSouthAdapters[
i].nDeviceId == 0x1183) {
1019 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1022 if(BaseMemAddress) {
1023 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1030 ULONG offs =
c << (SIS_182 ? 5 : 6);
1032 chan = &deviceExtension->
chan[
c];
1070 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1072 if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1078 if(BaseMemAddress) {
1082 ULONG BaseIoAddressBM_0;
1087 AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 4, 0,
1092 chan = &deviceExtension->
chan[
c];
1109 chan = &deviceExtension->
chan[
c];
1110 if((ChipFlags &
VIABAR) && (
c==2)) {
1138 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1140 if(!BaseMemAddress) {
1143 if((*ConfigInfo->AccessRanges)[0].RangeInMemory) {
1151 ULONG offs = 0x200 +
c*0x200;
1153 chan = &deviceExtension->
chan[
c];
1199 BaseIoAddressBM =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1201 if(BaseIoAddressBM) {
1204 if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
1237 if(deviceExtension->
DevID == 0x28288086 &&
1238 pciData->u.type0.SubVendorID == 0x106b) {
1243 BaseMemAddress =
AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1245 if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1253 chan = &deviceExtension->
chan[
c];
1256 if(ChipFlags &
ICH5) {
1258 if ((tmp8 & 0x04) == 0) {
1260 }
else if ((tmp8 & 0x02) == 0) {
1265 }
else if ((tmp8 & 0x02) != 0) {
1272 if(ChipFlags &
I6CH2) {
1277 switch(tmp8 & 0x03) {
1298 if(!(ChipFlags &
ICH7) && BaseMemAddress) {
1303 if((ChipFlags &
ICH5) || BaseMemAddress) {
1309 deviceExtension->
HwFlags |= ChipType;
1311 if(ChipFlags &
ICH7) {
1328 if(deviceExtension->
DevID == 0x01021078) {
1329 ConfigInfo->AlignmentMask = 0x0f;
1337 KdPrint((
" Check JMicron AHCI\n"));
1342 KdPrint((
" JMicron PATA/SATA\n"));
1345 #if 0 // do not touch, see Linux sources 1351 KdPrint((
" JMicron Combined\n"));
1389 slotData.
u.
bits.FunctionNumber = funcNumber;
1402 VendorID = pciData.VendorID;
1404 dev_id = (VendorID | (
DeviceID << 16));
1406 if (dev_id == 0x03051106 ||
1407 dev_id == 0x03911106 ||
1408 dev_id == 0x31021106 ||
1409 dev_id == 0x31121106) {
1414 if ((reg76 & 0xf0) != 0xd0) {
1455 slotData.
u.
bits.FunctionNumber = funcNumber;
1468 VendorID = pciData.VendorID;
1470 dev_id = (VendorID | (
DeviceID << 16));
1510 slotData.
u.
bits.FunctionNumber = funcNumber;
1523 VendorID = pciData.VendorID;
1525 dev_id = (VendorID | (
DeviceID << 16));
1542 PVOID HwDeviceExtension = (
PVOID)deviceExtension;
1543 ULONG slotNumber = deviceExtension->slotNumber;
1544 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1554 c = channel - deviceExtension->Channel;
1555 chan = &deviceExtension->chan[
c];
1557 slotData.
u.
AsULONG = deviceExtension->slotNumber;
1564 if(ChipType ==
HPT374 && slotData.
u.
bits.FunctionNumber == 1) {
1565 reg = channel ? 0x57 : 0x53;
1575 res =
res & (channel ? 0x01 : 0x02);
1645 PVOID HwDeviceExtension = (
PVOID)deviceExtension;
1646 ULONG slotNumber = deviceExtension->slotNumber;
1647 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1649 if(deviceExtension->MaxTransferMode <=
ATA_UDMA2) {
1650 KdPrint2((
PRINT_PREFIX "generic_cable80(%d, %#x, %d) <= UDMA2\n", channel, pci_reg, bit_offs));
1659 c = channel - deviceExtension->Channel;
1660 chan = &deviceExtension->chan[
c];
1668 if(!(tmp8 & (1 << (channel << bit_offs)))) {
1691 c = channel - deviceExtension->Channel;
1693 chan = &deviceExtension->chan[
c];
1798 c = channel - deviceExtension->
Channel;
1818 chan = &deviceExtension->
chan[
c];
1821 if(tmp32 != 0xffffffff) {
1853 chan = &deviceExtension->
chan[
c];
1856 if(tmp32 != 0xffffffff) {
1888 ULONG VendorID = deviceExtension->
DevID & 0xffff;
1915 channel += deviceExtension->
Channel;
1926 VendorID = 0xffffffff;
1977 chan = &deviceExtension->
chan[
c];
1980 if(RevID == 0xc2 || RevID == 0xc3) {
1982 SystemIoBusNumber, slotNumber,
c);
2058 chan = &deviceExtension->
chan[
c];
2099 chan = &deviceExtension->
chan[
c];
2101 if(ChipFlags &
ICH5) {
2103 if ((tmp8 & 0x04) == 0) {
2105 chan->
lun[0]->SATA_lun_map = (tmp8 & 0x01) ^
c;
2106 chan->
lun[1]->SATA_lun_map = 0;
2107 }
else if ((tmp8 & 0x02) == 0) {
2109 chan->
lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2110 chan->
lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2115 }
else if ((tmp8 & 0x02) != 0) {
2117 chan->
lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2118 chan->
lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2125 if(ChipFlags &
I6CH2) {
2128 chan->
lun[0]->SATA_lun_map =
c ? 0 : 1;
2129 chan->
lun[1]->SATA_lun_map = 0;
2132 switch(tmp8 & 0x03) {
2135 chan->
lun[0]->SATA_lun_map = 0+
c;
2136 chan->
lun[1]->SATA_lun_map = 2+
c;
2141 chan->
lun[0]->SATA_lun_map = 0;
2142 chan->
lun[1]->SATA_lun_map = 2;
2152 chan->
lun[0]->SATA_lun_map = 1;
2153 chan->
lun[1]->SATA_lun_map = 3;
2171 chan = &deviceExtension->
chan[
c];
2188 chan = &deviceExtension->
chan[
c];
2197 if(reg54 == 0x0000 || reg54 == 0xffff) {
2200 if( ((reg54 >> (channel*2)) & 30) == 0) {
2209 ULONG offs = (ChipFlags &
NV4OFF) ? 0x0440 : 0x0010;
2215 if(ChipFlags &
NVQ) {
2219 if(tmp32 & ~0xfffffff9) {
2221 tmp32 & 0xfffffff9);
2224 deviceExtension->
HwFlags = ChipFlags;
2226 if(ChipFlags &
NVQ) {
2233 tmp32 | ~0x00000006);
2286 chan = &deviceExtension->
chan[
c];
2288 if(Reg50 & (1 << (channel+10))) {
2298 chan = &deviceExtension->
chan[
c];
2309 (ChipFlags &
PRG2) ? 0x60 : 0x6c, 0x000000ff);
2316 chan = &deviceExtension->
chan[
c];
2333 SystemIoBusNumber, slotNumber);
2362 if ((tmp8 & 0x30) != 0x10)
2365 if ((tmp8 & 0x30) != 0x10) {
2377 chan = &deviceExtension->
chan[
c];
2379 if(Reg79 & (channel ? 0x02 : 0x01)) {
2410 if (ChipFlags &
SII4CH) {
2415 chan = &deviceExtension->
chan[
c];
2470 chan = &deviceExtension->
chan[
c];
2506 chan = &deviceExtension->
chan[
c];
2508 if(tmp16 & 0x8000) {
2517 chan = &deviceExtension->
chan[
c];
2519 if(tmp8 & (0x10 << channel)) {
2572 SystemIoBusNumber, slotNumber);
2593 chan = &deviceExtension->
chan[
c];
2596 if((ChipFlags &
VIABAR) && (
c >= 2)) {
2629 chan = &deviceExtension->
chan[
c];
2630 if(!(tmp16 & (channel ? 0x08 : 0x04))) {
2643 if(!(tmp8 & 0x40)) {
2666 c_swp = (reg40 & (1<<22)) ? 1 : 0;
2678 if(reg40 & (1 << 23)) {
2700 chan = &deviceExtension->
chan[
c];
2709 if(!(reg40 & (1<<5))) {
2712 if(!(reg40 & (1<<3))) {
2717 if(!(reg80 & (1<<21))) {
2720 if(!(reg80 & (1<<19))) {
2765 if(!BaseIoAddressBM_0) {
2768 for(
c=0;
c<deviceExtension->NumberChannels;
c++) {
2769 chan = &deviceExtension->chan[
c];
2773 if(BaseIoAddressBM_0) {
2774 BaseIoAddressBM_0++;
2821 MemIo = Proc =
FALSE;
2823 chan->RegTranslation[
idx].Addr =
addr;
2824 chan->RegTranslation[
idx].MemIo = MemIo;
2825 chan->RegTranslation[
idx].Proc = Proc;
2837 MemIo = Proc =
FALSE;
2840 IoRes->MemIo = MemIo;
2854 KdPrint2((
PRINT_PREFIX "AtapiSetupLunPtrs for channel %d of %d, %d luns \n",
c, deviceExtension->NumberChannels, deviceExtension->NumberLuns));
2856 if(!deviceExtension->NumberLuns) {
2861 chan->DeviceExtension = deviceExtension;
2863 chan->NumberLuns = deviceExtension->NumberLuns;
2864 for(
i=0;
i<deviceExtension->NumberLuns;
i++) {
2865 chan->lun[
i] = &(deviceExtension->lun[
c*deviceExtension->NumberLuns+
i]);
2869 chan->AltRegMap = deviceExtension->AltRegMap;
2870 chan->NextDpcChan = -1;
2871 chan->last_devsel = -1;
2872 for(
i=0;
i<deviceExtension->NumberLuns;
i++) {
2873 chan->lun[
i]->DeviceExtension = deviceExtension;
2874 chan->lun[
i]->chan = chan;
2875 chan->lun[
i]->Lun =
i;
2878 deviceExtension->AhciInternalAtaReq0 &&
2879 deviceExtension->AhciInternalSrb0) {
2880 chan->AhciInternalAtaReq = &(deviceExtension->AhciInternalAtaReq0[
c]);
2881 chan->AhciInternalSrb = &(deviceExtension->AhciInternalSrb0[
c]);
2883 chan->AhciInternalSrb->SrbExtension = chan->AhciInternalAtaReq;
2884 chan->AhciInternalAtaReq->Srb = chan->AhciInternalSrb;
2893 ULONG NewNumberChannels
2901 old_luns = deviceExtension->
lun;
2902 old_chans = deviceExtension->
chan;
2904 if(old_luns || old_chans) {
2937 if (!deviceExtension->
lun) {
2945 if (!deviceExtension->
chan) {
2960 if (deviceExtension->
lun) {
2964 if (deviceExtension->
chan) {
VOID NTAPI AtapiViaSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber)
BOOLEAN NTAPI UniataAllocateLunExt(PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
#define ChangePciConfig2(offs, _op)
ULONG NTAPI AtapiFindListedDev(PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG lim, IN PVOID HwDeviceExtension, IN ULONG BusNumber, IN ULONG SlotNumber, OUT PCI_SLOT_NUMBER *_slotData)
IDENTIFY_DATA2 IdentifyData
ULONG NTAPI hpt_cable80(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel)
VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
NTSYSAPI VOID NTAPI RtlCopyMemory(VOID UNALIGNED *Destination, CONST VOID UNALIGNED *Source, ULONG Length)
#define CHAN_NOT_SPECIFIED_CHECK_CABLE
#define PCI_DEV_SUBCLASS_IDE
VOID NTAPI UniataInitSyncBaseIO(IN PHW_CHANNEL chan)
NTSTATUS NTAPI UniataChipDetect(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN BOOLEAN *simplexOnly)
#define CHAN_NOT_SPECIFIED
ULONG opt_MaxTransferMode
#define ChangePciConfig1(offs, _op)
#define ATA_SILICON_IMAGE_ID
struct _SCSI_REQUEST_BLOCK * PSCSI_REQUEST_BLOCK
#define CTRFLAGS_NO_SLAVE
struct _HW_LU_EXTENSION * PHW_LU_EXTENSION
BOOLEAN NTAPI UniataAhciDetect(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo)
enum _BUS_DATA_TYPE BUS_DATA_TYPE
#define IDX_IO2_AltStatus
#define IDX_IO1_o_Command
#define ScsiPortConvertPhysicalAddressToUlong(Address)
PBUSMASTER_CONTROLLER_INFORMATION BMList
static BUSMASTER_CONTROLLER_INFORMATION_BASE const AtiSouthAdapters[]
PSCSI_REQUEST_BLOCK AhciInternalSrb0
VOID NTAPI AtapiSetupLunPtrs(IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
#define IDX_SATA_SControl
VOID NTAPI UniAtaReadLunConfig(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel, IN ULONG DeviceNumber)
ULONG DDKFASTAPI AtapiReadPort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
VOID NTAPI UniataSataWritePort4(IN PHW_CHANNEL chan, IN ULONG io_port_ndx, IN ULONG data, IN ULONG pm_port)
VOID NTAPI ScsiPortFreeDeviceBase(IN PVOID HwDeviceExtension, IN PVOID MappedAddress)
#define IDX_IO1_o_Feature
#define ATA_SERVERWORKS_ID
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
VOID UniataInitIoRes(IN PHW_CHANNEL chan, IN ULONG idx, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
#define SetPciConfig1(offs, op)
BOOLEAN g_opt_AtapiDmaRawRead
IORES BaseIoAddressSATA_0
USHORT NumberOfCurrentHeads
VOID NTAPI UniataFreeLunExt(PHW_DEVICE_EXTENSION deviceExtension)
VOID NTAPI UniataAhciReset(IN PVOID HwDeviceExtension, IN ULONG lChannel)
#define offsetof(TYPE, MEMBER)
VOID NTAPI UniataInitMapBase(IN PHW_CHANNEL chan, IN PIDE_REGISTERS_1 BaseIoAddress1, IN PIDE_REGISTERS_2 BaseIoAddress2)
VOID NTAPI AtapiAliSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber, IN ULONG c)
#define SetPciConfig2(offs, op)
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
VOID NTAPI AtapiRosbSouthBridgeFixup(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG SystemIoBusNumber, IN ULONG slotNumber)
#define BMLIST_TERMINATOR
#define DFLAGS_MANUAL_CHS
#define UNIATA_ALLOCATE_NEW_LUNS
#define ChangePciConfig4(offs, _op)
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
ULONG NTAPI AtapiRegCheckDevValue(IN PVOID HwDeviceExtension, IN ULONG chan, IN ULONG dev, IN PCWSTR Name, IN ULONG Default)
BOOLEAN NTAPI UniataAhciInit(IN PVOID HwDeviceExtension)
#define SetPciConfig4(offs, op)
#define GetPciConfig4(offs, op)
USHORT NTAPI UniataEnableIoPCI(IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
USHORT FirmwareRevision[4]
#define PCI_DEV_HW_SPEC_BM(idhi, idlo, rev, mode, name, flags)
union _PCI_SLOT_NUMBER::@3659 u
VOID NTAPI UniataInitMapBM(IN PHW_DEVICE_EXTENSION deviceExtension, IN PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0, IN BOOLEAN MemIo)
#define DEVNUM_NOT_SPECIFIED
VOID DDKFASTAPI AtapiWritePort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
BOOLEAN opt_WriteCacheEnable
#define ATA_MODE_NOT_SPEC
BOOLEAN NTAPI generic_cable80(IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG channel, IN ULONG pci_reg, IN ULONG bit_offs)
#define IDX_BM_DeviceSpecific0
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel) ?(CompletionRoutine !=NULL) :TRUE)
#define STATUS_UNSUCCESSFUL
#define IDX_BM_DeviceSpecific1
GLenum const GLvoid * addr
struct _HW_CHANNEL * PHW_CHANNEL
#define ExAllocatePool(type, size)
#define memcpy(s1, s2, n)
#define SATA_MAX_PM_UNITS
ULONG DmaSegmentAlignmentMask
UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
BOOLEAN opt_AtapiDmaControlCmd
USHORT NumberOfCurrentCylinders
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
#define ATA_C_F_APM_CNT_MIN_NO_STANDBY
BOOLEAN opt_AtapiDmaRawRead
ULONG NTAPI ScsiPortGetBusData(IN PVOID DeviceExtension, IN ULONG BusDataType, IN ULONG SystemIoBusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
BOOLEAN NTAPI UniataChipDetectChannels(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo)
BOOLEAN opt_AtapiDmaZeroTransfer
VOID UniataAhciSetupCmdPtr(IN OUT PATA_REQ AtaReq)
#define PCISLOTNUM_NOT_SPECIFIED
BOOLEAN opt_ReadCacheEnable
VOID UniataInitIoResEx(IN PIORES IoRes, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
#define Ata_is_ahci_dev(pciData)
#define ATA_C_F_AAM_CNT_MAX_POWER_SAVE
USHORT CurrentSectorsPerTrack
struct _BUSMASTER_CONTROLLER_INFORMATION_BASE * PBUSMASTER_CONTROLLER_INFORMATION_BASE
#define GetPciConfig2(offs, op)
ULONG DDKFASTAPI AtapiReadPortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
#define GetPciConfig1(offs, op)
#define AtapiStallExecution(dt)
struct _PCI_SLOT_NUMBER::@3659::@3660 bits
ULONGIO_PTR NTAPI AtapiGetIoRange(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
NTHALAPI ULONG NTAPI HalGetBusData(BUS_DATA_TYPE, ULONG, ULONG, PVOID, ULONG)
#define RtlZeroMemory(Destination, Length)
BUSMASTER_CONTROLLER_INFORMATION_BASE const BusMasterAdapters[]
__inline ULONG Ata_is_dev_listed(IN PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG VendorId, ULONG DeviceId, ULONG RevId, ULONG lim)
#define IDE_MAX_LUN_PER_CHAN
ULONG MaximumDmaTransferLength
GLboolean GLboolean GLboolean GLboolean a
_In_ PCHAR _In_ ULONG DeviceNumber
union _ATA_REQ * PATA_REQ
BOOLEAN NTAPI AtapiReadChipConfig(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
ULONG opt_PreferedTransferMode
ULONG g_opt_VirtualMachine
BOOLEAN opt_AtapiDmaReadWrite
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]
#define IDX_IO2_o_Control
BOOLEAN NTAPI AtapiChipInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
ULONG const NUM_BUSMASTER_ADAPTERS
#define UNIATA_SIMPLEX_ONLY
#define PCI_COMMON_HDR_LENGTH
PATA_REQ AhciInternalAtaReq0