ReactOS 0.4.16-dev-1946-g52006dd
id_init.cpp
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1/*++
2
3Copyright (c) 2004-2018 Alexandr A. Telyatnikov (Alter)
4
5Module Name:
6 id_init.cpp
7
8Abstract:
9 This is the chip-specific init module for ATA/ATAPI IDE controllers
10 with Busmaster DMA and Serial ATA support
11
12Author:
13 Alexander A. Telyatnikov (Alter)
14
15Environment:
16 kernel mode only
17
18Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31Revision History:
32
33 Some parts of code were taken from FreeBSD 5.1-6.1 ATA driver by
34 Søren Schmidt, Copyright (c) 1998-2007
35 added IT8172 IDE controller support from Linux
36 added VIA 8233/8235 fix from Linux
37 added 80-pin cable detection from Linux for
38 VIA, nVidia
39 added support for non-standard layout of registers
40 added SATA support
41 added AHCI support
42
43Licence:
44 GPLv2
45
46--*/
47
48#include "stdafx.h"
49
50static BUSMASTER_CONTROLLER_INFORMATION_BASE const AtiSouthAdapters[] = {
51 PCI_DEV_HW_SPEC_BM( 4385, 1002, 0x00, ATA_MODE_NOT_SPEC, "ATI South", 0 ),
52 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR, NULL , BMLIST_TERMINATOR )
53 };
54
55
56BOOLEAN
57NTAPI
58UniataChipDetectChannels(
59 IN PVOID HwDeviceExtension,
60 IN PPCI_COMMON_CONFIG pciData, // optional
61 IN ULONG DeviceNumber,
62 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
63 )
64{
65 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
66 //ULONG slotNumber = deviceExtension->slotNumber;
67 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
68 ULONG VendorID = deviceExtension->DevID & 0xffff;
69 //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
70 //ULONG RevID = deviceExtension->RevID;
71 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
72 ULONG ChipFlags= deviceExtension->HwFlags & CHIPFLAG_MASK;
73 ULONG i,n;
74
75 KdPrint2((PRINT_PREFIX "UniataChipDetectChannels:\n" ));
76
77 deviceExtension->AHCI_PI_mask = 0;
78
79 if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI)) {
80 if(!deviceExtension->NumberChannels) {
81 KdPrint2((PRINT_PREFIX "uninitialized SATA/AHCI port number -> 1\n"));
82 deviceExtension->NumberChannels = 1;
83 }
84 if(AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"IgnoreAhciPM", 1 /* DEBUG */)) {
85 KdPrint2((PRINT_PREFIX "SATA/AHCI w/o PM, max luns 1 or 2\n"));
86 deviceExtension->NumberLuns = 2; // we may be in Legacy mode
87 //chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
88 } else {
89 KdPrint2((PRINT_PREFIX "SATA/AHCI -> possible PM, max luns %d\n", SATA_MAX_PM_UNITS));
90 deviceExtension->NumberLuns = SATA_MAX_PM_UNITS;
91 //deviceExtension->NumberLuns = 1;
92 }
93 }
94 if(deviceExtension->MasterDev) {
95 KdPrint2((PRINT_PREFIX "MasterDev -> 1 chan\n"));
96 deviceExtension->NumberChannels = 1;
97 }
98 for(n=0; n<deviceExtension->NumberChannels; n++) {
99 if(AtapiRegCheckDevValue(deviceExtension, n, DEVNUM_NOT_SPECIFIED, L"Exclude", 0)) {
100 KdPrint2((PRINT_PREFIX "Channel %d excluded\n", n));
101 deviceExtension->AHCI_PI_mask &= ~((ULONG)1 << n);
102 } else {
103 deviceExtension->AHCI_PI_mask |= ((ULONG)1 << n);
104 }
105 }
106 KdPrint2((PRINT_PREFIX "PortMask %#x\n", deviceExtension->AHCI_PI_mask));
107 deviceExtension->AHCI_PI_mask =
108 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"PortMask", (ULONG)0xffffffff >> (32-deviceExtension->NumberChannels) );
109 KdPrint2((PRINT_PREFIX "Force PortMask %#x\n", deviceExtension->AHCI_PI_mask));
110
111 for(i=deviceExtension->AHCI_PI_mask, n=0; i; n++, i=i>>1);
112 KdPrint2((PRINT_PREFIX "mask -> %d chans\n", n));
113
114 switch(VendorID) {
115 case ATA_ACER_LABS_ID:
116 switch(deviceExtension->DevID) {
117 case 0x528710b9:
118 case 0x528810b9:
119 deviceExtension->NumberChannels = 4;
120 KdPrint2((PRINT_PREFIX "Acer 4 chan\n"));
121 }
122 break;
123 case ATA_PROMISE_ID:
124
125 if(ChipType != PRMIO) {
126 break;
127 }
128 if(!(ChipFlags & UNIATA_SATA)) {
129 deviceExtension->NumberChannels = 4;
130 KdPrint2((PRINT_PREFIX "Promise up to 4 chan\n"));
131 } else
132 if(ChipFlags & PRCMBO) {
133 deviceExtension->NumberChannels = 3;
134 KdPrint2((PRINT_PREFIX "Promise 3 chan\n"));
135 } else {
136 deviceExtension->NumberChannels = 4;
137 KdPrint2((PRINT_PREFIX "Promise 4 chan\n"));
138 }
139 break;
140 case ATA_MARVELL_ID:
141 KdPrint2((PRINT_PREFIX "Marvell\n"));
142 /* AHCI part has own DevID-based workaround */
143 switch(deviceExtension->DevID) {
144 case 0x610111ab:
145 /* 88SX6101 only have 1 PATA channel */
146 if(BMList[deviceExtension->DevIndex].channel) {
147 KdPrint2((PRINT_PREFIX "88SX6101/11 has no 2nd PATA chan\n"));
148 return FALSE;
149 }
150 deviceExtension->NumberChannels = 1;
151 KdPrint2((PRINT_PREFIX "88SX6101 PATA 1 chan\n"));
152 break;
153 }
154 break;
155 case ATA_ATI_ID:
156 KdPrint2((PRINT_PREFIX "ATI\n"));
157 switch(deviceExtension->DevID) {
158 case ATA_ATI_IXP600:
159 KdPrint2((PRINT_PREFIX " IXP600\n"));
160 /* IXP600 only have 1 PATA channel */
161 if(BMList[deviceExtension->DevIndex].channel) {
162 KdPrint2((PRINT_PREFIX "New ATI no 2nd PATA chan\n"));
163 return FALSE;
164 }
165 deviceExtension->NumberChannels = 1;
166 KdPrint2((PRINT_PREFIX "New ATI PATA 1 chan\n"));
167 break;
168
169 case ATA_ATI_IXP700: {
170 UCHAR satacfg = 0;
171 PCI_SLOT_NUMBER slotData;
172 ULONG j, slotNumber;
173
174 KdPrint2((PRINT_PREFIX " IXP700\n"));
175 /*
176 * When "combined mode" is enabled, an additional PATA channel is
177 * emulated with two SATA ports and appears on this device.
178 * This mode can only be detected via SMB controller.
179 */
180 j = AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION_BASE*)&AtiSouthAdapters[0], -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, &slotData);
181 if(j != BMLIST_TERMINATOR) {
182 slotNumber = slotData.u.AsULONG;
183
184 GetPciConfig1(0xad, satacfg);
185 KdPrint(("SATA controller %s (%s%s channel)\n",
186 (satacfg & 0x01) == 0 ? "disabled" : "enabled",
187 (satacfg & 0x08) == 0 ? "" : "combined mode, ",
188 (satacfg & 0x10) == 0 ? "primary" : "secondary"));
189 /*
190 * If SATA controller is enabled but combined mode is disabled,
191 * we have only one PATA channel. Ignore a non-existent channel.
192 */
193 if ((satacfg & 0x09) == 0x01) {
194 if(BMList[deviceExtension->DevIndex].channel) {
195 KdPrint2((PRINT_PREFIX "New ATI no 2nd PATA chan\n"));
196 return FALSE;
197 }
198 deviceExtension->NumberChannels = 1;
199 KdPrint2((PRINT_PREFIX "New ATI PATA 1 chan\n"));
200 break;
201 } else {
202 KdPrint2((PRINT_PREFIX "New ATI 2 chan\n"));
203 deviceExtension->NumberChannels = 2;
204 /*
205 if (BMList[deviceExtension->DevIndex].channel != ((satacfg & 0x10) >> 4)) {
206 ;
207 }
208 */
209
210 }
211 }
212
213 break; }
214 }
215 /* FALLTHROUGH */
216 case ATA_SILICON_IMAGE_ID:
217
218 if(ChipFlags & SIIBUG) {
219 /* work around errata in early chips */
220 deviceExtension->DmaSegmentLength = 15 * DEV_BSIZE;
221 deviceExtension->DmaSegmentAlignmentMask = 8192-1;
222 }
223 if(ChipType != SIIMIO) {
224 break;
225 }
226 if(!pciData) {
227 break;
228 }
229
230 if(VendorID == ATA_SILICON_IMAGE_ID) {
231 KdPrint2((PRINT_PREFIX "New SII\n"));
232 } else {
233 KdPrint2((PRINT_PREFIX "ATI SATA\n"));
234 }
235 if(deviceExtension->HwFlags & SII4CH) {
236 deviceExtension->NumberChannels = 4;
237 KdPrint2((PRINT_PREFIX "4 chan\n"));
238 }
239 break;
240 case ATA_VIA_ID:
241 if(/*(deviceExtension->DevID == 0x32491106) &&
242 ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)*/
243 deviceExtension->HwFlags & VIABAR) {
244 deviceExtension->NumberChannels = 3;
245 KdPrint2((PRINT_PREFIX "VIA 3 chan\n"));
246 }
247 if(ChipFlags & VIASATA) {
248 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
249 // do nothing, generic PATA INIT
250 KdPrint2((PRINT_PREFIX "VIA SATA without SATA regs -> no PM\n"));
251 deviceExtension->NumberLuns = 1;
252 }
253 break;
254 case ATA_ITE_ID:
255 /* ITE ATA133 controller */
256 if(deviceExtension->DevID == 0x82131283) {
257 if(BMList[deviceExtension->DevIndex].channel) {
258 KdPrint2((PRINT_PREFIX "New ITE has no 2nd PATA chan\n"));
259 return FALSE;
260 }
261 deviceExtension->NumberChannels = 1;
262 KdPrint2((PRINT_PREFIX "New ITE PATA 1 chan\n"));
263 }
264 break;
265#if 0
266 case ATA_INTEL_ID:
267 /* New Intel PATA controllers */
268 if(g_opt_VirtualMachine != VM_VBOX &&
269 /*deviceExtension->DevID == 0x27df8086 ||
270 deviceExtension->DevID == 0x269e8086 ||
271 deviceExtension->DevID == ATA_I82801HBM*/
272 ChipFlags & I1CH) {
273 if(BMList[deviceExtension->DevIndex].channel) {
274 KdPrint2((PRINT_PREFIX "New Intel PATA has no 2nd chan\n"));
275 return FALSE;
276 }
277 deviceExtension->NumberChannels = 1;
278 KdPrint2((PRINT_PREFIX "New Intel PATA 1 chan\n"));
279 }
280 break;
281#endif // this code is removed from newer FreeBSD
282#if 0
283 case ATA_JMICRON_ID:
284 /* New JMicron PATA controllers */
285 if(deviceExtension->DevID == ATA_JMB361 ||
286 deviceExtension->DevID == ATA_JMB363 ||
287 deviceExtension->DevID == ATA_JMB365 ||
288 deviceExtension->DevID == ATA_JMB366 ||
289 deviceExtension->DevID == ATA_JMB368) {
290
291 ULONG tmp32, port_mask;
292
293 port_mask = BMList[deviceExtension->DevIndex].channel;
294
295 GetPciConfig4(0x40, tmp32);
296
297 deviceExtension->NumberChannels = 2;
298 //KdPrint2((PRINT_PREFIX "New JMicron PATA 1 chan\n"));
299 }
300 break;
301#endif // this code is unnecessary since port mapping is implemented
302 case ATA_CYRIX_ID:
303 if(ChipType == CYRIX_OLD) {
304 UCHAR tmp8;
305 ULONG slotNumber;
306 slotNumber = deviceExtension->slotNumber;
307 KdPrint2((PRINT_PREFIX "Cyrix slot %#x\n", slotNumber));
308 GetPciConfig1(0x60, tmp8);
309 if(tmp8 & (1 << BMList[deviceExtension->DevIndex].channel)) {
310 KdPrint2((PRINT_PREFIX "Old Cyrix chan %d ok\n", BMList[deviceExtension->DevIndex].channel));
311 } else {
312 KdPrint2((PRINT_PREFIX "Old Cyrix no chan %d\n", BMList[deviceExtension->DevIndex].channel));
313 return FALSE;
314 }
315 }
316 break;
317 } // end switch(VendorID)
318
319 i = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"NumberChannels", n);
320 if(!i) {
321 i = n;
322 }
323 KdPrint2((PRINT_PREFIX "reg -> %d chans\n", n));
324
325 deviceExtension->NumberChannels = min(i, deviceExtension->NumberChannels);
326 if(!deviceExtension->NumberChannels) {
327 KdPrint2((PRINT_PREFIX "all channels blocked\n", n));
328 return FALSE;
329 }
330 deviceExtension->AHCI_PI_mask &= (ULONG)0xffffffff >> (32-deviceExtension->NumberChannels);
331 KdPrint2((PRINT_PREFIX "Final PortMask %#x\n", deviceExtension->AHCI_PI_mask));
332
333 return TRUE;
334
335} // end UniataChipDetectChannels()
336
337NTSTATUS
338NTAPI
339UniataChipDetect(
340 IN PVOID HwDeviceExtension,
341 IN PPCI_COMMON_CONFIG pciData, // optional
342 IN ULONG DeviceNumber,
343 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
344 IN BOOLEAN* simplexOnly
345 )
346{
347 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
348 ULONG slotNumber = deviceExtension->slotNumber;
349 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
350 ULONG VendorID = deviceExtension->DevID & 0xffff;
351 ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
352 ULONG RevID = deviceExtension->RevID;
353 ULONG i, c;
354 BUSMASTER_CONTROLLER_INFORMATION_BASE* DevTypeInfo;
355 PHW_CHANNEL chan;
356 ULONG ChipType;
357 ULONG ChipFlags;
358 ULONG tmp32;
359 UCHAR tmp8;
360 ULONG_PTR BaseMemAddress;
361 ULONG_PTR BaseIoAddress1;
362 ULONG_PTR BaseIoAddress2;
363 ULONG_PTR BaseIoAddressBM;
364 BOOLEAN MemIo = FALSE;
365 BOOLEAN IsPata = FALSE;
366
367 KdPrint2((PRINT_PREFIX "UniataChipDetect:\n" ));
368 KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags));
369
370 i = Ata_is_dev_listed((PBUSMASTER_CONTROLLER_INFORMATION_BASE)&BusMasterAdapters[0], VendorID, 0xffff, 0, NUM_BUSMASTER_ADAPTERS);
371
372 c = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"ForceSimplex", 0);
373 if(c) {
374 *simplexOnly = TRUE;
375 }
376
377 // defaults
378 BaseIoAddressBM = pciData->u.type0.BaseAddresses[4] & ~0x07;
379 deviceExtension->MaxTransferMode = BaseIoAddressBM ? ATA_DMA : ATA_PIO4;
380 ConfigInfo->MaximumTransferLength = DEV_BSIZE*256;
381 deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength;
382 //deviceExtension->NumberOfPhysicalBreaks = min(deviceExtension->MaximumDmaTransferLength/PAGE_SIZE+1, ATA_DMA_ENTRIES);
383 deviceExtension->DmaSegmentLength = 0x10000;
384 deviceExtension->DmaSegmentAlignmentMask = 0xffff;
385
386 KdPrint2((PRINT_PREFIX "i: %#x\n", i));
387 if(i != BMLIST_TERMINATOR) {
388 DevTypeInfo = (PBUSMASTER_CONTROLLER_INFORMATION_BASE)&BusMasterAdapters[i];
389 } else {
390unknown_dev:
391 if(Ata_is_ahci_dev(pciData)) {
392 KdPrint2((PRINT_PREFIX " AHCI candidate"));
393
394 deviceExtension->NumberChannels = 0;
395 if(!UniataAhciDetect(HwDeviceExtension, pciData, ConfigInfo)) {
396 KdPrint2((PRINT_PREFIX " AHCI init failed - not detected\n"));
397 return STATUS_UNSUCCESSFUL;
398 }
399 KdPrint2((PRINT_PREFIX " unknown AHCI dev, addr %#x ", deviceExtension->BaseIoAHCI_0.Addr));
400 }
401 KdPrint2((PRINT_PREFIX " unknown dev, BM addr %#x ", BaseIoAddressBM));
402 DevTypeInfo = NULL;
403 KdPrint2((PRINT_PREFIX " MaxTransferMode %#x\n", deviceExtension->MaxTransferMode));
404
405 if(!UniataChipDetectChannels(HwDeviceExtension, pciData, DeviceNumber, ConfigInfo)) {
406 return STATUS_UNSUCCESSFUL;
407 }
408 if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
409 return STATUS_UNSUCCESSFUL;
410 }
411 return STATUS_SUCCESS;
412 }
413
414 static BUSMASTER_CONTROLLER_INFORMATION_BASE const SiSAdapters[] = {
415 PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_SA150, "SiS 1183 IDE" , SIS133NEW),
416 PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150, "SiS 1182" , SISSATA | UNIATA_SATA),
417 PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150, "SiS 183 RAID" , SISSATA | UNIATA_SATA),
418 PCI_DEV_HW_SPEC_BM( 0182, 1039, 0x00, ATA_SA150, "SiS 182" , SISSATA | UNIATA_SATA),
419 PCI_DEV_HW_SPEC_BM( 0181, 1039, 0x00, ATA_SA150, "SiS 181" , SISSATA | UNIATA_SATA),
420 PCI_DEV_HW_SPEC_BM( 0180, 1039, 0x00, ATA_SA150, "SiS 180" , SISSATA | UNIATA_SATA),
421 PCI_DEV_HW_SPEC_BM( 0965, 1039, 0x00, ATA_UDMA6, "SiS 965" , SIS133NEW ),
422 PCI_DEV_HW_SPEC_BM( 0964, 1039, 0x00, ATA_UDMA6, "SiS 964" , SIS133NEW ),
423 PCI_DEV_HW_SPEC_BM( 0963, 1039, 0x00, ATA_UDMA6, "SiS 963" , SIS133NEW ),
424 PCI_DEV_HW_SPEC_BM( 0962, 1039, 0x00, ATA_UDMA6, "SiS 962" , SIS133NEW ),
425
426 PCI_DEV_HW_SPEC_BM( 0745, 1039, 0x00, ATA_UDMA5, "SiS 745" , SIS100NEW ),
427 PCI_DEV_HW_SPEC_BM( 0735, 1039, 0x00, ATA_UDMA5, "SiS 735" , SIS100NEW ),
428 PCI_DEV_HW_SPEC_BM( 0733, 1039, 0x00, ATA_UDMA5, "SiS 733" , SIS100NEW ),
429 PCI_DEV_HW_SPEC_BM( 0730, 1039, 0x00, ATA_UDMA5, "SiS 730" , SIS100OLD ),
430
431 PCI_DEV_HW_SPEC_BM( 0646, 1039, 0x00, ATA_UDMA6, "SiS 645DX", SIS133NEW ),
432/* PCI_DEV_HW_SPEC_BM( 0645, 1039, 0x00, ATA_UDMA6, "SiS 645" , SIS133NEW ),*/
433/* PCI_DEV_HW_SPEC_BM( 0640, 1039, 0x00, ATA_UDMA4, "SiS 640" , SIS_SOUTH ),*/
434 PCI_DEV_HW_SPEC_BM( 0635, 1039, 0x00, ATA_UDMA5, "SiS 635" , SIS100NEW ),
435 PCI_DEV_HW_SPEC_BM( 0633, 1039, 0x00, ATA_UDMA5, "SiS 633" , SIS100NEW ),
436 PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x30, ATA_UDMA5, "SiS 630S" , SIS100OLD ),
437 PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x00, ATA_UDMA4, "SiS 630" , SIS66 ),
438 PCI_DEV_HW_SPEC_BM( 0620, 1039, 0x00, ATA_UDMA4, "SiS 620" , SIS66 ),
439
440 PCI_DEV_HW_SPEC_BM( 0550, 1039, 0x00, ATA_UDMA5, "SiS 550" , SIS66 ),
441 PCI_DEV_HW_SPEC_BM( 0540, 1039, 0x00, ATA_UDMA4, "SiS 540" , SIS66 ),
442 PCI_DEV_HW_SPEC_BM( 0530, 1039, 0x00, ATA_UDMA4, "SiS 530" , SIS66 ),
443
444// PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x04, ATA_UDMA6, "SiS 962L" , SIS133OLD ), // ???
445// PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x00, ATA_UDMA6, "SiS 961" , SIS133OLD ),
446
447 PCI_DEV_HW_SPEC_BM( 5517, 1039, 0x00, ATA_UDMA5, "SiS 961" , SIS100NEW | SIS_BASE ),
448 PCI_DEV_HW_SPEC_BM( 5518, 1039, 0x00, ATA_UDMA6, "SiS 962/3", SIS133NEW | SIS_BASE ),
449 PCI_DEV_HW_SPEC_BM( 5513, 1039, 0xc2, ATA_UDMA2, "SiS 5513" , SIS33 | SIS_BASE ),
450 PCI_DEV_HW_SPEC_BM( 5513, 1039, 0x00, ATA_WDMA2, "SiS 5513" , SIS33 | SIS_BASE ),
451 PCI_DEV_HW_SPEC_BM( 0601, 1039, 0x00, ATA_UDMA2, "SiS 5513" , SIS33 | SIS_BASE ),
452 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR , NULL , BMLIST_TERMINATOR )
453 };
454
455 static BUSMASTER_CONTROLLER_INFORMATION_BASE const ViaAdapters[] = {
456 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x41, ATA_UDMA2, "VIA 82C586B", VIA33 | 0x00 ),
457 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x40, ATA_UDMA2, "VIA 82C586B", VIA33 | VIAPRQ ),
458 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x02, ATA_UDMA2, "VIA 82C586B", VIA33 | 0x00 ),
459 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x00, ATA_WDMA2, "VIA 82C586" , VIA33 | 0x00 ),
460 PCI_DEV_HW_SPEC_BM( 0596, 1106, 0x12, ATA_UDMA4, "VIA 82C596B", VIA66 | VIACLK ),
461 PCI_DEV_HW_SPEC_BM( 0596, 1106, 0x00, ATA_UDMA2, "VIA 82C596" , VIA33 | 0x00 ),
462 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x40, ATA_UDMA5, "VIA 82C686B", VIA100 | VIABUG ),
463 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x10, ATA_UDMA4, "VIA 82C686A", VIA66 | VIACLK ),
464 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x00, ATA_UDMA2, "VIA 82C686" , VIA33 | 0x00 ),
465 PCI_DEV_HW_SPEC_BM( 8231, 1106, 0x00, ATA_UDMA5, "VIA 8231" , VIA100 | VIABUG ),
466 PCI_DEV_HW_SPEC_BM( 3074, 1106, 0x00, ATA_UDMA5, "VIA 8233" , VIA100 | 0x00 ),
467 PCI_DEV_HW_SPEC_BM( 3109, 1106, 0x00, ATA_UDMA5, "VIA 8233C" , VIA100 | 0x00 ),
468 PCI_DEV_HW_SPEC_BM( 3147, 1106, 0x00, ATA_UDMA6, "VIA 8233A" , VIA133 | 0x00 ),
469 PCI_DEV_HW_SPEC_BM( 3177, 1106, 0x00, ATA_UDMA6, "VIA 8235" , VIA133 | 0x00 ),
470 PCI_DEV_HW_SPEC_BM( 3227, 1106, 0x00, ATA_UDMA6, "VIA 8237" , VIA133 | 0x00 ),
471 PCI_DEV_HW_SPEC_BM( 0591, 1106, 0x00, ATA_UDMA6, "VIA 8237A" , VIA133 | 0x00 ),
472 // presence of AHCI controller means something about isa-mapped part
473 PCI_DEV_HW_SPEC_BM( 5337, 1106, 0x00, ATA_UDMA6, "VIA 8237S" , VIA133 | 0x00 ),
474 PCI_DEV_HW_SPEC_BM( 5372, 1106, 0x00, ATA_UDMA6, "VIA 8237" , VIA133 | 0x00 ),
475 PCI_DEV_HW_SPEC_BM( 7372, 1106, 0x00, ATA_UDMA6, "VIA 8237" , VIA133 | 0x00 ),
476 PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_UDMA6, "VIA 8251" , VIA133 | 0x00 ),
477 PCI_DEV_HW_SPEC_BM( 8324, 1106, 0x00, ATA_SA150, "VIA CX700" , VIANEW | VIASATA),
478 PCI_DEV_HW_SPEC_BM( 8353, 1106, 0x00, ATA_SA150, "VIA VX800" , VIANEW | VIASATA),
479 PCI_DEV_HW_SPEC_BM( 8409, 1106, 0x00, ATA_UDMA6, "VIA VX855" , VIA133 | 0x00 ),
480 PCI_DEV_HW_SPEC_BM( 8410, 1106, 0x00, ATA_SA300, "VIA VX900" , VIANEW | VIASATA),
481 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR , NULL , BMLIST_TERMINATOR )
482 };
483
484 static BUSMASTER_CONTROLLER_INFORMATION_BASE const ViaSouthAdapters[] = {
485 PCI_DEV_HW_SPEC_BM( 3112, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8361", VIASOUTH ),
486 PCI_DEV_HW_SPEC_BM( 0305, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8363", VIASOUTH ),
487 PCI_DEV_HW_SPEC_BM( 0391, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8371", VIASOUTH ),
488 PCI_DEV_HW_SPEC_BM( 3102, 1106, 0x00, ATA_MODE_NOT_SPEC, "VIA 8662", VIASOUTH ),
489 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, BMLIST_TERMINATOR, NULL , BMLIST_TERMINATOR )
490 };
491
492 KdPrint2((PRINT_PREFIX "VendorID/DeviceID/Rev %#x/%#x/%#x\n", VendorID, DeviceID, RevID));
493
494 switch(VendorID) {
495
496 case ATA_SIS_ID:
497 /*
498 We shall get here for all SIS controllers, even unlisted.
499 Then perform bus scan to find SIS bridge and decide what to do with controller
500 */
501 KdPrint2((PRINT_PREFIX "ATA_SIS_ID\n"));
502 DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION_BASE*)&SiSAdapters[0];
503 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
504 if(i != BMLIST_TERMINATOR) {
505 deviceExtension->FullDevName = SiSAdapters[i].FullDevName;
506 }
507 goto for_ugly_chips;
508
509 case ATA_VIA_ID:
510 KdPrint2((PRINT_PREFIX "ATA_VIA_ID\n"));
511 // New chips have own DeviceId
512 if(deviceExtension->DevID != ATA_VIA82C571 &&
513 deviceExtension->DevID != ATA_VIACX700IDE &&
514 deviceExtension->DevID != ATA_VIASATAIDE &&
515 deviceExtension->DevID != ATA_VIASATAIDE2 &&
516 deviceExtension->DevID != ATA_VIASATAIDE3) {
517 KdPrint2((PRINT_PREFIX "Via new\n"));
518 break;
519 }
520 KdPrint2((PRINT_PREFIX "Via-old-style %x\n", deviceExtension->DevID));
521 // Traditionally, chips have same DeviceId, we can distinguish between them
522 // only by ISA Bridge DeviceId
523 DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION_BASE*)&ViaSouthAdapters[0];
524 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber,
525 PCISLOTNUM_NOT_SPECIFIED/*slotNumber*/, NULL);
526/* if(i == BMLIST_TERMINATOR) {
527 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
528 }*/
529 if(i != BMLIST_TERMINATOR) {
530 KdPrint2((PRINT_PREFIX "VIASOUTH\n"));
531 deviceExtension->HwFlags |= VIASOUTH;
532 }
533 DevTypeInfo = (BUSMASTER_CONTROLLER_INFORMATION_BASE*)&ViaAdapters[0];
534 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber,
535 PCISLOTNUM_NOT_SPECIFIED/*slotNumber*/, NULL);
536 if(i != BMLIST_TERMINATOR) {
537 deviceExtension->FullDevName = ViaAdapters[i].FullDevName;
538 }
539 goto for_ugly_chips;
540
541 default:
542
543 // do nothing
544 break;
545
546#if 0
547 KdPrint2((PRINT_PREFIX "Default\n"));
548
549 deviceExtension->MaxTransferMode = deviceExtension->BaseIoAddressBM_0 ? ATA_DMA : ATA_PIO4;
550 /* do extra chipset specific setups */
551 switch(deviceExtension->DevID) {
552
553 //case ATA_CYPRESS_ID:
554 case 0xc6931080: /* 82c693 ATA controller */
555 deviceExtension->MaxTransferMode = ATA_WDMA2;
556 break;
557
558 case 0x000116ca: /* Cenatek Rocket Drive controller */
559 deviceExtension->MaxTransferMode = ATA_WDMA2;
560 break;
561
562/* case ATA_CYRIX_ID:
563 DevTypeInfo = &CyrixAdapters[0];
564 break;*/
565 case 0x01021078: /* Cyrix 5530 ATA33 controller */
566 deviceExtension->MaxTransferMode = ATA_UDMA2;
567 break;
568
569 case 0x06401039: /* CMD 640 known bad, no DMA */
570 case 0x06011039:
571 *simplexOnly = TRUE;
572
573 /* FALLTHROUGH */
574
575 case 0x10001042: /* RZ 100x known bad, no DMA */
576 case 0x10011042:
577
578 if(deviceExtension->BaseIoAddressBM_0)
579 ScsiPortFreeDeviceBase(HwDeviceExtension,
580 deviceExtension->BaseIoAddressBM_0);
581
582 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, 0, FALSE, FALSE);
583 deviceExtension->BusMaster = DMA_MODE_NONE;
584 deviceExtension->MaxTransferMode = ATA_PIO4;
585 break;
586
587 case 0x81721283: /* IT8172 IDE controller */
588 deviceExtension->MaxTransferMode = ATA_UDMA2;
589 *simplexOnly = TRUE;
590 break;
591
592 default:
593 return STATUS_NOT_FOUND;
594 }
595 return STATUS_SUCCESS;
596#endif
597 }
598
599 i = Ata_is_dev_listed(DevTypeInfo, VendorID, DeviceID, RevID, -1);
600for_ugly_chips:
601 KdPrint2((PRINT_PREFIX "i: %#x\n", i));
602 if(i == BMLIST_TERMINATOR) {
603 goto unknown_dev;
604 //return STATUS_NOT_FOUND;
605 }
606 deviceExtension->MaxTransferMode = DevTypeInfo[i].MaxTransferMode;
607 deviceExtension->HwFlags |= DevTypeInfo[i].RaidFlags;
608
609 KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags));
610
611 tmp32 = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"HwFlagsOverride", deviceExtension->HwFlags);
612 KdPrint2((PRINT_PREFIX "HwFlagsOverride: %#x\n", tmp32));
613 deviceExtension->HwFlags = tmp32;
614
615 tmp32 = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"HwFlagsAdd", 0);
616 KdPrint2((PRINT_PREFIX "HwFlagsAdd: %#x\n", tmp32));
617 deviceExtension->HwFlags |= tmp32;
618
619 KdPrint2((PRINT_PREFIX "HwFlags (final): %#x\n", deviceExtension->HwFlags));
620 if(deviceExtension->HwFlags & UNIATA_SIMPLEX_ONLY) {
621 KdPrint2((PRINT_PREFIX "UNIATA_SIMPLEX_ONLY\n" ));
622 *simplexOnly = TRUE;
623 }
624
625 KdPrint2((PRINT_PREFIX "MaxTransferMode: %#x\n", deviceExtension->MaxTransferMode));
626 tmp32 = AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"MaxTransferMode", deviceExtension->MaxTransferMode);
627 if(tmp32 != 0xffffffff) {
628 KdPrint2((PRINT_PREFIX "MaxTransferMode (overriden): %#x\n", deviceExtension->MaxTransferMode));
629 deviceExtension->MaxTransferMode = tmp32;
630 }
631
632 if(deviceExtension->MaxTransferMode >= ATA_SA150) {
633 KdPrint2((PRINT_PREFIX "setting UNIATA_SATA flag\n"));
634 deviceExtension->HwFlags |= UNIATA_SATA;
635 }
636
637/*
638 ConfigInfo->MaximumTransferLength = DEV_BSIZE*256;
639 deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength;
640*/
641 ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
642 ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
643
644 /* for even more ugly AHCI-capable chips */
645 if(ChipFlags & UNIATA_AHCI) {
646 /*
647 Seems, some chips may have inoperable/alternative BAR5 in SATA mode
648 This can be detected via PCI SubClass
649 */
650 switch(VendorID) {
651 case ATA_NVIDIA_ID:
652 case ATA_ATI_ID:
653 KdPrint2((PRINT_PREFIX "ATA_xxx_ID check AHCI subclass\n"));
654 if((pciData)->SubClass == PCI_DEV_SUBCLASS_IDE) {
655 KdPrint2((PRINT_PREFIX "Non-AHCI mode\n"));
656 ChipFlags &= ~UNIATA_AHCI;
657 deviceExtension->HwFlags &= ~UNIATA_AHCI;
658 }
659 break;
660 default:
661#ifdef __REACTOS__
662 /* I assume:
663 * - RangeStart == 0LL, "always". (CORE-13346)
664 * - It will be updated by UniataAhciDetect() a few lines below...
665 */
666#else
667 if(!ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)) {
668 KdPrint2((PRINT_PREFIX "No BAR5, try BM\n"));
669 ChipFlags &= ~UNIATA_AHCI;
670 deviceExtension->HwFlags &= ~UNIATA_AHCI;
671 }
672#endif
673 break;
674 }
675 }
676
677 if(ChipFlags & UNIATA_AHCI) {
678
679 deviceExtension->NumberChannels = 0;
680 if(!UniataAhciDetect(HwDeviceExtension, pciData, ConfigInfo)) {
681 KdPrint2((PRINT_PREFIX " AHCI detect failed\n"));
682 return STATUS_UNSUCCESSFUL;
683 }
684
685 } else
686 if(!UniataChipDetectChannels(HwDeviceExtension, pciData, DeviceNumber, ConfigInfo)) {
687 return STATUS_UNSUCCESSFUL;
688 }
689 // UniataAhciDetect() sets proper number of channels
690 if(!UniataAllocateLunExt(deviceExtension, UNIATA_ALLOCATE_NEW_LUNS)) {
691 return STATUS_UNSUCCESSFUL;
692 }
693
694 switch(VendorID) {
695 case ATA_ACER_LABS_ID:
696 if(ChipFlags & UNIATA_SATA) {
697 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
698 BaseIoAddress1 = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
699 0, 0, 0x10);
700 BaseIoAddress2 = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
701 1, 0, 0x10);
702 BaseIoAddressBM = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
703 4, 0, deviceExtension->NumberChannels*sizeof(IDE_BUSMASTER_REGISTERS));
704 for(c=0; c<deviceExtension->NumberChannels; c++) {
705 //ULONG unit01 = (c & 1);
706 ULONG unit10 = (c & 2);
707 chan = &deviceExtension->chan[c];
708
709 for (i=0; i<=IDX_IO1_SZ; i++) {
710 UniataInitIoRes(chan, IDX_IO1+i, BaseIoAddress1 + i + (unit10 ? 8 : 0), FALSE, FALSE);
711 }
712 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseIoAddress2 + 2 + (unit10 ? 4 : 0), FALSE, FALSE);
713 UniataInitSyncBaseIO(chan);
714
715 for (i=0; i<=IDX_BM_IO_SZ; i++) {
716 UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM + i + (c * sizeof(IDE_BUSMASTER_REGISTERS)), FALSE, FALSE);
717 }
718
719 // SATA not supported yet
720
721 //chan->RegTranslation[IDX_BM_Command] = BaseMemAddress + 0x260 + offs7;
722 //chan->RegTranslation[IDX_BM_PRD_Table] = BaseMemAddress + 0x244 + offs7;
723 //chan->RegTranslation[IDX_BM_DeviceSpecific0] = BaseMemAddress + (c << 2);
724
725 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
726 }
727 }
728 break;
729 case ATA_NVIDIA_ID:
730 if(ChipFlags & UNIATA_SATA) {
731 KdPrint2((PRINT_PREFIX "NVIDIA SATA\n"));
732 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
733 5, 0, ((ChipFlags & NV4OFF) ? 0x400 : 0) + 0x40*2);
734 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
735 if(!BaseMemAddress) {
736 return STATUS_UNSUCCESSFUL;
737 }
738 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
739 KdPrint2((PRINT_PREFIX "MemIo\n"));
740 MemIo = TRUE;
741 }
742 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
743 for(c=0; c<deviceExtension->NumberChannels; c++) {
744 chan = &deviceExtension->chan[c];
745
746 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + (c << 6), MemIo, FALSE);
747 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + (c << 6), MemIo, FALSE);
748 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + (c << 6), MemIo, FALSE);
749
750 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
751 }
752 }
753 break;
754 case ATA_PROMISE_ID:
755
756 if(ChipType != PRMIO) {
757 break;
758 }
759 if(!pciData) {
760 break;
761 }
762 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
763
764 /* BAR4 -> res1 */
765 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
766 4, 0, 0x4000);
767 KdPrint2((PRINT_PREFIX "BaseMemAddress[4] %x\n", BaseMemAddress));
768 if(!BaseMemAddress) {
769 return STATUS_UNSUCCESSFUL;
770 }
771 if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
772 KdPrint2((PRINT_PREFIX "MemIo\n"));
773 MemIo = TRUE;
774 }
775 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
776
777 /* BAR3 -> res2 */
778 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
779 3, 0, 0xd0000);
780 KdPrint2((PRINT_PREFIX "BaseMemAddress[3] %x\n", BaseMemAddress));
781 if(!BaseMemAddress) {
782 return STATUS_UNSUCCESSFUL;
783 }
784 if((*ConfigInfo->AccessRanges)[3].RangeInMemory) {
785 KdPrint2((PRINT_PREFIX "MemIo\n"));
786 MemIo = TRUE;
787 }
788 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, BaseMemAddress, MemIo, FALSE);
789
790 if(!(ChipFlags & UNIATA_SATA)) {
791 UCHAR reg48;
792
793 reg48 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
794 deviceExtension->NumberChannels = ((reg48 & 0x01) ? 1 : 0) +
795 ((reg48 & 0x02) ? 1 : 0) +
796 2;
797 KdPrint2((PRINT_PREFIX "Channels -> %d\n", deviceExtension->NumberChannels));
798 }
799
800 for(c=0; c<deviceExtension->NumberChannels; c++) {
801
802 /* res2-based */
803 ULONG offs8, offs7;
804
805 chan = &deviceExtension->chan[c];
806
807 offs8 = c << 8;
808 offs7 = c << 7;
809
810 for (i=0; i<=IDX_IO1_SZ; i++) {
811 UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + 0x200 + (i << 2) + offs8, MemIo, FALSE);
812 }
813 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x238 + offs7, MemIo, FALSE);
814
815 UniataInitSyncBaseIO(chan);
816
817 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x260 + offs7, MemIo, FALSE);
818 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x244 + offs7, MemIo, FALSE);
819 UniataInitIoRes(chan, IDX_BM_DeviceSpecific0, BaseMemAddress + (c << 2), MemIo, FALSE);
820
821 if((ChipFlags & PRSATA) ||
822 ((ChipFlags & PRCMBO) && c<2)) {
823 KdPrint2((PRINT_PREFIX "Promise SATA\n"));
824
825 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x400 + offs7, MemIo, FALSE);
826 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x404 + offs7, MemIo, FALSE);
827 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x408 + offs7, MemIo, FALSE);
828
829 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
830 } else {
831 KdPrint2((PRINT_PREFIX "Promise PATA\n"));
832 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA6);
833 }
834 }
835 break;
836
837 case ATA_ATI_ID:
838 KdPrint2((PRINT_PREFIX "ATI\n"));
839 if(ChipType == ATI700) {
840 KdPrint2((PRINT_PREFIX "ATI700\n"));
841 if(!(ChipFlags & UNIATA_AHCI)) {
842 KdPrint2((PRINT_PREFIX "IXP700 PATA\n"));
843 chan = &deviceExtension->chan[0];
844 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
845 }
846 break;
847 }
848 /* FALLTHROUGH */
849 case ATA_SILICON_IMAGE_ID: {
850
851 if(ChipFlags & SIIBUG) {
852 }
853 if(ChipType != SIIMIO) {
854 break;
855 }
856 if(!pciData) {
857 break;
858 }
859
860 if(VendorID == ATA_SILICON_IMAGE_ID) {
861 KdPrint2((PRINT_PREFIX "New SII\n"));
862 } else {
863 KdPrint2((PRINT_PREFIX "ATI SATA\n"));
864 }
865 //if(deviceExtension->HwFlags & SII4CH) {
866 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
867 //}
868 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
869 5, 0, 0x800);
870 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
871 if(!BaseMemAddress) {
872 return STATUS_UNSUCCESSFUL;
873 }
874 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
875 KdPrint2((PRINT_PREFIX "MemIo\n"));
876 MemIo = TRUE;
877 }
878 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
879
880 for(c=0; c<deviceExtension->NumberChannels; c++) {
881 ULONG unit01 = (c & 1);
882 ULONG unit10 = (c & 2);
883
884 chan = &deviceExtension->chan[c];
885
886 if(deviceExtension->AltRegMap) {
887 for (i=0; i<=IDX_IO1_SZ; i++) {
888 UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + 0x80 + i + (unit01 << 6) + (unit10 << 8), MemIo, FALSE);
889 }
890 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x8a + (unit01 << 6) + (unit10 << 8), MemIo, FALSE);
891 UniataInitSyncBaseIO(chan);
892
893 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x00 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
894 UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + 0x02 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
895 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x04 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
896 UniataInitIoRes(chan, IDX_BM_DeviceSpecific0, BaseMemAddress + 0x10 + (unit01 << 3) + (unit10 << 8), MemIo, FALSE);
897 UniataInitIoRes(chan, IDX_BM_DeviceSpecific1, BaseMemAddress + 0x40 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE);
898 }
899
900 if(chan->MaxTransferMode < ATA_SA150) {
901 // do nothing for PATA part
902 KdPrint2((PRINT_PREFIX "No SATA regs for PATA part\n"));
903 } else
904 if(ChipFlags & UNIATA_SATA) {
905 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x104 + (unit01 << 7) + (unit10 << 8), MemIo, FALSE);
906 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x108 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE);
907 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x100 + (unit01 << 2) + (unit10 << 8), MemIo, FALSE);
908
909 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
910 }
911 }
912 break; }
913
914 case ATA_SERVERWORKS_ID: {
915
916 if(ChipType != SWKSMIO) {
917 break;
918 }
919 if(!pciData) {
920 break;
921 }
922
923 KdPrint2((PRINT_PREFIX "ServerWorks\n"));
924
925 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
926 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
927 5, 0, 0x400);
928 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
929 if(!BaseMemAddress) {
930 return STATUS_UNSUCCESSFUL;
931 }
932 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
933 KdPrint2((PRINT_PREFIX "MemIo\n"));
934 MemIo = TRUE;
935 }
936 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
937
938 for(c=0; c<deviceExtension->NumberChannels; c++) {
939 ULONG offs = c*0x100;
940
941 chan = &deviceExtension->chan[c];
942 for (i=0; i<=IDX_IO1_SZ; i++) {
943 UniataInitIoRes(chan, IDX_IO1+i, BaseMemAddress + offs + i*4, MemIo, FALSE);
944 }
945 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + offs + 0x20, MemIo, FALSE);
946 UniataInitSyncBaseIO(chan);
947
948 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + offs + 0x30, MemIo, FALSE);
949 UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + offs + 0x32, MemIo, FALSE);
950 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + offs + 0x34, MemIo, FALSE);
951
952 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + offs + 0x40, MemIo, FALSE);
953 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + offs + 0x44, MemIo, FALSE);
954 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + offs + 0x48, MemIo, FALSE);
955
956 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
957 }
958 break; }
959
960 case ATA_SIS_ID: {
961 //if(ChipType != SIS_SOUTH) {}
962 BOOLEAN SIS_182=FALSE;
963
964 if(!(ChipFlags & SIS_BASE)) {
965 KdPrint2((PRINT_PREFIX "Found SIS_SOUTH\n"));
966 //PrintNtConsole("Found SIS_SOUTH\n");
967 break;
968 }
969 // Make some additional checks
970 KdPrint2((PRINT_PREFIX "ChipType == SIS_BASE\n"));
971 ChangePciConfig1(0x57, (a & 0x7f));
972 GetPciConfig4(0x00, tmp32);
973 if(tmp32 == ATA_SIS5518) {
974 ChipType = SIS133NEW;
975 deviceExtension->HwFlags = (deviceExtension->HwFlags & ~CHIPTYPE_MASK) | SIS133NEW;
976 deviceExtension->MaxTransferMode = ATA_UDMA6;
977 KdPrint2((PRINT_PREFIX "UniataChipDetect: SiS 962/963 DMA %#x controller\n", deviceExtension->MaxTransferMode));
978 //PrintNtConsole("UniataChipDetect: SiS 962/963 DMA %#x controller\n", deviceExtension->MaxTransferMode);
979 // Restore device ID
980 ChangePciConfig1(0x57, (a | 0x80));
981 } else {
982 static BUSMASTER_CONTROLLER_INFORMATION_BASE const SiSSouthAdapters[] = {
983 PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x10, ATA_MODE_NOT_SPEC, "SiS 961", 0 ),
984// PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x00, ATA_MODE_NOT_SPEC, "SiS 961", 0 ),
985 PCI_DEV_HW_SPEC_BM( ffff, ffff, 0xff, ATA_MODE_NOT_SPEC, NULL , -1 )
986 };
987 // Save settings
988 GetPciConfig1(0x4a, tmp8);
989 ChangePciConfig1(0x4a, (a | 0x10));
990 if(tmp32 == ATA_SIS5513 ||
991 tmp32 == ATA_SIS5517) {
992 i = AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION_BASE*)&SiSSouthAdapters[0],
993 -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
994 if(i != BMLIST_TERMINATOR) {
995 KdPrint2((PRINT_PREFIX "SIS South\n"));
996 deviceExtension->HwFlags = (deviceExtension->HwFlags & ~CHIPTYPE_MASK) | SIS133OLD;
997 deviceExtension->MaxTransferMode = ATA_UDMA6;
998 //deviceExtension->MaxTransferMode = SiSSouthAdapters[i].MaxTransferMode;
999 if(SiSSouthAdapters[i].RaidFlags & UNIATA_SATA) {
1000 KdPrint2((PRINT_PREFIX "SIS South SATA\n"));
1001 deviceExtension->HwFlags |= UNIATA_SATA;
1002 if(SiSSouthAdapters[i].nDeviceId == 0x1182 ||
1003 SiSSouthAdapters[i].nDeviceId == 0x1183) {
1004 KdPrint2((PRINT_PREFIX "SIS_182\n"));
1005 SIS_182 = TRUE;
1006 }
1007 }
1008 } else {
1009 // SiS-South not found
1010 if(tmp32 == ATA_SIS5517) {
1011 deviceExtension->HwFlags = (deviceExtension->HwFlags & ~CHIPTYPE_MASK) | SIS100NEW;
1012 deviceExtension->MaxTransferMode = ATA_UDMA5;
1013 } else {
1014 // generic SiS33
1015 KdPrint2((PRINT_PREFIX "Generic SiS DMA\n"));
1016 }
1017 }
1018 }
1019 // Restore settings
1020 SetPciConfig1(0x4a, tmp8);
1021 KdPrint2((PRINT_PREFIX "UniataChipDetect: SiS 961 DMA %#x controller\n", deviceExtension->MaxTransferMode));
1022 //PrintNtConsole("UniataChipDetect: SiS 961 DMA %#x controller\n", deviceExtension->MaxTransferMode);
1023 if(deviceExtension->HwFlags & UNIATA_SATA) {
1024 KdPrint2((PRINT_PREFIX "SiS SATA\n"));
1025
1026 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1027 5, 0, 0x400);
1028 KdPrint2((PRINT_PREFIX "BaseMemAddress %x\n", BaseMemAddress));
1029 if(BaseMemAddress) {
1030 if((*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1031 KdPrint2((PRINT_PREFIX "MemIo\n"));
1032 MemIo = TRUE;
1033 }
1034 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1035
1036 for(c=0; c<deviceExtension->NumberChannels; c++) {
1037 ULONG offs = c << (SIS_182 ? 5 : 6);
1038
1039 chan = &deviceExtension->chan[c];
1040 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0 + offs, MemIo, FALSE);
1041 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + offs, MemIo, FALSE);
1042 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + offs, MemIo, FALSE);
1043
1044 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1045 }
1046 }
1047 }
1048 }
1049 //ChangePciConfig1(0x57, (a | 0x80));
1050 break; }
1051
1052 case ATA_VIA_ID: {
1053
1054 if(ChipFlags & VIASATA) {
1055 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
1056 // do nothing, generic PATA INIT
1057 KdPrint2((PRINT_PREFIX "VIA SATA without SATA regs\n"));
1058 break;
1059 }
1060 if(ChipFlags & UNIATA_SATA) {
1061
1062 ULONG IoSize = 0;
1063 BaseMemAddress = 0;
1064
1065 switch(DeviceID) {
1066 case 0x3149: // VIA 6420
1067 KdPrint2((PRINT_PREFIX "VIA 6420\n"));
1068 IoSize = 0x80;
1069 break;
1070 case 0x3249: // VIA 6421
1071 KdPrint2((PRINT_PREFIX "VIA 6421\n"));
1072 IoSize = 0x40;
1073 break;
1074 }
1075 if(IoSize) {
1076 KdPrint2((PRINT_PREFIX "IoSize %x\n", IoSize));
1077 /*deviceExtension->*/BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1078 5, 0, IoSize * deviceExtension->NumberChannels);
1079 if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1080 KdPrint2((PRINT_PREFIX "MemIo\n"));
1081 MemIo = TRUE;
1082 }
1083 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1084 }
1085 if(/*deviceExtension->*/BaseMemAddress) {
1086 KdPrint2((PRINT_PREFIX "UniataChipDetect: BAR5 %x\n", /*deviceExtension->*/BaseMemAddress));
1087 if(ChipFlags & VIABAR) {
1088
1089 ULONG BaseIoAddressBM_0;
1090 ULONG BaseIo;
1091
1092 KdPrint2((PRINT_PREFIX "UniataChipDetect: VIABAR\n"));
1093 /*deviceExtension->*/BaseIoAddressBM_0 = /*(PIDE_BUSMASTER_REGISTERS)*/
1094 AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, 4, 0,
1095 sizeof(IDE_BUSMASTER_REGISTERS)*deviceExtension->NumberChannels);
1096 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
1097 for(c=0; c<deviceExtension->NumberChannels; c++) {
1098
1099 chan = &deviceExtension->chan[c];
1100
1101 BaseIo = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber, c, 0, /*0x80*/ sizeof(IDE_REGISTERS_1) + sizeof(IDE_REGISTERS_2)*2);
1102
1103 for (i=0; i<=IDX_IO1_SZ; i++) {
1104 UniataInitIoRes(chan, IDX_IO1+i, BaseIo + i, FALSE, FALSE);
1105 }
1106 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseIo + sizeof(IDE_REGISTERS_1) + 2, FALSE, FALSE);
1107 UniataInitSyncBaseIO(chan);
1108
1109 for (i=0; i<=IDX_BM_IO_SZ; i++) {
1110 UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM_0 + sizeof(IDE_BUSMASTER_REGISTERS)*c + i, FALSE, FALSE);
1111 }
1112
1113 }
1114 }
1115 for(c=0; c<deviceExtension->NumberChannels; c++) {
1116 chan = &deviceExtension->chan[c];
1117 if((ChipFlags & VIABAR) && (c==2)) {
1118 // Do not setup SATA registers for PATA part
1119 for (i=0; i<=IDX_SATA_IO_SZ; i++) {
1120 UniataInitIoRes(chan, IDX_SATA_IO+i, 0, FALSE, FALSE);
1121 }
1122 break;
1123 }
1124 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + (c * IoSize), MemIo, FALSE);
1125 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 4 + (c * IoSize), MemIo, FALSE);
1126 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 8 + (c * IoSize), MemIo, FALSE);
1127
1128 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1129 }
1130
1131 }
1132 }
1133 break; }
1134 case ATA_INTEL_ID: {
1135
1136 if(!(ChipFlags & UNIATA_SATA)) {
1137 break;
1138 }
1139
1140 /* the intel 31244 needs special care if in DPA mode */
1141 if(DeviceID == 3200 && // Intel 31244
1142 pciData->SubClass != PCI_DEV_SUBCLASS_IDE) {
1143
1144 KdPrint2((PRINT_PREFIX "UniataChipDetect: Intel 31244, DPA mode\n"));
1145 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1146 0, 0, 0x0c00);
1147 if(!BaseMemAddress) {
1148 return STATUS_UNSUCCESSFUL;
1149 }
1150 if((*ConfigInfo->AccessRanges)[0].RangeInMemory) {
1151 KdPrint2((PRINT_PREFIX "MemIo\n"));
1152 MemIo = TRUE;
1153 }
1154 deviceExtension->AltRegMap = TRUE; // inform generic resource allocator
1155 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1156
1157 for(c=0; c<deviceExtension->NumberChannels; c++) {
1158 ULONG offs = 0x200 + c*0x200;
1159
1160 chan = &deviceExtension->chan[c];
1161 for (i=0; i<=IDX_IO1_SZ; i++) {
1162 UniataInitIoRes(chan, IDX_BM_IO+i, BaseMemAddress + i*4 + offs, MemIo, FALSE);
1163 }
1164
1165 UniataInitSyncBaseIO(chan);
1166
1167 UniataInitIoRes(chan, IDX_IO1_o_Command, BaseMemAddress + 0x1d + offs, MemIo, FALSE);
1168 UniataInitIoRes(chan, IDX_IO1_o_Feature, BaseMemAddress + 0x06 + offs, MemIo, FALSE);
1169 UniataInitIoRes(chan, IDX_IO2_o_Control, BaseMemAddress + 0x29 + offs, MemIo, FALSE);
1170
1171 UniataInitIoRes(chan, IDX_IO2_AltStatus, BaseMemAddress + 0x28 + offs, MemIo, FALSE);
1172
1173 UniataInitIoRes(chan, IDX_BM_Command, BaseMemAddress + 0x70 + offs, MemIo, FALSE);
1174 UniataInitIoRes(chan, IDX_BM_Status, BaseMemAddress + 0x72 + offs, MemIo, FALSE);
1175 UniataInitIoRes(chan, IDX_BM_PRD_Table, BaseMemAddress + 0x74 + offs, MemIo, FALSE);
1176
1177 UniataInitIoRes(chan, IDX_SATA_SStatus, BaseMemAddress + 0x100 + offs, MemIo, FALSE);
1178 UniataInitIoRes(chan, IDX_SATA_SError, BaseMemAddress + 0x104 + offs, MemIo, FALSE);
1179 UniataInitIoRes(chan, IDX_SATA_SControl, BaseMemAddress + 0x108 + offs, MemIo, FALSE);
1180
1181 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1182 }
1183
1184 break;
1185 }
1186 if(deviceExtension->MaxTransferMode >= ATA_SA150) {
1187
1188 BOOLEAN OrigAHCI = FALSE;
1189
1190 GetPciConfig1(0x90, tmp8);
1191 KdPrint2((PRINT_PREFIX "Intel chip config: %x\n", tmp8));
1192 /* SATA parts can be either compat or AHCI */
1193 MemIo = FALSE;
1194 if(ChipFlags & UNIATA_AHCI) {
1195 OrigAHCI = TRUE;
1196 if(tmp8 & 0xc0) {
1197 //KdPrint2((PRINT_PREFIX "AHCI not supported yet\n"));
1198 //return FALSE;
1199 KdPrint2((PRINT_PREFIX "try run AHCI\n"));
1200 if(ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)) {
1201 break;
1202 }
1203 KdPrint2((PRINT_PREFIX "No BAR5, try BM\n"));
1204 deviceExtension->HwFlags &= ~UNIATA_AHCI;
1205 }
1206 BaseIoAddressBM = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1207 4, 0, sizeof(IDE_BUSMASTER_REGISTERS));
1208 if(BaseIoAddressBM) {
1209 KdPrint2((PRINT_PREFIX "Intel BM check at %x\n", BaseIoAddressBM));
1210 /* check if we really have valid BM registers */
1211 if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
1212 KdPrint2((PRINT_PREFIX "MemIo[4]\n"));
1213 MemIo = TRUE;
1214 }
1215 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, BaseIoAddressBM, MemIo, FALSE);
1216
1217 tmp8 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),IDX_BM_Status);
1218 KdPrint2((PRINT_PREFIX "BM status: %x\n", tmp8));
1219 /* cleanup */
1220 ScsiPortFreeDeviceBase(HwDeviceExtension, (PCHAR)(ULONG_PTR)BaseIoAddressBM);
1221 UniataInitIoResEx(&deviceExtension->BaseIoAddressBM_0, 0, 0, FALSE);
1222
1223 if(tmp8 == 0xff) {
1224 KdPrint2((PRINT_PREFIX "invalid BM status, keep AHCI mode\n"));
1225 break;
1226 }
1227 }
1228 KdPrint2((PRINT_PREFIX "Compatible mode, reallocate LUNs\n"));
1229 deviceExtension->NumberLuns = 2; // we may be in Legacy mode
1230 if(!UniataAllocateLunExt(deviceExtension, 2)) {
1231 KdPrint2((PRINT_PREFIX "can't re-allocate Luns\n"));
1232 return STATUS_UNSUCCESSFUL;
1233 }
1234 }
1235 deviceExtension->HwFlags &= ~UNIATA_AHCI;
1236
1237 MemIo = FALSE;
1238 /* if BAR(5) is IO it should point to SATA interface registers */
1239 if(OrigAHCI) {
1240 /* Skip BAR(5) in compatible mode */
1241 KdPrint2((PRINT_PREFIX "Ignore BAR5 on compatible\n"));
1242 BaseMemAddress = 0;
1243 } else
1244 if(deviceExtension->DevID == 0x28288086 &&
1245 pciData->u.type0.SubVendorID == 0x106b) {
1246 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */
1247 KdPrint2((PRINT_PREFIX "Ignore BAR5 on ICH8M Apples\n"));
1248 BaseMemAddress = 0;
1249 } else {
1250 BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
1251 5, 0, 0x10);
1252 if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
1253 KdPrint2((PRINT_PREFIX "MemIo[5]\n"));
1254 MemIo = TRUE;
1255 }
1256 }
1257 UniataInitIoResEx(&deviceExtension->BaseIoAddressSATA_0, BaseMemAddress, MemIo, FALSE);
1258
1259 for(c=0; c<deviceExtension->NumberChannels; c++) {
1260 chan = &deviceExtension->chan[c];
1261 AtapiSetupLunPtrs(chan, deviceExtension, c);
1262 IsPata = FALSE;
1263 if(ChipFlags & ICH5) {
1264 KdPrint2((PRINT_PREFIX "ICH5\n"));
1265 if ((tmp8 & 0x04) == 0) {
1266 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1267 } else if ((tmp8 & 0x02) == 0) {
1268 if(c != 0) {
1269 IsPata = TRUE;
1270 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
1271 }
1272 } else if ((tmp8 & 0x02) != 0) {
1273 if(c != 1) {
1274 IsPata = TRUE;
1275 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
1276 }
1277 }
1278 } else
1279 if(ChipFlags & I6CH2) {
1280 KdPrint2((PRINT_PREFIX "I6CH2\n"));
1281 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1282 } else {
1283 KdPrint2((PRINT_PREFIX "other Intel\n"));
1284 switch(tmp8 & 0x03) {
1285 case 2:
1286 if(c!=0) {
1287 // PATA
1288 IsPata = TRUE;
1289 }
1290 break;
1291 case 1:
1292 if(c!=1) {
1293 // PATA
1294 IsPata = TRUE;
1295 }
1296 break;
1297 }
1298 }
1299
1300 if(IsPata) {
1301 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
1302 KdPrint2((PRINT_PREFIX "PATA part\n"));
1303 } else {
1304
1305 if(!(ChipFlags & ICH7) && BaseMemAddress) {
1306 KdPrint2((PRINT_PREFIX "BaseMemAddress[5] -> indexed\n"));
1307 UniataInitIoRes(chan, IDX_INDEXED_ADDR, BaseMemAddress + 0, MemIo, FALSE);
1308 UniataInitIoRes(chan, IDX_INDEXED_DATA, BaseMemAddress + 4, MemIo, FALSE);
1309 }
1310 if((ChipFlags & ICH5) || BaseMemAddress) {
1311
1312 KdPrint2((PRINT_PREFIX "io proc()\n"));
1313 // Rather interesting way of register access...
1314 ChipType = INTEL_IDX;
1315 deviceExtension->HwFlags &= ~CHIPTYPE_MASK;
1316 deviceExtension->HwFlags |= ChipType;
1317
1318 if(ChipFlags & ICH7) {
1319 KdPrint2((PRINT_PREFIX "ICH7 way\n"));
1320 }
1321 UniataInitIoRes(chan, IDX_SATA_SStatus, 0x200*c + 0, FALSE, TRUE); // this is fake non-zero value
1322 UniataInitIoRes(chan, IDX_SATA_SError, 0x200*c + 2, FALSE, TRUE);
1323 UniataInitIoRes(chan, IDX_SATA_SControl, 0x200*c + 1, FALSE, TRUE);
1324 }
1325 }
1326
1327 } // end for()
1328
1329 // rest of INIT staff is in AtapiChipInit()
1330
1331 } // ATA_SA150
1332 break; }
1333 case ATA_CYRIX_ID:
1334 /* Cyrix 5530 ATA33 controller */
1335 if(deviceExtension->DevID == 0x01021078) {
1336 ConfigInfo->AlignmentMask = 0x0f;
1337 deviceExtension->MaximumDmaTransferLength = 63*1024;
1338 }
1339 break;
1340 case ATA_JMICRON_ID:
1341 /* New JMicron PATA/SATA controllers */
1342 GetPciConfig1(0xdf, tmp8);
1343 if(tmp8 & 0x40) {
1344 KdPrint((" Check JMicron AHCI\n"));
1345 if(Ata_is_ahci_dev(pciData)) {
1346 ChipFlags |= UNIATA_AHCI;
1347 deviceExtension->HwFlags |= UNIATA_AHCI;
1348 } else {
1349 KdPrint((" JMicron PATA/SATA\n"));
1350 }
1351 } else {
1352#if 0 // do not touch, see Linux sources
1353 /* set controller configuration to a combined setup we support */
1354 SetPciConfig4(0x40, 0x80c0a131);
1355 SetPciConfig4(0x80, 0x01200000);
1356#endif
1357 //GetPciConfig1(0x40, tmp32);
1358 KdPrint((" JMicron Combined\n"));
1359 //return STATUS_NOT_FOUND;
1360 }
1361 break;
1362 }
1363
1364 return STATUS_SUCCESS;
1365
1366} // end UniataChipDetect()
1367
1368
1369/*
1370 Do some 'magic staff' for VIA SouthBridge
1371 This will prevent data losses
1372*/
1373VOID
1374NTAPI
1375AtapiViaSouthBridgeFixup(
1376 IN PVOID HwDeviceExtension,
1377 IN BUS_DATA_TYPE BusDataType,
1378 IN ULONG SystemIoBusNumber,
1379 IN ULONG slotNumber
1380 )
1381{
1382 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1383 PCI_COMMON_CONFIG pciData;
1384 ULONG funcNumber;
1385 ULONG busDataRead;
1386
1387 ULONG VendorID;
1388 ULONG DeviceID;
1389 PCI_SLOT_NUMBER slotData;
1390 ULONG dev_id;
1391 BOOLEAN found = FALSE;
1392
1393 slotData.u.AsULONG = slotNumber;
1394 for(funcNumber = 0; funcNumber < PCI_MAX_FUNCTION; funcNumber++) {
1395
1396 slotData.u.bits.FunctionNumber = funcNumber;
1397
1398 busDataRead = ScsiPortGetBusData(HwDeviceExtension,
1399 PCIConfiguration,
1400 SystemIoBusNumber,
1401 slotData.u.AsULONG,
1402 &pciData,
1403 PCI_COMMON_HDR_LENGTH);
1404
1405 if (busDataRead < (ULONG)PCI_COMMON_HDR_LENGTH) {
1406 continue;
1407 }
1408
1409 VendorID = pciData.VendorID;
1410 DeviceID = pciData.DeviceID;
1411 dev_id = (VendorID | (DeviceID << 16));
1412
1413 if (dev_id == 0x03051106 || /* VIA VT8363 */
1414 dev_id == 0x03911106 || /* VIA VT8371 */
1415 dev_id == 0x31021106 || /* VIA VT8662 */
1416 dev_id == 0x31121106) { /* VIA VT8361 */
1417 UCHAR reg76;
1418
1419 GetPciConfig1(0x76, reg76);
1420
1421 if ((reg76 & 0xf0) != 0xd0) {
1422 SetPciConfig1(0x75, 0x80);
1423 SetPciConfig1(0x76, (reg76 & 0x0f) | 0xd0);
1424 }
1425 found = TRUE;
1426 break;
1427 }
1428 }
1429 if(!found) {
1430 deviceExtension->HwFlags &= ~VIABUG;
1431 }
1432} // end AtapiViaSouthBridgeFixup()
1433
1434/*
1435 Do some 'magic staff' for ROSB SouthBridge
1436 This will prevent data losses
1437*/
1438VOID
1439NTAPI
1440AtapiRosbSouthBridgeFixup(
1441 IN PVOID HwDeviceExtension,
1442 IN BUS_DATA_TYPE BusDataType,
1443 IN ULONG SystemIoBusNumber,
1444 IN ULONG slotNumber
1445 )
1446{
1447 //PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1448 PCI_COMMON_CONFIG pciData;
1449 ULONG funcNumber;
1450 ULONG busDataRead;
1451
1452 ULONG VendorID;
1453 ULONG DeviceID;
1454 PCI_SLOT_NUMBER slotData;
1455 ULONG dev_id;
1456// BOOLEAN found = FALSE;
1457
1458 /* locate the ISA part in the southbridge and enable UDMA33 */
1459 slotData.u.AsULONG = slotNumber;
1460 for(funcNumber = 0; funcNumber < PCI_MAX_FUNCTION; funcNumber++) {
1461
1462 slotData.u.bits.FunctionNumber = funcNumber;
1463
1464 busDataRead = ScsiPortGetBusData(HwDeviceExtension,
1465 PCIConfiguration,
1466 SystemIoBusNumber,
1467 slotData.u.AsULONG,
1468 &pciData,
1469 PCI_COMMON_HDR_LENGTH);
1470
1471 if (busDataRead < (ULONG)PCI_COMMON_HDR_LENGTH) {
1472 continue;
1473 }
1474
1475 VendorID = pciData.VendorID;
1476 DeviceID = pciData.DeviceID;
1477 dev_id = (VendorID | (DeviceID << 16));
1478
1479 if (dev_id == ATA_ROSB4_ISA) { /* */
1480 ChangePciConfig4(0x64, ((a & ~0x00002000) | 0x00004000));
1481 break;
1482 }
1483 }
1484} // end AtapiRosbSouthBridgeFixup()
1485
1486/*
1487 Do some 'magic staff' for ROSB SouthBridge
1488 This will prevent data losses
1489*/
1490VOID
1491NTAPI
1492AtapiAliSouthBridgeFixup(
1493 IN PVOID HwDeviceExtension,
1494 IN BUS_DATA_TYPE BusDataType,
1495 IN ULONG SystemIoBusNumber,
1496 IN ULONG slotNumber,
1497 IN ULONG c
1498 )
1499{
1500 //PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1501 PCI_COMMON_CONFIG pciData;
1502 ULONG funcNumber;
1503 ULONG busDataRead;
1504
1505 ULONG VendorID;
1506 ULONG DeviceID;
1507 PCI_SLOT_NUMBER slotData;
1508 ULONG dev_id;
1509// BOOLEAN found = FALSE;
1510
1511 /* workaround for datacorruption bug found on at least SUN Blade-100
1512 * find the ISA function on the southbridge and disable then enable
1513 * the ATA channel tristate buffer */
1514 slotData.u.AsULONG = slotNumber;
1515 for(funcNumber = 0; funcNumber < PCI_MAX_FUNCTION; funcNumber++) {
1516
1517 slotData.u.bits.FunctionNumber = funcNumber;
1518
1519 busDataRead = ScsiPortGetBusData(HwDeviceExtension,
1520 PCIConfiguration,
1521 SystemIoBusNumber,
1522 slotData.u.AsULONG,
1523 &pciData,
1524 PCI_COMMON_HDR_LENGTH);
1525
1526 if (busDataRead < (ULONG)PCI_COMMON_HDR_LENGTH) {
1527 continue;
1528 }
1529
1530 VendorID = pciData.VendorID;
1531 DeviceID = pciData.DeviceID;
1532 dev_id = (VendorID | (DeviceID << 16));
1533
1534 if (dev_id == ATA_ALI_1533) { /* SOUTH */
1535 ChangePciConfig1(0x58, (a & ~(0x04 << c)));
1536 ChangePciConfig1(0x58, (a | (0x04 << c)));
1537 break;
1538 }
1539 }
1540} // end AtapiRosbSouthBridgeFixup()
1541
1542ULONG
1543NTAPI
1544hpt_cable80(
1545 IN PHW_DEVICE_EXTENSION deviceExtension,
1546 IN ULONG channel // physical channel number (0-1)
1547 )
1548{
1549 PVOID HwDeviceExtension = (PVOID)deviceExtension;
1550 ULONG slotNumber = deviceExtension->slotNumber;
1551 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1552
1553 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1554
1555 UCHAR reg, val, res;
1556 PCI_SLOT_NUMBER slotData;
1557
1558 PHW_CHANNEL chan;
1559 ULONG c; // logical channel (for Compatible Mode controllers)
1560
1561 c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1562 chan = &deviceExtension->chan[c];
1563
1564 slotData.u.AsULONG = deviceExtension->slotNumber;
1565
1566 if(deviceExtension->HwFlags & UNIATA_NO80CHK) {
1567 KdPrint2((PRINT_PREFIX "UNIATA_NO80CHK\n"));
1568 return TRUE;
1569 }
1570
1571 if(ChipType == HPT374 && slotData.u.bits.FunctionNumber == 1) {
1572 reg = channel ? 0x57 : 0x53;
1573 GetPciConfig1(reg, val);
1574 SetPciConfig1(reg, val | 0x80);
1575 }
1576 else {
1577 reg = 0x5b;
1578 GetPciConfig1(reg, val);
1579 SetPciConfig1(reg, val & 0xfe);
1580 }
1581 GetPciConfig1(0x5a, res);
1582 res = res & (channel ? 0x01 : 0x02);
1583 SetPciConfig1(reg, val);
1584 if(chan->Force80pin) {
1585 KdPrint2((PRINT_PREFIX "Force80pin\n"));
1586 res = 0;
1587 }
1588 KdPrint2((PRINT_PREFIX "hpt_cable80(%d) = %d\n", channel, !res));
1589 return !res;
1590} // end hpt_cable80()
1591
1592/*
1593ULONG
1594NTAPI
1595via_cable80(
1596 IN PHW_DEVICE_EXTENSION deviceExtension,
1597 IN ULONG channel // physical channel number (0-1)
1598 )
1599{
1600 PVOID HwDeviceExtension = (PVOID)deviceExtension;
1601 ULONG slotNumber = deviceExtension->slotNumber;
1602 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1603
1604 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1605
1606 ULONG reg50;
1607 ULONG a;
1608 ULONG i, j;
1609 BOOLEAN res;
1610
1611 GetPciConfig1(0x50, reg50);
1612
1613 switch(ChipType) {
1614 case VIA133:
1615 a = 8;
1616 break;
1617 case VIA100:
1618 a = 4;
1619 break;
1620 case VIA66:
1621 a = 2;
1622 break;
1623 default:
1624 return false;
1625 }
1626
1627 res = FALSE;
1628 for (j=0; j>=2; i -= 8) {
1629 i = (3-(channel*2+j))*8;
1630 if (((reg50 >> (i & 0x10)) & 8) &&
1631 ((reg50 >> i) & 0x20) &&
1632 (((reg50 >> i) & 7) < a)) {
1633
1634 res |= TRUE; //(1 << (1 - (i >> 4)));
1635 }
1636 }
1637 KdPrint2((PRINT_PREFIX "via_cable80(%d) = %d\n", channel, res));
1638 return res;
1639
1640} // end via_cable80()
1641*/
1642
1643BOOLEAN
1644NTAPI
1645generic_cable80(
1646 IN PHW_DEVICE_EXTENSION deviceExtension,
1647 IN ULONG channel, // physical channel number (0-1)
1648 IN ULONG pci_reg,
1649 IN ULONG bit_offs
1650 )
1651{
1652 PVOID HwDeviceExtension = (PVOID)deviceExtension;
1653 ULONG slotNumber = deviceExtension->slotNumber;
1654 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1655
1656 if(deviceExtension->MaxTransferMode <= ATA_UDMA2) {
1657 KdPrint2((PRINT_PREFIX "generic_cable80(%d, %#x, %d) <= UDMA2\n", channel, pci_reg, bit_offs));
1658 return FALSE;
1659 }
1660
1661 //ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1662 PHW_CHANNEL chan;
1663 ULONG c; // logical channel (for Compatible Mode controllers)
1664 UCHAR tmp8;
1665
1666 c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1667 chan = &deviceExtension->chan[c];
1668
1669 if(chan->Force80pin) {
1670 KdPrint2((PRINT_PREFIX "Force80pin\n"));
1671 return TRUE;
1672 }
1673
1674 GetPciConfig1(pci_reg, tmp8);
1675 if(!(tmp8 & (1 << (channel << bit_offs)))) {
1676 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
1677 KdPrint2((PRINT_PREFIX "generic_cable80(%d, %#x, %d) = 0\n", channel, pci_reg, bit_offs));
1678 return FALSE;
1679 }
1680
1681 KdPrint2((PRINT_PREFIX "generic_cable80(%d, %#x, %d) = 1\n", channel, pci_reg, bit_offs));
1682 return TRUE;
1683} // end generic_cable80()
1684
1685VOID
1686NTAPI
1687UniAtaReadLunConfig(
1688 IN PHW_DEVICE_EXTENSION deviceExtension,
1689 IN ULONG channel, // physical channel
1690 IN ULONG DeviceNumber
1691 )
1692{
1693 ULONG tmp32;
1694 PHW_CHANNEL chan;
1695 PHW_LU_EXTENSION LunExt;
1696 ULONG c;
1697
1698 c = channel - deviceExtension->Channel; // logical channel
1699
1700 chan = &deviceExtension->chan[c];
1701 DeviceNumber = (DeviceNumber % deviceExtension->NumberLuns);
1702 LunExt = chan->lun[DeviceNumber];
1703
1704 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"ReadCacheEnable", 1);
1705 LunExt->opt_ReadCacheEnable = tmp32 ? TRUE : FALSE;
1706
1707 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"WriteCacheEnable", 1);
1708 LunExt->opt_WriteCacheEnable = tmp32 ? TRUE : FALSE;
1709
1710 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"MaxTransferMode", chan->MaxTransferMode);
1711 LunExt->opt_MaxTransferMode = tmp32;
1712
1713 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"PreferedTransferMode", 0xffffffff);
1714 LunExt->opt_PreferedTransferMode = tmp32;
1715
1716 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"AdvancedPowerMode", ATA_C_F_APM_CNT_MIN_NO_STANDBY);
1717 if(tmp32 > 0xfe) {
1718 tmp32 = 0xfe; // max. performance
1719 }
1720 LunExt->opt_AdvPowerMode = (UCHAR)tmp32;
1721
1722 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"AcousticMgmt", ATA_C_F_AAM_CNT_MAX_POWER_SAVE);
1723 if(tmp32 > 0xfe) {
1724 tmp32 = 0xfe; // max. performance
1725 } else
1726 if(tmp32 < 0x80) {
1727 tmp32 = 0x0; // disable feature
1728 }
1729 LunExt->opt_AcousticMode = (UCHAR)tmp32;
1730
1731 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"StandbyTimer", 0);
1732 if(tmp32 == 0xfe) {
1733 tmp32 = 0xff;
1734 }
1735 LunExt->opt_StandbyTimer = (UCHAR)tmp32;
1736
1737 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"ReadOnly", 0);
1738 if(tmp32 <= 2) {
1739 LunExt->opt_ReadOnly = (UCHAR)tmp32;
1740 }
1741
1742 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"GeomType", 0xffffffff);
1743 if(tmp32 > GEOM_MANUAL) {
1744 tmp32 = 0xffffffff;
1745 }
1746 LunExt->opt_GeomType = tmp32;
1747 if(tmp32 == GEOM_MANUAL) {
1748 LunExt->DeviceFlags |= DFLAGS_MANUAL_CHS;
1749 LunExt->opt_GeomType = GEOM_ORIG;
1750 // assume IdentifyData is already zero-filled
1751 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"C", 0);
1752 LunExt->IdentifyData.NumberOfCurrentCylinders =
1753 LunExt->IdentifyData.NumberOfCylinders = (USHORT)tmp32;
1754 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"H", 0);
1755 LunExt->IdentifyData.NumberOfCurrentHeads =
1756 LunExt->IdentifyData.NumberOfHeads = (USHORT)tmp32;
1757 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"S", 0);
1758 LunExt->IdentifyData.CurrentSectorsPerTrack =
1759 LunExt->IdentifyData.SectorsPerTrack = (USHORT)tmp32;
1760 memcpy(LunExt->IdentifyData.ModelNumber, "SEIDH DD", 8); // ESDI HDD
1761 memcpy(LunExt->IdentifyData.SerialNumber, ".10", 4);
1762 memcpy(LunExt->IdentifyData.FirmwareRevision, ".10", 4);
1763 if(!LunExt->IdentifyData.SectorsPerTrack ||
1764 !LunExt->IdentifyData.NumberOfCylinders ||
1765 !LunExt->IdentifyData.NumberOfHeads) {
1766 // ERROR
1767 KdPrint2((PRINT_PREFIX "Wrong CHS\n"));
1768 LunExt->opt_GeomType = GEOM_AUTO;
1769 } else {
1770 LunExt->DeviceFlags |= DFLAGS_MANUAL_CHS;
1771 LunExt->opt_GeomType = GEOM_ORIG;
1772 }
1773 }
1774
1775 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"Hidden", 0);
1776 if(tmp32) {
1777 LunExt->DeviceFlags |= DFLAGS_HIDDEN;
1778 }
1779 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DeviceNumber, L"Exclude", 0);
1780 if(tmp32) {
1781 LunExt->DeviceFlags |= DFLAGS_HIDDEN;
1782 }
1783
1784 return;
1785} // end UniAtaReadLunConfig()
1786
1787BOOLEAN
1788NTAPI
1789AtapiReadChipConfig(
1790 IN PVOID HwDeviceExtension,
1791 IN ULONG DeviceNumber,
1792 IN ULONG channel // physical channel
1793 )
1794{
1795 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1796 PHW_CHANNEL chan;
1797 ULONG tmp32;
1798 ULONG c; // logical channel (for Compatible Mode controllers)
1799 ULONG i;
1800
1801 KdPrint2((PRINT_PREFIX "AtapiReadChipConfig: devExt %#x\n", deviceExtension ));
1802 ASSERT(deviceExtension);
1803
1804 if(channel != CHAN_NOT_SPECIFIED) {
1805 c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1806 } else {
1807 c = CHAN_NOT_SPECIFIED;
1808 }
1809
1810 KdPrint2((PRINT_PREFIX "AtapiReadChipConfig: dev %#x, ph chan %d\n", DeviceNumber, channel ));
1811
1812 if(channel == CHAN_NOT_SPECIFIED) {
1813 if(AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"ForceSimplex", FALSE)) {
1814 deviceExtension->simplexOnly = TRUE;
1815 }
1816 deviceExtension->opt_AtapiDmaZeroTransfer = FALSE;
1817 deviceExtension->opt_AtapiDmaControlCmd = FALSE;
1818 deviceExtension->opt_AtapiDmaRawRead = g_opt_AtapiDmaRawRead;
1819 deviceExtension->opt_AtapiDmaReadWrite = TRUE;
1820 }
1821
1822 if(c == CHAN_NOT_SPECIFIED) {
1823 KdPrint2((PRINT_PREFIX "MaxTransferMode (base): %#x\n", deviceExtension->MaxTransferMode));
1824 for(c=0; c<deviceExtension->NumberChannels; c++) {
1825 chan = &deviceExtension->chan[c];
1826 chan->MaxTransferMode = deviceExtension->MaxTransferMode;
1827 tmp32 = AtapiRegCheckDevValue(deviceExtension, channel, DEVNUM_NOT_SPECIFIED, L"MaxTransferMode", chan->MaxTransferMode);
1828 if(tmp32 != 0xffffffff) {
1829 KdPrint2((PRINT_PREFIX "MaxTransferMode (overriden): %#x\n", chan->MaxTransferMode));
1830 chan->MaxTransferMode = tmp32;
1831 }
1832 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"Force80pin", FALSE);
1833 chan->Force80pin = tmp32 ? TRUE : FALSE;
1834 if(chan->Force80pin) {
1835 KdPrint2((PRINT_PREFIX "Force80pin on chip\n"));
1836 deviceExtension->HwFlags |= UNIATA_NO80CHK;
1837 }
1838
1839 //UniAtaReadLunConfig(deviceExtension, c, 0);
1840 //UniAtaReadLunConfig(deviceExtension, c, 1);
1841 }
1842
1843 deviceExtension->opt_AtapiDmaZeroTransfer =
1844 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaZeroTransfer", deviceExtension->opt_AtapiDmaZeroTransfer) ?
1845 TRUE : FALSE;
1846
1847 deviceExtension->opt_AtapiDmaControlCmd =
1848 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaControlCmd", deviceExtension->opt_AtapiDmaControlCmd) ?
1849 TRUE : FALSE;
1850
1851 deviceExtension->opt_AtapiDmaRawRead =
1852 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaRawRead", deviceExtension->opt_AtapiDmaRawRead) ?
1853 TRUE : FALSE;
1854
1855 deviceExtension->opt_AtapiDmaReadWrite =
1856 AtapiRegCheckDevValue(deviceExtension, CHAN_NOT_SPECIFIED, DEVNUM_NOT_SPECIFIED, L"AtapiDmaReadWrite", deviceExtension->opt_AtapiDmaReadWrite) ?
1857 TRUE : FALSE;
1858
1859 } else {
1860 chan = &deviceExtension->chan[c];
1861 chan->MaxTransferMode = deviceExtension->MaxTransferMode;
1862 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"MaxTransferMode", chan->MaxTransferMode);
1863 if(tmp32 != 0xffffffff) {
1864 KdPrint2((PRINT_PREFIX "MaxTransferMode (overriden): %#x\n", chan->MaxTransferMode));
1865 chan->MaxTransferMode = tmp32;
1866 }
1867 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"ReorderEnable", TRUE);
1868 chan->UseReorder = tmp32 ? TRUE : FALSE;
1869
1870 tmp32 = AtapiRegCheckDevValue(deviceExtension, c, DEVNUM_NOT_SPECIFIED, L"Force80pin", FALSE);
1871 chan->Force80pin = tmp32 ? TRUE : FALSE;
1872 if(chan->Force80pin) {
1873 KdPrint2((PRINT_PREFIX "Force80pin on channel\n"));
1874 }
1875
1876 for(i=0; i<deviceExtension->NumberLuns; i++) {
1877 UniAtaReadLunConfig(deviceExtension, channel, i);
1878 }
1879 }
1880
1881 return TRUE;
1882} // end AtapiReadChipConfig()
1883
1884BOOLEAN
1885NTAPI
1886AtapiChipInit(
1887 IN PVOID HwDeviceExtension,
1888 IN ULONG DeviceNumber,
1889 IN ULONG channel // logical channel
1890 )
1891{
1892 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1893 ULONG slotNumber = deviceExtension->slotNumber;
1894 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1895 ULONG VendorID = deviceExtension->DevID & 0xffff;
1896 ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
1897 ULONG RevID = deviceExtension->RevID;
1898// ULONG i;
1899// BUSMASTER_CONTROLLER_INFORMATION_BASE* DevTypeInfo;
1900 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1901 ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
1902 PHW_CHANNEL chan;
1903 UCHAR tmp8;
1904 USHORT tmp16;
1905 ULONG tmp32;
1906 ULONG c; // logical channel (for Compatible Mode controllers)
1907 BOOLEAN CheckCable = FALSE;
1908 BOOLEAN GlobalInit = FALSE;
1909 //ULONG BaseIoAddress;
1910
1911 switch(channel) {
1912 case CHAN_NOT_SPECIFIED_CHECK_CABLE:
1913 CheckCable = TRUE;
1914 /* FALLTHROUGH */
1915 case CHAN_NOT_SPECIFIED:
1916 c = CHAN_NOT_SPECIFIED;
1917 GlobalInit = TRUE;
1918 break;
1919 default:
1920 //c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1921 c = channel;
1922 channel += deviceExtension->Channel;
1923 }
1924
1925 KdPrint2((PRINT_PREFIX "AtapiChipInit: dev %#x, ph chan %d, c %d\n", DeviceNumber, channel, c));
1926
1927 KdPrint2((PRINT_PREFIX "HwFlags: %#x\n", deviceExtension->HwFlags));
1928 KdPrint2((PRINT_PREFIX "VendorID/DeviceID/Rev %#x/%#x/%#x\n", VendorID, DeviceID, RevID));
1929
1930 if(deviceExtension->UnknownDev) {
1931 KdPrint2((PRINT_PREFIX " Unknown chip\n" ));
1932 //return TRUE;
1933 VendorID = 0xffffffff;
1934 }
1935
1936
1937 if(ChipFlags & UNIATA_AHCI) {
1938 /* if BAR(5) is IO it should point to SATA interface registers */
1939 if(!deviceExtension->BaseIoAHCI_0.Addr) {
1940 KdPrint2((PRINT_PREFIX " !BaseIoAHCI_0, exiting\n" ));
1941 return FALSE;
1942 }
1943 if(c == CHAN_NOT_SPECIFIED) {
1944 return UniataAhciInit(HwDeviceExtension);
1945 } else
1946 if(c<deviceExtension->NumberChannels) {
1947 KdPrint2((PRINT_PREFIX " AHCI single channel init\n" ));
1948 UniataAhciReset(HwDeviceExtension, c);
1949 return TRUE;
1950 } else {
1951 KdPrint2((PRINT_PREFIX " AHCI non-existent channel\n" ));
1952 return FALSE;
1953 }
1954 }
1955
1956 if((WinVer_Id() > WinVer_NT) &&
1957 GlobalInit &&
1958 deviceExtension->MasterDev) {
1959 PCI_COMMON_CONFIG pciData;
1960 ULONG busDataRead;
1961
1962 KdPrint2((PRINT_PREFIX " re-enable IO resources of MasterDev\n" ));
1963
1964 busDataRead = HalGetBusData
1965 //ScsiPortGetBusData
1966 (
1967 //HwDeviceExtension,
1968 PCIConfiguration, SystemIoBusNumber, slotNumber,
1969 &pciData, PCI_COMMON_HDR_LENGTH);
1970 if(busDataRead == PCI_COMMON_HDR_LENGTH) {
1971 UniataEnableIoPCI(SystemIoBusNumber, slotNumber, &pciData);
1972 } else {
1973 KdPrint2((PRINT_PREFIX " re-enable IO resources of MasterDev FAILED\n" ));
1974 }
1975 }
1976
1977 switch(VendorID) {
1978// case ATA_ACARD_ID:
1979// break;
1980 case ATA_ACER_LABS_ID:
1981 if(ChipFlags & UNIATA_SATA) {
1982 if(c == CHAN_NOT_SPECIFIED) {
1983 for(c=0; c<deviceExtension->NumberChannels; c++) {
1984 chan = &deviceExtension->chan[c];
1985 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
1986 /* the southbridge might need the data corruption fix */
1987 if(RevID == 0xc2 || RevID == 0xc3) {
1988 AtapiAliSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
1989 SystemIoBusNumber, slotNumber, c);
1990 }
1991 }
1992 /* enable PCI interrupt */
1993 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
1994 }
1995 } else
1996 if(ChipFlags & ALINEW) {
1997 if(c == CHAN_NOT_SPECIFIED) {
1998 /* use device interrupt as byte count end */
1999 ChangePciConfig1(0x4a, (a | 0x20));
2000 /* enable cable detection and UDMA support on newer chips, rev < 0xc7 */
2001 if(RevID < 0xc7) {
2002 ChangePciConfig1(0x4b, (a | 0x09));
2003 }
2004
2005 /* enable ATAPI UDMA mode */
2006 ChangePciConfig1(0x53, (a | (RevID >= 0xc7 ? 0x03 : 0x01)));
2007
2008 } else {
2009 // check 80-pin cable
2010 generic_cable80(deviceExtension, channel, 0x4a, 0);
2011 }
2012 } else {
2013 if(c == CHAN_NOT_SPECIFIED) {
2014 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
2015 ChangePciConfig1(0x53, (a | 0x03));
2016 } else {
2017 // ATAPI DMA R/O
2018 deviceExtension->chan[c].ChannelCtrlFlags |= CTRFLAGS_DMA_RO;
2019 }
2020 }
2021 break;
2022 case ATA_AMD_ID:
2023 if(c == CHAN_NOT_SPECIFIED) {
2024 /* set prefetch, postwrite */
2025 if(ChipFlags & AMDBUG) {
2026 ChangePciConfig1(0x41, (a & 0x0f));
2027 } else {
2028 ChangePciConfig1(0x41, (a | 0xf0));
2029 }
2030 }
2031 if(deviceExtension->MaxTransferMode < ATA_UDMA2)
2032 break;
2033 // check 80-pin cable
2034 if(!(ChipFlags & UNIATA_NO80CHK)) {
2035 if(c == CHAN_NOT_SPECIFIED) {
2036 // do nothing
2037 } else {
2038 generic_cable80(deviceExtension, channel, 0x42, 0);
2039 }
2040 }
2041 break;
2042 case ATA_HIGHPOINT_ID:
2043
2044 if(c == CHAN_NOT_SPECIFIED) {
2045
2046 if(ChipFlags & HPTOLD) {
2047 /* turn off interrupt prediction */
2048 ChangePciConfig1(0x51, (a & ~0x80));
2049 } else {
2050 /* turn off interrupt prediction */
2051 ChangePciConfig1(0x51, (a & ~0x03));
2052 ChangePciConfig1(0x55, (a & ~0x03));
2053 /* turn on interrupts */
2054 ChangePciConfig1(0x5a, (a & ~0x10));
2055 /* set clocks etc */
2056 if(ChipType < HPT372) {
2057 SetPciConfig1(0x5b, 0x22);
2058 } else {
2059 ChangePciConfig1(0x5b, ((a & 0x01) | 0x20));
2060 }
2061 }
2062
2063 } else {
2064 // check 80-pin cable
2065 chan = &deviceExtension->chan[c];
2066 if(!hpt_cable80(deviceExtension, channel)) {
2067 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2068 }
2069 }
2070 break;
2071 case ATA_INTEL_ID: {
2072 BOOLEAN IsPata;
2073 USHORT reg54;
2074 if(ChipFlags & UNIATA_SATA) {
2075
2076 KdPrint2((PRINT_PREFIX "Intel SATA\n"));
2077 if(ChipFlags & UNIATA_AHCI) {
2078 KdPrint2((PRINT_PREFIX "Do nothing for AHCI\n"));
2079 /* enable PCI interrupt */
2080 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2081 break;
2082 }
2083 if(c == CHAN_NOT_SPECIFIED) {
2084 KdPrint2((PRINT_PREFIX "Base init\n"));
2085 /* force all ports active "the legacy way" */
2086 ChangePciConfig2(0x92, (a | 0x0f));
2087
2088 if(deviceExtension->BaseIoAddressSATA_0.Addr && (ChipFlags & ICH7)) {
2089 /* Set SCRAE bit to enable registers access. */
2090 ChangePciConfig4(0x94, (a | (1 << 9)));
2091 /* Set Ports Implemented register bits. */
2092 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c,
2093 AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c) | 0x0f);
2094 }
2095 /* enable PCI interrupt */
2096 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2097
2098 } else {
2099
2100 KdPrint2((PRINT_PREFIX "channel init\n"));
2101
2102 GetPciConfig1(0x90, tmp8);
2103 KdPrint2((PRINT_PREFIX "reg 90: %x, init lun map\n", tmp8));
2104
2105 KdPrint2((PRINT_PREFIX "chan %d\n", c));
2106 chan = &deviceExtension->chan[c];
2107 IsPata = FALSE;
2108 if(ChipFlags & ICH5) {
2109 KdPrint2((PRINT_PREFIX "ICH5\n"));
2110 if ((tmp8 & 0x04) == 0) {
2111 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2112 chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ^ c;
2113 chan->lun[1]->SATA_lun_map = 0;
2114 } else if ((tmp8 & 0x02) == 0) {
2115 if(c == 0) {
2116 chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2117 chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2118 } else {
2119 IsPata = TRUE;
2120 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2121 }
2122 } else if ((tmp8 & 0x02) != 0) {
2123 if(c == 1) {
2124 chan->lun[0]->SATA_lun_map = (tmp8 & 0x01) ? 1 : 0;
2125 chan->lun[1]->SATA_lun_map = (tmp8 & 0x01) ? 0 : 1;
2126 } else {
2127 IsPata = TRUE;
2128 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2129 }
2130 }
2131 } else
2132 if(ChipFlags & I6CH2) {
2133 KdPrint2((PRINT_PREFIX "I6CH2\n"));
2134 chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2135 chan->lun[0]->SATA_lun_map = c ? 0 : 1;
2136 chan->lun[1]->SATA_lun_map = 0;
2137 } else {
2138 KdPrint2((PRINT_PREFIX "other Intel\n"));
2139 switch(tmp8 & 0x03) {
2140 case 0:
2141 KdPrint2((PRINT_PREFIX "0 -> %d/%d\n", 0+c, 2+c));
2142 chan->lun[0]->SATA_lun_map = 0+c;
2143 chan->lun[1]->SATA_lun_map = 2+c;
2144 break;
2145 case 2:
2146 if(c==0) {
2147 KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 0, 2));
2148 chan->lun[0]->SATA_lun_map = 0;
2149 chan->lun[1]->SATA_lun_map = 2;
2150 } else {
2151 // PATA
2152 KdPrint2((PRINT_PREFIX "PATA\n"));
2153 IsPata = TRUE;
2154 }
2155 break;
2156 case 1:
2157 if(c==1) {
2158 KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 1, 3));
2159 chan->lun[0]->SATA_lun_map = 1;
2160 chan->lun[1]->SATA_lun_map = 3;
2161 } else {
2162 // PATA
2163 KdPrint2((PRINT_PREFIX "PATA\n"));
2164 IsPata = TRUE;
2165 }
2166 break;
2167 }
2168 }
2169
2170 if(IsPata) {
2171 KdPrint2((PRINT_PREFIX "PATA part\n"));
2172 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2173 }
2174
2175 if(ChipType == INTEL_IDX) {
2176 KdPrint2((PRINT_PREFIX "io indexed\n"));
2177 //for(c=0; c<deviceExtension->NumberChannels; c++) {
2178 chan = &deviceExtension->chan[c];
2179 UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
2180 if(!(chan->ChannelCtrlFlags & CTRFLAGS_NO_SLAVE)) {
2181 UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 1);
2182 }
2183 //}
2184 }
2185 }
2186
2187 break;
2188 }
2189 if(deviceExtension->MaxTransferMode <= ATA_UDMA2)
2190 break;
2191 // check 80-pin cable
2192 if(c == CHAN_NOT_SPECIFIED) {
2193 // do nothing
2194 } else {
2195 chan = &deviceExtension->chan[c];
2196 GetPciConfig2(0x54, reg54);
2197 KdPrint2((PRINT_PREFIX " intel 80-pin check (reg54=%x)\n", reg54));
2198 if(deviceExtension->HwFlags & UNIATA_NO80CHK) {
2199 KdPrint2((PRINT_PREFIX " No check (administrative)\n"));
2200 if(chan->Force80pin) {
2201 KdPrint2((PRINT_PREFIX "Force80pin\n"));
2202 }
2203 } else
2204 if(reg54 == 0x0000 || reg54 == 0xffff) {
2205 KdPrint2((PRINT_PREFIX " check failed (not supported)\n"));
2206 } else
2207 if( ((reg54 >> (channel*2)) & 30) == 0) {
2208 KdPrint2((PRINT_PREFIX " intel 40-pin\n"));
2209 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2210 }
2211 }
2212 break; }
2213 case ATA_NVIDIA_ID: {
2214 if(ChipFlags & UNIATA_SATA) {
2215 if(c == CHAN_NOT_SPECIFIED) {
2216 ULONG offs = (ChipFlags & NV4OFF) ? 0x0440 : 0x0010;
2217 /* enable control access */
2218 ChangePciConfig1(0x50, (a | 0x04));
2219 /* MCP55 seems to need some time to allow r_res2 read. */
2220 AtapiStallExecution(10);
2221 KdPrint2((PRINT_PREFIX "BaseIoAddressSATA_0=%x\n", deviceExtension->BaseIoAddressSATA_0.Addr));
2222 if(ChipFlags & NVQ) {
2223 KdPrint2((PRINT_PREFIX "Disable NCQ\n"));
2224 tmp32 = AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400);
2225 KdPrint2((PRINT_PREFIX "MODE=%#x\n", tmp32));
2226 if(tmp32 & ~0xfffffff9) {
2227 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400,
2228 tmp32 & 0xfffffff9);
2229 }
2230 ChipFlags &= ~NVQ;
2231 deviceExtension->HwFlags = ChipFlags;
2232 }
2233 if(ChipFlags & NVQ) {
2234 /* disable ECO 398 */
2235 ChangePciConfig1(0x7f, (a & ~(1 << 7)));
2236
2237 KdPrint2((PRINT_PREFIX "Enable NCQ\n"));
2238 /* enable NCQ support */
2239 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0400,
2240 tmp32 | ~0x00000006);
2241
2242 /* clear interrupt status */
2243 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0x00ff00ff);
2244 /* enable device and PHY state change interrupts */
2245 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+4, 0x000d000d);
2246 } else {
2247 /* clear interrupt status */
2248 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs, 0xff);
2249 /* enable device and PHY state change interrupts */
2250 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),offs+1, 0xdd);
2251 }
2252 /* enable PCI interrupt */
2253 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2254 } else {
2255 //UniataSataPhyEnable(HwDeviceExtension, c);
2256 }
2257 } else {
2258 //UCHAR reg52;
2259
2260 if(c == CHAN_NOT_SPECIFIED) {
2261 /* set prefetch, postwrite */
2262 ChangePciConfig1(0x51, (a & 0x0f));
2263 } else {
2264 // check 80-pin cable
2265 generic_cable80(deviceExtension, channel, 0x52, 1);
2266/* chan = &deviceExtension->chan[c];
2267 GetPciConfig1(0x52, reg52);
2268 if( !((reg52 >> (channel*2)) & 0x01)) {
2269 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2270 }*/
2271 }
2272 }
2273 break; }
2274 case ATA_PROMISE_ID: {
2275 USHORT Reg50;
2276 switch(ChipType) {
2277 case PRNEW:
2278 /* setup clocks */
2279 if(c == CHAN_NOT_SPECIFIED) {
2280// ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
2281 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
2282 AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) | 0x0a );
2283 }
2284 /* FALLTHROUGH */
2285 case PROLD:
2286 /* enable burst mode */
2287// ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
2288 if(c == CHAN_NOT_SPECIFIED) {
2289 AtapiWritePortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f,
2290 AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x1f) | 0x01 );
2291 } else {
2292 // check 80-pin cable
2293 chan = &deviceExtension->chan[c];
2294 GetPciConfig2(0x50, Reg50);
2295 if(Reg50 & (1 << (channel+10))) {
2296 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2297 }
2298 }
2299 break;
2300 case PRTX:
2301 if(c == CHAN_NOT_SPECIFIED) {
2302 // do nothing
2303 } else {
2304 // check 80-pin cable
2305 chan = &deviceExtension->chan[c];
2306 AtapiWritePort1(chan, IDX_BM_DeviceSpecific0, 0x0b);
2307 if(AtapiReadPort1(chan, IDX_BM_DeviceSpecific1) & 0x04) {
2308 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2309 }
2310 }
2311 break;
2312 case PRMIO:
2313 if(c == CHAN_NOT_SPECIFIED) {
2314 /* clear SATA status and unmask interrupts */
2315 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),
2316 (ChipFlags & PRG2) ? 0x60 : 0x6c, 0x000000ff);
2317 if(ChipFlags & UNIATA_SATA) {
2318 /* enable "long burst length" on gen2 chips */
2319 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44,
2320 AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), 0x44) | 0x2000);
2321 }
2322 } else {
2323 chan = &deviceExtension->chan[c];
2324 AtapiWritePort4(chan, IDX_BM_Command,
2325 (AtapiReadPort4(chan, IDX_BM_Command) & ~0x00000f8f) | channel );
2326 AtapiWritePort4(chan, IDX_BM_DeviceSpecific0, 0x00000001);
2327 // check 80-pin cable
2328 if(chan->MaxTransferMode < ATA_SA150 &&
2329 (AtapiReadPort4(chan, IDX_BM_Command) & 0x01000000)) {
2330 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2331 }
2332 }
2333 break;
2334 }
2335 break; }
2336 case ATA_SERVERWORKS_ID:
2337 if(c == CHAN_NOT_SPECIFIED) {
2338 if(ChipType == SWKS33) {
2339 AtapiRosbSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
2340 SystemIoBusNumber, slotNumber);
2341 } else {
2342 ChangePciConfig1(0x5a, ((a & ~0x40) | ((ChipType == SWKS100) ? 0x03 : 0x02)));
2343 }
2344 }
2345 break;
2346 case ATA_ATI_ID:
2347 if(ChipType == SIIMIO) {
2348 KdPrint2((PRINT_PREFIX "ATI New\n"));
2349 // fall to SiI
2350 } else {
2351 KdPrint2((PRINT_PREFIX "ATI\n"));
2352 break;
2353 }
2354 /* FALLTHROUGH */
2355 case ATA_SILICON_IMAGE_ID:
2356 /* if(ChipFlags & SIIENINTR) {
2357 SetPciConfig1(0x71, 0x01);
2358 }*/
2359 switch(ChipType) {
2360 case SIIMIO: {
2361
2362 KdPrint2((PRINT_PREFIX "SII\n"));
2363 USHORT Reg79;
2364
2365 if(c == CHAN_NOT_SPECIFIED) {
2366 if(ChipFlags & SIISETCLK) {
2367 KdPrint2((PRINT_PREFIX "SIISETCLK\n"));
2368 GetPciConfig1(0x8a, tmp8);
2369 if ((tmp8 & 0x30) != 0x10)
2370 ChangePciConfig1(0x8a, (a & 0xcf) | 0x10);
2371 GetPciConfig1(0x8a, tmp8);
2372 if ((tmp8 & 0x30) != 0x10) {
2373 KdPrint2((PRINT_PREFIX "Sil 0680 could not set ATA133 clock\n"));
2374 deviceExtension->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2375 }
2376 }
2377 }
2378 if(deviceExtension->MaxTransferMode < ATA_SA150) {
2379 // check 80-pin cable
2380 if(c == CHAN_NOT_SPECIFIED) {
2381 // do nothing
2382 } else {
2383 KdPrint2((PRINT_PREFIX "Check UDMA66 cable\n"));
2384 chan = &deviceExtension->chan[c];
2385 GetPciConfig2(0x79, Reg79);
2386 if(Reg79 & (channel ? 0x02 : 0x01)) {
2387 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2388 }
2389 }
2390 } else {
2391 ULONG unit01 = (c & 1);
2392 ULONG unit10 = (c & 2);
2393 /* enable/disable PHY state change interrupt */
2394 if(c == CHAN_NOT_SPECIFIED) {
2395 for(c=0; c<deviceExtension->NumberChannels; c++) {
2396 unit01 = (c & 1);
2397 unit10 = (c & 2);
2398 if(ChipFlags & SIINOSATAIRQ) {
2399 KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c));
2400 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0);
2401 }
2402 }
2403 } else {
2404 if(ChipFlags & SIINOSATAIRQ) {
2405 KdPrint2((PRINT_PREFIX "Disable broken SATA intr on c=%x\n", c));
2406 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),0);
2407 } else {
2408 KdPrint2((PRINT_PREFIX "Enable SATA intr on c=%x\n", c));
2409 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
2410 }
2411 }
2412 }
2413 if(c == CHAN_NOT_SPECIFIED) {
2414 /* enable interrupt as BIOS might not */
2415 ChangePciConfig1(0x8a, (a & 0x3f));
2416 // Enable 3rd and 4th channels
2417 if (ChipFlags & SII4CH) {
2418 KdPrint2((PRINT_PREFIX "SII4CH\n"));
2419 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x0200, 0x00000002);
2420 }
2421 } else {
2422 chan = &deviceExtension->chan[c];
2423 /* dont block interrupts */
2424 //ChangePciConfig4(0x48, (a & ~0x03c00000));
2425 /*tmp32 =*/ AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
2426 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48, (1 << 22) << c);
2427 // flush
2428 /*tmp32 =*/ AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0),0x48);
2429
2430 /* Initialize FIFO PCI bus arbitration */
2431 GetPciConfig1(offsetof(PCI_COMMON_CONFIG, CacheLineSize), tmp8);
2432 if(tmp8) {
2433 KdPrint2((PRINT_PREFIX "SII: CacheLine=%d\n", tmp8));
2434 tmp8 = (tmp8/8)+1;
2435 AtapiWritePort2(chan, IDX_BM_DeviceSpecific1, ((USHORT)tmp8) << 8 | tmp8);
2436 } else {
2437 KdPrint2((PRINT_PREFIX "SII: CacheLine=0 !!!\n"));
2438 }
2439 }
2440 break; }
2441
2442 case SIICMD: {
2443
2444 KdPrint2((PRINT_PREFIX "SII_CMD\n"));
2445 if(c == CHAN_NOT_SPECIFIED) {
2446 /* Setup interrupts. */
2447 SetPciConfig1(0x71, 0x01);
2448
2449 /* GetPciConfig1(0x8a, tmp8);
2450 tmp8 &= ~(0x30);
2451 SetPciConfig1(0x71, tmp8);*/
2452
2453 /* Use MEMORY READ LINE for reads.
2454 * NOTE: Although not mentioned in the PCI0646U specs,
2455 * these bits are write only and won't be read
2456 * back as set or not. The PCI0646U2 specs clarify
2457 * this point.
2458 */
2459 /* tmp8 |= 0x02;
2460 SetPciConfig1(0x71, tmp8);
2461 */
2462 /* Set reasonable active/recovery/address-setup values. */
2463 SetPciConfig1(0x53, 0x40);
2464 SetPciConfig1(0x54, 0x3f);
2465 SetPciConfig1(0x55, 0x40);
2466 SetPciConfig1(0x56, 0x3f);
2467 SetPciConfig1(0x57, 0x1c);
2468 SetPciConfig1(0x58, 0x3f);
2469 SetPciConfig1(0x5b, 0x3f);
2470 }
2471
2472 break; }
2473 case ATI700:
2474 KdPrint2((PRINT_PREFIX "ATI700\n"));
2475 if(c == 0 && !(ChipFlags & UNIATA_AHCI)) {
2476 KdPrint2((PRINT_PREFIX "IXP700 PATA\n"));
2477 chan = &deviceExtension->chan[c];
2478 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA5);
2479 }
2480 break;
2481 } /* switch(ChipType) */
2482 break;
2483 case ATA_SIS_ID:
2484 if(c == CHAN_NOT_SPECIFIED) {
2485 switch(ChipType) {
2486 case SIS33:
2487 break;
2488 case SIS66:
2489 case SIS100OLD:
2490 ChangePciConfig1(0x52, (a & ~0x04));
2491 break;
2492 case SIS100NEW:
2493 case SIS133OLD:
2494 ChangePciConfig1(0x49, (a & ~0x01));
2495 break;
2496 case SIS133NEW:
2497 ChangePciConfig2(0x50, (a | 0x0008));
2498 ChangePciConfig2(0x52, (a | 0x0008));
2499 break;
2500 case SISSATA:
2501 ChangePciConfig2(0x04, (a & ~0x0400));
2502 break;
2503 }
2504 }
2505 if(deviceExtension->HwFlags & UNIATA_SATA) {
2506 // do nothing for SATA
2507 } else
2508 if(ChipType == SIS133NEW) {
2509 // check 80-pin cable
2510 if(c == CHAN_NOT_SPECIFIED) {
2511 // do nothing
2512 } else {
2513 chan = &deviceExtension->chan[c];
2514 GetPciConfig2(channel ? 0x52 : 0x50, tmp16);
2515 if(tmp16 & 0x8000) {
2516 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2517 }
2518 }
2519 } else {
2520 // check 80-pin cable
2521 if(c == CHAN_NOT_SPECIFIED) {
2522 // do nothing
2523 } else {
2524 chan = &deviceExtension->chan[c];
2525 GetPciConfig1(48, tmp8);
2526 if(tmp8 & (0x10 << channel)) {
2527 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2528 }
2529 }
2530 }
2531 break;
2532 case ATA_VIA_ID:
2533
2534/* if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI | VIASATA) {
2535 break;
2536 }*/
2537 if(c == CHAN_NOT_SPECIFIED) {
2538 /* prepare for ATA-66 on the 82C686a and 82C596b */
2539 if(ChipFlags & VIACLK) {
2540 ChangePciConfig4(0x50, (a | 0x030b030b));
2541 }
2542 // no init for SATA
2543 if(ChipFlags & (UNIATA_SATA | VIASATA)) {
2544 /* enable PCI interrupt */
2545 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
2546
2547 /*
2548 * vt6420/1 has problems talking to some drives. The following
2549 * is based on the fix from Joseph Chan <JosephChan@via.com.tw>.
2550 *
2551 * When host issues HOLD, device may send up to 20DW of data
2552 * before acknowledging it with HOLDA and the host should be
2553 * able to buffer them in FIFO. Unfortunately, some WD drives
2554 * send upto 40DW before acknowledging HOLD and, in the
2555 * default configuration, this ends up overflowing vt6421's
2556 * FIFO, making the controller abort the transaction with
2557 * R_ERR.
2558 *
2559 * Rx52[2] is the internal 128DW FIFO Flow control watermark
2560 * adjusting mechanism enable bit and the default value 0
2561 * means host will issue HOLD to device when the left FIFO
2562 * size goes below 32DW. Setting it to 1 makes the watermark
2563 * 64DW.
2564 *
2565 * http://www.reactos.org/bugzilla/show_bug.cgi?id=6500
2566 */
2567#ifdef __REACTOS__
2568 // New URL is https://jira.reactos.org/browse/CORE-5897
2569#endif
2570
2571 if(DeviceID == 0x3149 || DeviceID == 0x3249) { //vt6420 or vt6421
2572 KdPrint2((PRINT_PREFIX "VIA 642x FIFO\n"));
2573 ChangePciConfig1(0x52, a | (1 << 2));
2574 }
2575
2576 break;
2577 }
2578
2579 /* the southbridge might need the data corruption fix */
2580 if(ChipFlags & VIABUG) {
2581 AtapiViaSouthBridgeFixup(HwDeviceExtension, PCIConfiguration,
2582 SystemIoBusNumber, slotNumber);
2583 }
2584 /* set prefetch, postwrite */
2585 if(ChipType != VIA133) {
2586 ChangePciConfig1(0x41, (a | 0xf0));
2587 }
2588
2589 /* set fifo configuration half'n'half */
2590 ChangePciConfig1(0x43, ((a & ((ChipFlags & VIAPRQ) ? 0x80 : 0x90)) | 0x2a));
2591
2592 /* set status register read retry */
2593 ChangePciConfig1(0x44, (a | 0x08));
2594
2595 /* set DMA read & end-of-sector fifo flush */
2596 ChangePciConfig1(0x46, ((a & 0x0c) | 0xf0));
2597
2598 /* set sector size */
2599 SetPciConfig2(0x60, DEV_BSIZE);
2600 SetPciConfig2(0x68, DEV_BSIZE);
2601 } else {
2602
2603 chan = &deviceExtension->chan[c];
2604 // no init for SATA
2605 if(ChipFlags & (UNIATA_SATA | VIASATA)) {
2606 if((ChipFlags & VIABAR) && (c >= 2)) {
2607 // this is PATA channel
2608 chan->MaxTransferMode = ATA_UDMA5;
2609 break;
2610 }
2611 UniataSataWritePort4(chan, IDX_SATA_SError, 0xffffffff, 0);
2612 break;
2613 }
2614/*
2615 // check 80-pin cable
2616 if(!via_cable80(deviceExtension, channel)) {
2617 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2618 }
2619*/
2620 }
2621
2622 break;
2623
2624 case ATA_ITE_ID:
2625 if(ChipType == ITE_33 || ChipType == ITE_133_NEW) {
2626 break;
2627 }
2628 if(ChipType == ITE_133) {
2629 if(c == CHAN_NOT_SPECIFIED) {
2630 /* set PCI mode and 66Mhz reference clock */
2631 ChangePciConfig1(0x50, a & ~0x83);
2632
2633 /* set default active & recover timings */
2634 SetPciConfig1(0x54, 0x31);
2635 SetPciConfig1(0x56, 0x31);
2636 } else {
2637 // check 80-pin cable
2638 GetPciConfig2(0x40, tmp16);
2639 chan = &deviceExtension->chan[c];
2640 if(!(tmp16 & (channel ? 0x08 : 0x04))) {
2641 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2642 }
2643 }
2644 } else
2645 if(ChipType == ITE_133_NEW) {
2646 }
2647 break;
2648 case ATA_CYRIX_ID:
2649 KdPrint2((PRINT_PREFIX "Cyrix\n"));
2650 if(ChipType == CYRIX_OLD) {
2651 if(c == CHAN_NOT_SPECIFIED) {
2652 GetPciConfig1(0x60, tmp8);
2653 if(!(tmp8 & 0x40)) {
2654 KdPrint2((PRINT_PREFIX "Enable DMA\n"));
2655 tmp8 |= 0x40;
2656 SetPciConfig1(0x60, tmp8);
2657 }
2658 }
2659 }
2660 break;
2661 case ATA_JMICRON_ID:
2662 /* New JMicron PATA controllers */
2663 if(deviceExtension->DevID == ATA_JMB361 ||
2664 deviceExtension->DevID == ATA_JMB363 ||
2665 deviceExtension->DevID == ATA_JMB365 ||
2666 deviceExtension->DevID == ATA_JMB366 ||
2667 deviceExtension->DevID == ATA_JMB368) {
2668 KdPrint2((PRINT_PREFIX "JMicron\n"));
2669
2670 ULONG c_swp = 0;
2671 ULONG reg40, reg80;
2672
2673 GetPciConfig4(0x40, reg40);
2674 KdPrint2((PRINT_PREFIX "reg 40: %x\n", reg40));
2675
2676 c_swp = (reg40 & (1<<22)) ? 1 : 0; // 1=swap, 0=keep
2677 KdPrint2((PRINT_PREFIX "c_swp: %x\n", c_swp));
2678
2679 GetPciConfig4(0x80, reg80);
2680 KdPrint2((PRINT_PREFIX "reg 80: %x\n", reg80));
2681
2682 if(c == CHAN_NOT_SPECIFIED) {
2683 UCHAR P1mode;
2684
2685 P1mode = (reg80 & (1<<24)) ? ATA_UDMA6 : ATA_SA300;
2686 KdPrint2((PRINT_PREFIX "p1 mode: %x\n", P1mode));
2687
2688 if(reg40 & (1 << 23)) {
2689 KdPrint2((PRINT_PREFIX "SATA+PATA0\n"));
2690 deviceExtension->chan[0 ^ c_swp].MaxTransferMode = P1mode;
2691 deviceExtension->chan[1 ^ c_swp].MaxTransferMode = ATA_UDMA6;
2692 deviceExtension->chan[1 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2693
2694 } else {
2695 KdPrint2((PRINT_PREFIX "SATA+SATA\n"));
2696 deviceExtension->chan[0 ^ c_swp].MaxTransferMode = P1mode;
2697 //deviceExtension->chan[0 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2698 deviceExtension->chan[1 ^ c_swp].MaxTransferMode = ATA_SA300;
2699 deviceExtension->chan[1 ^ c_swp].ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
2700 }
2701
2702 } else {
2703 /*
2704 deviceExtension->chan[0 ^ c_swp].lun[0]->SATA_lun_map =
2705 deviceExtension->chan[0 ^ c_swp].lun[0]->SATA_lun_map = 0;
2706 deviceExtension->chan[1 ^ c_swp].lun[0]->SATA_lun_map =
2707 deviceExtension->chan[1 ^ c_swp].lun[0]->SATA_lun_map = 1;
2708 */
2709 KdPrint2((PRINT_PREFIX "chan %d\n", c));
2710 chan = &deviceExtension->chan[c];
2711
2712 UCHAR ph_channel = (UCHAR)(c ^ c_swp);
2713 //c_swp = chan->lun[0]->SATA_lun_map;
2714 if(chan->MaxTransferMode >= ATA_SA150) {
2715 KdPrint2((PRINT_PREFIX "SATA, map -> %x\n", ph_channel));
2716 } else {
2717 KdPrint2((PRINT_PREFIX "PATA, map -> %x\n", ph_channel));
2718 if(!ph_channel) {
2719 if(!(reg40 & (1<<5))) {
2720 KdPrint2((PRINT_PREFIX "disabled\n", ph_channel));
2721 } else
2722 if(!(reg40 & (1<<3))) {
2723 KdPrint2((PRINT_PREFIX "40-pin\n"));
2724 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2725 }
2726 } else {
2727 if(!(reg80 & (1<<21))) {
2728 KdPrint2((PRINT_PREFIX "disabled\n", ph_channel));
2729 } else
2730 if(!(reg80 & (1<<19))) {
2731 KdPrint2((PRINT_PREFIX "40-pin\n"));
2732 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2733 }
2734 }
2735 }
2736 }
2737
2738 }
2739 break;
2740 default:
2741 if(c != CHAN_NOT_SPECIFIED) {
2742 // We don't know how to check for 80-pin cable on unknown controllers.
2743 // Later we shall check bit in IDENTIFY structure, but it is not reliable way.
2744 // So, leave this flag to use as hint in error recovery procedures
2745 KdPrint2((PRINT_PREFIX "UNIATA_NO80CHK\n"));
2746 deviceExtension->HwFlags |= UNIATA_NO80CHK;
2747 }
2748 break;
2749 }
2750
2751 // In all places separate channels are inited after common controller init
2752 // The only exception is probe. But there we may need info about 40/80 pin and MaxTransferRate
2753 // Do not check UNIATA_SATA here since we may have controller with mixed ports
2754 if(CheckCable && !(ChipFlags & (UNIATA_NO80CHK/* | UNIATA_SATA*/))) {
2755 for(c=0; c<deviceExtension->NumberChannels; c++) {
2756 AtapiChipInit(HwDeviceExtension, DeviceNumber, c);
2757 }
2758 }
2759
2760 return TRUE;
2761} // end AtapiChipInit()
2762
2763VOID
2764NTAPI
2765UniataInitMapBM(
2766 IN PHW_DEVICE_EXTENSION deviceExtension,
2767 IN PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0,
2768 IN BOOLEAN MemIo
2769 )
2770{
2771 PHW_CHANNEL chan;
2772 ULONG c;
2773 ULONG i;
2774
2775 if(!BaseIoAddressBM_0) {
2776 MemIo = FALSE;
2777 }
2778 for(c=0; c<deviceExtension->NumberChannels; c++) {
2779 chan = &deviceExtension->chan[c];
2780 for (i=0; i<IDX_BM_IO_SZ; i++) {
2781 UniataInitIoRes(chan, IDX_BM_IO+i, BaseIoAddressBM_0 ? ((ULONGIO_PTR)BaseIoAddressBM_0 + i) : 0, MemIo, FALSE);
2782 }
2783 if(BaseIoAddressBM_0) {
2784 BaseIoAddressBM_0++;
2785 }
2786 }
2787 return;
2788} // end UniataInitMapBM()
2789
2790VOID
2791NTAPI
2792UniataInitMapBase(
2793 IN PHW_CHANNEL chan,
2794 IN PIDE_REGISTERS_1 BaseIoAddress1,
2795 IN PIDE_REGISTERS_2 BaseIoAddress2
2796 )
2797{
2798 ULONG i;
2799
2800 for (i=0; i<IDX_IO1_SZ; i++) {
2801 UniataInitIoRes(chan, IDX_IO1+i, BaseIoAddress1 ? ((ULONGIO_PTR)BaseIoAddress1 + i) : 0, FALSE, FALSE);
2802 }
2803 for (i=0; i<IDX_IO2_SZ; i++) {
2804 UniataInitIoRes(chan, IDX_IO2+i, BaseIoAddress2 ? ((ULONGIO_PTR)BaseIoAddress2 + i) : 0, FALSE, FALSE);
2805 }
2806 UniataInitSyncBaseIO(chan);
2807 return;
2808} // end UniataInitMapBase()
2809
2810VOID
2811NTAPI
2812UniataInitSyncBaseIO(
2813 IN PHW_CHANNEL chan
2814 )
2815{
2816 RtlCopyMemory(&chan->RegTranslation[IDX_IO1_o], &chan->RegTranslation[IDX_IO1], IDX_IO1_SZ*sizeof(chan->RegTranslation[0]));
2817 RtlCopyMemory(&chan->RegTranslation[IDX_IO2_o], &chan->RegTranslation[IDX_IO2], IDX_IO2_SZ*sizeof(chan->RegTranslation[0]));
2818 return;
2819} // end UniataInitSyncBaseIO()
2820
2821VOID
2822UniataInitIoRes(
2823 IN PHW_CHANNEL chan,
2824 IN ULONG idx,
2825 IN ULONG addr,
2826 IN BOOLEAN MemIo,
2827 IN BOOLEAN Proc
2828 )
2829{
2830 if(!addr) {
2831 MemIo = Proc = FALSE;
2832 }
2833 chan->RegTranslation[idx].Addr = addr;
2834 chan->RegTranslation[idx].MemIo = MemIo;
2835 chan->RegTranslation[idx].Proc = Proc;
2836} // end UniataInitIoRes()
2837
2838VOID
2839UniataInitIoResEx(
2840 IN PIORES IoRes,
2841 IN ULONG addr,
2842 IN BOOLEAN MemIo,
2843 IN BOOLEAN Proc
2844 )
2845{
2846 if(!addr) {
2847 MemIo = Proc = FALSE;
2848 }
2849 IoRes->Addr = addr;
2850 IoRes->MemIo = MemIo;
2851 IoRes->Proc = Proc;
2852} // end UniataInitIoResEx()
2853
2854VOID
2855NTAPI
2856AtapiSetupLunPtrs(
2857 IN PHW_CHANNEL chan,
2858 IN PHW_DEVICE_EXTENSION deviceExtension,
2859 IN ULONG c
2860 )
2861{
2862 ULONG i;
2863
2864 KdPrint2((PRINT_PREFIX "AtapiSetupLunPtrs for channel %d of %d, %d luns \n", c, deviceExtension->NumberChannels, deviceExtension->NumberLuns));
2865
2866 if(!deviceExtension->NumberLuns) {
2867 KdPrint2((PRINT_PREFIX "Achtung !deviceExtension->NumberLuns \n"));
2868 deviceExtension->NumberLuns = IDE_MAX_LUN_PER_CHAN;
2869 }
2870 KdPrint2((PRINT_PREFIX " Chan %#x\n", chan));
2871 chan->DeviceExtension = deviceExtension;
2872 chan->lChannel = c;
2873 chan->NumberLuns = deviceExtension->NumberLuns;
2874 for(i=0; i<deviceExtension->NumberLuns; i++) {
2875 chan->lun[i] = &(deviceExtension->lun[c*deviceExtension->NumberLuns+i]);
2876 KdPrint2((PRINT_PREFIX " Lun %#x\n", i));
2877 KdPrint2((PRINT_PREFIX " Lun ptr %#x\n", chan->lun[i]));
2878 }
2879 chan->AltRegMap = deviceExtension->AltRegMap;
2880 chan->NextDpcChan = -1;
2881 chan->last_devsel = -1;
2882 for(i=0; i<deviceExtension->NumberLuns; i++) {
2883 chan->lun[i]->DeviceExtension = deviceExtension;
2884 chan->lun[i]->chan = chan;
2885 chan->lun[i]->Lun = i;
2886 }
2887 if((deviceExtension->HwFlags & UNIATA_AHCI) &&
2888 deviceExtension->AhciInternalAtaReq0 &&
2889 deviceExtension->AhciInternalSrb0) {
2890 chan->AhciInternalAtaReq = &(deviceExtension->AhciInternalAtaReq0[c]);
2891 chan->AhciInternalSrb = &(deviceExtension->AhciInternalSrb0[c]);
2892 UniataAhciSetupCmdPtr(chan->AhciInternalAtaReq);
2893 chan->AhciInternalSrb->SrbExtension = chan->AhciInternalAtaReq;
2894 chan->AhciInternalAtaReq->Srb = chan->AhciInternalSrb;
2895 }
2896 return;
2897} // end AtapiSetupLunPtrs()
2898
2899BOOLEAN
2900NTAPI
2901UniataAllocateLunExt(
2902 PHW_DEVICE_EXTENSION deviceExtension,
2903 ULONG NewNumberChannels
2904 )
2905{
2906 PHW_LU_EXTENSION old_luns = NULL;
2907 PHW_CHANNEL old_chans = NULL;
2908
2909 KdPrint2((PRINT_PREFIX "allocate %d Luns for %d channels\n", deviceExtension->NumberLuns, deviceExtension->NumberChannels));
2910
2911 old_luns = deviceExtension->lun;
2912 old_chans = deviceExtension->chan;
2913
2914 if(old_luns || old_chans) {
2915 if(NewNumberChannels == UNIATA_ALLOCATE_NEW_LUNS) {
2916 KdPrint2((PRINT_PREFIX "already allocated!\n"));
2917 return FALSE;
2918 }
2919 }
2920
2921 if(!deviceExtension->NumberLuns) {
2922 KdPrint2((PRINT_PREFIX "default NumberLuns=2\n"));
2923 deviceExtension->NumberLuns = 2;
2924 }
2925
2926 if(deviceExtension->HwFlags & UNIATA_AHCI) {
2927 if(!deviceExtension->AhciInternalAtaReq0) {
2928 deviceExtension->AhciInternalAtaReq0 = (PATA_REQ)ExAllocatePool(NonPagedPool, sizeof(ATA_REQ)*deviceExtension->NumberChannels);
2929 if (!deviceExtension->AhciInternalAtaReq0) {
2930 KdPrint2((PRINT_PREFIX "!deviceExtension->AhciInternalAtaReq0 => SP_RETURN_ERROR\n"));
2931 return FALSE;
2932 }
2933 RtlZeroMemory(deviceExtension->AhciInternalAtaReq0, sizeof(ATA_REQ)*deviceExtension->NumberChannels);
2934 }
2935 if(!deviceExtension->AhciInternalSrb0) {
2936 deviceExtension->AhciInternalSrb0 = (PSCSI_REQUEST_BLOCK)ExAllocatePool(NonPagedPool, sizeof(SCSI_REQUEST_BLOCK)*deviceExtension->NumberChannels);
2937 if (!deviceExtension->AhciInternalSrb0) {
2938 KdPrint2((PRINT_PREFIX "!deviceExtension->AhciInternalSrb0 => SP_RETURN_ERROR\n"));
2939 UniataFreeLunExt(deviceExtension);
2940 return FALSE;
2941 }
2942 RtlZeroMemory(deviceExtension->AhciInternalSrb0, sizeof(SCSI_REQUEST_BLOCK)*deviceExtension->NumberChannels);
2943 }
2944 }
2945
2946 deviceExtension->lun = (PHW_LU_EXTENSION)ExAllocatePool(NonPagedPool, sizeof(HW_LU_EXTENSION) * (deviceExtension->NumberChannels+1) * deviceExtension->NumberLuns);
2947 if (!deviceExtension->lun) {
2948 KdPrint2((PRINT_PREFIX "!deviceExtension->lun => SP_RETURN_ERROR\n"));
2949 UniataFreeLunExt(deviceExtension);
2950 return FALSE;
2951 }
2952 RtlZeroMemory(deviceExtension->lun, sizeof(HW_LU_EXTENSION) * (deviceExtension->NumberChannels+1) * deviceExtension->NumberLuns);
2953
2954 deviceExtension->chan = (PHW_CHANNEL)ExAllocatePool(NonPagedPool, sizeof(HW_CHANNEL) * (deviceExtension->NumberChannels+1));
2955 if (!deviceExtension->chan) {
2956 UniataFreeLunExt(deviceExtension);
2957 KdPrint2((PRINT_PREFIX "!deviceExtension->chan => SP_RETURN_ERROR\n"));
2958 return FALSE;
2959 }
2960 RtlZeroMemory(deviceExtension->chan, sizeof(HW_CHANNEL) * (deviceExtension->NumberChannels+1));
2961 return TRUE;
2962} // end UniataAllocateLunExt()
2963
2964VOID
2965NTAPI
2966UniataFreeLunExt(
2967 PHW_DEVICE_EXTENSION deviceExtension
2968 )
2969{
2970 if (deviceExtension->lun) {
2971 ExFreePool(deviceExtension->lun);
2972 deviceExtension->lun = NULL;
2973 }
2974 if (deviceExtension->chan) {
2975 ExFreePool(deviceExtension->chan);
2976 deviceExtension->chan = NULL;
2977 }
2978 if(deviceExtension->AhciInternalAtaReq0) {
2979 ExFreePool(deviceExtension->AhciInternalAtaReq0);
2980 deviceExtension->AhciInternalAtaReq0 = NULL;
2981 }
2982 if(deviceExtension->AhciInternalSrb0) {
2983 ExFreePool(deviceExtension->AhciInternalSrb0);
2984 deviceExtension->AhciInternalSrb0 = NULL;
2985 }
2986
2987 return;
2988} // end UniataFreeLunExt()
2989
BOOLEAN
unsigned char BOOLEAN
Definition: ProcessorBind.h:185
PHW_DEVICE_EXTENSION
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
PHW_LU_EXTENSION
struct _HW_LU_EXTENSION * PHW_LU_EXTENSION
NTSTATUS
LONG NTSTATUS
Definition: precomp.h:26
BusMasterAdapters
BUSMASTER_CONTROLLER_INFORMATION_BASE const BusMasterAdapters[]
Definition: bm_devs.h:40
UNIATA_NO80CHK
#define UNIATA_NO80CHK
Definition: bm_devs_decl.h:630
UNIATA_SIMPLEX_ONLY
#define UNIATA_SIMPLEX_ONLY
Definition: bm_devs_decl.h:624
ITE_33
#define ITE_33
Definition: bm_devs_decl.h:722
ATA_ATI_IXP600
#define ATA_ATI_IXP600
Definition: bm_devs_decl.h:154
ATA_JMB366
#define ATA_JMB366
Definition: bm_devs_decl.h:324
ATA_VIACX700IDE
#define ATA_VIACX700IDE
Definition: bm_devs_decl.h:595
SISSATA
#define SISSATA
Definition: bm_devs_decl.h:676
ATA_INTEL_ID
#define ATA_INTEL_ID
Definition: bm_devs_decl.h:184
ATA_CYRIX_ID
#define ATA_CYRIX_ID
Definition: bm_devs_decl.h:168
NV4OFF
#define NV4OFF
Definition: bm_devs_decl.h:697
NUM_BUSMASTER_ADAPTERS
#define NUM_BUSMASTER_ADAPTERS
Definition: bm_devs_decl.h:742
ALINEW
#define ALINEW
Definition: bm_devs_decl.h:637
SIS33
#define SIS33
Definition: bm_devs_decl.h:682
ATA_SIS5518
#define ATA_SIS5518
Definition: bm_devs_decl.h:526
SWKSMIO
#define SWKSMIO
Definition: bm_devs_decl.h:661
ATI700
#define ATI700
Definition: bm_devs_decl.h:666
VIABAR
#define VIABAR
Definition: bm_devs_decl.h:709
PRNEW
#define PRNEW
Definition: bm_devs_decl.h:646
ICH5
#define ICH5
Definition: bm_devs_decl.h:691
HPT372
#define HPT372
Definition: bm_devs_decl.h:641
SIS133NEW
#define SIS133NEW
Definition: bm_devs_decl.h:677
ATA_VIASATAIDE
#define ATA_VIASATAIDE
Definition: bm_devs_decl.h:597
PBUSMASTER_CONTROLLER_INFORMATION_BASE
struct _BUSMASTER_CONTROLLER_INFORMATION_BASE * PBUSMASTER_CONTROLLER_INFORMATION_BASE
NVQ
#define NVQ
Definition: bm_devs_decl.h:698
Ata_is_dev_listed
__inline ULONG Ata_is_dev_listed(IN PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG VendorId, ULONG DeviceId, ULONG RevId, ULONG lim)
Definition: bm_devs_decl.h:753
ATA_VIA82C571
#define ATA_VIA82C571
Definition: bm_devs_decl.h:572
ATA_VIASATAIDE2
#define ATA_VIASATAIDE2
Definition: bm_devs_decl.h:599
ITE_133
#define ITE_133
Definition: bm_devs_decl.h:723
PRTX
#define PRTX
Definition: bm_devs_decl.h:647
SIINOSATAIRQ
#define SIINOSATAIRQ
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PCI_DEV_HW_SPEC_BM
#define PCI_DEV_HW_SPEC_BM(idhi, idlo, rev, mode, name, flags)
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CHIPTYPE_MASK
#define CHIPTYPE_MASK
Definition: bm_devs_decl.h:620
SIS100OLD
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Definition: bm_devs_decl.h:680
SIIMIO
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Definition: bm_devs_decl.h:665
ATA_SIS5517
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UNIATA_SATA
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HPTOLD
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#define UNIATA_AHCI
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SIS100NEW
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ATA_PROMISE_ID
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Definition: bm_devs_decl.h:715
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ATA_JMB368
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ATA_SIS_ID
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I6CH2
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VIACLK
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ATA_SIS5513
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ATA_ATI_IXP700
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CHIPFLAG_MASK
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BMLIST_TERMINATOR
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ATA_VIASATAIDE3
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ScsiPortFreeDeviceBase
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Definition: scsiport.c:553
ScsiPortGetBusData
ULONG NTAPI ScsiPortGetBusData(IN PVOID DeviceExtension, IN ULONG BusDataType, IN ULONG SystemIoBusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
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IDX_INDEXED_ADDR
#define IDX_INDEXED_ADDR
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PHW_CHANNEL
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AtapiWritePortEx1
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#define ChangePciConfig1(offs, _op)
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AtapiFindListedDev
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#define IDX_SATA_SControl
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#define IDX_SATA_IO_SZ
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IDX_BM_DeviceSpecific0
#define IDX_BM_DeviceSpecific0
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AtapiReadPort1
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
AtapiReadPort4
ULONG DDKFASTAPI AtapiReadPort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
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#define GetPciConfig1(offs, op)
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#define IDX_BM_PRD_Table
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IDX_INDEXED_DATA
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AtapiReadPortEx4
ULONG DDKFASTAPI AtapiReadPortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
g_opt_VirtualMachine
ULONG g_opt_VirtualMachine
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#define GetPciConfig4(offs, op)
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Definition: bsmaster.h:103
IDX_BM_IO_SZ
#define IDX_BM_IO_SZ
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AtapiWritePort4
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
PATA_REQ
union _ATA_REQ * PATA_REQ
UNIATA_ALLOCATE_NEW_LUNS
#define UNIATA_ALLOCATE_NEW_LUNS
Definition: bsmaster.h:1398
AtapiWritePort2
VOID DDKFASTAPI AtapiWritePort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
IDX_BM_Command
#define IDX_BM_Command
Definition: bsmaster.h:167
SetPciConfig2
#define SetPciConfig2(offs, op)
Definition: bsmaster.h:1659
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#define GEOM_AUTO
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Definition: bsmaster.h:119
PCISLOTNUM_NOT_SPECIFIED
#define PCISLOTNUM_NOT_SPECIFIED
Definition: bsmaster.h:1452
SATA_MAX_PM_UNITS
#define SATA_MAX_PM_UNITS
Definition: bsmaster.h:110
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BOOLEAN g_opt_AtapiDmaRawRead
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Definition: bsmaster.h:1903
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#define GetPciConfig2(offs, op)
Definition: bsmaster.h:1649
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VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
CTRFLAGS_NO_SLAVE
#define CTRFLAGS_NO_SLAVE
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Definition: glfuncs.h:248
j
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
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Definition: id_init.cpp:2901
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Definition: id_init.cpp:50
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Definition: id_init.cpp:339
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VOID UniataInitIoRes(IN PHW_CHANNEL chan, IN ULONG idx, IN ULONG addr, IN BOOLEAN MemIo, IN BOOLEAN Proc)
Definition: id_init.cpp:2822
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VOID NTAPI AtapiSetupLunPtrs(IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
Definition: id_init.cpp:2856
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Definition: id_init.cpp:58
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Definition: id_init.cpp:2839
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Definition: id_init.cpp:2765
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Definition: id_init.cpp:2812
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Definition: id_init.cpp:1544
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Definition: id_init.cpp:1886
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Definition: id_init.cpp:1440
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Definition: id_init.cpp:1492
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Definition: id_init.cpp:1687
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Definition: id_init.cpp:1375
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Definition: id_init.cpp:1789
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enum _BUS_DATA_TYPE BUS_DATA_TYPE
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Definition: bsmaster.h:1059
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struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]
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Definition: bsmaster.h:1296
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IORES BaseIoAHCI_0
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PATA_REQ AhciInternalAtaReq0
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ULONG MaximumDmaTransferLength
Definition: bsmaster.h:1317
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IORES BaseIoAddressBM_0
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struct _PCI_SLOT_NUMBER::@4322::@4323 bits
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union _PCI_SLOT_NUMBER::@4322 u
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