40#define DFLAGS_DEVICE_PRESENT 0x0001
41#define DFLAGS_ATAPI_DEVICE 0x0002
42#define DFLAGS_TAPE_DEVICE 0x0004
43#define DFLAGS_INT_DRQ 0x0008
45#define DFLAGS_REMOVABLE_DRIVE 0x0010
47#define DFLAGS_MEDIA_STATUS_ENABLED 0x0020
48#define DFLAGS_ATAPI_CHANGER 0x0040
49#define DFLAGS_SANYO_ATAPI_CHANGER 0x0080
50#define DFLAGS_CHANGER_INITED 0x0100
61#define ATAPI_MODE_SENSE 0x5A
62#define ATAPI_MODE_SELECT 0x55
63#define ATAPI_FORMAT_UNIT 0x24
102#define IDE_COMMAND_ATAPI_RESET 0x08
103#define IDE_COMMAND_RECALIBRATE 0x10
104#define IDE_COMMAND_READ 0x20
105#define IDE_COMMAND_WRITE 0x30
106#define IDE_COMMAND_VERIFY 0x40
107#define IDE_COMMAND_SEEK 0x70
108#define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91
109#define IDE_COMMAND_ATAPI_PACKET 0xA0
110#define IDE_COMMAND_ATAPI_IDENTIFY 0xA1
111#define IDE_COMMAND_READ_MULTIPLE 0xC4
112#define IDE_COMMAND_WRITE_MULTIPLE 0xC5
113#define IDE_COMMAND_SET_MULTIPLE 0xC6
114#define IDE_COMMAND_READ_DMA 0xC8
115#define IDE_COMMAND_WRITE_DMA 0xCA
116#define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
117#define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF
118#define IDE_COMMAND_IDENTIFY 0xEC
119#define IDE_COMMAND_MEDIA_EJECT 0xED
125#define IDE_STATUS_ERROR 0x01
126#define IDE_STATUS_INDEX 0x02
127#define IDE_STATUS_CORRECTED_ERROR 0x04
128#define IDE_STATUS_DRQ 0x08
129#define IDE_STATUS_DSC 0x10
130#define IDE_STATUS_DRDY 0x40
131#define IDE_STATUS_IDLE 0x50
132#define IDE_STATUS_BUSY 0x80
138#define IDE_DRIVE_SELECT_1 0xA0
139#define IDE_DRIVE_SELECT_2 0x10
145#define IDE_DC_DISABLE_INTERRUPTS 0x02
146#define IDE_DC_RESET_CONTROLLER 0x04
147#define IDE_DC_REENABLE_CONTROLLER 0x00
153#define IDE_ERROR_BAD_BLOCK 0x80
154#define IDE_ERROR_DATA_ERROR 0x40
155#define IDE_ERROR_MEDIA_CHANGE 0x20
156#define IDE_ERROR_ID_NOT_FOUND 0x10
157#define IDE_ERROR_MEDIA_CHANGE_REQ 0x08
158#define IDE_ERROR_COMMAND_ABORTED 0x04
159#define IDE_ERROR_END_OF_MEDIA 0x02
160#define IDE_ERROR_ILLEGAL_LENGTH 0x01
185#define ATAPI_IR_COD 0x01
186#define ATAPI_IR_IO 0x02
280#define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
286#define IDENTIFY_CAPABILITIES_DMA_SUPPORTED 0x0100
287#define IDENTIFY_CAPABILITIES_LBA_SUPPORTED 0x0200
293#define IDENTIFY_DMA_CYCLES_MODE_0 0x00
294#define IDENTIFY_DMA_CYCLES_MODE_1 0x01
295#define IDENTIFY_DMA_CYCLES_MODE_2 0x02
306 {
"1095", 4,
"0640", 4},
307 {
"1039", 4,
"0601", 4}
310#define BROKEN_ADAPTERS (sizeof(BrokenAdapters) / sizeof(BROKEN_CONTROLLER_INFORMATION))
320 {
"10ad", 4,
"0105", 4}
322#define NUM_NATIVE_MODE_ADAPTERS (sizeof(NativeModeAdapters) / sizeof(NATIVE_MODE_CONTROLLER_INFORMATION))
328#define GetStatus(BaseIoAddress, Status) \
329 Status = ScsiPortReadPortUchar(&BaseIoAddress->AlternateStatus);
331#define GetBaseStatus(BaseIoAddress, Status) \
332 Status = ScsiPortReadPortUchar(&BaseIoAddress->Command);
334#define WriteCommand(BaseIoAddress, Command) \
335 ScsiPortWritePortUchar(&BaseIoAddress->Command, Command);
339#define ReadBuffer(BaseIoAddress, Buffer, Count) \
340 ScsiPortReadPortBufferUshort(&BaseIoAddress->Data, \
344#define WriteBuffer(BaseIoAddress, Buffer, Count) \
345 ScsiPortWritePortBufferUshort(&BaseIoAddress->Data, \
349#define ReadBuffer2(BaseIoAddress, Buffer, Count) \
350 ScsiPortReadPortBufferUlong(&BaseIoAddress->Data, \
354#define WriteBuffer2(BaseIoAddress, Buffer, Count) \
355 ScsiPortWritePortBufferUlong(&BaseIoAddress->Data, \
359#define WaitOnBusy(BaseIoAddress, Status) \
362 for (i=0; i<20000; i++) { \
363 GetStatus(BaseIoAddress, Status); \
364 if (Status & IDE_STATUS_BUSY) { \
365 ScsiPortStallExecution(150); \
373#define WaitOnBaseBusy(BaseIoAddress, Status) \
376 for (i=0; i<20000; i++) { \
377 GetBaseStatus(BaseIoAddress, Status); \
378 if (Status & IDE_STATUS_BUSY) { \
379 ScsiPortStallExecution(150); \
387#define WaitForDrq(BaseIoAddress, Status) \
390 for (i=0; i<1000; i++) { \
391 GetStatus(BaseIoAddress, Status); \
392 if (Status & IDE_STATUS_BUSY) { \
393 ScsiPortStallExecution(100); \
394 } else if (Status & IDE_STATUS_DRQ) { \
397 ScsiPortStallExecution(200); \
403#define WaitShortForDrq(BaseIoAddress, Status) \
406 for (i=0; i<2; i++) { \
407 GetStatus(BaseIoAddress, Status); \
408 if (Status & IDE_STATUS_BUSY) { \
409 ScsiPortStallExecution(100); \
410 } else if (Status & IDE_STATUS_DRQ) { \
413 ScsiPortStallExecution(100); \
418#define AtapiSoftReset(BaseIoAddress,DeviceNumber) \
421 ULONG i = 1000*1000;\
422 ScsiPortWritePortUchar(&BaseIoAddress->DriveSelect,(UCHAR)(((DeviceNumber & 0x1) << 4) | 0xA0)); \
423 ScsiPortStallExecution(500);\
424 ScsiPortWritePortUchar(&BaseIoAddress->Command, IDE_COMMAND_ATAPI_RESET); \
425 while ((ScsiPortReadPortUchar(&BaseIoAddress->Command) & IDE_STATUS_BUSY) && i--)\
426 ScsiPortStallExecution(30);\
427 ScsiPortWritePortUchar(&BaseIoAddress->DriveSelect,(UCHAR)((DeviceNumber << 4) | 0xA0)); \
428 WaitOnBusy( ((PIDE_REGISTERS_2)((PUCHAR)BaseIoAddress + 0x206)), statusByte); \
429 ScsiPortStallExecution(500);\
432#define IdeHardReset(BaseIoAddress,result) \
436 ScsiPortWritePortUchar(&BaseIoAddress->AlternateStatus,IDE_DC_RESET_CONTROLLER );\
437 ScsiPortStallExecution(50 * 1000);\
438 ScsiPortWritePortUchar(&BaseIoAddress->AlternateStatus,IDE_DC_REENABLE_CONTROLLER);\
439 for (i = 0; i < 1000 * 1000; i++) {\
440 statusByte = ScsiPortReadPortUchar(&BaseIoAddress->AlternateStatus);\
441 if (statusByte != IDE_STATUS_IDLE && statusByte != 0x0) {\
442 ScsiPortStallExecution(5);\
447 if (i == 1000*1000) {\
453#define IS_RDP(OperationCode)\
454 ((OperationCode == SCSIOP_ERASE)||\
455 (OperationCode == SCSIOP_LOAD_UNLOAD)||\
456 (OperationCode == SCSIOP_LOCATE)||\
457 (OperationCode == SCSIOP_REWIND) ||\
458 (OperationCode == SCSIOP_SPACE)||\
459 (OperationCode == SCSIOP_SEEK)||\
460 (OperationCode == SCSIOP_WRITE_FILEMARKS))
struct _IDENTIFY_DATA * PIDENTIFY_DATA
struct _IDE_REGISTERS_3 * PIDE_REGISTERS_3
struct _MODE_SENSE_10 MODE_SENSE_10
struct _IDENTIFY_DATA IDENTIFY_DATA
struct _IDE_REGISTERS_2 IDE_REGISTERS_2
struct _ATAPI_REGISTERS_2 ATAPI_REGISTERS_2
struct _ATAPI_REGISTERS_1 ATAPI_REGISTERS_1
struct _IDE_REGISTERS_2 * PIDE_REGISTERS_2
struct _BROKEN_CONTROLLER_INFORMATION * PBROKEN_CONTROLLER_INFORMATION
struct _IDENTIFY_DATA2 IDENTIFY_DATA2
struct _NATIVE_MODE_CONTROLLER_INFORMATION NATIVE_MODE_CONTROLLER_INFORMATION
struct _IDE_REGISTERS_1 IDE_REGISTERS_1
struct _IDE_REGISTERS_3 IDE_REGISTERS_3
struct _MODE_SELECT_10 MODE_SELECT_10
struct _MODE_PARAMETER_HEADER_10 MODE_PARAMETER_HEADER_10
struct _NATIVE_MODE_CONTROLLER_INFORMATION * PNATIVE_MODE_CONTROLLER_INFORMATION
struct _BROKEN_CONTROLLER_INFORMATION BROKEN_CONTROLLER_INFORMATION
struct _MODE_PARAMETER_HEADER_10 * PMODE_PARAMETER_HEADER_10
struct _IDENTIFY_DATA2 * PIDENTIFY_DATA2
struct _IDE_REGISTERS_1 * PIDE_REGISTERS_1
struct _MODE_SENSE_10 * PMODE_SENSE_10
BROKEN_CONTROLLER_INFORMATION const BrokenAdapters[]
struct _ATAPI_REGISTERS_2 * PATAPI_REGISTERS_2
struct _ATAPI_REGISTERS_1 * PATAPI_REGISTERS_1
NATIVE_MODE_CONTROLLER_INFORMATION const NativeModeAdapters[]
struct _MODE_SELECT_10 * PMODE_SELECT_10
USHORT TranslationFieldsValid
USHORT CurrentSectorsPerTrack
USHORT UnformattedBytesPerSector
UCHAR MaximumBlockTransfer
USHORT NumberOfCurrentHeads
USHORT FirmwareRevision[4]
USHORT GeneralConfiguration
USHORT UnformattedBytesPerTrack
ULONG CurrentSectorCapacity
USHORT NumberOfCurrentCylinders
USHORT NumberOfCurrentCylinders
USHORT UnformattedBytesPerSector
USHORT SingleWordDMASupport
USHORT NumberOfCurrentHeads
ULONG UserAddressableSectors
USHORT MultiWordDMASupport
USHORT GeneralConfiguration
USHORT CurrentSectorsPerTrack
USHORT CurrentMultiSectorSetting
USHORT TranslationFieldsValid
USHORT ReleaseTimeServiceCommand
USHORT UnformattedBytesPerTrack
USHORT SingleWordDMAActive
USHORT FirmwareRevision[4]
UCHAR MaximumBlockTransfer
USHORT MultiWordDMAActive
USHORT SpecialFunctionsEnabled
USHORT RecommendedMWXferCycleTime
USHORT MinimumPIOCycleTimeIORDY
USHORT MinimumMWXferCycleTime
USHORT ReleaseTimeOverlapped
ULONG CurrentSectorCapacity
USHORT MinimumPIOCycleTime
UCHAR ParameterListLengthLsb
UCHAR ParameterListLengthMsb
UCHAR ParameterListLengthMsb
UCHAR ParameterListLengthLsb
_Reserved_ PVOID Reserved