44#ifndef __IDE_BUSMASTER_H__
45#define __IDE_BUSMASTER_H__
55#define ATA_IMMEDIATE 0x1
56#define ATA_WAIT_INTR 0x2
57#define ATA_WAIT_READY 0x3
59#define ATA_ACTIVE_ATA 0x5
60#define ATA_ACTIVE_ATAPI 0x6
61#define ATA_REINITING 0x7
62#define ATA_WAIT_BASE_READY 0x8
63#define ATA_WAIT_IDLE 0x9
80#define IP_PC98_BANK 0x432
81#define IO_FLOPPY_INT 0x3F6
83#define PCI_ADDRESS_IOMASK 0xfffffff0
85#define ATA_BM_OFFSET1 0x08
86#define ATA_IOSIZE 0x08
87#define ATA_ALTOFFSET 0x206
88#define ATA_PCCARD_ALTOFFSET 0x0e
89#define ATA_ALTIOSIZE 0x01
90#define ATA_BMIOSIZE 0x20
91#define ATA_PC98_BANKIOSIZE 0x01
94#define ATA_MAX_IOLBA28 DEF_U64(0x0fffff80)
95#define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
97#define ATA_MAX_IOLBA32 DEF_U64(0xffffff80)
98#define ATA_MAX_LBA32 DEF_U64(0xffffffff)
100#define ATA_DMA_ENTRIES 256
101#define ATA_DMA_EOT 0x80000000
105#define ATAPI_MAGIC_LSB 0x14
106#define ATAPI_MAGIC_MSB 0xeb
108#define AHCI_MAX_PORT 32
110#define SATA_MAX_PM_UNITS 16
117#define PCI_DEV_CLASS_STORAGE 0x01
119#define PCI_DEV_SUBCLASS_IDE 0x01
120#define PCI_DEV_SUBCLASS_RAID 0x04
121#define PCI_DEV_SUBCLASS_ATA 0x05
122#define PCI_DEV_SUBCLASS_SATA 0x06
124#define PCI_DEV_PROGIF_AHCI_1_0 0x01
142#define BM_STATUS_ACTIVE 0x01
143#define BM_STATUS_ERR 0x02
144#define BM_STATUS_INTR 0x04
145#define BM_STATUS_MASK 0x07
146#define BM_STATUS_DRIVE_0_DMA 0x20
147#define BM_STATUS_DRIVE_1_DMA 0x40
148#define BM_STATUS_SIMPLEX_ONLY 0x80
150#define BM_COMMAND_START_STOP 0x01
153#define BM_COMMAND_WRITE 0x00
154#define BM_COMMAND_READ 0x08
156#define BM_DS0_SII_DMA_ENABLE (1 << 0)
157#define BM_DS0_SII_IRQ (1 << 3)
158#define BM_DS0_SII_DMA_SATA_IRQ (1 << 4)
159#define BM_DS0_SII_DMA_ERROR (1 << 17)
160#define BM_DS0_SII_DMA_COMPLETE (1 << 18)
163#define IDX_BM_IO (IDX_IO2_o+IDX_IO2_o_SZ)
165#define IDX_BM_IO_SZ 5
167#define IDX_BM_Command (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
168#define IDX_BM_DeviceSpecific0 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
169#define IDX_BM_Status (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
170#define IDX_BM_DeviceSpecific1 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
171#define IDX_BM_PRD_Table (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
200#define AHCI_CAP_NOP_MASK 0x0000001f
201#define AHCI_CAP_CCC 0x00000080
202#define AHCI_CAP_NCS_MASK 0x00001f00
203#define AHCI_CAP_PMD 0x00008000
204#define AHCI_CAP_SPM 0x00020000
205#define AHCI_CAP_SAM 0x00040000
206#define AHCI_CAP_ISS_MASK 0x00f00000
207#define AHCI_CAP_SCLO 0x01000000
208#define AHCI_CAP_SNTF 0x20000000
209#define AHCI_CAP_NCQ 0x40000000
210#define AHCI_CAP_S64A 0x80000000
221#define AHCI_GHC_HR 0x00000001
222#define AHCI_GHC_IE 0x00000002
223#define AHCI_GHC_AE 0x80000000
245#define AHCI_CAP2_BOH 0x00000001
246#define AHCI_CAP2_NVMP 0x00000002
247#define AHCI_CAP2_APST 0x00000004
259#define AHCI_BOHC_BB 0x00000001
260#define AHCI_BOHC_OOC 0x00000002
261#define AHCI_BOHC_SOOE 0x00000004
262#define AHCI_BOHC_OOS 0x00000008
263#define AHCI_BOHC_BOS 0x00000010
270#define IDX_AHCI_CAP (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
271#define IDX_AHCI_GHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
272#define IDX_AHCI_IS (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
273#define IDX_AHCI_VS (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
274#define IDX_AHCI_PI (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
275#define IDX_AHCI_CAP2 (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))
276#define IDX_AHCI_BOHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))
284#define SStatus_DET_NoDev 0x00
285#define SStatus_DET_Dev_NoPhy 0x01
286#define SStatus_DET_Dev_Ok 0x03
287#define SStatus_DET_Offline 0x04
291#define SStatus_SPD_NoDev 0x00
292#define SStatus_SPD_Gen1 0x01
293#define SStatus_SPD_Gen2 0x02
294#define SStatus_SPD_Gen3 0x03
298#define SStatus_IPM_NoDev 0x00
299#define SStatus_IPM_Active 0x01
300#define SStatus_IPM_Partial 0x02
301#define SStatus_IPM_Slumber 0x06
309#define ATA_SS_DET_MASK 0x0000000f
310#define ATA_SS_DET_NO_DEVICE 0x00000000
311#define ATA_SS_DET_DEV_PRESENT 0x00000001
312#define ATA_SS_DET_PHY_ONLINE 0x00000003
313#define ATA_SS_DET_PHY_OFFLINE 0x00000004
315#define ATA_SS_SPD_MASK 0x000000f0
316#define ATA_SS_SPD_NO_SPEED 0x00000000
317#define ATA_SS_SPD_GEN1 0x00000010
318#define ATA_SS_SPD_GEN2 0x00000020
320#define ATA_SS_IPM_MASK 0x00000f00
321#define ATA_SS_IPM_NO_DEVICE 0x00000000
322#define ATA_SS_IPM_ACTIVE 0x00000100
323#define ATA_SS_IPM_PARTIAL 0x00000200
324#define ATA_SS_IPM_SLUMBER 0x00000600
331#define SControl_DET_DoNothing 0x00
332#define SControl_DET_Idle 0x00
333#define SControl_DET_Init 0x01
334#define SControl_DET_Disable 0x04
338#define SControl_SPD_NoRestrict 0x00
339#define SControl_SPD_LimGen1 0x01
340#define SControl_SPD_LimGen2 0x02
341#define SControl_SPD_LimGen3 0x03
345#define SControl_IPM_NoRestrict 0x00
346#define SControl_IPM_NoPartial 0x01
347#define SControl_IPM_NoSlumber 0x02
348#define SControl_IPM_NoPartialSlumber 0x03
358#define ATA_SC_DET_MASK 0x0000000f
359#define ATA_SC_DET_IDLE 0x00000000
360#define ATA_SC_DET_RESET 0x00000001
361#define ATA_SC_DET_DISABLE 0x00000004
363#define ATA_SC_SPD_MASK 0x000000f0
364#define ATA_SC_SPD_NO_SPEED 0x00000000
365#define ATA_SC_SPD_SPEED_GEN1 0x00000010
366#define ATA_SC_SPD_SPEED_GEN2 0x00000020
367#define ATA_SC_SPD_SPEED_GEN3 0x00000040
369#define ATA_SC_IPM_MASK 0x00000f00
370#define ATA_SC_IPM_NONE 0x00000000
371#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
372#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
409#define ATA_SE_DATA_CORRECTED 0x00000001
410#define ATA_SE_COMM_CORRECTED 0x00000002
411#define ATA_SE_DATA_ERR 0x00000100
412#define ATA_SE_COMM_ERR 0x00000200
413#define ATA_SE_PROT_ERR 0x00000400
414#define ATA_SE_HOST_ERR 0x00000800
415#define ATA_SE_PHY_CHANGED 0x00010000
416#define ATA_SE_PHY_IERROR 0x00020000
417#define ATA_SE_COMM_WAKE 0x00040000
418#define ATA_SE_DECODE_ERR 0x00080000
419#define ATA_SE_PARITY_ERR 0x00100000
420#define ATA_SE_CRC_ERR 0x00200000
421#define ATA_SE_HANDSHAKE_ERR 0x00400000
422#define ATA_SE_LINKSEQ_ERR 0x00800000
423#define ATA_SE_TRANSPORT_ERR 0x01000000
424#define ATA_SE_UNKNOWN_FIS 0x02000000
453#define IDX_SATA_IO (IDX_BM_IO+IDX_BM_IO_SZ)
455#define IDX_SATA_IO_SZ 5
457#define IDX_SATA_SStatus (0+IDX_SATA_IO)
458#define IDX_SATA_SError (1+IDX_SATA_IO)
459#define IDX_SATA_SControl (2+IDX_SATA_IO)
460#define IDX_SATA_SActive (3+IDX_SATA_IO)
461#define IDX_SATA_SNTF_PMN (4+IDX_SATA_IO)
463#define IDX_INDEXED_IO (IDX_SATA_IO+IDX_SATA_IO_SZ)
464#define IDX_INDEXED_IO_SZ 2
466#define IDX_INDEXED_ADDR (0+IDX_INDEXED_IO)
467#define IDX_INDEXED_DATA (1+IDX_INDEXED_IO)
469#define IDX_MAX_REG (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
499#define ATA_AHCI_P_IX_DHR 0x00000001
500#define ATA_AHCI_P_IX_PS 0x00000002
501#define ATA_AHCI_P_IX_DS 0x00000004
502#define ATA_AHCI_P_IX_SDB 0x00000008
503#define ATA_AHCI_P_IX_UF 0x00000010
504#define ATA_AHCI_P_IX_DP 0x00000020
505#define ATA_AHCI_P_IX_PC 0x00000040
506#define ATA_AHCI_P_IX_DI 0x00000080
508#define ATA_AHCI_P_IX_PRC 0x00400000
509#define ATA_AHCI_P_IX_IPM 0x00800000
510#define ATA_AHCI_P_IX_OF 0x01000000
511#define ATA_AHCI_P_IX_INF 0x04000000
512#define ATA_AHCI_P_IX_IF 0x08000000
513#define ATA_AHCI_P_IX_HBD 0x10000000
514#define ATA_AHCI_P_IX_HBF 0x20000000
515#define ATA_AHCI_P_IX_TFE 0x40000000
516#define ATA_AHCI_P_IX_CPD 0x80000000
518#define AHCI_CLB_ALIGNEMENT_MASK ((ULONGLONG)(1024-1))
519#define AHCI_FIS_ALIGNEMENT_MASK ((ULONGLONG)(256-1))
520#define AHCI_CMD_ALIGNEMENT_MASK ((ULONGLONG)(128-1))
600#define SATA_CMD_ICC_Idle 0x00
601#define SATA_CMD_ICC_NoOp 0x00
602#define SATA_CMD_ICC_Active 0x01
603#define SATA_CMD_ICC_Partial 0x02
604#define SATA_CMD_ICC_Slumber 0x06
682#define IDX_AHCI_P_CLB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
683#define IDX_AHCI_P_FB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
684#define IDX_AHCI_P_IS (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
685#define IDX_AHCI_P_IE (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))
686#define IDX_AHCI_P_CI (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
687#define IDX_AHCI_P_TFD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
688#define IDX_AHCI_P_SIG (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
689#define IDX_AHCI_P_CMD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
690#define IDX_AHCI_P_SStatus (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))
691#define IDX_AHCI_P_SControl (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))
692#define IDX_AHCI_P_SError (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))
693#define IDX_AHCI_P_ACT (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
695#define IDX_AHCI_P_SNTF (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
698#define ATA_AHCI_P_CMD_ST 0x00000001
699#define ATA_AHCI_P_CMD_SUD 0x00000002
700#define ATA_AHCI_P_CMD_POD 0x00000004
701#define ATA_AHCI_P_CMD_CLO 0x00000008
702#define ATA_AHCI_P_CMD_FRE 0x00000010
703#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
704#define ATA_AHCI_P_CMD_ISS 0x00002000
705#define ATA_AHCI_P_CMD_FR 0x00004000
706#define ATA_AHCI_P_CMD_CR 0x00008000
707#define ATA_AHCI_P_CMD_CPS 0x00010000
708#define ATA_AHCI_P_CMD_PMA 0x00020000
709#define ATA_AHCI_P_CMD_HPCP 0x00040000
710#define ATA_AHCI_P_CMD_ISP 0x00080000
711#define ATA_AHCI_P_CMD_CPD 0x00100000
712#define ATA_AHCI_P_CMD_ESP 0x00200000
713#define ATA_AHCI_P_CMD_ATAPI 0x01000000
714#define ATA_AHCI_P_CMD_DLAE 0x02000000
715#define ATA_AHCI_P_CMD_ALPE 0x04000000
716#define ATA_AHCI_P_CMD_ASP 0x08000000
717#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
718#define ATA_AHCI_P_CMD_NOOP 0x00000000
719#define ATA_AHCI_P_CMD_ACTIVE 0x10000000
720#define ATA_AHCI_P_CMD_PARTIAL 0x20000000
721#define ATA_AHCI_P_CMD_SLUMBER 0x60000000
749#define ATA_AHCI_DMA_ENTRIES (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY))
750#define ATA_AHCI_MAX_TAGS 32
752#define AHCI_FIS_TYPE_ATA_H2D 0x27
753#define AHCI_FIS_TYPE_ATA_D2H 0x34
754#define AHCI_FIS_TYPE_DMA_D2H 0x39
755#define AHCI_FIS_TYPE_DMA_BiDi 0x41
756#define AHCI_FIS_TYPE_DATA_BiDi 0x46
757#define AHCI_FIS_TYPE_BIST_BiDi 0x58
758#define AHCI_FIS_TYPE_PIO_D2H 0x5f
759#define AHCI_FIS_TYPE_DEV_BITS_D2H 0xA1
785#define IDX_AHCI_o_Command (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))
786#define IDX_AHCI_o_Feature (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))
787#define IDX_AHCI_o_BlockNumber (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))
788#define IDX_AHCI_o_CylinderLow (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))
789#define IDX_AHCI_o_CylinderHigh (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))
790#define IDX_AHCI_o_DriveSelect (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))
791#define IDX_AHCI_o_BlockCount (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))
792#define IDX_AHCI_o_Control (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))
793#define IDX_AHCI_o_FeatureExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))
794#define IDX_AHCI_o_BlockNumberExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))
795#define IDX_AHCI_o_CylinderLowExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))
796#define IDX_AHCI_o_CylinderHighExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))
797#define IDX_AHCI_o_BlockCountExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))
799#define AHCI_FIS_COMM_PM (0x80 | AHCI_DEV_SEL_PM)
801#define AHCI_DEV_SEL_1 0x00
802#define AHCI_DEV_SEL_2 0x01
803#define AHCI_DEV_SEL_PM 0x0f
815#define ATA_AHCI_CMD_ATAPI 0x0020
816#define ATA_AHCI_CMD_WRITE 0x0040
817#define ATA_AHCI_CMD_PREFETCH 0x0080
818#define ATA_AHCI_CMD_RESET 0x0100
819#define ATA_AHCI_CMD_BIST 0x0200
820#define ATA_AHCI_CMD_CLR_BUSY 0x0400
853#define IsBusMaster(pciData) \
854 ( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER)) == \
855 (PCI_ENABLE_BUS_MASTER))
857#define PCI_IDE_PROGIF_NATIVE_1 0x01
858#define PCI_IDE_PROGIF_NATIVE_2 0x04
859#define PCI_IDE_PROGIF_NATIVE_ALL 0x05
861#define IsMasterDev(pciData) \
862 ( ((pciData)->ProgIf & 0x80) && \
863 ((pciData)->ProgIf & PCI_IDE_PROGIF_NATIVE_ALL) != PCI_IDE_PROGIF_NATIVE_ALL )
931#define REQ_FLAG_FORCE_DOWNRATE 0x01
932#define REQ_FLAG_DMA_OPERATION 0x02
933#define REQ_FLAG_REORDERABLE_CMD 0x04
934#define REQ_FLAG_RW_MASK 0x08
935#define REQ_FLAG_READ 0x08
936#define REQ_FLAG_WRITE 0x00
937#define REQ_FLAG_FORCE_DOWNRATE_LBA48 0x10
938#define REQ_FLAG_DMA_DBUF 0x20
939#define REQ_FLAG_DMA_DBUF_PRD 0x40
940#define REQ_FLAG_LBA48 0x80
943#define REQ_STATE_NONE 0x00
944#define REQ_STATE_QUEUED 0x10
946#define REQ_STATE_PREPARE_TO_TRANSFER 0x20
947#define REQ_STATE_PREPARE_TO_NEXT 0x21
948#define REQ_STATE_READY_TO_TRANSFER 0x30
950#define REQ_STATE_EXPECTING_INTR 0x40
951#define REQ_STATE_ATAPI_EXPECTING_CMD_INTR 0x41
952#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR 0x42
953#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2 0x43
954#define REQ_STATE_ATAPI_DO_NOTHING_INTR 0x44
956#define REQ_STATE_EARLY_INTR 0x48
958#define REQ_STATE_PROCESSING_INTR 0x50
960#define REQ_STATE_DPC_INTR_REQ 0x51
961#define REQ_STATE_DPC_RESET_REQ 0x52
962#define REQ_STATE_DPC_COMPLETE_REQ 0x53
964#define REQ_STATE_DPC_WAIT_BUSY0 0x57
965#define REQ_STATE_DPC_WAIT_BUSY1 0x58
966#define REQ_STATE_DPC_WAIT_BUSY 0x59
967#define REQ_STATE_DPC_WAIT_DRQ 0x5a
968#define REQ_STATE_DPC_WAIT_DRQ0 0x5b
969#define REQ_STATE_DPC_WAIT_DRQ_ERR 0x5c
971#define REQ_STATE_TRANSFER_COMPLETE 0x7f
974#define CMD_ACTION_PREPARE 0x01
975#define CMD_ACTION_EXEC 0x02
976#define CMD_ACTION_ALL (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
979#define REORDER_COST_MAX ((DEF_I64(0x1) << 60) - 1)
980#define REORDER_COST_TTL (REORDER_COST_MAX - 1)
981#define REORDER_COST_INTERSECT (REORDER_COST_MAX - 2)
982#define REORDER_COST_DENIED (REORDER_COST_MAX - 3)
983#define REORDER_COST_RESELECT (REORDER_COST_MAX/4)
985#define REORDER_COST_SWITCH_RW_CD (REORDER_COST_MAX/8)
986#define REORDER_MCOST_SWITCH_RW_CD (0)
987#define REORDER_MCOST_SEEK_BACK_CD (16)
989#define REORDER_COST_SWITCH_RW_HDD (0)
990#define REORDER_MCOST_SWITCH_RW_HDD (4)
991#define REORDER_MCOST_SEEK_BACK_HDD (2)
1066#define CHECK_INTR_ACTIVE 0x03
1067#define CHECK_INTR_DETECTED 0x02
1068#define CHECK_INTR_CHECK 0x01
1069#define CHECK_INTR_IDLE 0x00
1116#ifdef QUEUE_STATISTICS
1131#define CTRFLAGS_DMA_ACTIVE 0x0001
1132#define CTRFLAGS_DMA_RO 0x0002
1133#define CTRFLAGS_DMA_OPERATION 0x0004
1134#define CTRFLAGS_INTR_DISABLED 0x0008
1135#define CTRFLAGS_DPC_REQ 0x0010
1136#define CTRFLAGS_ENABLE_INTR_REQ 0x0020
1137#define CTRFLAGS_LBA48 0x0040
1138#define CTRFLAGS_DSC_BSY 0x0080
1139#define CTRFLAGS_NO_SLAVE 0x0100
1143#define CTRFLAGS_AHCI_PM 0x0400
1144#define CTRFLAGS_AHCI_PM2 0x0800
1146#define CTRFLAGS_PERMANENT (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
1148#define GEOM_AUTO 0xffffffff
1149#define GEOM_STD 0x0000
1150#define GEOM_UNIATA 0x0001
1151#define GEOM_ORIG 0x0002
1152#define GEOM_MANUAL 0x0003
1154#define DPC_STATE_NONE 0x00
1155#define DPC_STATE_ISR 0x10
1156#define DPC_STATE_DPC 0x20
1157#define DPC_STATE_TIMER 0x30
1158#define DPC_STATE_COMPLETE 0x40
1358#define HBAFLAGS_DMA_DISABLED 0x01
1359#define HBAFLAGS_DMA_DISABLED_LBA48 0x02
1398#define UNIATA_ALLOCATE_NEW_LUNS 0x00
1403 ULONG NewNumberChannels
1451#define PCIBUSNUM_NOT_SPECIFIED (0xffffffffL)
1452#define PCISLOTNUM_NOT_SPECIFIED (0xffffffffL)
1498 PVOID HwDeviceExtension,
1620#define GetPciConfig1(offs, op) { \
1621 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1623 SystemIoBusNumber, \
1630#define SetPciConfig1(offs, op) { \
1632 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1634 SystemIoBusNumber, \
1641#define ChangePciConfig1(offs, _op) { \
1643 GetPciConfig1(offs, a); \
1645 SetPciConfig1(offs, a); \
1649#define GetPciConfig2(offs, op) { \
1650 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1652 SystemIoBusNumber, \
1659#define SetPciConfig2(offs, op) { \
1661 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1663 SystemIoBusNumber, \
1670#define ChangePciConfig2(offs, _op) { \
1672 GetPciConfig2(offs, a); \
1673 a = (USHORT)(_op); \
1674 SetPciConfig2(offs, a); \
1678#define GetPciConfig4(offs, op) { \
1679 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1681 SystemIoBusNumber, \
1688#define SetPciConfig4(offs, op) { \
1690 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1692 SystemIoBusNumber, \
1699#define ChangePciConfig4(offs, _op) { \
1701 GetPciConfig4(offs, a); \
1703 SetPciConfig4(offs, a); \
1706#define DMA_MODE_NONE 0x00
1707#define DMA_MODE_BM 0x01
1708#define DMA_MODE_AHCI 0x02
1711#define GetDmaStatus(de, c) \
1712 (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
1716#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1717 AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
1719#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1720 (ScsiPortConvertPhysicalAddressToUlong( \
1721 ScsiPortGetPhysicalAddress(hwde, srb, phaddr, plen)))
1847#define GET_CHANNEL(Srb) (Srb->PathId)
1850#define GET_CDEV(Srb) (Srb->TargetId)
1904#define VM_VMWARE 0x03
1906#define VM_BOCHS 0x05
1909#define VM_MAX_KNOWN VM_PCEM
BUSMASTER_CONTROLLER_INFORMATION_BASE const BusMasterAdapters[]
#define IDE_MAX_LUN_PER_CHAN
VOID DDKFASTAPI AtapiWriteBuffer2(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
struct _IDE_BUSMASTER_REGISTERS IDE_BUSMASTER_REGISTERS
VOID DDKFASTAPI AtapiWriteBuffer4(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
VOID NTAPI AtapiDmaInit__(IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt)
BOOLEAN NTAPI UniataAllocateLunExt(PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
union _SATA_SERROR_REG * PSATA_SERROR_REG
UCHAR NTAPI AtapiDmaDone(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
struct _HW_CHANNEL * PHW_CHANNEL
struct _IDE_AHCI_CHANNEL_CTL_BLOCK IDE_AHCI_CHANNEL_CTL_BLOCK
VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
NTSTATUS NTAPI UniataChipDetect(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN BOOLEAN *simplexOnly)
struct _AHCI_ATA_H2D_FIS * PAHCI_ATA_H2D_FIS
struct _IDE_AHCI_RCV_FIS IDE_AHCI_RCV_FIS
ULONG NTAPI UniataFindCompatBusMasterController1(IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
union _SATA_SSTATUS_REG SATA_SSTATUS_REG
struct _IDE_AHCI_CMD * PIDE_AHCI_CMD
#define ATA_AHCI_MAX_TAGS
ULONG NTAPI UniataFindCompatBusMasterController2(IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
VOID NTAPI AtapiSetupLunPtrs(IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
union _SATA_SERROR_REG SATA_SERROR_REG
struct _IDE_AHCI_CMD IDE_AHCI_CMD
struct _IDE_AHCI_PRD_ENTRY IDE_AHCI_PRD_ENTRY
BOOLEAN NTAPI UniataChipDetectChannels(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo)
ULONG NTAPI AtapiFindDev(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN ULONG dev_id, IN ULONG RevID)
BOOLEAN NTAPI AtapiDmaDBPreSync(IN PVOID HwDeviceExtension, PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
struct _IDE_AHCI_CMD_LIST * PIDE_AHCI_CMD_LIST
BOOLEAN NTAPI AtapiDmaSetup(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb, IN PUCHAR data, IN ULONG count)
struct _IDE_AHCI_PRD_ENTRY * PIDE_AHCI_PRD_ENTRY
ULONG NTAPI AtapiFindListedDev(PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG lim, IN PVOID HwDeviceExtension, IN ULONG BusNumber, IN ULONG SlotNumber, OUT PCI_SLOT_NUMBER *_slotData)
struct _IDE_AHCI_CHANNEL_CTL_BLOCK * PIDE_AHCI_CHANNEL_CTL_BLOCK
struct _HW_CHANNEL HW_CHANNEL
BOOLEAN NTAPI AtapiDmaDBSync(PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
ULONG g_opt_WaitBusyResetCount
VOID NTAPI UniataForgetDevice(PHW_LU_EXTENSION LunExt)
VOID DDKFASTAPI AtapiReadBuffer4(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
union _SATA_SSTATUS_REG * PSATA_SSTATUS_REG
ULONG DDKFASTAPI AtapiReadPort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
ULONG NTAPI UniataFindBusMasterController(IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
struct _ISR2_DEVICE_EXTENSION * PISR2_DEVICE_EXTENSION
struct _IDE_AHCI_CMD_LIST IDE_AHCI_CMD_LIST
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
union _AHCI_IS_REG * PAHCI_IS_REG
struct _IDE_AHCI_PORT_REGISTERS IDE_AHCI_PORT_REGISTERS
union _SATA_SCONTROL_REG * PSATA_SCONTROL_REG
NTSTATUS NTAPI UniataClaimLegacyPCIIDE(ULONG i)
struct _BUSMASTER_CTX * PBUSMASTER_CTX
NTSTATUS NTAPI UniataConnectIntr2(IN PVOID HwDeviceExtension)
ULONG NTAPI ScsiPortGetBusDataByOffset(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
struct _HW_LU_EXTENSION HW_LU_EXTENSION
struct _IDE_BUSMASTER_REGISTERS * PIDE_BUSMASTER_REGISTERS
union _AHCI_IS_REG AHCI_IS_REG
struct BM_DMA_ENTRY * PBM_DMA_ENTRY
ULONG DDKFASTAPI AtapiReadPortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
struct _IDE_AHCI_REGISTERS IDE_AHCI_REGISTERS
struct _IDE_AHCI_REGISTERS * PIDE_AHCI_REGISTERS
VOID NTAPI AtapiDmaAlloc(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN ULONG lChannel)
ULONG g_opt_VirtualMachine
struct _IDE_SATA_REGISTERS * PIDE_SATA_REGISTERS
UNICODE_STRING SavedRegPath
VOID DDKFASTAPI AtapiReadBuffer2(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
ISR2_DEVICE_EXTENSION PCIIDE_DEVICE_EXTENSION
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
#define ATA_AHCI_DMA_ENTRIES
PISR2_DEVICE_EXTENSION PPCIIDE_DEVICE_EXTENSION
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
struct _HW_LU_EXTENSION * PHW_LU_EXTENSION
union _ATA_REQ * PATA_REQ
struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION
struct _AHCI_ATA_H2D_FIS AHCI_ATA_H2D_FIS
VOID NTAPI AtapiDmaInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN SCHAR apiomode, IN SCHAR wdmamode, IN SCHAR udmamode)
VOID DDKFASTAPI AtapiWritePort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
BOOLEAN NTAPI AtapiDmaPioSync(PVOID HwDeviceExtension, PSCSI_REQUEST_BLOCK Srb, PUCHAR data, ULONG count)
ULONGIO_PTR NTAPI AtapiGetIoRange(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
struct _IDE_AHCI_PORT_REGISTERS * PIDE_AHCI_PORT_REGISTERS
PDRIVER_OBJECT SavedDriverObject
BOOLEAN NTAPI AtapiReadChipConfig(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
BOOLEAN NTAPI AtapiInterrupt2(IN PKINTERRUPT Interrupt, IN PVOID HwDeviceExtension)
BOOLEAN g_opt_AtapiDmaRawRead
VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
struct _IDE_SATA_REGISTERS IDE_SATA_REGISTERS
struct _BUSMASTER_CTX BUSMASTER_CTX
VOID NTAPI AtapiDmaReinit(IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt, IN PATA_REQ AtaReq)
NTSTATUS NTAPI UniataDisconnectIntr2(IN PVOID HwDeviceExtension)
USHORT NTAPI UniataEnableIoPCI(IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
VOID NTAPI UniataFreeLunExt(PHW_DEVICE_EXTENSION deviceExtension)
struct _IDE_AHCI_RCV_FIS * PIDE_AHCI_RCV_FIS
USHORT DDKFASTAPI AtapiReadPort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
BOOLEAN NTAPI AtapiChipInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG c)
VOID NTAPI AtapiDmaStart(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
VOID NTAPI UniataEnumBusMasterController(IN PVOID DriverObject, PVOID Argument2)
struct _ISR2_DEVICE_EXTENSION ISR2_DEVICE_EXTENSION
union _SATA_SCONTROL_REG SATA_SCONTROL_REG
PBUSMASTER_CONTROLLER_INFORMATION BMList
_In_ PSCSI_REQUEST_BLOCK Srb
_In_ PCHAR _In_ ULONG DeviceNumber
VOID(NTAPI * PHW_TIMER)(IN PVOID DeviceExtension)
GLuint GLuint GLsizei count
GLint GLenum GLsizei GLsizei GLsizei GLint GLsizei const GLvoid * data
GLuint GLsizei GLsizei * length
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
enum _INTERFACE_TYPE INTERFACE_TYPE
_In_ ULONG _In_ ULONG Offset
_In_ ULONG _In_ ULONG _In_ ULONG Length
enum _BUS_DATA_TYPE BUS_DATA_TYPE
PBUSMASTER_CONTROLLER_INFORMATION * BMListPtr
ULONG MechStatusRetryCount
ULONG ChannelSelectWaitCount
SENSE_DATA MechStatusSense
SCSI_REQUEST_BLOCK InternalSrb
UCHAR ReturningMediaStatus
PATA_REQ AhciInternalAtaReq
LONGLONG TryReorderHeadCount
IORES RegTranslation[IDX_MAX_REG]
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock0
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]
BOOLEAN ExpectingInterrupt
MECHANICAL_STATUS_INFORMATION_HEADER MechStatusData
ULONGLONG AHCI_CTL_PhAddr
LONGLONG TryReorderTailCount
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock
LONGLONG QueueStat[MAX_QUEUE_STAT]
PSCSI_REQUEST_BLOCK AhciInternalSrb
struct _HW_DEVICE_EXTENSION * DeviceExtension
PSCSI_REQUEST_BLOCK AhciInternalSrb0
IDENTIFY_DATA FullIdentifyData
INTERFACE_TYPE AdapterInterfaceType
BOOLEAN opt_AtapiDmaReadWrite
PATA_REQ AhciInternalAtaReq0
PDEVICE_OBJECT Isr2DevObj
ULONG FirstChannelToCheck
ULONG MaximumDmaTransferLength
INTERFACE_TYPE OrigAdapterInterfaceType
BOOLEAN opt_AtapiDmaRawRead
UCHAR LastInterruptedChannel
IORES BaseIoAddressSATA_0
ULONG DmaSegmentAlignmentMask
BOOLEAN opt_AtapiDmaControlCmd
BOOLEAN opt_AtapiDmaZeroTransfer
struct _SBadBlockRange * arrBadBlocks
BOOLEAN opt_ReadCacheEnable
struct _HW_DEVICE_EXTENSION * DeviceExtension
struct _HW_CHANNEL * chan
ULONG opt_MaxTransferMode
IDENTIFY_DATA2 IdentifyData
LONGLONG ModeErrorCount[MAX_RETRIES]
struct _SBadBlockListItem * bbListDescr
LONGLONG RecoverCount[MAX_RETRIES]
UCHAR LimitedTransferMode
ULONG opt_PreferedTransferMode
BOOLEAN opt_WriteCacheEnable
ULONG AtapiReadyWaitDelay
UCHAR ReturningMediaStatus
IDE_AHCI_CMD_LIST cmd_list[ATA_AHCI_MAX_TAGS]
IDE_AHCI_PRD_ENTRY prd_tab[ATA_AHCI_DMA_ENTRIES]
union _IDE_AHCI_PORT_REGISTERS::@1146 FBS
union _IDE_AHCI_PORT_REGISTERS::@1134 CMD
union _IDE_AHCI_PORT_REGISTERS::@1133 IE
struct _IDE_AHCI_PORT_REGISTERS::@1135::@1155::@1157 STS
union _IDE_AHCI_PORT_REGISTERS::@1135 TFD
union _IDE_AHCI_PORT_REGISTERS::@1145 SNTF
union _IDE_AHCI_PORT_REGISTERS::@1136 SIG
struct _IDE_AHCI_REGISTERS::@1106 CAP2
struct _IDE_AHCI_REGISTERS::@1107 BOHC
struct _IDE_AHCI_REGISTERS::@1104 CAP
struct _IDE_AHCI_REGISTERS::@1105 GHC
union _IDE_SATA_REGISTERS::@1122 SNTF
SATA_SCONTROL_REG SControl
PHW_DEVICE_EXTENSION HwDeviceExtension
UCHAR padding_4kb[PAGE_SIZE]
struct _ATA_REQ::@1174::@1176::@1180::@1182 ata
struct _ATA_REQ::@1174::@1176::@1180::@1183 ahci
union _ATA_REQ * next_req
PIDE_AHCI_CMD ahci_cmd_ptr
PSCSI_REQUEST_BLOCK OriginalSrb
union _ATA_REQ * prev_req
BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES]
struct _SATA_SERROR_REG::@1112::@1115 DIAG
struct _SATA_SERROR_REG::@1112::@1114 ERR
_In_ WDFDEVICE _In_ PPNP_BUS_INFORMATION BusInformation
_Must_inspect_result_ _In_ PDRIVER_OBJECT DriverObject
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_INTERRUPT_CONFIG _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFINTERRUPT * Interrupt
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
_Reserved_ PVOID Reserved
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE _In_ ULONG BusNumber