ReactOS 0.4.15-dev-5666-gc548b97
bsmaster.h
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1/*++
2
3Copyright (c) 2002-2018 Alexandr A. Telyatnikov (Alter)
4
5Module Name:
6 bsmaster.h
7
8Abstract:
9 This file contains DMA/UltraDMA and IDE BusMastering related definitions,
10 internal structures and useful macros
11
12Author:
13 Alexander A. Telyatnikov (Alter)
14
15Environment:
16 kernel mode only
17
18Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31Revision History:
32
33 Code was created by
34 Alter, Copyright (c) 2002-2015
35
36 Some definitions were taken from FreeBSD 4.3-9.2 ATA driver by
37 Søren Schmidt, Copyright (c) 1998-2014
38
39Licence:
40 GPLv2
41
42--*/
43
44#ifndef __IDE_BUSMASTER_H__
45#define __IDE_BUSMASTER_H__
46
47#include "config.h"
48
49#include "tools.h"
50
51//
52//
53//
54#define ATA_IDLE 0x0
55#define ATA_IMMEDIATE 0x1
56#define ATA_WAIT_INTR 0x2
57#define ATA_WAIT_READY 0x3
58#define ATA_ACTIVE 0x4
59#define ATA_ACTIVE_ATA 0x5
60#define ATA_ACTIVE_ATAPI 0x6
61#define ATA_REINITING 0x7
62#define ATA_WAIT_BASE_READY 0x8
63#define ATA_WAIT_IDLE 0x9
64
65
66#include "bm_devs_decl.h"
67
68#include "uata_ctl.h"
69
70#pragma pack(push, 8)
71
72#define MAX_RETRIES 6
73#define RETRY_UDMA2 1
74#define RETRY_WDMA 2
75#define RETRY_PIO 3
76
77
78#define IO_WD1 0x1F0 /* Primary Fixed Disk Controller */
79#define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
80#define IP_PC98_BANK 0x432
81#define IO_FLOPPY_INT 0x3F6 /* AltStatus inside Floppy I/O range */
82
83#define PCI_ADDRESS_IOMASK 0xfffffff0
84
85#define ATA_BM_OFFSET1 0x08
86#define ATA_IOSIZE 0x08
87#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
88#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
89#define ATA_ALTIOSIZE 0x01 /* alternate registers size */
90#define ATA_BMIOSIZE 0x20
91#define ATA_PC98_BANKIOSIZE 0x01
92//#define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
93// Hitachi 1 Tb HDD didn't allow LBA28 with BCount > 1 beyond this LBA
94#define ATA_MAX_IOLBA28 DEF_U64(0x0fffff80)
95#define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
96
97#define ATA_MAX_IOLBA32 DEF_U64(0xffffff80)
98#define ATA_MAX_LBA32 DEF_U64(0xffffffff)
99
100#define ATA_DMA_ENTRIES 256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
101#define ATA_DMA_EOT 0x80000000
102
103#define DEV_BSIZE 512
104
105#define ATAPI_MAGIC_LSB 0x14
106#define ATAPI_MAGIC_MSB 0xeb
107
108#define AHCI_MAX_PORT 32
109
110#define SATA_MAX_PM_UNITS 16
111
112typedef struct _BUSMASTER_CTX {
116
117#define PCI_DEV_CLASS_STORAGE 0x01
118
119#define PCI_DEV_SUBCLASS_IDE 0x01
120#define PCI_DEV_SUBCLASS_RAID 0x04
121#define PCI_DEV_SUBCLASS_ATA 0x05
122#define PCI_DEV_SUBCLASS_SATA 0x06
123
124#define PCI_DEV_PROGIF_AHCI_1_0 0x01
125
126#pragma pack(push, 1)
127
128/* structure for holding DMA address data */
129typedef struct BM_DMA_ENTRY {
133
141
142#define BM_STATUS_ACTIVE 0x01
143#define BM_STATUS_ERR 0x02
144#define BM_STATUS_INTR 0x04
145#define BM_STATUS_MASK 0x07
146#define BM_STATUS_DRIVE_0_DMA 0x20
147#define BM_STATUS_DRIVE_1_DMA 0x40
148#define BM_STATUS_SIMPLEX_ONLY 0x80
149
150#define BM_COMMAND_START_STOP 0x01
151/*#define BM_COMMAND_WRITE 0x08
152#define BM_COMMAND_READ 0x00*/
153#define BM_COMMAND_WRITE 0x00
154#define BM_COMMAND_READ 0x08
155
156#define BM_DS0_SII_DMA_ENABLE (1 << 0) /* DMA run switch */
157#define BM_DS0_SII_IRQ (1 << 3) /* ??? */
158#define BM_DS0_SII_DMA_SATA_IRQ (1 << 4) /* OR of all SATA IRQs */
159#define BM_DS0_SII_DMA_ERROR (1 << 17) /* PCI bus error */
160#define BM_DS0_SII_DMA_COMPLETE (1 << 18) /* cmd complete / IRQ pending */
161
162
163#define IDX_BM_IO (IDX_IO2_o+IDX_IO2_o_SZ)
164//#define IDX_BM_IO_SZ sizeof(IDE_BUSMASTER_REGISTERS)
165#define IDX_BM_IO_SZ 5
166
167#define IDX_BM_Command (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
168#define IDX_BM_DeviceSpecific0 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
169#define IDX_BM_Status (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
170#define IDX_BM_DeviceSpecific1 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
171#define IDX_BM_PRD_Table (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
172
173typedef struct _IDE_AHCI_REGISTERS {
174 // HBA Capabilities
175 struct {
176 ULONG NOP:5; // number of ports
177 ULONG SXS:1; // Supports External SATA
178 ULONG EMS:1; // Enclosure Management Supported
179 ULONG CCCS:1; // Command Completion Coalescing Supported
180 ULONG NCS:5; // number of command slots
181 ULONG PSC:1; // partial state capable
182 ULONG SSC:1; // slumber state capable
183 ULONG PMD:1; // PIO multiple DRQ block
184 ULONG FBSS:1; // FIS-based Switching Supported
185
186 ULONG SPM:1; // port multiplier
187 ULONG SAM:1; // AHCI mode only
188 ULONG SNZO:1; // non-zero DMA offset
189 ULONG ISS:4; // interface speed
190 ULONG SCLO:1; // command list override
191 ULONG SAL:1; // activity LED
192 ULONG SALP:1; // aggressive link power management
193 ULONG SSS:1; // staggered spin-up
194 ULONG SIS:1; // interlock switch
195 ULONG SSNTF:1; // Supports SNotification Register
196 ULONG SNCQ:1; // native command queue
197 ULONG S64A:1; // 64bit addr
199
200#define AHCI_CAP_NOP_MASK 0x0000001f
201#define AHCI_CAP_CCC 0x00000080
202#define AHCI_CAP_NCS_MASK 0x00001f00
203#define AHCI_CAP_PMD 0x00008000
204#define AHCI_CAP_SPM 0x00020000
205#define AHCI_CAP_SAM 0x00040000
206#define AHCI_CAP_ISS_MASK 0x00f00000
207#define AHCI_CAP_SCLO 0x01000000
208#define AHCI_CAP_SNTF 0x20000000
209#define AHCI_CAP_NCQ 0x40000000
210#define AHCI_CAP_S64A 0x80000000
211
212 // Global HBA Control
213 struct {
214 ULONG HR:1; // HBA Reset
215 ULONG IE:1; // interrupt enable
217 ULONG AE:1; // AHCI enable
219
220#define AHCI_GHC 0x04
221#define AHCI_GHC_HR 0x00000001
222#define AHCI_GHC_IE 0x00000002
223#define AHCI_GHC_AE 0x80000000
224
225 // Interrupt status (bit mask)
226 ULONG IS; // 0x08
227 // Ports implemented (bit mask)
228 ULONG PI; // 0x0c
229 // AHCI Version
230 ULONG VS; // 0x10
231
232 ULONG CCC_CTL; // 0x14
234 ULONG EM_LOC; // 0x1c
235 ULONG EM_CTL; // 0x20
236
237 // Extended HBA Capabilities
238 struct { // 0x24
239 ULONG BOH:1; // BIOS/OS Handoff
240 ULONG NVMP:1; // NVMHCI Present
241 ULONG APST:1; // Automatic Partial to Slumber Transitions
244
245#define AHCI_CAP2_BOH 0x00000001
246#define AHCI_CAP2_NVMP 0x00000002
247#define AHCI_CAP2_APST 0x00000004
248
249 // BIOS/OS Handoff Control and Status
250 struct { // 0x28
251 ULONG BB:1; // BIOS Busy
252 ULONG OOC:1; // OS Ownership Change
253 ULONG SOOE:1; // SMI on OS Ownership Change Enable
254 ULONG OOS:1; // OS Owned Semaphore
255 ULONG BOS:1; // BIOS Owned Semaphore
256 ULONG Reserved:27;
258
259#define AHCI_BOHC_BB 0x00000001
260#define AHCI_BOHC_OOC 0x00000002
261#define AHCI_BOHC_SOOE 0x00000004
262#define AHCI_BOHC_OOS 0x00000008
263#define AHCI_BOHC_BOS 0x00000010
264
266
269
270#define IDX_AHCI_CAP (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
271#define IDX_AHCI_GHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
272#define IDX_AHCI_IS (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
273#define IDX_AHCI_VS (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
274#define IDX_AHCI_PI (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
275#define IDX_AHCI_CAP2 (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP2))
276#define IDX_AHCI_BOHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, BOHC))
277
278
279typedef union _SATA_SSTATUS_REG {
280
281 struct {
282 ULONG DET:4; // Device Detection
283
284#define SStatus_DET_NoDev 0x00
285#define SStatus_DET_Dev_NoPhy 0x01
286#define SStatus_DET_Dev_Ok 0x03
287#define SStatus_DET_Offline 0x04
288
289 ULONG SPD:4; // Current Interface Speed
290
291#define SStatus_SPD_NoDev 0x00
292#define SStatus_SPD_Gen1 0x01
293#define SStatus_SPD_Gen2 0x02
294#define SStatus_SPD_Gen3 0x03
295
296 ULONG IPM:4; // Interface Power Management
297
298#define SStatus_IPM_NoDev 0x00
299#define SStatus_IPM_Active 0x01
300#define SStatus_IPM_Partial 0x02
301#define SStatus_IPM_Slumber 0x06
302
304 };
306
308
309#define ATA_SS_DET_MASK 0x0000000f
310#define ATA_SS_DET_NO_DEVICE 0x00000000
311#define ATA_SS_DET_DEV_PRESENT 0x00000001
312#define ATA_SS_DET_PHY_ONLINE 0x00000003
313#define ATA_SS_DET_PHY_OFFLINE 0x00000004
314
315#define ATA_SS_SPD_MASK 0x000000f0
316#define ATA_SS_SPD_NO_SPEED 0x00000000
317#define ATA_SS_SPD_GEN1 0x00000010
318#define ATA_SS_SPD_GEN2 0x00000020
319
320#define ATA_SS_IPM_MASK 0x00000f00
321#define ATA_SS_IPM_NO_DEVICE 0x00000000
322#define ATA_SS_IPM_ACTIVE 0x00000100
323#define ATA_SS_IPM_PARTIAL 0x00000200
324#define ATA_SS_IPM_SLUMBER 0x00000600
325
326typedef union _SATA_SCONTROL_REG {
327
328 struct {
329 ULONG DET:4; // Device Detection Init
330
331#define SControl_DET_DoNothing 0x00
332#define SControl_DET_Idle 0x00
333#define SControl_DET_Init 0x01
334#define SControl_DET_Disable 0x04
335
336 ULONG SPD:4; // Speed Allowed
337
338#define SControl_SPD_NoRestrict 0x00
339#define SControl_SPD_LimGen1 0x01
340#define SControl_SPD_LimGen2 0x02
341#define SControl_SPD_LimGen3 0x03
342
343 ULONG IPM:4; // Interface Power Management Transitions Allowed
344
345#define SControl_IPM_NoRestrict 0x00
346#define SControl_IPM_NoPartial 0x01
347#define SControl_IPM_NoSlumber 0x02
348#define SControl_IPM_NoPartialSlumber 0x03
349
350 ULONG SPM:4; // Select Power Management, unused by AHCI
351 ULONG PMP:4; // Port Multiplier Port, unused by AHCI
353 };
355
357
358#define ATA_SC_DET_MASK 0x0000000f
359#define ATA_SC_DET_IDLE 0x00000000
360#define ATA_SC_DET_RESET 0x00000001
361#define ATA_SC_DET_DISABLE 0x00000004
362
363#define ATA_SC_SPD_MASK 0x000000f0
364#define ATA_SC_SPD_NO_SPEED 0x00000000
365#define ATA_SC_SPD_SPEED_GEN1 0x00000010
366#define ATA_SC_SPD_SPEED_GEN2 0x00000020
367#define ATA_SC_SPD_SPEED_GEN3 0x00000040
368
369#define ATA_SC_IPM_MASK 0x00000f00
370#define ATA_SC_IPM_NONE 0x00000000
371#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
372#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
373
374typedef union _SATA_SERROR_REG {
375
376 struct {
377 struct {
378 UCHAR I:1; // Recovered Data Integrity Error
379 UCHAR M:1; // Recovered Communications Error
381
382 UCHAR T:1; // Transient Data Integrity Error
383 UCHAR C:1; // Persistent Communication or Data Integrity Error
384 UCHAR P:1; // Protocol Error
385 UCHAR E:1; // Internal Error
388
389 struct {
390 UCHAR N:1; // PhyRdy Change, PIS.PRCS
391 UCHAR I:1; // Phy Internal Error
392 UCHAR W:1; // Comm Wake
393 UCHAR B:1; // 10B to 8B Decode Error
394 UCHAR D:1; // Disparity Error, not used by AHCI
395 UCHAR C:1; // CRC Error
396 UCHAR H:1; // Handshake Error
397 UCHAR S:1; // Link Sequence Error
398
399 UCHAR T:1; // Transport state transition error
400 UCHAR F:1; // Unknown FIS Type
401 UCHAR X:1; // Exchanged
404 };
406
408
409#define ATA_SE_DATA_CORRECTED 0x00000001
410#define ATA_SE_COMM_CORRECTED 0x00000002
411#define ATA_SE_DATA_ERR 0x00000100
412#define ATA_SE_COMM_ERR 0x00000200
413#define ATA_SE_PROT_ERR 0x00000400
414#define ATA_SE_HOST_ERR 0x00000800
415#define ATA_SE_PHY_CHANGED 0x00010000
416#define ATA_SE_PHY_IERROR 0x00020000
417#define ATA_SE_COMM_WAKE 0x00040000
418#define ATA_SE_DECODE_ERR 0x00080000
419#define ATA_SE_PARITY_ERR 0x00100000
420#define ATA_SE_CRC_ERR 0x00200000
421#define ATA_SE_HANDSHAKE_ERR 0x00400000
422#define ATA_SE_LINKSEQ_ERR 0x00800000
423#define ATA_SE_TRANSPORT_ERR 0x01000000
424#define ATA_SE_UNKNOWN_FIS 0x02000000
425
426typedef struct _IDE_SATA_REGISTERS {
427 union {
430 };
431 union {
434 };
435 union {
438 };
439
440 // SATA 1.2
441
443 union {
445 struct {
446 USHORT PMN; // PM Notify, bitmask
448 };
452
453#define IDX_SATA_IO (IDX_BM_IO+IDX_BM_IO_SZ)
454//#define IDX_SATA_IO_SZ sizeof(IDE_SATA_REGISTERS)
455#define IDX_SATA_IO_SZ 5
456
457#define IDX_SATA_SStatus (0+IDX_SATA_IO)
458#define IDX_SATA_SError (1+IDX_SATA_IO)
459#define IDX_SATA_SControl (2+IDX_SATA_IO)
460#define IDX_SATA_SActive (3+IDX_SATA_IO)
461#define IDX_SATA_SNTF_PMN (4+IDX_SATA_IO)
462
463#define IDX_INDEXED_IO (IDX_SATA_IO+IDX_SATA_IO_SZ)
464#define IDX_INDEXED_IO_SZ 2
465
466#define IDX_INDEXED_ADDR (0+IDX_INDEXED_IO)
467#define IDX_INDEXED_DATA (1+IDX_INDEXED_IO)
468
469#define IDX_MAX_REG (IDX_INDEXED_IO+IDX_INDEXED_IO_SZ)
470
471
472typedef union _AHCI_IS_REG {
473 struct {
474 ULONG DHRS:1;// Device to Host Register FIS Interrupt
475 ULONG PSS:1; // PIO Setup FIS Interrupt
476 ULONG DSS:1; // DMA Setup FIS Interrupt
477 ULONG SDBS:1;// Set Device Bits Interrupt
478 ULONG UFS:1; // Unknown FIS Interrupt
479 ULONG DPS:1; // Descriptor Processed
480 ULONG PCS:1; // Port Connect Change Status
481 ULONG DMPS:1;// Device Mechanical Presence Status
482
484 ULONG PRCS:1;// PhyRdy Change Status
485 ULONG IPMS:1;// Incorrect Port Multiplier Status
486
487 ULONG OFS:1; // Overflow Status
489 ULONG INFS:1;// Interface Non-fatal Error Status
490 ULONG IFS:1; // Interface Fatal Error Status
491 ULONG HBDS:1;// Host Bus Data Error Status
492 ULONG HBFS:1;// Host Bus Fatal Error Status
493 ULONG TFES:1;// Task File Error Status
494 ULONG CPDS:1;// Cold Port Detect Status
495 };
498
499#define ATA_AHCI_P_IX_DHR 0x00000001
500#define ATA_AHCI_P_IX_PS 0x00000002
501#define ATA_AHCI_P_IX_DS 0x00000004
502#define ATA_AHCI_P_IX_SDB 0x00000008
503#define ATA_AHCI_P_IX_UF 0x00000010
504#define ATA_AHCI_P_IX_DP 0x00000020
505#define ATA_AHCI_P_IX_PC 0x00000040
506#define ATA_AHCI_P_IX_DI 0x00000080
507
508#define ATA_AHCI_P_IX_PRC 0x00400000
509#define ATA_AHCI_P_IX_IPM 0x00800000
510#define ATA_AHCI_P_IX_OF 0x01000000
511#define ATA_AHCI_P_IX_INF 0x04000000
512#define ATA_AHCI_P_IX_IF 0x08000000
513#define ATA_AHCI_P_IX_HBD 0x10000000
514#define ATA_AHCI_P_IX_HBF 0x20000000
515#define ATA_AHCI_P_IX_TFE 0x40000000
516#define ATA_AHCI_P_IX_CPD 0x80000000
517
518#define AHCI_CLB_ALIGNEMENT_MASK ((ULONGLONG)(1024-1))
519#define AHCI_FIS_ALIGNEMENT_MASK ((ULONGLONG)(256-1))
520#define AHCI_CMD_ALIGNEMENT_MASK ((ULONGLONG)(128-1))
521
523 union {
524 struct {
525 ULONG CLB; // command list base address, 1K-aligned
526 ULONG CLBU; // command list base address (upper 32bits)
527 };
529 }; // 0x100 + 0x80*c + 0x0000
530
531 union {
532 struct {
533 ULONG FB; // FIS base address
534 ULONG FBU; // FIS base address (upper 32bits)
535 };
537 }; // 0x100 + 0x80*c + 0x0008
538
539 union {
540 ULONG IS_Reg; // interrupt status
542 }; // 0x100 + 0x80*c + 0x0010
543
544 union {
545 ULONG Reg; // interrupt enable
546 struct {
547 ULONG DHRE:1;// Device to Host Register FIS Interrupt Enable
548 ULONG PSE:1; // PIO Setup FIS Interrupt Enable
549 ULONG DSE:1; // DMA Setup FIS Interrupt Enable
550 ULONG SDBE:1;// Set Device Bits FIS Interrupt Enable
551 ULONG UFE:1; // Unknown FIS Interrupt Enable
552 ULONG DPE:1; // Descriptor Processed Interrupt Enable
553 ULONG PCE:1; // Port Change Interrupt Enable
554 ULONG DPME:1;// Device Mechanical Presence Enable
555
557 ULONG PRCE:1;// PhyRdy Change Interrupt Enable
558 ULONG IPME:1;// Incorrect Port Multiplier Enable
559 ULONG OFE:1; // Overflow Enable
561 ULONG INFE:1;// Interface Non-fatal Error Enable
562 ULONG IFE:1; // Interface Fatal Error Enable
563 ULONG HBDE:1;// Host Bus Data Error Enable
564 ULONG HBFE:1;// Host Bus Fatal Error Enable
565 ULONG TFEE:1;// Task File Error Enable
566 ULONG CPDE:1;// Cold Port Detect Enable
567 };
568 } IE; // 0x100 + 0x80*c + 0x0014
569
570 union {
571 ULONG Reg; // command register
572 struct {
573
574 ULONG ST:1; // Start
575 ULONG SUD:1; // Spin-Up Device
576 ULONG POD:1; // Power On Device
577 ULONG CLO:1; // Command List Override
578 ULONG FRE:1; // FIS Receive Enable
580
581 ULONG CCS:5; // Current Command Slot
582 ULONG MPSS:1;// Mechanical Presence Switch State
583 ULONG FR:1; // FIS Receive Running
584 ULONG CR:1; // Command List Running
585
586 ULONG CPS:1; // Cold Presence State
587 ULONG PMA:1; // Port Multiplier Attached
588 ULONG HPCP:1;// Hot Plug Capable Port
589 ULONG MPSP:1;// Mechanical Presence Switch Attached to Port
590 ULONG CPD:1; // Cold Presence Detection
591 ULONG ESP:1; // External SATA Port
593
594 ULONG ATAPI:1; // Device is ATAPI
595 ULONG DLAE:1;// Drive LED on ATAPI Enable
596 ULONG ALPE:1;// Aggressive Link Power Management Enable
597 ULONG ASP:1; // Aggressive Slumber / Partial
598 ULONG ICC:4; // Interface Communication Control
599
600#define SATA_CMD_ICC_Idle 0x00
601#define SATA_CMD_ICC_NoOp 0x00
602#define SATA_CMD_ICC_Active 0x01
603#define SATA_CMD_ICC_Partial 0x02
604#define SATA_CMD_ICC_Slumber 0x06
605 };
606 } CMD; // 0x100 + 0x80*c + 0x0018
607
609
610 union {
611 ULONG Reg; // Task File Data
612 struct {
613 struct {
615 UCHAR cs1:2;// command-specific
617 UCHAR cs2:3;// command-specific
620 UCHAR ERR; // Contains the latest copy of the task file error register.
622 };
623 } TFD; // 0x100 + 0x80*c + 0x0020
624
625 union {
626 ULONG Reg; // signature
627 struct {
629 UCHAR LbaLow; // IDX_IO1_i_BlockNumber
630 UCHAR LbaMid; // IDX_IO1_i_CylinderLow
631 UCHAR LbaHigh; // IDX_IO1_i_CylinderHigh
632 };
633 } SIG; // 0x100 + 0x80*c + 0x0024
634 union {
635 ULONG SStatus; // SCR0
637 }; // 0x100 + 0x80*c + 0x0028
638 union {
641 }; // 0x100 + 0x80*c + 0x002c
642 union {
643 ULONG SError; // SCR1
645 }; // 0x100 + 0x80*c + 0x0030
646 union {
647 ULONG SACT; // SCR3
648 ULONG SActive; // bitmask
649 }; // 0x100 + 0x80*c + 0x0034
650
651 ULONG CI; // Command issue, bitmask, 0x100 + 0x80*c + 0x0038
652
653 // AHCI 1.1
654 union {
655 ULONG Reg;
656 struct {
657 USHORT PMN; // PM Notify, bitmask
659 };
660 } SNTF; // 0x100 + 0x80*c + 0x003c
661
662 // AHCI 1.2
663 union {
664 ULONG Reg;
665 struct {
666 ULONG EN:1; // Enable
667 ULONG DEC:1; // Device Error Clear
668 ULONG SDE:1; // Single Device Error
669 ULONG Reserved_3_7:5; // Reserved
670 ULONG DEV:4; // Device To Issue
671 ULONG ADO:4; // Active Device Optimization (recommended parallelism)
672 ULONG DWE:4; // Device With Error
673 ULONG Reserved_20_31:12; // Reserved
674 };
675 } FBS; // 0x100 + 0x80*c + 0x0040
676
679
681
682#define IDX_AHCI_P_CLB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
683#define IDX_AHCI_P_FB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
684#define IDX_AHCI_P_IS (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
685#define IDX_AHCI_P_IE (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IE))
686#define IDX_AHCI_P_CI (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
687#define IDX_AHCI_P_TFD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
688#define IDX_AHCI_P_SIG (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
689#define IDX_AHCI_P_CMD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
690#define IDX_AHCI_P_SStatus (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))
691#define IDX_AHCI_P_SControl (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))
692#define IDX_AHCI_P_SError (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))
693#define IDX_AHCI_P_ACT (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
694
695#define IDX_AHCI_P_SNTF (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
696
697// AHCI commands ( -> IDX_AHCI_P_CMD)
698#define ATA_AHCI_P_CMD_ST 0x00000001
699#define ATA_AHCI_P_CMD_SUD 0x00000002
700#define ATA_AHCI_P_CMD_POD 0x00000004
701#define ATA_AHCI_P_CMD_CLO 0x00000008
702#define ATA_AHCI_P_CMD_FRE 0x00000010
703#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
704#define ATA_AHCI_P_CMD_ISS 0x00002000
705#define ATA_AHCI_P_CMD_FR 0x00004000
706#define ATA_AHCI_P_CMD_CR 0x00008000
707#define ATA_AHCI_P_CMD_CPS 0x00010000
708#define ATA_AHCI_P_CMD_PMA 0x00020000
709#define ATA_AHCI_P_CMD_HPCP 0x00040000
710#define ATA_AHCI_P_CMD_ISP 0x00080000
711#define ATA_AHCI_P_CMD_CPD 0x00100000
712#define ATA_AHCI_P_CMD_ESP 0x00200000
713#define ATA_AHCI_P_CMD_ATAPI 0x01000000
714#define ATA_AHCI_P_CMD_DLAE 0x02000000
715#define ATA_AHCI_P_CMD_ALPE 0x04000000
716#define ATA_AHCI_P_CMD_ASP 0x08000000
717#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
718#define ATA_AHCI_P_CMD_NOOP 0x00000000
719#define ATA_AHCI_P_CMD_ACTIVE 0x10000000
720#define ATA_AHCI_P_CMD_PARTIAL 0x20000000
721#define ATA_AHCI_P_CMD_SLUMBER 0x60000000
722
723
724typedef struct _IDE_AHCI_PRD_ENTRY {
725 union {
728 struct {
730 union {
733 };
734 };
735 };
737
738 union {
739 struct {
743 };
745 };
746
748
749#define ATA_AHCI_DMA_ENTRIES (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
750#define ATA_AHCI_MAX_TAGS 32
751
752#define AHCI_FIS_TYPE_ATA_H2D 0x27
753#define AHCI_FIS_TYPE_ATA_D2H 0x34
754#define AHCI_FIS_TYPE_DMA_D2H 0x39
755#define AHCI_FIS_TYPE_DMA_BiDi 0x41
756#define AHCI_FIS_TYPE_DATA_BiDi 0x46
757#define AHCI_FIS_TYPE_BIST_BiDi 0x58
758#define AHCI_FIS_TYPE_PIO_D2H 0x5f
759#define AHCI_FIS_TYPE_DEV_BITS_D2H 0xA1
760
761typedef struct _AHCI_ATA_H2D_FIS {
762 UCHAR FIS_Type; // = 0x27
764 UCHAR Cmd:1; // update Command register
767
772
777
781 UCHAR Control; // [15]
782
784
785#define IDX_AHCI_o_Command (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Command))
786#define IDX_AHCI_o_Feature (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Feature))
787#define IDX_AHCI_o_BlockNumber (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumber ))
788#define IDX_AHCI_o_CylinderLow (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLow ))
789#define IDX_AHCI_o_CylinderHigh (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHigh))
790#define IDX_AHCI_o_DriveSelect (FIELD_OFFSET(AHCI_ATA_H2D_FIS, DriveSelect ))
791#define IDX_AHCI_o_BlockCount (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCount))
792#define IDX_AHCI_o_Control (FIELD_OFFSET(AHCI_ATA_H2D_FIS, Control))
793#define IDX_AHCI_o_FeatureExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, FeatureExp))
794#define IDX_AHCI_o_BlockNumberExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockNumberExp ))
795#define IDX_AHCI_o_CylinderLowExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderLowExp ))
796#define IDX_AHCI_o_CylinderHighExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, CylinderHighExp))
797#define IDX_AHCI_o_BlockCountExp (FIELD_OFFSET(AHCI_ATA_H2D_FIS, BlockCountExp))
798
799#define AHCI_FIS_COMM_PM (0x80 | AHCI_DEV_SEL_PM)
800
801#define AHCI_DEV_SEL_1 0x00
802#define AHCI_DEV_SEL_2 0x01
803#define AHCI_DEV_SEL_PM 0x0f
804
805/* 128-byte aligned */
806typedef struct _IDE_AHCI_CMD {
812
813
814/* cmd_flags */
815#define ATA_AHCI_CMD_ATAPI 0x0020
816#define ATA_AHCI_CMD_WRITE 0x0040
817#define ATA_AHCI_CMD_PREFETCH 0x0080
818#define ATA_AHCI_CMD_RESET 0x0100
819#define ATA_AHCI_CMD_BIST 0x0200
820#define ATA_AHCI_CMD_CLR_BUSY 0x0400
821
822/* 128-byte aligned */
823typedef struct _IDE_AHCI_CMD_LIST {
825 USHORT prd_length; /* PRD entries */
827 ULONGLONG cmd_table_phys; /* points to IDE_AHCI_CMD */
830
831/* 256-byte aligned */
832typedef struct _IDE_AHCI_RCV_FIS {
843
844/* 1K-byte aligned */
848 IDE_AHCI_CMD cmd; // for single internal commands w/o associated AtaReq
850
851#pragma pack(pop)
852
853#define IsBusMaster(pciData) \
854 ( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \
855 (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/))
856
857#define PCI_IDE_PROGIF_NATIVE_1 0x01
858#define PCI_IDE_PROGIF_NATIVE_2 0x04
859#define PCI_IDE_PROGIF_NATIVE_ALL 0x05
860
861#define IsMasterDev(pciData) \
862 ( ((pciData)->ProgIf & 0x80) && \
863 ((pciData)->ProgIf & PCI_IDE_PROGIF_NATIVE_ALL) != PCI_IDE_PROGIF_NATIVE_ALL )
864
865//#define INT_Q_SIZE 32
866#define MIN_REQ_TTL 4
867
868union _ATA_REQ;
869
870typedef union _ATA_REQ {
871// ULONG reqId; // serial
872 struct {
873
874 //union {
875
876 struct {
879
880 PSCSI_REQUEST_BLOCK Srb; // Current request on controller.
881
882 PUSHORT DataBuffer; // Data buffer pointer.
883 ULONG WordsLeft; // Data words left.
884 ULONG TransferLength; // Originally requested transfer length
886 ULONG WordsTransfered;// Data words already transfered.
888
891 // UCHAR tag;
894
895 PSCSI_REQUEST_BLOCK OriginalSrb; // Mechanism Status Srb Data
896
898 union {
899 // for ATA
900 struct {
904 // for AHCI
905 struct {
915 };
916 };
917 //UCHAR padding_128b[128]; // Note: we assume, NT allocates block > 4k as PAGE-aligned
918 //};
919 struct {
920 union {
922 IDE_AHCI_CMD ahci_cmd0; // for AHCI, 128-byte aligned
923 };
924 };
925 };
926
928
930
931#define REQ_FLAG_FORCE_DOWNRATE 0x01
932#define REQ_FLAG_DMA_OPERATION 0x02
933#define REQ_FLAG_REORDERABLE_CMD 0x04
934#define REQ_FLAG_RW_MASK 0x08
935#define REQ_FLAG_READ 0x08
936#define REQ_FLAG_WRITE 0x00
937#define REQ_FLAG_FORCE_DOWNRATE_LBA48 0x10
938#define REQ_FLAG_DMA_DBUF 0x20
939#define REQ_FLAG_DMA_DBUF_PRD 0x40
940#define REQ_FLAG_LBA48 0x80
941
942// Request states
943#define REQ_STATE_NONE 0x00
944#define REQ_STATE_QUEUED 0x10
945
946#define REQ_STATE_PREPARE_TO_TRANSFER 0x20
947#define REQ_STATE_PREPARE_TO_NEXT 0x21
948#define REQ_STATE_READY_TO_TRANSFER 0x30
949
950#define REQ_STATE_EXPECTING_INTR 0x40
951#define REQ_STATE_ATAPI_EXPECTING_CMD_INTR 0x41
952#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR 0x42
953#define REQ_STATE_ATAPI_EXPECTING_DATA_INTR2 0x43
954#define REQ_STATE_ATAPI_DO_NOTHING_INTR 0x44
955
956#define REQ_STATE_EARLY_INTR 0x48
957
958#define REQ_STATE_PROCESSING_INTR 0x50
959
960#define REQ_STATE_DPC_INTR_REQ 0x51
961#define REQ_STATE_DPC_RESET_REQ 0x52
962#define REQ_STATE_DPC_COMPLETE_REQ 0x53
963
964#define REQ_STATE_DPC_WAIT_BUSY0 0x57
965#define REQ_STATE_DPC_WAIT_BUSY1 0x58
966#define REQ_STATE_DPC_WAIT_BUSY 0x59
967#define REQ_STATE_DPC_WAIT_DRQ 0x5a
968#define REQ_STATE_DPC_WAIT_DRQ0 0x5b
969#define REQ_STATE_DPC_WAIT_DRQ_ERR 0x5c
970
971#define REQ_STATE_TRANSFER_COMPLETE 0x7f
972
973// Command actions:
974#define CMD_ACTION_PREPARE 0x01
975#define CMD_ACTION_EXEC 0x02
976#define CMD_ACTION_ALL (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
977
978// predefined Reorder costs
979#define REORDER_COST_MAX ((DEF_I64(0x1) << 60) - 1)
980#define REORDER_COST_TTL (REORDER_COST_MAX - 1)
981#define REORDER_COST_INTERSECT (REORDER_COST_MAX - 2)
982#define REORDER_COST_DENIED (REORDER_COST_MAX - 3)
983#define REORDER_COST_RESELECT (REORDER_COST_MAX/4)
984
985#define REORDER_COST_SWITCH_RW_CD (REORDER_COST_MAX/8)
986#define REORDER_MCOST_SWITCH_RW_CD (0)
987#define REORDER_MCOST_SEEK_BACK_CD (16)
988
989#define REORDER_COST_SWITCH_RW_HDD (0)
990#define REORDER_MCOST_SWITCH_RW_HDD (4)
991#define REORDER_MCOST_SEEK_BACK_HDD (2)
992
993/*typedef struct _ATA_QUEUE {
994 struct _ATA_REQ* head_req; // index
995 struct _ATA_REQ* tail_req; // index
996 ULONG req_count;
997 ULONG dma_base;
998 BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
999} ATA_QUEUE, *PATA_QUEUE;*/
1000
1002struct _HW_LU_EXTENSION;
1003
1004typedef struct _IORES {
1005 union {
1006#ifdef __REACTOS__
1007 ULONG_PTR Addr; /* Base address*/
1008#else
1009 ULONG Addr; /* Base address*/
1010#endif
1011 PVOID pAddr; /* Base address in pointer form */
1012 };
1013 ULONG MemIo:1; /* Memory mapping (1) vs IO ports (0) */
1014 ULONG Proc:1; /* Need special processing via IO_Proc */
1017
1018// Channel extension
1019typedef struct _HW_CHANNEL {
1020
1023 ULONG last_cdev; /* device for which we have configured timings last time */
1024 ULONG last_devsel; /* device selected during last call to SelectDrive() */
1025/* PATA_REQ first_req;
1026 PATA_REQ last_req;*/
1029
1031
1032 BOOLEAN ExpectingInterrupt; // Indicates expecting an interrupt
1033 BOOLEAN RDP; // Indicate last tape command was DSC Restrictive.
1034 // Indicates whether '0x1f0' is the base address. Used
1035 // in SMART Ioctl calls.
1037 // Placeholder for the sub-command value of the last
1038 // SMART command.
1040 // Reorder anabled
1042 // Placeholder for status register after a GET_MEDIA_STATUS command
1044
1046 //BOOLEAN MemIo;
1049
1051
1056
1057 ULONG MaxTransferMode; // may differ from Controller's value due to 40-pin cable
1058
1063
1065
1066#define CHECK_INTR_ACTIVE 0x03
1067#define CHECK_INTR_DETECTED 0x02
1068#define CHECK_INTR_CHECK 0x01
1069#define CHECK_INTR_IDLE 0x00
1070
1074#if 0
1075 PHW_TIMER HwScsiTimer1;
1076 PHW_TIMER HwScsiTimer2;
1077 LONGLONG DpcTime1;
1078// PHW_TIMER CurDpc;
1079// LARGE_INTEGER ActivationTime;
1080
1081// KDPC Dpc;
1082// KTIMER Timer;
1083// PHW_TIMER HwScsiTimer;
1084// KSPIN_LOCK QueueSpinLock;
1085// KIRQL QueueOldIrql;
1086#endif
1089
1092
1093 // Double-buffering support
1098
1100
1101 //
1110 //PVOID AHCI_FIS; // is not actually used by UniATA now, but is required by AHCI controller
1111 //ULONGLONG AHCI_FIS_PhAddr;
1112 // Note: in contrast to FBSD, we keep PRD and CMD item in AtaReq structure
1115
1116#ifdef QUEUE_STATISTICS
1122 LONGLONG TryReorderTailCount; /* in-order requests */
1123#endif //QUEUE_STATISTICS
1124
1125 //ULONG BaseMemAddress;
1126 //ULONG BaseMemAddressOffset;
1128
1130
1131#define CTRFLAGS_DMA_ACTIVE 0x0001
1132#define CTRFLAGS_DMA_RO 0x0002
1133#define CTRFLAGS_DMA_OPERATION 0x0004
1134#define CTRFLAGS_INTR_DISABLED 0x0008
1135#define CTRFLAGS_DPC_REQ 0x0010
1136#define CTRFLAGS_ENABLE_INTR_REQ 0x0020
1137#define CTRFLAGS_LBA48 0x0040
1138#define CTRFLAGS_DSC_BSY 0x0080
1139#define CTRFLAGS_NO_SLAVE 0x0100
1140//#define CTRFLAGS_DMA_BEFORE_R 0x0200
1141//#define CTRFLAGS_PATA 0x0200
1142//#define CTRFLAGS_NOT_PRESENT 0x0200
1143#define CTRFLAGS_AHCI_PM 0x0400
1144#define CTRFLAGS_AHCI_PM2 0x0800
1145
1146#define CTRFLAGS_PERMANENT (CTRFLAGS_DMA_RO | CTRFLAGS_NO_SLAVE)
1147
1148#define GEOM_AUTO 0xffffffff
1149#define GEOM_STD 0x0000
1150#define GEOM_UNIATA 0x0001
1151#define GEOM_ORIG 0x0002
1152#define GEOM_MANUAL 0x0003
1153
1154#define DPC_STATE_NONE 0x00
1155#define DPC_STATE_ISR 0x10
1156#define DPC_STATE_DPC 0x20
1157#define DPC_STATE_TIMER 0x30
1158#define DPC_STATE_COMPLETE 0x40
1159
1160// Logical unit extension
1161typedef struct _HW_LU_EXTENSION {
1164 ULONG DeviceFlags; // Flags word for each possible device. DFLAGS_XXX
1165 ULONG DiscsPresent; // Indicates number of platters on changer-ish devices.
1166 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
1170
1171 UCHAR TransferMode; // current transfer mode
1172 UCHAR LimitedTransferMode; // user-defined or IDE cable limitation
1173 UCHAR OrigTransferMode; // transfer mode, returned by device IDENTIFY (can be changed via IOCTL)
1174 UCHAR PhyTransferMode; // phy transfer mode (actual bus transfer mode for PATA DMA and SATA)
1175
1176 ULONG ErrorCount; // Count of errors. Used to turn off features.
1177 // ATA_QUEUE cmd_queue;
1184 //
1189
1192
1193 // tuning options
1203 UCHAR opt_Padding[2]; // padding
1204
1208
1209 // Controller-specific LUN options
1210 union {
1211 /* for tricky controllers, those can change Logical-to-Physical LUN mapping.
1212 mainly for mapping SATA ports to compatible PATA registers
1213 Treated as PHYSICAL port number, regardless of logical mapping.
1214 */
1216 };
1217
1221
1226
1227#ifdef IO_STATISTICS
1228
1233
1234#endif//IO_STATISTICS
1236
1237// Device extension
1238typedef struct _HW_DEVICE_EXTENSION {
1240 //PIDE_REGISTERS_1 BaseIoAddress1[IDE_MAX_CHAN]; // Base register locations
1241 //PIDE_REGISTERS_2 BaseIoAddress2[IDE_MAX_CHAN];
1242 ULONG BusInterruptLevel; // Interrupt level
1243 ULONG InterruptMode; // Interrupt Mode (Level or Edge)
1245 // Number of channels being supported by one instantiation
1246 // of the device extension. Normally (and correctly) one, but
1247 // with so many broken PCI IDE controllers being sold, we have
1248 // to support them.
1252#if 0
1254 HW_CHANNEL chan[AHCI_MAX_PORT/*IDE_MAX_CHAN*/];
1255#else
1256 PHW_LU_EXTENSION lun; // lun array
1257 PHW_CHANNEL chan; // channel array
1258#endif
1260 // Indicates the number of blocks transferred per int. according to the
1261 // identify data.
1262 BOOLEAN DriverMustPoll; // Driver is being used by the crash dump utility or ntldr.
1264 BOOLEAN UseDpc; // Indicates use of DPC on long waits
1265 IDENTIFY_DATA FullIdentifyData; // Identify data for device
1266 // BusMaster specific data
1267// PBM_DMA_ENTRY dma_tab_0;
1268 //KSPIN_LOCK DpcSpinLock;
1269
1272 ULONG ExpectingInterrupt; // Indicates entire controller expecting an interrupt
1273/*
1274 PHW_TIMER HwScsiTimer1;
1275 PHW_TIMER HwScsiTimer2;
1276 LONGLONG DpcTime1;
1277 LONGLONG DpcTime2;
1278*/
1280
1282
1283 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0;
1285 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM[IDE_MAX_CHAN];
1286
1287 // Device identification
1293
1294 ULONG InitMethod; // vendor specific
1295
1297
1300 //BOOLEAN MemIo;
1305 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
1306/* // Indicates, that HW Initialized is already called for this controller
1307 // 0 bit for Primary, 1 - for Secondary. Is used to manage AltInit under w2k+
1308 UCHAR Initialized; */
1310
1312
1313 ULONG MaxTransferMode; // max transfer mode supported by controller
1320 ULONG DmaSegmentAlignmentMask; // must be PAGE-aligned
1321
1322 //ULONG BaseMemAddress;
1323
1324 //PIDE_SATA_REGISTERS BaseIoAddressSATA_0;
1326 //PIDE_SATA_REGISTERS BaseIoAddressSATA[IDE_MAX_CHAN];
1327
1329 //PIDE_AHCI_PORT_REGISTERS BaseIoAHCIPort[AHCI_MAX_PORT];
1332 ULONG AHCI_PI_mask; // for port exclusion, usually = AHCI_PI
1335
1340
1342
1343 // Controller specific state/options
1344 union {
1346 };
1347
1349
1354
1357
1358#define HBAFLAGS_DMA_DISABLED 0x01
1359#define HBAFLAGS_DMA_DISABLED_LBA48 0x02
1360
1361extern UCHAR pciBuffer[256];
1363extern ULONG BMListLen;
1364extern ULONG IsaCount;
1365extern ULONG MCACount;
1367
1368//extern const CHAR retry_Wdma[MAX_RETRIES+1];
1369//extern const CHAR retry_Udma[MAX_RETRIES+1];
1370
1371extern VOID
1372NTAPI
1376 );
1377
1378extern ULONG NTAPI
1380 IN PVOID HwDeviceExtension,
1383 IN PCHAR ArgumentString,
1385 OUT PBOOLEAN Again
1386 );
1387
1388extern ULONG NTAPI
1390 IN PVOID HwDeviceExtension,
1393 IN PCHAR ArgumentString,
1395 OUT PBOOLEAN Again
1396 );
1397
1398#define UNIATA_ALLOCATE_NEW_LUNS 0x00
1399
1400extern BOOLEAN NTAPI
1402 PHW_DEVICE_EXTENSION deviceExtension,
1403 ULONG NewNumberChannels
1404 );
1405
1406extern VOID NTAPI
1408 PHW_DEVICE_EXTENSION deviceExtension
1409 );
1410
1411extern ULONG NTAPI
1413 IN PVOID HwDeviceExtension,
1416 IN PCHAR ArgumentString,
1418 OUT PBOOLEAN Again
1419 );
1420
1421extern NTSTATUS
1422NTAPI
1424 ULONG i
1425 );
1426
1427extern NTSTATUS
1428NTAPI
1430 IN PVOID HwDeviceExtension
1431 );
1432
1433extern NTSTATUS
1434NTAPI
1436 IN PVOID HwDeviceExtension
1437 );
1438
1439extern ULONG
1440NTAPI
1442 IN PVOID HwDeviceExtension,
1443 IN BUS_DATA_TYPE BusDataType,
1446 IN PVOID Buffer,
1447 IN ULONG Offset,
1449 );
1450
1451#define PCIBUSNUM_NOT_SPECIFIED (0xffffffffL)
1452#define PCISLOTNUM_NOT_SPECIFIED (0xffffffffL)
1453
1454extern ULONG
1455NTAPI
1458 ULONG lim,
1459 IN PVOID HwDeviceExtension,
1462 OUT PCI_SLOT_NUMBER* _slotData // optional
1463 );
1464
1465extern ULONG
1466NTAPI
1468 IN PVOID HwDeviceExtension,
1469 IN BUS_DATA_TYPE BusDataType,
1472 IN ULONG dev_id,
1473 IN ULONG RevID
1474 );
1475
1476extern VOID
1477NTAPI
1479 IN PVOID HwDeviceExtension,
1481 IN ULONG lChannel // logical channel,
1482 );
1483
1484extern BOOLEAN
1485NTAPI
1487 IN PVOID HwDeviceExtension,
1489 IN ULONG lChannel, // logical channel,
1491 IN PUCHAR data,
1492 IN ULONG count
1493 );
1494
1495extern BOOLEAN
1496NTAPI
1498 PVOID HwDeviceExtension,
1500 PUCHAR data,
1501 ULONG count
1502 );
1503
1504extern BOOLEAN
1505NTAPI
1507 PHW_CHANNEL chan,
1509 );
1510
1511extern BOOLEAN
1512NTAPI
1514 IN PVOID HwDeviceExtension,
1515 PHW_CHANNEL chan,
1517 );
1518
1519extern VOID
1520NTAPI
1522 IN PVOID HwDeviceExtension,
1524 IN ULONG lChannel, // logical channel,
1526 );
1527
1528extern UCHAR
1529NTAPI
1531 IN PVOID HwDeviceExtension,
1533 IN ULONG lChannel, // logical channel,
1535 );
1536
1537extern VOID
1538NTAPI
1540 IN PHW_DEVICE_EXTENSION deviceExtension,
1541 IN PHW_LU_EXTENSION LunExt,
1542 IN PATA_REQ AtaReq
1543 );
1544
1545extern VOID
1546NTAPI
1548 IN PHW_DEVICE_EXTENSION deviceExtension,
1549 IN PHW_LU_EXTENSION LunExt
1550 );
1551
1552extern VOID
1553NTAPI
1555 IN PVOID HwDeviceExtension,
1557 IN ULONG lChannel, // logical channel,
1558 // is always 0 except simplex-only and multi-channel controllers
1559 IN SCHAR apiomode,
1560 IN SCHAR wdmamode,
1561 IN SCHAR udmamode
1562 );
1563
1564extern BOOLEAN NTAPI
1567 IN PVOID HwDeviceExtension
1568 );
1569
1571
1572extern BOOLEAN
1573NTAPI
1575 IN PVOID HwDeviceExtension,
1576 IN PPCI_COMMON_CONFIG pciData, // optional
1579 );
1580
1581extern NTSTATUS
1582NTAPI
1584 IN PVOID HwDeviceExtension,
1585 IN PPCI_COMMON_CONFIG pciData, // optional
1588 IN BOOLEAN* simplexOnly
1589 );
1590
1591extern BOOLEAN
1592NTAPI
1594 IN PVOID HwDeviceExtension,
1596 IN ULONG c
1597 );
1598
1599extern ULONGIO_PTR
1600NTAPI
1602 IN PVOID HwDeviceExtension,
1604 IN PPCI_COMMON_CONFIG pciData,
1605 IN ULONG SystemIoBusNumber,
1606 IN ULONG rid,
1607 IN ULONG offset,
1608 IN ULONG length //range id
1609 );
1610
1611extern USHORT
1612NTAPI
1614 IN ULONG busNumber,
1615 IN ULONG slotNumber,
1616 IN OUT PPCI_COMMON_CONFIG pciData
1617 );
1618
1619/****************** 1 *****************/
1620#define GetPciConfig1(offs, op) { \
1621 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1622 PCIConfiguration, \
1623 SystemIoBusNumber, \
1624 slotNumber, \
1625 &op, \
1626 offs, \
1627 1); \
1628}
1629
1630#define SetPciConfig1(offs, op) { \
1631 UCHAR _a = op; \
1632 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1633 PCIConfiguration, \
1634 SystemIoBusNumber, \
1635 slotNumber, \
1636 &_a, \
1637 offs, \
1638 1); \
1639}
1640
1641#define ChangePciConfig1(offs, _op) { \
1642 UCHAR a = 0; \
1643 GetPciConfig1(offs, a); \
1644 a = (UCHAR)(_op); \
1645 SetPciConfig1(offs, a); \
1646}
1647
1648/****************** 2 *****************/
1649#define GetPciConfig2(offs, op) { \
1650 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1651 PCIConfiguration, \
1652 SystemIoBusNumber, \
1653 slotNumber, \
1654 &op, \
1655 offs, \
1656 2); \
1657}
1658
1659#define SetPciConfig2(offs, op) { \
1660 USHORT _a = op; \
1661 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1662 PCIConfiguration, \
1663 SystemIoBusNumber, \
1664 slotNumber, \
1665 &_a, \
1666 offs, \
1667 2); \
1668}
1669
1670#define ChangePciConfig2(offs, _op) { \
1671 USHORT a = 0; \
1672 GetPciConfig2(offs, a); \
1673 a = (USHORT)(_op); \
1674 SetPciConfig2(offs, a); \
1675}
1676
1677/****************** 4 *****************/
1678#define GetPciConfig4(offs, op) { \
1679 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1680 PCIConfiguration, \
1681 SystemIoBusNumber, \
1682 slotNumber, \
1683 &op, \
1684 offs, \
1685 4); \
1686}
1687
1688#define SetPciConfig4(offs, op) { \
1689 ULONG _a = op; \
1690 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1691 PCIConfiguration, \
1692 SystemIoBusNumber, \
1693 slotNumber, \
1694 &_a, \
1695 offs, \
1696 4); \
1697}
1698
1699#define ChangePciConfig4(offs, _op) { \
1700 ULONG a = 0; \
1701 GetPciConfig4(offs, a); \
1702 a = _op; \
1703 SetPciConfig4(offs, a); \
1704}
1705
1706#define DMA_MODE_NONE 0x00
1707#define DMA_MODE_BM 0x01
1708#define DMA_MODE_AHCI 0x02
1709
1710#ifndef GetDmaStatus
1711#define GetDmaStatus(de, c) \
1712 (((de)->BusMaster == DMA_MODE_BM) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
1713#endif //GetDmaStatus
1714
1715#ifdef USE_OWN_DMA
1716#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1717 AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
1718#else
1719#define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1720 (ScsiPortConvertPhysicalAddressToUlong/*(ULONG)ScsiPortGetVirtualAddress*/(/*hwde,*/ \
1721 ScsiPortGetPhysicalAddress(hwde, srb, phaddr, plen)))
1722#endif //USE_OWN_DMA
1723
1724VOID
1727 IN PHW_CHANNEL chan,
1729 IN ULONG data
1730 );
1731
1732VOID
1735 IN PHW_CHANNEL chan,
1737 IN USHORT data
1738 );
1739
1740VOID
1743 IN PHW_CHANNEL chan,
1745 IN UCHAR data
1746 );
1747
1748VOID
1751 IN PHW_CHANNEL chan,
1753 IN ULONG offs,
1754 IN ULONG data
1755 );
1756
1757VOID
1760 IN PHW_CHANNEL chan,
1762 IN ULONG offs,
1763 IN UCHAR data
1764 );
1765
1766ULONG
1769 IN PHW_CHANNEL chan,
1771 );
1772
1773USHORT
1776 IN PHW_CHANNEL chan,
1778 );
1779
1780UCHAR
1783 IN PHW_CHANNEL chan,
1785 );
1786
1787ULONG
1790 IN PHW_CHANNEL chan,
1792 IN ULONG offs
1793 );
1794
1795UCHAR
1798 IN PHW_CHANNEL chan,
1800 IN ULONG offs
1801 );
1802
1803VOID
1806 IN PHW_CHANNEL chan,
1807 IN ULONGIO_PTR _port,
1808 IN PVOID Buffer,
1809 IN ULONG Count,
1810 IN ULONG Timing
1811 );
1812
1813VOID
1816 IN PHW_CHANNEL chan,
1817 IN ULONGIO_PTR _port,
1818 IN PVOID Buffer,
1819 IN ULONG Count,
1820 IN ULONG Timing
1821 );
1822
1823VOID
1826 IN PHW_CHANNEL chan,
1827 IN ULONGIO_PTR _port,
1828 IN PVOID Buffer,
1829 IN ULONG Count,
1830 IN ULONG Timing
1831 );
1832
1833VOID
1836 IN PHW_CHANNEL chan,
1837 IN ULONGIO_PTR _port,
1838 IN PVOID Buffer,
1839 IN ULONG Count,
1840 IN ULONG Timing
1841 );
1842
1843/*#define GET_CHANNEL(Srb) (Srb->TargetId >> 1)
1844#define GET_LDEV(Srb) (Srb->TargetId)
1845#define GET_LDEV2(P, T, L) (T)*/
1846
1847#define GET_CHANNEL(Srb) (Srb->PathId)
1848//#define GET_LDEV(Srb) (Srb->TargetId | (Srb->PathId << 1))
1849//#define GET_LDEV2(P, T, L) (T | ((P)<<1))
1850#define GET_CDEV(Srb) (Srb->TargetId)
1851
1852VOID
1853NTAPI
1855 IN PHW_CHANNEL chan,
1856 IN PHW_DEVICE_EXTENSION deviceExtension,
1857 IN ULONG c
1858 );
1859/*
1860#define AtapiSetupLunPtrs(chan, deviceExtension, c) \
1861{ \
1862 chan->DeviceExtension = deviceExtension; \
1863 chan->lChannel = c; \
1864 chan->lun[0] = &(deviceExtension->lun[c*2+0]); \
1865 chan->lun[1] = &(deviceExtension->lun[c*2+1]); \
1866 chan->AltRegMap = deviceExtension->AltRegMap; \
1867 chan->NextDpcChan = -1; \
1868 chan->lun[0]->DeviceExtension = deviceExtension; \
1869 chan->lun[1]->DeviceExtension = deviceExtension; \
1870}
1871*/
1872BOOLEAN
1873NTAPI
1875 IN PVOID HwDeviceExtension,
1877 IN ULONG channel // physical channel
1878 );
1879
1880VOID
1881NTAPI
1883 PHW_LU_EXTENSION LunExt
1884 );
1885
1886extern ULONG SkipRaids;
1887extern ULONG ForceSimplex;
1889extern BOOLEAN hasPCI;
1890
1891extern BOOLEAN InDriverEntry;
1892extern BOOLEAN g_Dump;
1893
1894extern BOOLEAN g_opt_Verbose;
1896
1898
1899extern ULONG CPU_num;
1900
1901#define VM_AUTO 0x00
1902#define VM_NONE 0x01
1903#define VM_VBOX 0x02
1904#define VM_VMWARE 0x03
1905#define VM_QEMU 0x04
1906#define VM_BOCHS 0x05
1907#define VM_PCEM 0x06
1908
1909#define VM_MAX_KNOWN VM_PCEM
1910
1912
1913#pragma pack(pop)
1914
1915#endif //__IDE_BUSMASTER_H__
unsigned char BOOLEAN
LONG NTSTATUS
Definition: precomp.h:26
BUSMASTER_CONTROLLER_INFORMATION_BASE const BusMasterAdapters[]
Definition: bm_devs.h:40
#define IDE_MAX_LUN_PER_CHAN
Definition: bm_devs_decl.h:46
#define MAX_QUEUE_STAT
Definition: bm_devs_decl.h:50
#define IDE_MAX_LUN
Definition: bm_devs_decl.h:48
VOID DDKFASTAPI AtapiWriteBuffer2(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
struct _IDE_BUSMASTER_REGISTERS IDE_BUSMASTER_REGISTERS
VOID DDKFASTAPI AtapiWriteBuffer4(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
VOID NTAPI AtapiDmaInit__(IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt)
Definition: id_dma.cpp:857
BOOLEAN NTAPI UniataAllocateLunExt(PHW_DEVICE_EXTENSION deviceExtension, ULONG NewNumberChannels)
Definition: id_init.cpp:2891
union _SATA_SERROR_REG * PSATA_SERROR_REG
UCHAR NTAPI AtapiDmaDone(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
Definition: id_dma.cpp:685
BOOLEAN WinVer_WDM_Model
Definition: id_ata.cpp:112
#define IDX_MAX_REG
Definition: bsmaster.h:469
struct _HW_CHANNEL * PHW_CHANNEL
struct _IDE_AHCI_CHANNEL_CTL_BLOCK IDE_AHCI_CHANNEL_CTL_BLOCK
ULONG BMListLen
Definition: id_probe.cpp:54
VOID DDKFASTAPI AtapiWritePortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN UCHAR data)
NTSTATUS NTAPI UniataChipDetect(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN BOOLEAN *simplexOnly)
Definition: id_init.cpp:339
struct _AHCI_ATA_H2D_FIS * PAHCI_ATA_H2D_FIS
struct _IDE_AHCI_RCV_FIS IDE_AHCI_RCV_FIS
ULONG NTAPI UniataFindCompatBusMasterController1(IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
Definition: id_probe.cpp:924
union _SATA_SSTATUS_REG SATA_SSTATUS_REG
struct _IDE_AHCI_CMD * PIDE_AHCI_CMD
#define ATA_AHCI_MAX_TAGS
Definition: bsmaster.h:750
ULONG NTAPI UniataFindCompatBusMasterController2(IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
Definition: id_probe.cpp:945
VOID NTAPI AtapiSetupLunPtrs(IN PHW_CHANNEL chan, IN PHW_DEVICE_EXTENSION deviceExtension, IN ULONG c)
Definition: id_init.cpp:2846
union _SATA_SERROR_REG SATA_SERROR_REG
struct _IDE_AHCI_CMD IDE_AHCI_CMD
struct _IDE_AHCI_PRD_ENTRY IDE_AHCI_PRD_ENTRY
BOOLEAN NTAPI UniataChipDetectChannels(IN PVOID HwDeviceExtension, IN PPCI_COMMON_CONFIG pciData, IN ULONG DeviceNumber, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo)
Definition: id_init.cpp:58
ULONG NTAPI AtapiFindDev(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN ULONG dev_id, IN ULONG RevID)
Definition: id_probe.cpp:871
BOOLEAN NTAPI AtapiDmaDBPreSync(IN PVOID HwDeviceExtension, PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
Definition: id_dma.cpp:553
struct _IDE_AHCI_CMD_LIST * PIDE_AHCI_CMD_LIST
BOOLEAN NTAPI AtapiDmaSetup(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb, IN PUCHAR data, IN ULONG count)
Definition: id_dma.cpp:247
struct _IDE_AHCI_PRD_ENTRY * PIDE_AHCI_PRD_ENTRY
ULONG NTAPI AtapiFindListedDev(PBUSMASTER_CONTROLLER_INFORMATION_BASE BusMasterAdapters, ULONG lim, IN PVOID HwDeviceExtension, IN ULONG BusNumber, IN ULONG SlotNumber, OUT PCI_SLOT_NUMBER *_slotData)
struct _IDE_AHCI_CHANNEL_CTL_BLOCK * PIDE_AHCI_CHANNEL_CTL_BLOCK
ULONG IsaCount
Definition: id_probe.cpp:55
struct _HW_CHANNEL HW_CHANNEL
BOOLEAN NTAPI AtapiDmaDBSync(PHW_CHANNEL chan, PSCSI_REQUEST_BLOCK Srb)
Definition: id_dma.cpp:532
ULONG g_opt_WaitBusyResetCount
Definition: id_ata.cpp:89
VOID NTAPI UniataForgetDevice(PHW_LU_EXTENSION LunExt)
Definition: id_ata.cpp:2385
VOID DDKFASTAPI AtapiReadBuffer4(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
UCHAR DDKFASTAPI AtapiReadPort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
union _SATA_SSTATUS_REG * PSATA_SSTATUS_REG
ULONG DDKFASTAPI AtapiReadPort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
ULONG NTAPI UniataFindBusMasterController(IN PVOID HwDeviceExtension, IN PVOID Context, IN PVOID BusInformation, IN PCHAR ArgumentString, IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo, OUT PBOOLEAN Again)
Definition: id_probe.cpp:988
struct _ISR2_DEVICE_EXTENSION * PISR2_DEVICE_EXTENSION
struct _IORES * PIORES
struct _IDE_AHCI_CMD_LIST IDE_AHCI_CMD_LIST
VOID DDKFASTAPI AtapiWritePortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs, IN ULONG data)
union _AHCI_IS_REG * PAHCI_IS_REG
struct _IDE_AHCI_PORT_REGISTERS IDE_AHCI_PORT_REGISTERS
union _SATA_SCONTROL_REG * PSATA_SCONTROL_REG
NTSTATUS NTAPI UniataClaimLegacyPCIIDE(ULONG i)
Definition: id_probe.cpp:1939
ULONG MCACount
Definition: id_probe.cpp:56
struct _BUSMASTER_CTX * PBUSMASTER_CTX
BOOLEAN g_opt_Verbose
Definition: id_ata.cpp:110
ULONG CPU_num
Definition: id_ata.cpp:113
NTSTATUS NTAPI UniataConnectIntr2(IN PVOID HwDeviceExtension)
Definition: id_probe.cpp:2034
struct _IORES IORES
ULONG NTAPI ScsiPortGetBusDataByOffset(IN PVOID HwDeviceExtension, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: id_probe.cpp:741
struct _HW_LU_EXTENSION HW_LU_EXTENSION
union _ATA_REQ ATA_REQ
struct _IDE_BUSMASTER_REGISTERS * PIDE_BUSMASTER_REGISTERS
union _AHCI_IS_REG AHCI_IS_REG
struct BM_DMA_ENTRY * PBM_DMA_ENTRY
ULONG DDKFASTAPI AtapiReadPortEx4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
struct _IDE_AHCI_REGISTERS IDE_AHCI_REGISTERS
struct _IDE_AHCI_REGISTERS * PIDE_AHCI_REGISTERS
VOID NTAPI AtapiDmaAlloc(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN ULONG lChannel)
Definition: id_dma.cpp:138
ULONG g_opt_VirtualMachine
Definition: id_ata.cpp:105
ULONG SkipRaids
Definition: id_ata.cpp:77
struct _IDE_SATA_REGISTERS * PIDE_SATA_REGISTERS
UNICODE_STRING SavedRegPath
Definition: id_ata.cpp:69
VOID DDKFASTAPI AtapiReadBuffer2(IN PHW_CHANNEL chan, IN ULONGIO_PTR _port, IN PVOID Buffer, IN ULONG Count, IN ULONG Timing)
ISR2_DEVICE_EXTENSION PCIIDE_DEVICE_EXTENSION
Definition: bsmaster.h:1355
struct _HW_DEVICE_EXTENSION * PHW_DEVICE_EXTENSION
#define ATA_AHCI_DMA_ENTRIES
Definition: bsmaster.h:749
#define ATA_DMA_ENTRIES
Definition: bsmaster.h:100
PISR2_DEVICE_EXTENSION PPCIIDE_DEVICE_EXTENSION
Definition: bsmaster.h:1356
VOID DDKFASTAPI AtapiWritePort4(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG data)
struct _HW_LU_EXTENSION * PHW_LU_EXTENSION
union _ATA_REQ * PATA_REQ
struct _HW_DEVICE_EXTENSION HW_DEVICE_EXTENSION
BOOLEAN g_Dump
Definition: id_ata.cpp:108
struct _AHCI_ATA_H2D_FIS AHCI_ATA_H2D_FIS
VOID NTAPI AtapiDmaInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN SCHAR apiomode, IN SCHAR wdmamode, IN SCHAR udmamode)
Definition: id_dma.cpp:975
VOID DDKFASTAPI AtapiWritePort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN USHORT data)
UCHAR pciBuffer[256]
Definition: id_probe.cpp:66
BOOLEAN NTAPI AtapiDmaPioSync(PVOID HwDeviceExtension, PSCSI_REQUEST_BLOCK Srb, PUCHAR data, ULONG count)
Definition: id_dma.cpp:467
ULONGIO_PTR NTAPI AtapiGetIoRange(IN PVOID HwDeviceExtension, IN PPORT_CONFIGURATION_INFORMATION ConfigInfo, IN PPCI_COMMON_CONFIG pciData, IN ULONG SystemIoBusNumber, IN ULONG rid, IN ULONG offset, IN ULONG length)
Definition: id_probe.cpp:153
struct _IDE_AHCI_PORT_REGISTERS * PIDE_AHCI_PORT_REGISTERS
PDRIVER_OBJECT SavedDriverObject
Definition: id_probe.cpp:69
BOOLEAN NTAPI AtapiReadChipConfig(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG channel)
Definition: id_init.cpp:1782
BOOLEAN InDriverEntry
Definition: id_ata.cpp:107
BOOLEAN NTAPI AtapiInterrupt2(IN PKINTERRUPT Interrupt, IN PVOID HwDeviceExtension)
Definition: id_ata.cpp:4192
BOOLEAN g_opt_AtapiDmaRawRead
Definition: id_ata.cpp:100
VOID DDKFASTAPI AtapiWritePort1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN UCHAR data)
struct _IDE_SATA_REGISTERS IDE_SATA_REGISTERS
struct _BUSMASTER_CTX BUSMASTER_CTX
VOID NTAPI AtapiDmaReinit(IN PHW_DEVICE_EXTENSION deviceExtension, IN PHW_LU_EXTENSION LunExt, IN PATA_REQ AtaReq)
Definition: id_dma.cpp:754
NTSTATUS NTAPI UniataDisconnectIntr2(IN PVOID HwDeviceExtension)
Definition: id_probe.cpp:2156
USHORT NTAPI UniataEnableIoPCI(IN ULONG busNumber, IN ULONG slotNumber, IN OUT PPCI_COMMON_CONFIG pciData)
Definition: id_probe.cpp:95
UCHAR DDKFASTAPI AtapiReadPortEx1(IN PHW_CHANNEL chan, IN ULONGIO_PTR port, IN ULONG offs)
VOID NTAPI UniataFreeLunExt(PHW_DEVICE_EXTENSION deviceExtension)
Definition: id_init.cpp:2956
struct _IDE_AHCI_RCV_FIS * PIDE_AHCI_RCV_FIS
USHORT DDKFASTAPI AtapiReadPort2(IN PHW_CHANNEL chan, IN ULONGIO_PTR port)
BOOLEAN NTAPI AtapiChipInit(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG c)
Definition: id_init.cpp:1879
VOID NTAPI AtapiDmaStart(IN PVOID HwDeviceExtension, IN ULONG DeviceNumber, IN ULONG lChannel, IN PSCSI_REQUEST_BLOCK Srb)
Definition: id_dma.cpp:588
VOID NTAPI UniataEnumBusMasterController(IN PVOID DriverObject, PVOID Argument2)
Definition: id_probe.cpp:245
struct _ISR2_DEVICE_EXTENSION ISR2_DEVICE_EXTENSION
#define MAX_RETRIES
Definition: bsmaster.h:72
union _SATA_SCONTROL_REG SATA_SCONTROL_REG
#define AHCI_MAX_PORT
Definition: bsmaster.h:108
PBUSMASTER_CONTROLLER_INFORMATION BMList
Definition: id_probe.cpp:53
ULONG ForceSimplex
Definition: id_ata.cpp:78
BOOLEAN hasPCI
Definition: id_ata.cpp:103
_In_ PSCSI_REQUEST_BLOCK Srb
Definition: cdrom.h:989
Definition: bufpool.h:45
_In_ PVOID Argument2
Definition: classpnp.h:721
_In_ PCHAR _In_ ULONG DeviceNumber
Definition: classpnp.h:1230
USHORT port
Definition: uri.c:228
#define DDKFASTAPI
Definition: config.h:144
#define ULONGIO_PTR
Definition: config.h:102
VOID(NTAPI * PHW_TIMER)(IN PVOID DeviceExtension)
Definition: srb.h:456
#define PAGE_SIZE
Definition: env_spec_w32.h:49
GLuint GLuint GLsizei count
Definition: gl.h:1545
GLint GLenum GLsizei GLsizei GLsizei GLint GLsizei const GLvoid * data
Definition: gl.h:1950
const GLubyte * c
Definition: glext.h:8905
GLuint GLsizei GLsizei * length
Definition: glext.h:6040
GLintptr offset
Definition: glext.h:5920
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
enum _INTERFACE_TYPE INTERFACE_TYPE
signed char * PCHAR
Definition: retypes.h:7
char * PBOOLEAN
Definition: retypes.h:11
unsigned short * PUSHORT
Definition: retypes.h:2
unsigned char * PUCHAR
Definition: retypes.h:3
unsigned int ULONG
Definition: retypes.h:1
int Count
Definition: noreturn.cpp:7
CONST CHAR * PCCH
Definition: ntbasedef.h:392
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:102
long LONG
Definition: pedump.c:60
unsigned short USHORT
Definition: pedump.c:61
enum _BUS_DATA_TYPE BUS_DATA_TYPE
signed char SCHAR
Definition: sqltypes.h:14
Definition: bsmaster.h:129
ULONG count
Definition: bsmaster.h:131
ULONG base
Definition: bsmaster.h:130
UCHAR CylinderHigh
Definition: bsmaster.h:770
UCHAR CylinderLowExp
Definition: bsmaster.h:774
UCHAR BlockCountExp
Definition: bsmaster.h:779
UCHAR BlockNumberExp
Definition: bsmaster.h:773
UCHAR CylinderHighExp
Definition: bsmaster.h:775
PBUSMASTER_CONTROLLER_INFORMATION * BMListPtr
Definition: bsmaster.h:113
ULONG * BMListLen
Definition: bsmaster.h:114
BOOLEAN PrimaryAddress
Definition: bsmaster.h:1036
PATA_REQ cur_req
Definition: bsmaster.h:1021
ULONG ChannelCtrlFlags
Definition: bsmaster.h:1059
BOOLEAN RDP
Definition: bsmaster.h:1033
ULONG MechStatusRetryCount
Definition: bsmaster.h:1054
ULONG queue_depth
Definition: bsmaster.h:1027
ULONG ChannelSelectWaitCount
Definition: bsmaster.h:1028
PVOID DB_IO
Definition: bsmaster.h:1096
SENSE_DATA MechStatusSense
Definition: bsmaster.h:1053
LONG CheckIntr
Definition: bsmaster.h:1062
ULONG NumberLuns
Definition: bsmaster.h:1090
ULONG AhciPrevCI
Definition: bsmaster.h:1106
SCSI_REQUEST_BLOCK InternalSrb
Definition: bsmaster.h:1055
PHW_TIMER HwScsiTimer
Definition: bsmaster.h:1072
ULONG cur_cdev
Definition: bsmaster.h:1022
UCHAR ReturningMediaStatus
Definition: bsmaster.h:1043
IORES BaseIoAHCI_Port
Definition: bsmaster.h:1105
PATA_REQ AhciInternalAtaReq
Definition: bsmaster.h:1113
LONGLONG TryReorderHeadCount
Definition: bsmaster.h:1121
ULONG lChannel
Definition: bsmaster.h:1064
ULONG last_devsel
Definition: bsmaster.h:1024
ULONG PmLunMap
Definition: bsmaster.h:1091
LONG DisableIntr
Definition: bsmaster.h:1061
PVOID DB_PRD
Definition: bsmaster.h:1094
ULONG AhciLastIS
Definition: bsmaster.h:1108
ULONG DB_PRD_PhAddr
Definition: bsmaster.h:1095
IORES RegTranslation[IDX_MAX_REG]
Definition: bsmaster.h:1127
ULONG AhciLastSError
Definition: bsmaster.h:1109
ULONG NextDpcChan
Definition: bsmaster.h:1071
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock0
Definition: bsmaster.h:1102
BOOLEAN UseReorder
Definition: bsmaster.h:1041
BOOLEAN AltRegMap
Definition: bsmaster.h:1047
UCHAR DpcState
Definition: bsmaster.h:1030
struct _HW_LU_EXTENSION * lun[IDE_MAX_LUN_PER_CHAN]
Definition: bsmaster.h:1088
LONGLONG IntersectCount
Definition: bsmaster.h:1119
BOOLEAN Force80pin
Definition: bsmaster.h:1048
BOOLEAN ExpectingInterrupt
Definition: bsmaster.h:1032
LONGLONG ReorderCount
Definition: bsmaster.h:1118
MECHANICAL_STATUS_INFORMATION_HEADER MechStatusData
Definition: bsmaster.h:1052
ULONGLONG AHCI_CTL_PhAddr
Definition: bsmaster.h:1104
UCHAR SmartCommand
Definition: bsmaster.h:1039
LONGLONG TryReorderTailCount
Definition: bsmaster.h:1122
ULONG AhciCompleteCI
Definition: bsmaster.h:1107
ULONG last_cdev
Definition: bsmaster.h:1023
LONGLONG TryReorderCount
Definition: bsmaster.h:1120
PIDE_AHCI_CHANNEL_CTL_BLOCK AhciCtlBlock
Definition: bsmaster.h:1103
LONGLONG QueueStat[MAX_QUEUE_STAT]
Definition: bsmaster.h:1117
ULONG DB_IO_PhAddr
Definition: bsmaster.h:1097
PSCSI_REQUEST_BLOCK AhciInternalSrb
Definition: bsmaster.h:1114
LONGLONG DpcTime
Definition: bsmaster.h:1073
ULONG ResetInProgress
Definition: bsmaster.h:1060
PUCHAR DmaBuffer
Definition: bsmaster.h:1099
ULONG MaxTransferMode
Definition: bsmaster.h:1057
struct _HW_DEVICE_EXTENSION * DeviceExtension
Definition: bsmaster.h:1087
BOOLEAN CopyDmaBuffer
Definition: bsmaster.h:1045
PSCSI_REQUEST_BLOCK AhciInternalSrb0
Definition: bsmaster.h:1334
IDENTIFY_DATA FullIdentifyData
Definition: atapi.c:145
ULONG NumberChannels
Definition: atapi.c:68
BOOLEAN DriverMustPoll
Definition: atapi.c:111
PHW_LU_EXTENSION lun
Definition: bsmaster.h:1256
INTERFACE_TYPE AdapterInterfaceType
Definition: bsmaster.h:1316
BOOLEAN opt_AtapiDmaReadWrite
Definition: bsmaster.h:1339
PATA_REQ AhciInternalAtaReq0
Definition: bsmaster.h:1333
PDEVICE_OBJECT Isr2DevObj
Definition: bsmaster.h:1281
BOOLEAN DWordIO
Definition: atapi.c:117
ULONG MaximumDmaTransferLength
Definition: bsmaster.h:1317
INTERFACE_TYPE OrigAdapterInterfaceType
Definition: bsmaster.h:1315
BOOLEAN opt_AtapiDmaRawRead
Definition: bsmaster.h:1338
ULONG InterruptMode
Definition: atapi.c:47
UCHAR LastInterruptedChannel
Definition: bsmaster.h:1259
ULONG DmaSegmentAlignmentMask
Definition: bsmaster.h:1320
PHW_CHANNEL chan
Definition: bsmaster.h:1257
BOOLEAN opt_AtapiDmaControlCmd
Definition: bsmaster.h:1337
BOOLEAN opt_AtapiDmaZeroTransfer
Definition: bsmaster.h:1336
UCHAR opt_StandbyTimer
Definition: bsmaster.h:1202
UCHAR opt_AdvPowerMode
Definition: bsmaster.h:1200
PATA_REQ first_req
Definition: bsmaster.h:1185
struct _SBadBlockRange * arrBadBlocks
Definition: bsmaster.h:1206
BOOLEAN DWordIO
Definition: bsmaster.h:1166
LONGLONG RwSwitchMCost
Definition: bsmaster.h:1182
BOOLEAN opt_ReadCacheEnable
Definition: bsmaster.h:1197
UCHAR opt_ReadOnly
Definition: bsmaster.h:1199
ULONGLONG NumOfSectors
Definition: bsmaster.h:1163
LONGLONG RwSwitchCost
Definition: bsmaster.h:1181
struct _HW_DEVICE_EXTENSION * DeviceExtension
Definition: bsmaster.h:1218
struct _HW_CHANNEL * chan
Definition: bsmaster.h:1219
UCHAR TransferMode
Definition: bsmaster.h:1171
UCHAR errPadding[3]
Definition: bsmaster.h:1225
ULONG opt_MaxTransferMode
Definition: bsmaster.h:1195
IDENTIFY_DATA2 IdentifyData
Definition: bsmaster.h:1162
LONGLONG ModeErrorCount[MAX_RETRIES]
Definition: bsmaster.h:1229
ULONGLONG errLastLba
Definition: bsmaster.h:1222
PATA_REQ last_req
Definition: bsmaster.h:1186
struct _SBadBlockListItem * bbListDescr
Definition: bsmaster.h:1205
LONGLONG RecoverCount[MAX_RETRIES]
Definition: bsmaster.h:1230
UCHAR MaximumBlockXfer
Definition: bsmaster.h:1168
ULONG SATA_lun_map
Definition: bsmaster.h:1215
LONGLONG WriteCmdCost
Definition: bsmaster.h:1179
ULONG DiscsPresent
Definition: bsmaster.h:1165
UCHAR LimitedTransferMode
Definition: bsmaster.h:1172
ULONG opt_PreferedTransferMode
Definition: bsmaster.h:1196
UCHAR OrigTransferMode
Definition: bsmaster.h:1173
LONGLONG IoCount
Definition: bsmaster.h:1231
UCHAR PhyTransferMode
Definition: bsmaster.h:1174
BOOLEAN opt_WriteCacheEnable
Definition: bsmaster.h:1198
ULONG LunSelectWaitCount
Definition: bsmaster.h:1190
LONGLONG OtherCmdCost
Definition: bsmaster.h:1180
ULONG AtapiReadyWaitDelay
Definition: bsmaster.h:1191
UCHAR opt_Padding[2]
Definition: bsmaster.h:1203
LONGLONG BlockIoCount
Definition: bsmaster.h:1232
LONGLONG ReadCmdCost
Definition: bsmaster.h:1178
UCHAR ReturningMediaStatus
Definition: bsmaster.h:1167
ULONG opt_GeomType
Definition: bsmaster.h:1194
LONGLONG SeekBackMCost
Definition: bsmaster.h:1183
UCHAR opt_AcousticMode
Definition: bsmaster.h:1201
IDE_AHCI_CMD_LIST cmd_list[ATA_AHCI_MAX_TAGS]
Definition: bsmaster.h:846
IDE_AHCI_RCV_FIS rcv_fis
Definition: bsmaster.h:847
ULONGLONG cmd_table_phys
Definition: bsmaster.h:827
UCHAR cfis[64]
Definition: bsmaster.h:807
IDE_AHCI_PRD_ENTRY prd_tab[ATA_AHCI_DMA_ENTRIES]
Definition: bsmaster.h:810
UCHAR acmd[16]
Definition: bsmaster.h:808
union _IDE_AHCI_PORT_REGISTERS::@1113 FBS
union _IDE_AHCI_PORT_REGISTERS::@1100 IE
union _IDE_AHCI_PORT_REGISTERS::@1101 CMD
union _IDE_AHCI_PORT_REGISTERS::@1103 SIG
struct _IDE_AHCI_PORT_REGISTERS::@1102::@1122::@1124 STS
ULONG Reserved_44_7f[11]
Definition: bsmaster.h:677
SATA_SSTATUS_REG SSTS
Definition: bsmaster.h:636
SATA_SERROR_REG SERR
Definition: bsmaster.h:644
union _IDE_AHCI_PORT_REGISTERS::@1112 SNTF
union _IDE_AHCI_PORT_REGISTERS::@1102 TFD
SATA_SCONTROL_REG SCTL
Definition: bsmaster.h:640
Definition: bsmaster.h:724
ULONG DBAU
Definition: bsmaster.h:731
ULONG DBC_ULONG
Definition: bsmaster.h:744
ULONG base
Definition: bsmaster.h:726
ULONG Reserved2
Definition: bsmaster.h:741
ULONG baseu
Definition: bsmaster.h:732
ULONG DBC
Definition: bsmaster.h:740
ULONG DBA
Definition: bsmaster.h:729
ULONG Reserved1
Definition: bsmaster.h:736
ULONGLONG base64
Definition: bsmaster.h:727
ULONG I
Definition: bsmaster.h:742
UCHAR dsfis[28]
Definition: bsmaster.h:833
UCHAR Reserved4[96]
Definition: bsmaster.h:841
UCHAR rfis[20]
Definition: bsmaster.h:837
UCHAR Reserved2[12]
Definition: bsmaster.h:836
UCHAR SDBFIS[8]
Definition: bsmaster.h:839
UCHAR ufis[64]
Definition: bsmaster.h:840
UCHAR Reserved1[4]
Definition: bsmaster.h:834
UCHAR psfis[20]
Definition: bsmaster.h:835
UCHAR Reserved3[4]
Definition: bsmaster.h:838
struct _IDE_AHCI_REGISTERS::@1073 CAP2
UCHAR Reserved2[0x74]
Definition: bsmaster.h:265
struct _IDE_AHCI_REGISTERS::@1071 CAP
UCHAR VendorSpec[0x60]
Definition: bsmaster.h:267
struct _IDE_AHCI_REGISTERS::@1074 BOHC
struct _IDE_AHCI_REGISTERS::@1072 GHC
SATA_SERROR_REG SError
Definition: bsmaster.h:432
ULONG SReserved[11]
Definition: bsmaster.h:450
union _IDE_SATA_REGISTERS::@1089 SNTF
SATA_SCONTROL_REG SControl
Definition: bsmaster.h:436
SATA_SSTATUS_REG SStatus
Definition: bsmaster.h:428
ULONG Proc
Definition: bsmaster.h:1014
ULONG Reserved
Definition: bsmaster.h:1015
PVOID pAddr
Definition: bsmaster.h:1011
ULONG MemIo
Definition: bsmaster.h:1013
ULONG Addr
Definition: bsmaster.h:1009
PHW_DEVICE_EXTENSION HwDeviceExtension
Definition: bsmaster.h:1351
int64_t LONGLONG
Definition: typedefs.h:68
#define NTAPI
Definition: typedefs.h:36
uint32_t ULONG_PTR
Definition: typedefs.h:65
#define IN
Definition: typedefs.h:39
uint64_t ULONGLONG
Definition: typedefs.h:67
#define OUT
Definition: typedefs.h:40
ULONG OFS
Definition: bsmaster.h:487
ULONG DMPS
Definition: bsmaster.h:481
ULONG TFES
Definition: bsmaster.h:493
ULONG PRCS
Definition: bsmaster.h:484
ULONG IPMS
Definition: bsmaster.h:485
ULONG CPDS
Definition: bsmaster.h:494
ULONG Reg
Definition: bsmaster.h:496
ULONG INFS
Definition: bsmaster.h:489
ULONG Reserved_8_21
Definition: bsmaster.h:483
ULONG HBDS
Definition: bsmaster.h:491
ULONG Reserved_25
Definition: bsmaster.h:488
ULONG IFS
Definition: bsmaster.h:490
ULONG SDBS
Definition: bsmaster.h:477
ULONG PSS
Definition: bsmaster.h:475
ULONG DSS
Definition: bsmaster.h:476
ULONG HBFS
Definition: bsmaster.h:492
ULONG DPS
Definition: bsmaster.h:479
ULONG UFS
Definition: bsmaster.h:478
ULONG DHRS
Definition: bsmaster.h:474
ULONG PCS
Definition: bsmaster.h:480
ULONGLONG ahci_base64
Definition: bsmaster.h:906
struct _ATA_REQ::@1141::@1143::@1147::@1150 ahci
ULONG dma_baseu
Definition: bsmaster.h:902
UCHAR in_error
Definition: bsmaster.h:913
IDE_AHCI_CMD ahci_cmd0
Definition: bsmaster.h:922
ULONG bcount
Definition: bsmaster.h:887
UCHAR retry
Definition: bsmaster.h:889
UCHAR padding_4kb[PAGE_SIZE]
Definition: bsmaster.h:927
ULONG in_bcount
Definition: bsmaster.h:909
USHORT io_cmd_flags
Definition: bsmaster.h:912
ULONG WordsTransfered
Definition: bsmaster.h:886
LONGLONG lba
Definition: bsmaster.h:885
PSCSI_REQUEST_BLOCK Srb
Definition: bsmaster.h:880
PUSHORT DataBuffer
Definition: bsmaster.h:882
ULONGLONG in_lba
Definition: bsmaster.h:907
ULONG TransferLength
Definition: bsmaster.h:884
struct _ATA_REQ::@1141::@1143::@1147::@1149 ata
ULONG in_status
Definition: bsmaster.h:910
ULONG dma_base
Definition: bsmaster.h:901
ULONG in_serror
Definition: bsmaster.h:911
union _ATA_REQ * next_req
Definition: bsmaster.h:877
PIDE_AHCI_CMD ahci_cmd_ptr
Definition: bsmaster.h:908
PSCSI_REQUEST_BLOCK OriginalSrb
Definition: bsmaster.h:895
union _ATA_REQ * prev_req
Definition: bsmaster.h:878
BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES]
Definition: bsmaster.h:921
ULONG dma_entries
Definition: bsmaster.h:897
UCHAR Flags
Definition: bsmaster.h:892
UCHAR ReqState
Definition: bsmaster.h:893
ULONG WordsLeft
Definition: bsmaster.h:883
UCHAR ttl
Definition: bsmaster.h:890
UCHAR Reserved_12_15
Definition: bsmaster.h:386
UCHAR Reserved_27_31
Definition: bsmaster.h:402
struct _SATA_SERROR_REG::@1079::@1081 ERR
struct _SATA_SERROR_REG::@1079::@1082 DIAG
UCHAR Reserved_2_7
Definition: bsmaster.h:380
_In_ WDFDEVICE _In_ PPNP_BUS_INFORMATION BusInformation
Definition: wdfdevice.h:3915
_Must_inspect_result_ _In_ PDRIVER_OBJECT DriverObject
Definition: wdfdriver.h:213
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_INTERRUPT_CONFIG _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFINTERRUPT * Interrupt
Definition: wdfinterrupt.h:379
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
Definition: wdfresource.h:68
_Reserved_ PVOID Reserved
Definition: winddi.h:3974
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE _In_ ULONG BusNumber
Definition: halfuncs.h:160
unsigned char UCHAR
Definition: xmlstorage.h:181
char CHAR
Definition: xmlstorage.h:175