bus.h File Reference

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Classes
struct	_PCIPBUSDATA
struct	_PCI_CONFIG_HANDLER
struct	_PCI_REGISTRY_INFO_INTERNAL
struct	_PCI_TYPE1_CFG_BITS
struct	_PCI_TYPE2_CSE_BITS
struct	_PCI_TYPE2_ADDRESS_BITS
struct	_PCI_TYPE0_CFG_CYCLE_BITS
union	_PCI_TYPE1_CFG_CYCLE_BITS
struct	_ARRAY
struct	_HAL_BUS_HANDLER

Macros
#define	PCI_ADDRESS_MEMORY_SPACE   0x00000000
#define	PASTE2(x, y)   x ## y
#define	POINTER_TO_(x)   PASTE2(P,x)
#define	READ_FROM(x)   PASTE2(READ_PORT_, x)
#define	WRITE_TO(x)   PASTE2(WRITE_PORT_, x)
#define	TYPE_DEFINE(x, y)
#define	TYPE1_DEFINE(x)   TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
#define	TYPE2_DEFINE(x)   TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
#define	TYPE1_START(x, y)
#define	TYPE1_END(y)    return sizeof(y); }
#define	TYPE2_END   TYPE1_END
#define	TYPE1_READ(x, y)
#define	TYPE1_WRITE(x, y)
#define	TYPE2_START(x, y)
#define	TYPE2_READ(x, y)
#define	TYPE2_WRITE(x, y)
#define	PCI_TYPE1_ADDRESS_PORT   (PULONG)0xCF8
#define	PCI_TYPE1_DATA_PORT   0xCFC
#define	PCI_TYPE2_CSE_PORT   (PUCHAR)0xCF8
#define	PCI_TYPE2_FORWARD_PORT   (PUCHAR)0xCFA
#define	PCI_TYPE2_ADDRESS_BASE   0xC

Typedefs
typedef NTSTATUS(NTAPI *	PciIrqRange) (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER PciSlot, OUT PSUPPORTED_RANGE *Interrupt)
typedef struct _PCIPBUSDATA	PCIPBUSDATA
typedef struct _PCIPBUSDATA *	PPCIPBUSDATA
typedef ULONG(NTAPI *	FncConfigIO) (IN PPCIPBUSDATA BusData, IN PVOID State, IN PUCHAR Buffer, IN ULONG Offset)
typedef VOID(NTAPI *	FncSync) (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PKIRQL Irql, IN PVOID State)
typedef VOID(NTAPI *	FncReleaseSync) (IN PBUS_HANDLER BusHandler, IN KIRQL Irql)
typedef struct _PCI_CONFIG_HANDLER	PCI_CONFIG_HANDLER
typedef struct _PCI_CONFIG_HANDLER *	PPCI_CONFIG_HANDLER
typedef struct _PCI_REGISTRY_INFO_INTERNAL	PCI_REGISTRY_INFO_INTERNAL
typedef struct _PCI_REGISTRY_INFO_INTERNAL *	PPCI_REGISTRY_INFO_INTERNAL
typedef struct _PCI_TYPE1_CFG_BITS	PCI_TYPE1_CFG_BITS
typedef struct _PCI_TYPE1_CFG_BITS *	PPCI_TYPE1_CFG_BITS
typedef struct _PCI_TYPE2_CSE_BITS	PCI_TYPE2_CSE_BITS
typedef struct _PCI_TYPE2_CSE_BITS	PPCI_TYPE2_CSE_BITS
typedef struct _PCI_TYPE2_ADDRESS_BITS	PCI_TYPE2_ADDRESS_BITS
typedef struct _PCI_TYPE2_ADDRESS_BITS *	PPCI_TYPE2_ADDRESS_BITS
typedef struct _PCI_TYPE0_CFG_CYCLE_BITS	PCI_TYPE0_CFG_CYCLE_BITS
typedef struct _PCI_TYPE0_CFG_CYCLE_BITS *	PPCI_TYPE0_CFG_CYCLE_BITS
typedef union _PCI_TYPE1_CFG_CYCLE_BITS	PCI_TYPE1_CFG_CYCLE_BITS
typedef union _PCI_TYPE1_CFG_CYCLE_BITS *	PPCI_TYPE1_CFG_CYCLE_BITS
typedef struct _ARRAY	ARRAY
typedef struct _ARRAY *	PARRAY
typedef struct _HAL_BUS_HANDLER	HAL_BUS_HANDLER
typedef struct _HAL_BUS_HANDLER *	PHAL_BUS_HANDLER

Functions
PPCI_REGISTRY_INFO_INTERNAL NTAPI	HalpQueryPciRegistryInfo (VOID)
VOID NTAPI	HalpPCISynchronizeType1 (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PKIRQL Irql, IN PPCI_TYPE1_CFG_BITS PciCfg)
VOID NTAPI	HalpPCIReleaseSynchronzationType1 (IN PBUS_HANDLER BusHandler, IN KIRQL Irql)
VOID NTAPI	HalpPCISynchronizeType2 (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PKIRQL Irql, IN PPCI_TYPE2_ADDRESS_BITS PciCfg)
VOID NTAPI	HalpPCIReleaseSynchronizationType2 (IN PBUS_HANDLER BusHandler, IN KIRQL Irql)
	TYPE1_DEFINE (HalpPCIReadUcharType1)
	TYPE1_DEFINE (HalpPCIReadUshortType1)
	TYPE1_DEFINE (HalpPCIReadUlongType1)
	TYPE2_DEFINE (HalpPCIReadUcharType2)
	TYPE2_DEFINE (HalpPCIReadUshortType2)
	TYPE2_DEFINE (HalpPCIReadUlongType2)
	TYPE1_DEFINE (HalpPCIWriteUcharType1)
	TYPE1_DEFINE (HalpPCIWriteUshortType1)
	TYPE1_DEFINE (HalpPCIWriteUlongType1)
	TYPE2_DEFINE (HalpPCIWriteUcharType2)
	TYPE2_DEFINE (HalpPCIWriteUshortType2)
	TYPE2_DEFINE (HalpPCIWriteUlongType2)
BOOLEAN NTAPI	HalpValidPCISlot (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot)
VOID NTAPI	HalpReadPCIConfig (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
VOID NTAPI	HalpWritePCIConfig (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
ULONG NTAPI	HalpGetPCIData (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootBusHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
ULONG NTAPI	HalpSetPCIData (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootBusHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
NTSTATUS NTAPI	HalpAssignPCISlotResources (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName OPTIONAL, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject OPTIONAL, IN ULONG Slot, IN OUT PCM_RESOURCE_LIST *pAllocatedResources)
ULONG	HalpPhase0GetPciDataByOffset (_In_ ULONG Bus, _In_ PCI_SLOT_NUMBER PciSlot, _Out_writes_bytes_all_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
ULONG	HalpPhase0SetPciDataByOffset (_In_ ULONG Bus, _In_ PCI_SLOT_NUMBER PciSlot, _In_reads_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
ULONG NTAPI	HalpGetRootInterruptVector (_In_ ULONG BusInterruptLevel, _In_ ULONG BusInterruptVector, _Out_ PKIRQL Irql, _Out_ PKAFFINITY Affinity)
ULONG NTAPI	HalpGetCmosData (_In_ ULONG BusNumber, _In_ ULONG SlotNumber, _Out_writes_bytes_(Length) PVOID Buffer, _In_ ULONG Length)
ULONG NTAPI	HalpSetCmosData (IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
VOID NTAPI	HalpInitializePciBus (VOID)
VOID NTAPI	HalpInitializePciStubs (VOID)
BOOLEAN NTAPI	HalpTranslateBusAddress (IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
NTSTATUS NTAPI	HalpAssignSlotResources (IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject, IN INTERFACE_TYPE BusType, IN ULONG BusNumber, IN ULONG SlotNumber, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
BOOLEAN NTAPI	HalpFindBusAddressTranslation (IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress, IN OUT PULONG_PTR Context, IN BOOLEAN NextBus)
VOID NTAPI	HalpRegisterPciDebuggingDeviceInfo (VOID)
BOOLEAN NTAPI	HaliTranslateBusAddress (IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
BOOLEAN NTAPI	HaliFindBusAddressTranslation (IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress, IN OUT PULONG_PTR Context, IN BOOLEAN NextBus)
NTSTATUS NTAPI	HalpAdjustPCIResourceList (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList)
ULONG NTAPI	HalpGetPCIIntOnISABus (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
VOID NTAPI	HalpPCIPin2ISALine (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciData)
VOID NTAPI	HalpPCIISALine2Pin (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciNewData, IN PPCI_COMMON_CONFIG PciOldData)
NTSTATUS NTAPI	HalpGetISAFixedPCIIrq (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER PciSlot, OUT PSUPPORTED_RANGE *Range)
VOID NTAPI	HalpInitBusHandler (VOID)
PBUS_HANDLER NTAPI	HalpContextToBusHandler (IN ULONG_PTR ContextValue)
PBUS_HANDLER FASTCALL	HaliReferenceHandlerForConfigSpace (IN BUS_DATA_TYPE ConfigType, IN ULONG BusNumber)
ULONG NTAPI	HalpNoBusData (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
ULONG NTAPI	HalpcGetCmosData (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
ULONG NTAPI	HalpcSetCmosData (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
BOOLEAN NTAPI	HalpTranslateSystemBusAddress (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
BOOLEAN NTAPI	HalpTranslateIsaBusAddress (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
ULONG NTAPI	HalpGetSystemInterruptVector (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)

Variables
PCI_CONFIG_HANDLER	PCIConfigHandler
PCI_CONFIG_HANDLER	PCIConfigHandlerType1
PCI_CONFIG_HANDLER	PCIConfigHandlerType2
ULONG	HalpBusType
BOOLEAN	HalpPCIConfigInitialized
BUS_HANDLER	HalpFakePciBusHandler
ULONG	HalpMinPciBus
ULONG	HalpMaxPciBus
LIST_ENTRY	HalpAllBusHandlers

Macro Definition Documentation

PASTE2

#define PASTE2	(		x,
			y
	)		x ## y

Definition at line 8 of file bus.h.

PCI_ADDRESS_MEMORY_SPACE

#define PCI_ADDRESS_MEMORY_SPACE   0x00000000

Definition at line 3 of file bus.h.

PCI_TYPE1_ADDRESS_PORT

#define PCI_TYPE1_ADDRESS_PORT   (PULONG)0xCF8

Definition at line 164 of file bus.h.

PCI_TYPE1_DATA_PORT

#define PCI_TYPE1_DATA_PORT   0xCFC

Definition at line 165 of file bus.h.

PCI_TYPE2_ADDRESS_BASE

#define PCI_TYPE2_ADDRESS_BASE   0xC

Definition at line 172 of file bus.h.

PCI_TYPE2_CSE_PORT

#define PCI_TYPE2_CSE_PORT   (PUCHAR)0xCF8

Definition at line 170 of file bus.h.

PCI_TYPE2_FORWARD_PORT

#define PCI_TYPE2_FORWARD_PORT   (PUCHAR)0xCFA

Definition at line 171 of file bus.h.

POINTER_TO_

#define POINTER_TO_

(

x

)

PASTE2(P,x)

Definition at line 9 of file bus.h.

READ_FROM

#define READ_FROM

(

x

)

PASTE2(READ_PORT_, x)

Definition at line 10 of file bus.h.

TYPE1_DEFINE

#define TYPE1_DEFINE

(

x

)

TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);

Definition at line 25 of file bus.h.

TYPE1_END

#define TYPE1_END

(

y

)

return sizeof(y); }

Definition at line 37 of file bus.h.

TYPE1_READ

#define TYPE1_READ	(		x,
			y
	)

Value:

    TYPE1_START(x, y)                                                   \
    *((POINTER_TO_(y))Buffer) =                                         \
    READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i));     \
    TYPE1_END(y)

Definition at line 44 of file bus.h.

TYPE1_START

#define TYPE1_START	(		x,
			y
	)

Value:

    TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS)                                 \
{                                                                       \
    ULONG i = Offset % sizeof(ULONG);                                   \
    PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG);             \
    WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);

Definition at line 31 of file bus.h.

TYPE1_WRITE

#define TYPE1_WRITE	(		x,
			y
	)

Value:

    TYPE1_START(x, y)                                                   \
    WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i),       \
                *((POINTER_TO_(y))Buffer));                             \
    TYPE1_END(y)

Definition at line 53 of file bus.h.

TYPE2_DEFINE

#define TYPE2_DEFINE

(

x

)

TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);

Definition at line 26 of file bus.h.

TYPE2_END

#define TYPE2_END   TYPE1_END

Definition at line 39 of file bus.h.

TYPE2_READ

#define TYPE2_READ	(		x,
			y
	)

Value:

    TYPE2_START(x, y)                                                   \
    *((POINTER_TO_(y))Buffer) =                                         \
        READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT);        \
    TYPE2_END(y)

Definition at line 70 of file bus.h.

TYPE2_START

#define TYPE2_START	(		x,
			y
	)

Value:

    TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS)                             \
{                                                                       \
    PciCfg->u.bits.RegisterNumber = (USHORT)Offset;

Definition at line 62 of file bus.h.

TYPE2_WRITE

#define TYPE2_WRITE	(		x,
			y
	)

Value:

    TYPE2_START(x, y)                                                   \
    WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT,              \
                *((POINTER_TO_(y))Buffer));                             \
    TYPE2_END(y)

Definition at line 79 of file bus.h.

TYPE_DEFINE

#define TYPE_DEFINE	(		x,
			y
	)

Value:

    ULONG                                                               \
    NTAPI                                                               \
    x(                                                                  \
        IN PPCIPBUSDATA BusData,                                        \
        IN y PciCfg,                                                    \
        IN PUCHAR Buffer,                                               \
        IN ULONG Offset                                                 \
    )

Definition at line 16 of file bus.h.

WRITE_TO

#define WRITE_TO

(

x

)

PASTE2(WRITE_PORT_, x)

Definition at line 11 of file bus.h.

Typedef Documentation

ARRAY

typedef struct _ARRAY ARRAY

FncConfigIO

typedef ULONG(NTAPI * FncConfigIO) (IN PPCIPBUSDATA BusData, IN PVOID State, IN PUCHAR Buffer, IN ULONG Offset)

Definition at line 121 of file bus.h.

FncReleaseSync

typedef VOID(NTAPI * FncReleaseSync) (IN PBUS_HANDLER BusHandler, IN KIRQL Irql)

Definition at line 137 of file bus.h.

FncSync

typedef VOID(NTAPI * FncSync) (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PKIRQL Irql, IN PVOID State)

Definition at line 129 of file bus.h.

HAL_BUS_HANDLER

typedef struct _HAL_BUS_HANDLER HAL_BUS_HANDLER

PARRAY

typedef struct _ARRAY * PARRAY

PCI_CONFIG_HANDLER

typedef struct _PCI_CONFIG_HANDLER PCI_CONFIG_HANDLER

PCI_REGISTRY_INFO_INTERNAL

typedef struct _PCI_REGISTRY_INFO_INTERNAL PCI_REGISTRY_INFO_INTERNAL

PCI_TYPE0_CFG_CYCLE_BITS

typedef struct _PCI_TYPE0_CFG_CYCLE_BITS PCI_TYPE0_CFG_CYCLE_BITS

PCI_TYPE1_CFG_BITS

typedef struct _PCI_TYPE1_CFG_BITS PCI_TYPE1_CFG_BITS

PCI_TYPE1_CFG_CYCLE_BITS

typedef union _PCI_TYPE1_CFG_CYCLE_BITS PCI_TYPE1_CFG_CYCLE_BITS

PCI_TYPE2_ADDRESS_BITS

typedef struct _PCI_TYPE2_ADDRESS_BITS PCI_TYPE2_ADDRESS_BITS

PCI_TYPE2_CSE_BITS

typedef struct _PCI_TYPE2_CSE_BITS PCI_TYPE2_CSE_BITS

PciIrqRange

typedef NTSTATUS(NTAPI * PciIrqRange) (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER PciSlot, OUT PSUPPORTED_RANGE *Interrupt)

Definition at line 85 of file bus.h.

PCIPBUSDATA

typedef struct _PCIPBUSDATA PCIPBUSDATA

PHAL_BUS_HANDLER

typedef struct _HAL_BUS_HANDLER * PHAL_BUS_HANDLER

PPCI_CONFIG_HANDLER

typedef struct _PCI_CONFIG_HANDLER * PPCI_CONFIG_HANDLER

PPCI_REGISTRY_INFO_INTERNAL

typedef struct _PCI_REGISTRY_INFO_INTERNAL * PPCI_REGISTRY_INFO_INTERNAL

PPCI_TYPE0_CFG_CYCLE_BITS

typedef struct _PCI_TYPE0_CFG_CYCLE_BITS * PPCI_TYPE0_CFG_CYCLE_BITS

PPCI_TYPE1_CFG_BITS

typedef struct _PCI_TYPE1_CFG_BITS * PPCI_TYPE1_CFG_BITS

PPCI_TYPE1_CFG_CYCLE_BITS

typedef union _PCI_TYPE1_CFG_CYCLE_BITS * PPCI_TYPE1_CFG_CYCLE_BITS

PPCI_TYPE2_ADDRESS_BITS

typedef struct _PCI_TYPE2_ADDRESS_BITS * PPCI_TYPE2_ADDRESS_BITS

PPCI_TYPE2_CSE_BITS

typedef struct _PCI_TYPE2_CSE_BITS PPCI_TYPE2_CSE_BITS

PPCIPBUSDATA

typedef struct _PCIPBUSDATA * PPCIPBUSDATA

Function Documentation

HaliFindBusAddressTranslation()

BOOLEAN NTAPI HaliFindBusAddressTranslation	(	IN PHYSICAL_ADDRESS	BusAddress,
		IN OUT PULONG	AddressSpace,
		OUT PPHYSICAL_ADDRESS	TranslatedAddress,
		IN OUT PULONG_PTR	Context,
		IN BOOLEAN	NextBus
	)

Definition at line 1327 of file bussupp.c.

{
    PHAL_BUS_HANDLER BusHandler;
    PBUS_HANDLER Handler;
    PLIST_ENTRY NextEntry;
    ULONG ContextValue;
 
    /* Make sure we have a context */
    if (!Context) return FALSE;
    ASSERT((*Context) || (NextBus == TRUE));
 
    /* Read the context */
    ContextValue = *Context;
 
    /* Find the bus handler */
    Handler = HalpContextToBusHandler(ContextValue);
    if (!Handler) return FALSE;
 
    /* Check if this is an ongoing lookup */
    if (NextBus)
    {
        /* Get the HAL bus handler */
        BusHandler = CONTAINING_RECORD(Handler, HAL_BUS_HANDLER, Handler);
        NextEntry = &BusHandler->AllHandlers;
 
        /* Get the next one if we were already with one */
        if (ContextValue) NextEntry = NextEntry->Flink;
 
        /* Start scanning */
        while (TRUE)
        {
            /* Check if this is the last one */
            if (NextEntry == &HalpAllBusHandlers)
            {
                /* Quit */
                *Context = 1;
                return FALSE;
            }
 
            /* Call this translator */
            BusHandler = CONTAINING_RECORD(NextEntry, HAL_BUS_HANDLER, AllHandlers);
            if (HalTranslateBusAddress(BusHandler->Handler.InterfaceType,
                                       BusHandler->Handler.BusNumber,
                                       BusAddress,
                                       AddressSpace,
                                       TranslatedAddress)) break;
 
            /* Try the next one */
            NextEntry = NextEntry->Flink;
        }
 
        /* If we made it, we're done */
        *Context = (ULONG_PTR)&BusHandler->Handler;
        return TRUE;
    }
 
    /* Try the first one through */
    if (!HalTranslateBusAddress(Handler->InterfaceType,
                                Handler->BusNumber,
                                BusAddress,
                                AddressSpace,
                                TranslatedAddress)) return FALSE;
 
    /* Remember for next time */
    *Context = (ULONG_PTR)Handler;
    return TRUE;
}

Referenced by HalpInitBusHandler().

HaliReferenceHandlerForConfigSpace()

PBUS_HANDLER FASTCALL HaliReferenceHandlerForConfigSpace	(	IN BUS_DATA_TYPE	ConfigType,
		IN ULONG	BusNumber
	)

Definition at line 197 of file bushndlr.c.

{
    /* Lookup the configuration in the configuration table and add a reference */
    return HalpLookupHandler(HalpConfigTable, ConfigType, BusNumber, TRUE);
}

Referenced by HalGetBusDataByOffset(), and HalSetBusDataByOffset().

HaliTranslateBusAddress()

BOOLEAN NTAPI HaliTranslateBusAddress	(	IN INTERFACE_TYPE	InterfaceType,
		IN ULONG	BusNumber,
		IN PHYSICAL_ADDRESS	BusAddress,
		IN OUT PULONG	AddressSpace,
		OUT PPHYSICAL_ADDRESS	TranslatedAddress
	)

Definition at line 1401 of file bussupp.c.

{
    PBUS_HANDLER Handler;
    BOOLEAN Status;
 
    /* Find the handler */
    Handler = HalReferenceHandlerForBus(InterfaceType, BusNumber);
    if (!(Handler) || !(Handler->TranslateBusAddress))
    {
        DPRINT1("No translator Interface: %x, Bus: %x, Handler: %p, BusAddress: %x!\n", InterfaceType, BusNumber, Handler, BusAddress);
        return FALSE;
    }
 
    /* Do the assignment */
    Status = Handler->TranslateBusAddress(Handler,
                                          Handler,
                                          BusAddress,
                                          AddressSpace,
                                          TranslatedAddress);
 
    /* Dereference the handler and return */
    HalDereferenceBusHandler(Handler);
    return Status;
}

Referenced by HalpInitBusHandler(), and HalTranslateBusAddress().

HalpAdjustPCIResourceList()

NTSTATUS NTAPI HalpAdjustPCIResourceList	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *	pResourceList
	)

Definition at line 757 of file pcibus.c.

{
    PPCIPBUSDATA BusData;
    PCI_SLOT_NUMBER SlotNumber;
    PSUPPORTED_RANGE Interrupt;
    NTSTATUS Status;
 
    /* Get PCI bus data */
    BusData = BusHandler->BusData;
    SlotNumber.u.AsULONG = (*pResourceList)->SlotNumber;
 
    /* Get the IRQ supported range */
    Status = BusData->GetIrqRange(BusHandler, RootHandler, SlotNumber, &Interrupt);
    if (!NT_SUCCESS(Status)) return Status;
#ifndef _MINIHAL_
    /* Handle the /PCILOCK feature */
    if (HalpPciLockSettings)
    {
        /* /PCILOCK is not yet supported */
        UNIMPLEMENTED_DBGBREAK("/PCILOCK boot switch is not yet supported.");
    }
#endif
    /* Now create the correct resource list based on the supported bus ranges */
#if 0
    Status = HaliAdjustResourceListRange(BusHandler->BusAddresses,
                                         Interrupt,
                                         pResourceList);
#else
    DPRINT1("HAL: No PCI Resource Adjustment done! Hardware may malfunction\n");
    Status = STATUS_SUCCESS;
#endif
 
    /* Return to caller */
    ExFreePool(Interrupt);
    return Status;
}

Referenced by HalpAllocateAndInitPciBusHandler().

HalpAssignPCISlotResources()

NTSTATUS NTAPI HalpAssignPCISlotResources	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN PUNICODE_STRING	RegistryPath,
		IN PUNICODE_STRING DriverClassName	OPTIONAL,
		IN PDRIVER_OBJECT	DriverObject,
		IN PDEVICE_OBJECT DeviceObject	OPTIONAL,
		IN ULONG	Slot,
		IN OUT PCM_RESOURCE_LIST *	pAllocatedResources
	)

Definition at line 798 of file pcibus.c.

{
    PCI_COMMON_CONFIG PciConfig;
    SIZE_T Address;
    ULONG ResourceCount;
    ULONG Size[PCI_TYPE0_ADDRESSES];
    NTSTATUS Status = STATUS_SUCCESS;
    UCHAR Offset;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor;
    PCI_SLOT_NUMBER SlotNumber;
    ULONG WriteBuffer;
    DPRINT1("WARNING: PCI Slot Resource Assignment is FOOBAR\n");
 
    /* FIXME: Should handle 64-bit addresses */
 
    /* Read configuration data */
    SlotNumber.u.AsULONG = Slot;
    HalpReadPCIConfig(BusHandler, SlotNumber, &PciConfig, 0, PCI_COMMON_HDR_LENGTH);
 
    /* Check if we read it correctly */
    if (PciConfig.VendorID == PCI_INVALID_VENDORID)
        return STATUS_NO_SUCH_DEVICE;
 
    /* Read the PCI configuration space for the device and store base address and
    size information in temporary storage. Count the number of valid base addresses */
    ResourceCount = 0;
    for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
    {
        if (0xffffffff == PciConfig.u.type0.BaseAddresses[Address])
            PciConfig.u.type0.BaseAddresses[Address] = 0;
 
        /* Memory resource */
        if (0 != PciConfig.u.type0.BaseAddresses[Address])
        {
            ResourceCount++;
 
            Offset = (UCHAR)FIELD_OFFSET(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
 
            /* Write 0xFFFFFFFF there */
            WriteBuffer = 0xffffffff;
            HalpWritePCIConfig(BusHandler, SlotNumber, &WriteBuffer, Offset, sizeof(ULONG));
 
            /* Read that figure back from the config space */
            HalpReadPCIConfig(BusHandler, SlotNumber, &Size[Address], Offset, sizeof(ULONG));
 
            /* Write back initial value */
            HalpWritePCIConfig(BusHandler, SlotNumber, &PciConfig.u.type0.BaseAddresses[Address], Offset, sizeof(ULONG));
        }
    }
 
    /* Interrupt resource */
    if (0 != PciConfig.u.type0.InterruptPin &&
        0 != PciConfig.u.type0.InterruptLine &&
        0xFF != PciConfig.u.type0.InterruptLine)
        ResourceCount++;
 
    /* Allocate output buffer and initialize */
    *AllocatedResources = ExAllocatePoolWithTag(
        PagedPool,
        sizeof(CM_RESOURCE_LIST) +
        (ResourceCount - 1) * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR),
        TAG_HAL);
 
    if (NULL == *AllocatedResources)
        return STATUS_NO_MEMORY;
 
    (*AllocatedResources)->Count = 1;
    (*AllocatedResources)->List[0].InterfaceType = PCIBus;
    (*AllocatedResources)->List[0].BusNumber = BusHandler->BusNumber;
    (*AllocatedResources)->List[0].PartialResourceList.Version = 1;
    (*AllocatedResources)->List[0].PartialResourceList.Revision = 1;
    (*AllocatedResources)->List[0].PartialResourceList.Count = ResourceCount;
    Descriptor = (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
 
    /* Store configuration information */
    for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
    {
        if (0 != PciConfig.u.type0.BaseAddresses[Address])
        {
            if (PCI_ADDRESS_MEMORY_SPACE ==
                (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
            {
                Descriptor->Type = CmResourceTypeMemory;
                Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
                Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;             /* FIXME Just a guess */
                Descriptor->u.Memory.Start.QuadPart = (PciConfig.u.type0.BaseAddresses[Address] & PCI_ADDRESS_MEMORY_ADDRESS_MASK);
                Descriptor->u.Memory.Length = PciSize(Size[Address], PCI_ADDRESS_MEMORY_ADDRESS_MASK);
            }
            else if (PCI_ADDRESS_IO_SPACE ==
                (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
            {
                Descriptor->Type = CmResourceTypePort;
                Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
                Descriptor->Flags = CM_RESOURCE_PORT_IO;                       /* FIXME Just a guess */
                Descriptor->u.Port.Start.QuadPart = PciConfig.u.type0.BaseAddresses[Address] &= PCI_ADDRESS_IO_ADDRESS_MASK;
                Descriptor->u.Port.Length = PciSize(Size[Address], PCI_ADDRESS_IO_ADDRESS_MASK & 0xffff);
            }
            else
            {
                ASSERT(FALSE);
                return STATUS_UNSUCCESSFUL;
            }
            Descriptor++;
        }
    }
 
    if (0 != PciConfig.u.type0.InterruptPin &&
        0 != PciConfig.u.type0.InterruptLine &&
        0xFF != PciConfig.u.type0.InterruptLine)
    {
        Descriptor->Type = CmResourceTypeInterrupt;
        Descriptor->ShareDisposition = CmResourceShareShared;          /* FIXME Just a guess */
        Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;     /* FIXME Just a guess */
        Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
        Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
        Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
 
        Descriptor++;
    }
 
    ASSERT(Descriptor == (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors + ResourceCount);
 
    /* FIXME: Should store the resources in the registry resource map */
 
    return Status;
}

Referenced by HalpAllocateAndInitPciBusHandler(), and HalpAssignSlotResources().

HalpAssignSlotResources()

NTSTATUS NTAPI HalpAssignSlotResources	(	IN PUNICODE_STRING	RegistryPath,
		IN PUNICODE_STRING	DriverClassName,
		IN PDRIVER_OBJECT	DriverObject,
		IN PDEVICE_OBJECT	DeviceObject,
		IN INTERFACE_TYPE	BusType,
		IN ULONG	BusNumber,
		IN ULONG	SlotNumber,
		IN OUT PCM_RESOURCE_LIST *	AllocatedResources
	)

Definition at line 45 of file busemul.c.

{
    BUS_HANDLER BusHandler;
    PAGED_CODE();
 
    /* Only PCI is supported */
    if (BusType != PCIBus) return STATUS_NOT_IMPLEMENTED;
 
    /* Setup fake PCI Bus handler */
    RtlCopyMemory(&BusHandler, &HalpFakePciBusHandler, sizeof(BUS_HANDLER));
    BusHandler.BusNumber = BusNumber;
 
    /* Call the PCI function */
    return HalpAssignPCISlotResources(&BusHandler,
                                      &BusHandler,
                                      RegistryPath,
                                      DriverClassName,
                                      DriverObject,
                                      DeviceObject,
                                      SlotNumber,
                                      AllocatedResources);
}

Referenced by HalAssignSlotResources(), HalpInitBusHandler(), and HalpInitNonBusHandler().

HalpcGetCmosData()

ULONG NTAPI HalpcGetCmosData	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN ULONG	SlotNumber,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 21 of file cmosbus.c.

{
    UNIMPLEMENTED_DBGBREAK("CMOS GetData\n");
    return 0;
}

Referenced by HalpRegisterInternalBusHandlers().

HalpContextToBusHandler()

PBUS_HANDLER NTAPI HalpContextToBusHandler

(

IN ULONG_PTR

ContextValue

)

Definition at line 206 of file bushndlr.c.

{
    PLIST_ENTRY NextEntry;
    PHAL_BUS_HANDLER BusHandler, ThisHandler;
 
    /* Start lookup */
    NextEntry = HalpAllBusHandlers.Flink;
    ThisHandler = CONTAINING_RECORD(NextEntry, HAL_BUS_HANDLER, AllHandlers);
    if (ContextValue)
    {
        /* If the list is empty, quit */
        if (IsListEmpty(&HalpAllBusHandlers)) return NULL;
 
        /* Otherwise, scan the list */
        BusHandler = CONTAINING_RECORD(ContextValue, HAL_BUS_HANDLER, Handler);
        do
        {
            /* Check if we've reached the right one */
            ThisHandler = CONTAINING_RECORD(NextEntry, HAL_BUS_HANDLER, AllHandlers);
            if (ThisHandler == BusHandler) break;
 
            /* Try the next one */
            NextEntry = NextEntry->Flink;
        } while (NextEntry != &HalpAllBusHandlers);
    }
 
    /* If we looped back to the end, we didn't find anything */
    if (NextEntry == &HalpAllBusHandlers) return NULL;
 
    /* Otherwise return the handler */
    return &ThisHandler->Handler;
}

Referenced by HaliFindBusAddressTranslation().

HalpcSetCmosData()

ULONG NTAPI HalpcSetCmosData	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN ULONG	SlotNumber,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 34 of file cmosbus.c.

{
    UNIMPLEMENTED_DBGBREAK("CMOS SetData\n");
    return 0;
}

Referenced by HalpRegisterInternalBusHandlers().

HalpFindBusAddressTranslation()

BOOLEAN NTAPI HalpFindBusAddressTranslation	(	IN PHYSICAL_ADDRESS	BusAddress,
		IN OUT PULONG	AddressSpace,
		OUT PPHYSICAL_ADDRESS	TranslatedAddress,
		IN OUT PULONG_PTR	Context,
		IN BOOLEAN	NextBus
	)

Definition at line 90 of file busemul.c.

{
    /* Make sure we have a context */
    if (!Context) return FALSE;
 
    /* If we have data in the context, then this shouldn't be a new lookup */
    if ((*Context != 0) && (NextBus != FALSE)) return FALSE;
 
    /* Return bus data */
    TranslatedAddress->QuadPart = BusAddress.QuadPart;
 
    /* Set context value and return success */
    *Context = 1;
    return TRUE;
}

Referenced by HalpInitNonBusHandler().

HalpGetCmosData()

ULONG NTAPI HalpGetCmosData	(	_In_ ULONG	BusNumber,
		_In_ ULONG	SlotNumber,
		_Out_writes_bytes_(Length) PVOID	Buffer,
		_In_ ULONG	Length
	)

Definition at line 49 of file cmos.c.

{
    PUCHAR Ptr = (PUCHAR)Buffer;
    ULONG Address = SlotNumber;
    ULONG Len = Length;
 
    /* Do nothing if we don't have a length */
    if (!Length) return 0;
 
    /* Acquire CMOS Lock */
    HalpAcquireCmosSpinLock();
 
    /* Check if this is simple CMOS */
    if (BusNumber == 0)
    {
        /* Loop the buffer up to 0xFF */
        while ((Len > 0) && (Address < 0x100))
        {
            /* Read the data */
            *Ptr = HalpReadCmos((UCHAR)Address);
 
            /* Update position and length */
            Ptr++;
            Address++;
            Len--;
        }
    }
    else if (BusNumber == 1)
    {
        /* Loop the buffer up to 0xFFFF */
        while ((Len > 0) && (Address < 0x10000))
        {
            /* Write the data */
            *Ptr = HalpReadCmos((UCHAR)Address);
 
            /* Update position and length */
            Ptr++;
            Address++;
            Len--;
        }
    }
 
    /* Release CMOS Lock */
    HalpReleaseCmosSpinLock();
 
    /* Return length read */
    return Length - Len;
}

Referenced by HalGetBusDataByOffset().

HalpGetISAFixedPCIIrq()

NTSTATUS NTAPI HalpGetISAFixedPCIIrq	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN PCI_SLOT_NUMBER	PciSlot,
		OUT PSUPPORTED_RANGE *	Range
	)

Definition at line 702 of file pcibus.c.

{
    PCI_COMMON_HEADER PciData;
 
    /* Read PCI configuration data */
    HalGetBusData(PCIConfiguration,
                  BusHandler->BusNumber,
                  PciSlot.u.AsULONG,
                  &PciData,
                  PCI_COMMON_HDR_LENGTH);
 
    /* Make sure it's a real device */
    if (PciData.VendorID == PCI_INVALID_VENDORID) return STATUS_UNSUCCESSFUL;
 
    /* Allocate the supported range structure */
    *Range = ExAllocatePoolWithTag(PagedPool, sizeof(SUPPORTED_RANGE), TAG_HAL);
    if (!*Range) return STATUS_INSUFFICIENT_RESOURCES;
 
    /* Set it up */
    RtlZeroMemory(*Range, sizeof(SUPPORTED_RANGE));
    (*Range)->Base = 1;
 
    /* If the PCI device has no IRQ, nothing to do */
    if (!PciData.u.type0.InterruptPin) return STATUS_SUCCESS;
 
    /* FIXME: The PCI IRQ Routing Miniport should be called */
 
    /* Also if the INT# seems bogus, nothing to do either */
    if ((PciData.u.type0.InterruptLine == 0) ||
        (PciData.u.type0.InterruptLine == 255))
    {
        /* Fake success */
        return STATUS_SUCCESS;
    }
 
    /* Otherwise, the INT# should be valid, return it to the caller */
    (*Range)->Base = PciData.u.type0.InterruptLine;
    (*Range)->Limit = PciData.u.type0.InterruptLine;
    return STATUS_SUCCESS;
}

Referenced by HalpAllocateAndInitPciBusHandler().

HalpGetPCIData()

ULONG NTAPI HalpGetPCIData	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootBusHandler,
		IN ULONG	SlotNumber,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 507 of file pcibus.c.

{
    PCI_SLOT_NUMBER Slot;
    UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
    PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
    ULONG Len = 0;
 
    Slot.u.AsULONG = SlotNumber;
#ifdef SARCH_XBOX
    if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
    {
        RtlFillMemory(Buffer, Length, 0xFF);
        return Length;
    }
#endif
 
    /* Normalize the length */
    if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
 
    /* Check if this is a vendor-specific read */
    if (Offset >= PCI_COMMON_HDR_LENGTH)
    {
        /* Read the header */
        HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
 
        /* Make sure the vendor is valid */
        if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
    }
    else
    {
        /* Read the entire header */
        Len = PCI_COMMON_HDR_LENGTH;
        HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
 
        /* Validate the vendor ID */
        if (PciConfig->VendorID == PCI_INVALID_VENDORID)
        {
            /* It's invalid, but we want to return this much */
            Len = sizeof(USHORT);
        }
 
        /* Now check if there's space left */
        if (Len < Offset) return 0;
 
        /* There is, so return what's after the offset and normalize */
        Len -= Offset;
        if (Len > Length) Len = Length;
 
        /* Copy the data into the caller's buffer */
        RtlMoveMemory(Buffer, PciBuffer + Offset, Len);
 
        /* Update buffer and offset, decrement total length */
        Offset += Len;
        Buffer = (PVOID)((ULONG_PTR)Buffer + Len);
        Length -= Len;
    }
 
    /* Now we still have something to copy */
    if (Length)
    {
        /* Check if it's vendor-specific data */
        if (Offset >= PCI_COMMON_HDR_LENGTH)
        {
            /* Read it now */
            HalpReadPCIConfig(BusHandler, Slot, Buffer, Offset, Length);
            Len += Length;
        }
    }
 
    /* Update the total length read */
    return Len;
}

Referenced by HalGetBusDataByOffset(), and HalpAllocateAndInitPciBusHandler().

HalpGetPCIIntOnISABus()

ULONG NTAPI HalpGetPCIIntOnISABus	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN ULONG	BusInterruptLevel,
		IN ULONG	BusInterruptVector,
		OUT PKIRQL	Irql,
		OUT PKAFFINITY	Affinity
	)

Definition at line 658 of file pcibus.c.

{
    /* Validate the level first */
    if (BusInterruptLevel < 1) return 0;
 
    /* PCI has its IRQs on top of ISA IRQs, so pass it on to the ISA handler */
    return HalGetInterruptVector(Isa,
                                 0,
                                 BusInterruptLevel,
                                 0,
                                 Irql,
                                 Affinity);
}

Referenced by HalpAllocateAndInitPciBusHandler().

HalpGetRootInterruptVector()

ULONG NTAPI HalpGetRootInterruptVector	(	_In_ ULONG	BusInterruptLevel,
		_In_ ULONG	BusInterruptVector,
		_Out_ PKIRQL	Irql,
		_Out_ PKAFFINITY	Affinity
	)

Definition at line 400 of file apic.c.

{
    UCHAR Vector;
    KIRQL Irql;
 
    /* Get the vector currently registered */
    Vector = HalpIrqToVector(BusInterruptLevel);
 
    /* Check if it's used */
    if (Vector != APIC_FREE_VECTOR)
    {
        /* Calculate IRQL */
        NT_ASSERT(HalpVectorToIndex[Vector] == BusInterruptLevel);
        *OutIrql = HalpVectorToIrql(Vector);
    }
    else
    {
        ULONG Offset;
 
        /* Outer loop to find alternative slots, when all IRQLs are in use */
        for (Offset = 0; Offset < 15; Offset++)
        {
            /* Loop allowed IRQL range */
            for (Irql = CLOCK_LEVEL - 1; Irql >= CMCI_LEVEL; Irql--)
            {
                /* Calculate the vactor */
                Vector = IrqlToTpr(Irql) + Offset;
 
                /* Check if the vector is free */
                if (HalpVectorToIrq(Vector) == APIC_FREE_VECTOR)
                {
                    /* Found one, allocate the interrupt */
                    Vector = HalpAllocateSystemInterrupt(BusInterruptLevel, Vector);
                    *OutIrql = Irql;
                    goto Exit;
                }
            }
        }
 
        DPRINT1("Failed to get an interrupt vector for IRQ %lu\n", BusInterruptLevel);
        *OutAffinity = 0;
        *OutIrql = 0;
        return 0;
    }
 
Exit:
 
    *OutAffinity = HalpDefaultInterruptAffinity;
    ASSERT(HalpDefaultInterruptAffinity);
 
    return Vector;
}

Referenced by HalGetInterruptVector(), and HalpGetSystemInterruptVector().

HalpGetSystemInterruptVector()

ULONG NTAPI HalpGetSystemInterruptVector	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN ULONG	BusInterruptLevel,
		IN ULONG	BusInterruptVector,
		OUT PKIRQL	Irql,
		OUT PKAFFINITY	Affinity
	)

Definition at line 115 of file sysbus.c.

{
    ULONG Vector;
 
    /* Get the root vector */
    Vector = HalpGetRootInterruptVector(BusInterruptLevel,
                                        BusInterruptVector,
                                        Irql,
                                        Affinity);
 
    /* Check if the vector is owned by the HAL and fail if it is */
    if (HalpIDTUsageFlags[Vector].Flags & IDT_REGISTERED) DPRINT1("Vector %lx is ALREADY IN USE!\n", Vector);
    return (HalpIDTUsageFlags[Vector].Flags & IDT_REGISTERED) ? 0 : Vector;
}

Referenced by HalpRegisterInternalBusHandlers().

HalpInitBusHandler()

VOID NTAPI HalpInitBusHandler

(

VOID

)

Definition at line 420 of file bushndlr.c.

{
    /* Setup the bus lock */
    KeInitializeSpinLock(&HalpBusDatabaseSpinLock);
 
    /* Setup the bus event */
    KeInitializeEvent(&HalpBusDatabaseEvent, SynchronizationEvent, TRUE);
 
    /* Setup the bus configuration and bus table */
    HalpBusTable = HalpAllocateArray(0);
    HalpConfigTable = HalpAllocateArray(0);
 
    /* Setup the bus list */
    InitializeListHead(&HalpAllBusHandlers);
 
    /* Setup the HAL Dispatch routines */
#ifndef _MINIHAL_
    HalRegisterBusHandler = HaliRegisterBusHandler;
    HalHandlerForBus = HaliHandlerForBus;
    HalHandlerForConfigSpace = HaliHandlerForConfigSpace;
    HalReferenceHandlerForBus = HaliReferenceHandlerForBus;
    HalReferenceBusHandler = HaliReferenceBusHandler;
    HalDereferenceBusHandler = HaliDereferenceBusHandler;
#endif
    HalPciAssignSlotResources = HalpAssignSlotResources;
    HalPciTranslateBusAddress = HaliTranslateBusAddress; /* PCI Driver can override */
    if (!HalFindBusAddressTranslation) HalFindBusAddressTranslation = HaliFindBusAddressTranslation;
}

Referenced by HalpRegisterInternalBusHandlers(), and LoadBootDeviceDriver().

HalpInitializePciBus()

VOID NTAPI HalpInitializePciBus

(

VOID

)

Definition at line 913 of file halacpi.c.

{
    /* Setup the PCI stub support */
    HalpInitializePciStubs();
 
    /* Set the NMI crash flag */
    HalpGetNMICrashFlag();
}

Referenced by HalReportResourceUsage().

HalpInitializePciStubs()

VOID NTAPI HalpInitializePciStubs

(

VOID

)

Definition at line 1190 of file pcibus.c.

{
    PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
    UCHAR PciType;
    PPCIPBUSDATA BusData = (PPCIPBUSDATA)HalpFakePciBusHandler.BusData;
    ULONG i;
    PCI_SLOT_NUMBER j;
    ULONG VendorId = 0;
    ULONG MaxPciBusNumber;
 
    /* Query registry information */
    PciRegistryInfo = HalpQueryPciRegistryInfo();
    if (!PciRegistryInfo)
    {
        /* Assume type 1 */
        PciType = 1;
 
        /* Force a manual bus scan later */
        MaxPciBusNumber = MAXULONG;
    }
    else
    {
        /* Get the PCI type */
        PciType = PciRegistryInfo->HardwareMechanism & 0xF;
 
        /* Get MaxPciBusNumber and make it 0-based */
        MaxPciBusNumber = PciRegistryInfo->NoBuses - 1;
 
        /* Free the info structure */
        ExFreePoolWithTag(PciRegistryInfo, TAG_HAL);
    }
 
    /* Initialize the PCI lock */
    KeInitializeSpinLock(&HalpPCIConfigLock);
 
    /* Check the type of PCI bus */
    switch (PciType)
    {
        /* Type 1 PCI Bus */
        case 1:
 
            /* Copy the Type 1 handler data */
            RtlCopyMemory(&PCIConfigHandler,
                          &PCIConfigHandlerType1,
                          sizeof(PCIConfigHandler));
 
            /* Set correct I/O Ports */
            BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
            BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
            break;
 
        /* Type 2 PCI Bus */
        case 2:
 
            /* Copy the Type 2 handler data */
            RtlCopyMemory(&PCIConfigHandler,
                          &PCIConfigHandlerType2,
                          sizeof (PCIConfigHandler));
 
            /* Set correct I/O Ports */
            BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
            BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
            BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
 
            /* Only 16 devices supported, not 32 */
            BusData->MaxDevice = 16;
            break;
 
        default:
 
            /* Invalid type */
            DbgPrint("HAL: Unknown PCI type\n");
    }
 
    /* Run a forced bus scan if needed */
    if (MaxPciBusNumber == MAXULONG)
    {
        /* Initialize the max bus number to 0xFF */
        HalpMaxPciBus = 0xFF;
 
        /* Initialize the counter */
        MaxPciBusNumber = 0;
 
        /* Loop all possible buses */
        for (i = 0; i < HalpMaxPciBus; i++)
        {
            /* Loop all devices */
            for (j.u.AsULONG = 0; j.u.AsULONG < BusData->MaxDevice; j.u.AsULONG++)
            {
                /* Query the interface */
                if (HaliPciInterfaceReadConfig(NULL,
                                               i,
                                               j,
                                               &VendorId,
                                               0,
                                               sizeof(ULONG)))
                {
                    /* Validate the vendor ID */
                    if ((VendorId & 0xFFFF) != PCI_INVALID_VENDORID)
                    {
                        /* Set this as the maximum ID */
                        MaxPciBusNumber = i;
                        break;
                    }
                }
            }
        }
    }
 
    /* Set the real max bus number */
    HalpMaxPciBus = MaxPciBusNumber;
 
    /* We're done */
    HalpPCIConfigInitialized = TRUE;
}

Referenced by HalpInitializePciBus(), HalReportResourceUsage(), and LoadBootDeviceDriver().

HalpNoBusData()

ULONG NTAPI HalpNoBusData	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN ULONG	SlotNumber,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 108 of file bushndlr.c.

{
    /* Not implemented */
    DPRINT1("STUB GetSetBusData\n");
    return 0;
}

Referenced by HaliRegisterBusHandler(), and HalpRegisterInternalBusHandlers().

HalpPCIISALine2Pin()

VOID NTAPI HalpPCIISALine2Pin	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN PCI_SLOT_NUMBER	SlotNumber,
		IN PPCI_COMMON_CONFIG	PciNewData,
		IN PPCI_COMMON_CONFIG	PciOldData
	)

Definition at line 690 of file pcibus.c.

{
    UNIMPLEMENTED_DBGBREAK();
}

Referenced by HalpAllocateAndInitPciBusHandler().

HalpPCIPin2ISALine()

VOID NTAPI HalpPCIPin2ISALine	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN PCI_SLOT_NUMBER	SlotNumber,
		IN PPCI_COMMON_CONFIG	PciData
	)

Definition at line 680 of file pcibus.c.

{
    UNIMPLEMENTED_DBGBREAK();
}

Referenced by HalpAllocateAndInitPciBusHandler().

HalpPCIReleaseSynchronizationType2()

VOID NTAPI HalpPCIReleaseSynchronizationType2	(	IN PBUS_HANDLER	BusHandler,
		IN KIRQL	Irql
	)

Definition at line 193 of file pcibus.c.

{
    PCI_TYPE2_CSE_BITS PciCfg2Cse;
    PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
 
    /* Clear CSE and bus number */
    PciCfg2Cse.u.AsUCHAR = 0;
    WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
    WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
 
    /* Release the lock */
    KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
}

HalpPCIReleaseSynchronzationType1()

VOID NTAPI HalpPCIReleaseSynchronzationType1	(	IN PBUS_HANDLER	BusHandler,
		IN KIRQL	Irql
	)

Definition at line 137 of file pcibus.c.

{
    PCI_TYPE1_CFG_BITS PciCfg1;
 
    /* Clear the PCI Configuration Register */
    PciCfg1.u.AsULONG = 0;
    WRITE_PORT_ULONG(((PPCIPBUSDATA)BusHandler->BusData)->Config.Type1.Address,
                     PciCfg1.u.AsULONG);
 
    /* Release the lock */
    KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
}

HalpPCISynchronizeType1()

VOID NTAPI HalpPCISynchronizeType1	(	IN PBUS_HANDLER	BusHandler,
		IN PCI_SLOT_NUMBER	Slot,
		IN PKIRQL	Irql,
		IN PPCI_TYPE1_CFG_BITS	PciCfg
	)

HalpPCISynchronizeType2()

VOID NTAPI HalpPCISynchronizeType2	(	IN PBUS_HANDLER	BusHandler,
		IN PCI_SLOT_NUMBER	Slot,
		IN PKIRQL	Irql,
		IN PPCI_TYPE2_ADDRESS_BITS	PciCfg
	)

HalpPhase0GetPciDataByOffset()

ULONG HalpPhase0GetPciDataByOffset	(	_In_ ULONG	Bus,
		_In_ PCI_SLOT_NUMBER	PciSlot,
		_Out_writes_bytes_all_(Length) PVOID	Buffer,
		_In_ ULONG	Offset,
		_In_ ULONG	Length
	)

Definition at line 368 of file pcibus.c.

{
    ULONG BytesLeft = Length;
    PUCHAR BufferPtr = Buffer;
    PCI_TYPE1_CFG_BITS PciCfg;
 
#ifdef SARCH_XBOX
    if (HalpXboxBlacklistedPCISlot(Bus, PciSlot))
    {
        RtlFillMemory(Buffer, Length, 0xFF);
        return Length;
    }
#endif
 
    PciCfg.u.AsULONG = 0;
    PciCfg.u.bits.BusNumber = Bus;
    PciCfg.u.bits.DeviceNumber = PciSlot.u.bits.DeviceNumber;
    PciCfg.u.bits.FunctionNumber = PciSlot.u.bits.FunctionNumber;
    PciCfg.u.bits.Enable = TRUE;
 
    while (BytesLeft)
    {
        ULONG i;
 
        PciCfg.u.bits.RegisterNumber = Offset / sizeof(ULONG);
        WRITE_PORT_ULONG((PULONG)PCI_TYPE1_ADDRESS_PORT, PciCfg.u.AsULONG);
 
        i = PCIDeref[Offset % sizeof(ULONG)][BytesLeft % sizeof(ULONG)];
        switch (i)
        {
            case 0:
            {
                *(PULONG)BufferPtr = READ_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT);
 
                /* Number of bytes read */
                i = sizeof(ULONG);
                break;
            }
            case 1:
            {
                *BufferPtr = READ_PORT_UCHAR((PUCHAR)(PCI_TYPE1_DATA_PORT +
                                             Offset % sizeof(ULONG)));
                break;
            }
            case 2:
            {
                *(PUSHORT)BufferPtr = READ_PORT_USHORT((PUSHORT)(PCI_TYPE1_DATA_PORT +
                                                                 Offset % sizeof(ULONG)));
                break;
            }
 
            DEFAULT_UNREACHABLE;
        }
 
        Offset += i;
        BufferPtr += i;
        BytesLeft -= i;
    }
 
    return Length;
}

Referenced by HalpConfigureDebuggingDevice(), and HalpFindMatchingDebuggingDevice().

HalpPhase0SetPciDataByOffset()

ULONG HalpPhase0SetPciDataByOffset	(	_In_ ULONG	Bus,
		_In_ PCI_SLOT_NUMBER	PciSlot,
		_In_reads_bytes_(Length) PVOID	Buffer,
		_In_ ULONG	Offset,
		_In_ ULONG	Length
	)

Definition at line 437 of file pcibus.c.

{
    ULONG BytesLeft = Length;
    PUCHAR BufferPtr = Buffer;
    PCI_TYPE1_CFG_BITS PciCfg;
 
#ifdef SARCH_XBOX
    if (HalpXboxBlacklistedPCISlot(Bus, PciSlot))
    {
        return 0;
    }
#endif
 
    PciCfg.u.AsULONG = 0;
    PciCfg.u.bits.BusNumber = Bus;
    PciCfg.u.bits.DeviceNumber = PciSlot.u.bits.DeviceNumber;
    PciCfg.u.bits.FunctionNumber = PciSlot.u.bits.FunctionNumber;
    PciCfg.u.bits.Enable = TRUE;
 
    while (BytesLeft)
    {
        ULONG i;
 
        PciCfg.u.bits.RegisterNumber = Offset / sizeof(ULONG);
        WRITE_PORT_ULONG((PULONG)PCI_TYPE1_ADDRESS_PORT, PciCfg.u.AsULONG);
 
        i = PCIDeref[Offset % sizeof(ULONG)][BytesLeft % sizeof(ULONG)];
        switch (i)
        {
            case 0:
            {
                WRITE_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT, *(PULONG)BufferPtr);
 
                /* Number of bytes written */
                i = sizeof(ULONG);
                break;
            }
            case 1:
            {
                WRITE_PORT_UCHAR((PUCHAR)(PCI_TYPE1_DATA_PORT + Offset % sizeof(ULONG)),
                                 *BufferPtr);
                break;
            }
            case 2:
            {
                WRITE_PORT_USHORT((PUSHORT)(PCI_TYPE1_DATA_PORT + Offset % sizeof(ULONG)),
                                  *(PUSHORT)BufferPtr);
                break;
            }
 
            DEFAULT_UNREACHABLE;
        }
 
        Offset += i;
        BufferPtr += i;
        BytesLeft -= i;
    }
 
    return Length;
}

Referenced by HalpConfigureDebuggingDevice().

HalpQueryPciRegistryInfo()

PPCI_REGISTRY_INFO_INTERNAL NTAPI HalpQueryPciRegistryInfo

(

VOID

)

Definition at line 957 of file pcibus.c.

{
#ifndef _MINIHAL_
    WCHAR NameBuffer[8];
    OBJECT_ATTRIBUTES  ObjectAttributes;
    UNICODE_STRING KeyName, ConfigName, IdentName;
    HANDLE KeyHandle, BusKeyHandle, CardListHandle;
    NTSTATUS Status;
    UCHAR KeyBuffer[sizeof(CM_FULL_RESOURCE_DESCRIPTOR) + 100];
    PKEY_VALUE_FULL_INFORMATION ValueInfo = (PVOID)KeyBuffer;
    UCHAR PartialKeyBuffer[sizeof(KEY_VALUE_PARTIAL_INFORMATION) +
                           sizeof(PCI_CARD_DESCRIPTOR)];
    PKEY_VALUE_PARTIAL_INFORMATION PartialValueInfo = (PVOID)PartialKeyBuffer;
    KEY_FULL_INFORMATION KeyInformation;
    ULONG ResultLength;
    PWSTR Tag;
    ULONG i, ElementCount;
    PCM_FULL_RESOURCE_DESCRIPTOR FullDescriptor;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptor;
    PPCI_REGISTRY_INFO PciRegInfo;
    PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
    PPCI_CARD_DESCRIPTOR CardDescriptor;
 
    /* Setup the object attributes for the key */
    RtlInitUnicodeString(&KeyName,
                         L"\\Registry\\Machine\\Hardware\\Description\\"
                         L"System\\MultiFunctionAdapter");
    InitializeObjectAttributes(&ObjectAttributes,
                               &KeyName,
                               OBJ_CASE_INSENSITIVE,
                               NULL,
                               NULL);
 
    /* Open the key */
    Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
    if (!NT_SUCCESS(Status)) return NULL;
 
    /* Setup the receiving string */
    KeyName.Buffer = NameBuffer;
    KeyName.MaximumLength = sizeof(NameBuffer);
 
    /* Setup the configuration and identifier key names */
    RtlInitUnicodeString(&ConfigName, L"Configuration Data");
    RtlInitUnicodeString(&IdentName, L"Identifier");
 
    /* Keep looping for each ID */
    for (i = 0; TRUE; i++)
    {
        /* Setup the key name */
        RtlIntegerToUnicodeString(i, 10, &KeyName);
        InitializeObjectAttributes(&ObjectAttributes,
                                   &KeyName,
                                   OBJ_CASE_INSENSITIVE,
                                   KeyHandle,
                                   NULL);
 
        /* Open it */
        Status = ZwOpenKey(&BusKeyHandle, KEY_READ, &ObjectAttributes);
        if (!NT_SUCCESS(Status))
        {
            /* None left, fail */
            ZwClose(KeyHandle);
            return NULL;
        }
 
        /* Read the registry data */
        Status = ZwQueryValueKey(BusKeyHandle,
                                 &IdentName,
                                 KeyValueFullInformation,
                                 ValueInfo,
                                 sizeof(KeyBuffer),
                                 &ResultLength);
        if (!NT_SUCCESS(Status))
        {
            /* Failed, try the next one */
            ZwClose(BusKeyHandle);
            continue;
        }
 
        /* Get the PCI Tag and validate it */
        Tag = (PWSTR)((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
        if ((Tag[0] != L'P') ||
            (Tag[1] != L'C') ||
            (Tag[2] != L'I') ||
            (Tag[3]))
        {
            /* Not a valid PCI entry, skip it */
            ZwClose(BusKeyHandle);
            continue;
        }
 
        /* Now read our PCI structure */
        Status = ZwQueryValueKey(BusKeyHandle,
                                 &ConfigName,
                                 KeyValueFullInformation,
                                 ValueInfo,
                                 sizeof(KeyBuffer),
                                 &ResultLength);
        ZwClose(BusKeyHandle);
        if (!NT_SUCCESS(Status)) continue;
 
        /* We read it OK! Get the actual resource descriptors */
        FullDescriptor  = (PCM_FULL_RESOURCE_DESCRIPTOR)
                          ((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
        PartialDescriptor = (PCM_PARTIAL_RESOURCE_DESCRIPTOR)
                            ((ULONG_PTR)FullDescriptor->
                                        PartialResourceList.PartialDescriptors);
 
        /* Check if this is our PCI Registry Information */
        if (PartialDescriptor->Type == CmResourceTypeDeviceSpecific)
        {
            /* It is, stop searching */
            break;
        }
    }
 
    /* Close the key */
    ZwClose(KeyHandle);
 
    /* Save the PCI information for later */
    PciRegInfo = (PPCI_REGISTRY_INFO)(PartialDescriptor + 1);
 
    /* Assume no Card List entries */
    ElementCount = 0;
 
    /* Set up for checking the PCI Card List key */
    RtlInitUnicodeString(&KeyName,
                         L"\\Registry\\Machine\\System\\CurrentControlSet\\"
                         L"Control\\PnP\\PCI\\CardList");
    InitializeObjectAttributes(&ObjectAttributes,
                               &KeyName,
                               OBJ_CASE_INSENSITIVE,
                               NULL,
                               NULL);
 
    /* Attempt to open it */
    Status = ZwOpenKey(&CardListHandle, KEY_READ, &ObjectAttributes);
    if (NT_SUCCESS(Status))
    {
        /* It exists, so let's query it */
        Status = ZwQueryKey(CardListHandle,
                            KeyFullInformation,
                            &KeyInformation,
                            sizeof(KEY_FULL_INFORMATION),
                            &ResultLength);
        if (!NT_SUCCESS(Status))
        {
            /* Failed to query, so no info */
            PciRegistryInfo = NULL;
        }
        else
        {
            /* Allocate the full structure */
            PciRegistryInfo =
                ExAllocatePoolWithTag(NonPagedPool,
                                      sizeof(PCI_REGISTRY_INFO_INTERNAL) +
                                      (KeyInformation.Values *
                                       sizeof(PCI_CARD_DESCRIPTOR)),
                                       TAG_HAL);
            if (PciRegistryInfo)
            {
                /* Get the first card descriptor entry */
                CardDescriptor = (PPCI_CARD_DESCRIPTOR)(PciRegistryInfo + 1);
 
                /* Loop all the values */
                for (i = 0; i < KeyInformation.Values; i++)
                {
                    /* Attempt to get the value */
                    Status = ZwEnumerateValueKey(CardListHandle,
                                                 i,
                                                 KeyValuePartialInformation,
                                                 PartialValueInfo,
                                                 sizeof(PartialKeyBuffer),
                                                 &ResultLength);
                    if (!NT_SUCCESS(Status))
                    {
                        /* Something went wrong, stop the search */
                        break;
                    }
 
                    /* Make sure it is correctly sized */
                    if (PartialValueInfo->DataLength == sizeof(PCI_CARD_DESCRIPTOR))
                    {
                        /* Sure is, copy it over */
                        *CardDescriptor = *(PPCI_CARD_DESCRIPTOR)
                                           PartialValueInfo->Data;
 
                        /* One more Card List entry */
                        ElementCount++;
 
                        /* Move to the next descriptor */
                        CardDescriptor = (CardDescriptor + 1);
                    }
                }
            }
        }
 
        /* Close the Card List key */
        ZwClose(CardListHandle);
    }
    else
    {
       /* No key, no Card List */
       PciRegistryInfo = NULL;
    }
 
    /* Check if we failed to get the full structure */
    if (!PciRegistryInfo)
    {
        /* Just allocate the basic structure then */
        PciRegistryInfo = ExAllocatePoolWithTag(NonPagedPool,
                                                sizeof(PCI_REGISTRY_INFO_INTERNAL),
                                                TAG_HAL);
        if (!PciRegistryInfo) return NULL;
    }
 
    /* Save the info we got */
    PciRegistryInfo->MajorRevision = PciRegInfo->MajorRevision;
    PciRegistryInfo->MinorRevision = PciRegInfo->MinorRevision;
    PciRegistryInfo->NoBuses = PciRegInfo->NoBuses;
    PciRegistryInfo->HardwareMechanism = PciRegInfo->HardwareMechanism;
    PciRegistryInfo->ElementCount = ElementCount;
 
    /* Return it */
    return PciRegistryInfo;
#else
    return NULL;
#endif
}

Referenced by HalpInitializePciBus(), and HalpInitializePciStubs().

HalpReadPCIConfig()

VOID NTAPI HalpReadPCIConfig	(	IN PBUS_HANDLER	BusHandler,
		IN PCI_SLOT_NUMBER	Slot,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 257 of file pcibus.c.

{
    /* Validate the PCI Slot */
    if (!HalpValidPCISlot(BusHandler, Slot))
    {
        /* Fill the buffer with invalid data */
        RtlFillMemory(Buffer, Length, -1);
    }
    else
    {
        /* Send the request */
        HalpPCIConfig(BusHandler,
                      Slot,
                      Buffer,
                      Offset,
                      Length,
                      PCIConfigHandler.ConfigRead);
    }
}

Referenced by HaliPciInterfaceReadConfig(), HalpAllocateAndInitPciBusHandler(), HalpAssignPCISlotResources(), HalpDebugPciDumpBus(), HalpGetPciBridgeConfig(), HalpGetPCIData(), HalpInitializePciBus(), HalpIsValidPCIDevice(), HalpSetPCIData(), and HalpValidPCISlot().

HalpRegisterPciDebuggingDeviceInfo()

VOID NTAPI HalpRegisterPciDebuggingDeviceInfo

(

VOID

)

Definition at line 331 of file kdpci.c.

{
    ULONG i;
    NTSTATUS Status;
    WCHAR StringBuffer[16];
    BOOLEAN HasDebuggingDevice = FALSE;
    UNICODE_STRING KeyName = RTL_CONSTANT_STRING(L"\\Registry\\Machine\\System\\"
                                                 L"CurrentControlSet\\Services\\PCI\\Debug");
    HANDLE Handle, KeyHandle;
 
    PAGED_CODE();
 
    for (i = 0; i < RTL_NUMBER_OF(HalpPciDebuggingDevice); ++i)
    {
        if (HalpPciDebuggingDevice[i].InUse)
        {
            HasDebuggingDevice = TRUE;
            break;
        }
    }
    if (!HasDebuggingDevice)
    {
        /* Nothing to register */
        return;
    }
 
    Status = HalpOpenRegistryKey(&Handle, 0, &KeyName, KEY_ALL_ACCESS, TRUE);
    if (!NT_SUCCESS(Status))
        return;
 
    for (i = 0; i < RTL_NUMBER_OF(HalpPciDebuggingDevice); ++i)
    {
        ULONG Value;
        PCI_SLOT_NUMBER PciSlot;
 
        if (!HalpPciDebuggingDevice[i].InUse)
            continue;
 
        RtlInitEmptyUnicodeString(&KeyName, StringBuffer, sizeof(StringBuffer));
        RtlIntegerToUnicodeString(i, 10, &KeyName);
        Status = HalpOpenRegistryKey(&KeyHandle,
                                     Handle,
                                     &KeyName,
                                     KEY_ALL_ACCESS,
                                     TRUE);
        if (!NT_SUCCESS(Status))
            continue;
 
        Value = HalpPciDebuggingDevice[i].BusNumber;
        RtlInitUnicodeString(&KeyName, L"Bus");
        ZwSetValueKey(KeyHandle,
                      &KeyName,
                      0,
                      REG_DWORD,
                      &Value,
                      sizeof(Value));
 
        PciSlot.u.AsULONG = 0;
        PciSlot.u.bits.DeviceNumber = HalpPciDebuggingDevice[i].DeviceNumber;
        PciSlot.u.bits.FunctionNumber = HalpPciDebuggingDevice[i].FunctionNumber;
        Value = PciSlot.u.AsULONG;
        RtlInitUnicodeString(&KeyName, L"Slot");
        ZwSetValueKey(KeyHandle,
                      &KeyName,
                      0,
                      REG_DWORD,
                      &Value,
                      sizeof(Value));
 
        ZwClose(KeyHandle);
    }
 
    ZwClose(Handle);
}

Referenced by HalReportResourceUsage().

HalpSetCmosData()

ULONG NTAPI HalpSetCmosData	(	IN ULONG	BusNumber,
		IN ULONG	SlotNumber,
		IN PVOID	Buffer,
		IN ULONG	Length
	)

Definition at line 104 of file cmos.c.

{
    PUCHAR Ptr = (PUCHAR)Buffer;
    ULONG Address = SlotNumber;
    ULONG Len = Length;
 
    /* Do nothing if we don't have a length */
    if (!Length) return 0;
 
    /* Acquire CMOS Lock */
    HalpAcquireCmosSpinLock();
 
    /* Check if this is simple CMOS */
    if (BusNumber == 0)
    {
        /* Loop the buffer up to 0xFF */
        while ((Len > 0) && (Address < 0x100))
        {
            /* Write the data */
            HalpWriteCmos((UCHAR)Address, *Ptr);
 
            /* Update position and length */
            Ptr++;
            Address++;
            Len--;
        }
    }
    else if (BusNumber == 1)
    {
        /* Loop the buffer up to 0xFFFF */
        while ((Len > 0) && (Address < 0x10000))
        {
            /* Write the data */
            HalpWriteCmos((UCHAR)Address, *Ptr);
 
            /* Update position and length */
            Ptr++;
            Address++;
            Len--;
        }
    }
 
    /* Release CMOS Lock */
    HalpReleaseCmosSpinLock();
 
    /* Return length read */
    return Length - Len;
}

Referenced by HalSetBusDataByOffset().

HalpSetPCIData()

ULONG NTAPI HalpSetPCIData	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootBusHandler,
		IN ULONG	SlotNumber,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 587 of file pcibus.c.

{
    PCI_SLOT_NUMBER Slot;
    UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
    PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
    ULONG Len = 0;
 
    Slot.u.AsULONG = SlotNumber;
#ifdef SARCH_XBOX
    if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
        return 0;
#endif
 
    /* Normalize the length */
    if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
 
    /* Check if this is a vendor-specific read */
    if (Offset >= PCI_COMMON_HDR_LENGTH)
    {
        /* Read the header */
        HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
 
        /* Make sure the vendor is valid */
        if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
    }
    else
    {
        /* Read the entire header and validate the vendor ID */
        Len = PCI_COMMON_HDR_LENGTH;
        HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
        if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
 
        /* Return what's after the offset and normalize */
        Len -= Offset;
        if (Len > Length) Len = Length;
 
        /* Copy the specific caller data */
        RtlMoveMemory(PciBuffer + Offset, Buffer, Len);
 
        /* Write the actual configuration data */
        HalpWritePCIConfig(BusHandler, Slot, PciBuffer + Offset, Offset, Len);
 
        /* Update buffer and offset, decrement total length */
        Offset += Len;
        Buffer = (PVOID)((ULONG_PTR)Buffer + Len);
        Length -= Len;
    }
 
    /* Now we still have something to copy */
    if (Length)
    {
        /* Check if it's vendor-specific data */
        if (Offset >= PCI_COMMON_HDR_LENGTH)
        {
            /* Read it now */
            HalpWritePCIConfig(BusHandler, Slot, Buffer, Offset, Length);
            Len += Length;
        }
    }
 
    /* Update the total length read */
    return Len;
}

Referenced by HalpAllocateAndInitPciBusHandler(), and HalSetBusDataByOffset().

HalpTranslateBusAddress()

BOOLEAN NTAPI HalpTranslateBusAddress	(	IN INTERFACE_TYPE	InterfaceType,
		IN ULONG	BusNumber,
		IN PHYSICAL_ADDRESS	BusAddress,
		IN OUT PULONG	AddressSpace,
		OUT PPHYSICAL_ADDRESS	TranslatedAddress
	)

Definition at line 77 of file busemul.c.

{
    /* Translation is easy */
    TranslatedAddress->QuadPart = BusAddress.QuadPart;
    return TRUE;
}

Referenced by HalpInitNonBusHandler().

HalpTranslateIsaBusAddress()

BOOLEAN NTAPI HalpTranslateIsaBusAddress	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN PHYSICAL_ADDRESS	BusAddress,
		IN OUT PULONG	AddressSpace,
		OUT PPHYSICAL_ADDRESS	TranslatedAddress
	)

Definition at line 21 of file isabus.c.

{
    BOOLEAN Status;
 
    /* Use system translation */
    Status = HalpTranslateSystemBusAddress(BusHandler,
                                           RootHandler,
                                           BusAddress,
                                           AddressSpace,
                                           TranslatedAddress);
 
    /* If it didn't work and it was memory address space... */
    if (!(Status) && (*AddressSpace == 0))
    {
        /* Try EISA translation instead */
        Status = HalTranslateBusAddress(Eisa,
                                        BusHandler->BusNumber,
                                        BusAddress,
                                        AddressSpace,
                                        TranslatedAddress);
    }
 
    /* Return the result */
    return Status;
}

Referenced by HalpRegisterInternalBusHandlers().

HalpTranslateSystemBusAddress()

BOOLEAN NTAPI HalpTranslateSystemBusAddress	(	IN PBUS_HANDLER	BusHandler,
		IN PBUS_HANDLER	RootHandler,
		IN PHYSICAL_ADDRESS	BusAddress,
		IN OUT PULONG	AddressSpace,
		OUT PPHYSICAL_ADDRESS	TranslatedAddress
	)

Definition at line 21 of file sysbus.c.

{
    PSUPPORTED_RANGE Range = NULL;
 
    /* Check what kind of address space this is */
    switch (*AddressSpace)
    {
        /* Memory address */
        case 0:
 
            /* Loop all prefetch memory */
            for (Range = &BusHandler->BusAddresses->PrefetchMemory;
                 Range;
                 Range = Range->Next)
            {
                /* Check if it's in a valid range */
                if ((BusAddress.QuadPart >= Range->Base) &&
                    (BusAddress.QuadPart <= Range->Limit))
                {
                    /* Get out */
                    break;
                }
            }
 
            /* Check if we haven't found anything yet */
            if (!Range)
            {
                /* Loop all bus memory */
                for (Range = &BusHandler->BusAddresses->Memory;
                     Range;
                     Range = Range->Next)
                {
                    /* Check if it's in a valid range */
                    if ((BusAddress.QuadPart >= Range->Base) &&
                        (BusAddress.QuadPart <= Range->Limit))
                    {
                        /* Get out */
                        break;
                    }
                }
            }
 
            /* Done */
            break;
 
        /* I/O Space */
        case 1:
 
            /* Loop all bus I/O memory */
            for (Range = &BusHandler->BusAddresses->IO;
                 Range;
                 Range = Range->Next)
            {
                /* Check if it's in a valid range */
                if ((BusAddress.QuadPart >= Range->Base) &&
                    (BusAddress.QuadPart <= Range->Limit))
                {
                    /* Get out */
                    break;
                }
            }
 
            /* Done */
            break;
    }
 
    /* Check if we found a range */
    if (Range)
    {
        /* Do the translation and return the kind of address space this is */
        TranslatedAddress->QuadPart = BusAddress.QuadPart + Range->SystemBase;
        if ((TranslatedAddress->QuadPart != BusAddress.QuadPart) ||
            (*AddressSpace != Range->SystemAddressSpace))
        {
            /* Different than what the old HAL would do */
            DPRINT1("Translation of %I64x is %I64x %s\n",
                    BusAddress.QuadPart, TranslatedAddress->QuadPart,
                    Range->SystemAddressSpace ? "In I/O Space" : "In RAM");
        }
        *AddressSpace = Range->SystemAddressSpace;
        return TRUE;
    }
 
    /* Nothing found */
    DPRINT1("Translation of %I64x failed!\n", BusAddress.QuadPart);
    return FALSE;
}

Referenced by HalpRegisterInternalBusHandlers(), and HalpTranslateIsaBusAddress().

HalpValidPCISlot()

BOOLEAN NTAPI HalpValidPCISlot	(	IN PBUS_HANDLER	BusHandler,
		IN PCI_SLOT_NUMBER	Slot
	)

Definition at line 329 of file pcibus.c.

{
    PCI_SLOT_NUMBER MultiSlot;
    PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
    UCHAR HeaderType;
    //ULONG Device;
 
    /* Simple validation */
    if (Slot.u.bits.Reserved) return FALSE;
    if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice) return FALSE;
 
#ifdef SARCH_XBOX
    if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
        return FALSE;
#endif
 
    /* Function 0 doesn't need checking */
    if (!Slot.u.bits.FunctionNumber) return TRUE;
 
    /* Functions 0+ need Multi-Function support, so check the slot */
    //Device = Slot.u.bits.DeviceNumber;
    MultiSlot = Slot;
    MultiSlot.u.bits.FunctionNumber = 0;
 
    /* Send function 0 request to get the header back */
    HalpReadPCIConfig(BusHandler,
                      MultiSlot,
                      &HeaderType,
                      FIELD_OFFSET(PCI_COMMON_CONFIG, HeaderType),
                      sizeof(UCHAR));
 
    /* Now make sure the header is multi-function */
    if (!(HeaderType & PCI_MULTIFUNCTION) || (HeaderType == 0xFF)) return FALSE;
    return TRUE;
}

Referenced by HalpReadPCIConfig(), and HalpWritePCIConfig().

HalpWritePCIConfig()

VOID NTAPI HalpWritePCIConfig	(	IN PBUS_HANDLER	BusHandler,
		IN PCI_SLOT_NUMBER	Slot,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 283 of file pcibus.c.

{
    /* Validate the PCI Slot */
    if (HalpValidPCISlot(BusHandler, Slot))
    {
        /* Send the request */
        HalpPCIConfig(BusHandler,
                      Slot,
                      Buffer,
                      Offset,
                      Length,
                      PCIConfigHandler.ConfigWrite);
    }
}

Referenced by HalpAllocateAndInitPciBusHandler(), HalpAssignPCISlotResources(), HalpDebugPciDumpBus(), and HalpSetPCIData().

TYPE1_DEFINE() [1/6]

TYPE1_DEFINE

(

HalpPCIReadUcharType1

)

TYPE1_DEFINE() [2/6]

TYPE1_DEFINE

(

HalpPCIReadUlongType1

)

TYPE1_DEFINE() [3/6]

TYPE1_DEFINE

(

HalpPCIReadUshortType1

)

TYPE1_DEFINE() [4/6]

TYPE1_DEFINE

(

HalpPCIWriteUcharType1

)

TYPE1_DEFINE() [5/6]

TYPE1_DEFINE

(

HalpPCIWriteUlongType1

)

TYPE1_DEFINE() [6/6]

TYPE1_DEFINE

(

HalpPCIWriteUshortType1

)

TYPE2_DEFINE() [1/6]

TYPE2_DEFINE

(

HalpPCIReadUcharType2

)

TYPE2_DEFINE() [2/6]

TYPE2_DEFINE

(

HalpPCIReadUlongType2

)

TYPE2_DEFINE() [3/6]

TYPE2_DEFINE

(

HalpPCIReadUshortType2

)

TYPE2_DEFINE() [4/6]

TYPE2_DEFINE

(

HalpPCIWriteUcharType2

)

TYPE2_DEFINE() [5/6]

TYPE2_DEFINE

(

HalpPCIWriteUlongType2

)

TYPE2_DEFINE() [6/6]

TYPE2_DEFINE

(

HalpPCIWriteUshortType2

)

Variable Documentation

HalpAllBusHandlers

LIST_ENTRY HalpAllBusHandlers

extern

Definition at line 19 of file bushndlr.c.

Referenced by HaliFindBusAddressTranslation(), HaliRegisterBusHandler(), HalpContextToBusHandler(), and HalpInitBusHandler().

HalpBusType

ULONG HalpBusType

extern

Definition at line 18 of file pcibus.c.

Referenced by HalHandleNMI(), HalInitSystem(), HalpInitDma(), HalpInitializeCmos(), HalpIs16BitPortDecodeSupported(), HalpRegisterInternalBusHandlers(), and HalReportResourceUsage().

HalpFakePciBusHandler

BUS_HANDLER HalpFakePciBusHandler

extern

Definition at line 94 of file pcibus.c.

Referenced by HalGetBusDataByOffset(), HaliPciInterfaceReadConfig(), HalpAssignSlotResources(), HalpInitializePciStubs(), and HalSetBusDataByOffset().

HalpMaxPciBus

ULONG HalpMaxPciBus

Definition at line 640 of file bus.h.

Referenced by HalGetBusDataByOffset().

HalpMinPciBus

ULONG HalpMinPciBus

extern

Definition at line 21 of file pcibus.c.

Referenced by HalGetBusDataByOffset().

HalpPCIConfigInitialized

BOOLEAN HalpPCIConfigInitialized

extern

Definition at line 20 of file pcibus.c.

Referenced by HalGetBusDataByOffset(), HalpInitializePciStubs(), and HalSetBusDataByOffset().

PCIConfigHandler

PCI_CONFIG_HANDLER PCIConfigHandler

extern

Definition at line 23 of file pcibus.c.

Referenced by HalpAllocateAndInitPciBusHandler(), HalpInitializePciStubs(), HalpPCIConfig(), HalpReadPCIConfig(), and HalpWritePCIConfig().

PCIConfigHandlerType1

PCI_CONFIG_HANDLER PCIConfigHandlerType1

extern

Definition at line 35 of file pcibus.c.

Referenced by HalpAllocateAndInitPciBusHandler(), and HalpInitializePciStubs().

PCIConfigHandlerType2

PCI_CONFIG_HANDLER PCIConfigHandlerType2

extern

Definition at line 57 of file pcibus.c.

Referenced by HalpAllocateAndInitPciBusHandler(), and HalpInitializePciStubs().