ReactOS 0.4.15-dev-8145-ga541a46
bussupp.c
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1/*
2 * PROJECT: ReactOS HAL
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: hal/halx86/legacy/bussupp.c
5 * PURPOSE: HAL Legacy Bus Support Code
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9/* INCLUDES *******************************************************************/
10
11#include <hal.h>
12#define NDEBUG
13#include <debug.h>
14
15CODE_SEG("INIT")
19 IN ULONG PciType,
20 IN ULONG BusNo,
21 IN BOOLEAN TestAllocation
22);
23
24CODE_SEG("INIT")
25VOID
28 IN ULONG BusCount
29);
30
31CODE_SEG("INIT")
35 IN USHORT VendorId,
36 IN USHORT DeviceId,
37 IN UCHAR RevisionId,
39);
40
41CODE_SEG("INIT")
45 IN ULONG PciType,
46 IN PUCHAR BusCount
47);
48
49CODE_SEG("INIT")
54);
55
56CODE_SEG("INIT")
61);
62
63CODE_SEG("INIT")
67 IN PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo,
68 IN PPCI_COMMON_CONFIG PciData,
70);
71
72CODE_SEG("INIT")
76 IN PBUS_HANDLER BusHandler,
78);
79
80CODE_SEG("INIT")
84 IN BOOLEAN OverrideEnable
85);
86
87CODE_SEG("INIT")
88VOID
91 VOID
92);
93
94CODE_SEG("INIT")
95VOID
99);
100
101/* GLOBALS ********************************************************************/
102
105
106/* PRIVATE FUNCTIONS **********************************************************/
107
109NTAPI
111 IN BUS_DATA_TYPE BusDataType,
113 IN INTERFACE_TYPE ParentBusInterfaceType,
114 IN ULONG ParentBusNumber,
115 IN ULONG BusSpecificData)
116{
117 PBUS_HANDLER Bus;
118
119 /* Register the bus handler */
121 BusDataType,
122 BusNumber,
123 ParentBusInterfaceType,
124 ParentBusNumber,
125 BusSpecificData,
126 NULL,
127 &Bus);
128 if (!Bus)
129 {
130 return NULL;
131 }
132
133 /* Check for a valid interface */
135 {
136 /* Allocate address ranges and zero them out */
138 sizeof(SUPPORTED_RANGES),
139 TAG_HAL);
141
142 /* Build the data structure */
144 Bus->BusAddresses->Dma.Limit = 7;
145 Bus->BusAddresses->Memory.Limit = 0xFFFFFFFF;
146 Bus->BusAddresses->IO.Limit = 0xFFFF;
149 }
150
151 /* Return the bus address */
152 return Bus;
153}
154
155#ifndef _MINIHAL_
156CODE_SEG("INIT")
157VOID
158NTAPI
160{
161 PBUS_HANDLER Bus;
162
163 /* Only do processor 1 */
164 if (KeGetCurrentPrcb()->Number) return;
165
166 /* Register root support */
168
169 /* Allocate the system bus */
172 0,
174 0,
175 0);
176 if (Bus)
177 {
178 /* Set it up */
181 }
182
183 /* Allocate the CMOS bus */
185 Cmos,
186 0,
188 0,
189 0);
190 if (Bus)
191 {
192 /* Set it up */
195 }
196
197 /* Allocate the CMOS bus */
199 Cmos,
200 1,
202 0,
203 0);
204 if (Bus)
205 {
206 /* Set it up */
209 }
210
211 /* Allocate ISA bus */
214 0,
215 Internal,
216 0,
217 0);
218 if (Bus)
219 {
220 /* Set it up */
222 Bus->BusAddresses->Memory.Limit = 0xFFFFFF;
224 }
225
226 /* No support for EISA or MCA */
228}
229#endif // _MINIHAL_
230
231#ifndef _MINIHAL_
232CODE_SEG("INIT")
234NTAPI
236{
238 UNICODE_STRING KeyString;
239 ULONG Data = OverrideEnable;
241
242 /* Open CCS key */
243 RtlInitUnicodeString(&KeyString,
244 L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET");
246 if (NT_SUCCESS(Status))
247 {
248 /* Open PNP Bios key */
249 RtlInitUnicodeString(&KeyString, L"Control\\Biosinfo\\PNPBios");
251 Handle,
252 &KeyString,
254 TRUE);
255
256 /* Close root key */
258
259 /* Check if PNP BIOS key exists */
260 if (NT_SUCCESS(Status))
261 {
262 /* Set the override value */
263 RtlInitUnicodeString(&KeyString, L"FullDecodeChipsetOverride");
264 Status = ZwSetValueKey(KeyHandle,
265 &KeyString,
266 0,
267 REG_DWORD,
268 &Data,
269 sizeof(Data));
270
271 /* Close subkey */
273 }
274 }
275
276 /* Return status */
277 return Status;
278}
279
280CODE_SEG("INIT")
282NTAPI
284 IN ULONG BusNo,
285 IN BOOLEAN TestAllocation)
286{
287 PBUS_HANDLER Bus;
288 PPCIPBUSDATA BusData;
289
290 /* Allocate the bus handler */
293 BusNo,
294 Internal,
295 0,
296 sizeof(PCIPBUSDATA));
297
298 /* Set it up */
304 Bus->BusAddresses->Dma.Limit = 0;
305
306 /* Get our custom bus data */
307 BusData = (PPCIPBUSDATA)Bus->BusData;
308
309 /* Setup custom bus data */
310 BusData->CommonData.Tag = PCI_DATA_TAG;
316 BusData->MaxDevice = PCI_MAX_DEVICES;
318
319 /* Initialize the bitmap */
320 RtlInitializeBitMap(&BusData->DeviceConfigured, BusData->ConfiguredBits, 256);
321
322 /* Check the type of PCI bus */
323 switch (PciType)
324 {
325 /* Type 1 PCI Bus */
326 case 1:
327
328 /* Copy the Type 1 handler data */
331 sizeof(PCIConfigHandler));
332
333 /* Set correct I/O Ports */
334 BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
335 BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
336 break;
337
338 /* Type 2 PCI Bus */
339 case 2:
340
341 /* Copy the Type 1 handler data */
344 sizeof (PCIConfigHandler));
345
346 /* Set correct I/O Ports */
347 BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
348 BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
349 BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
350
351 /* Only 16 devices supported, not 32 */
352 BusData->MaxDevice = 16;
353 break;
354
355 default:
356
357 /* Invalid type */
358 DbgPrint("HAL: Unknown PCI type\n");
359 }
360
361 /* Return the bus handler */
362 return Bus;
363}
364
365CODE_SEG("INIT")
367NTAPI
369 IN PCI_SLOT_NUMBER Slot)
370{
371 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
372 PPCI_COMMON_CONFIG PciHeader = (PVOID)DataBuffer;
373 ULONG i;
375
376 /* Read the PCI header */
377 HalpReadPCIConfig(BusHandler, Slot, PciHeader, 0, PCI_COMMON_HDR_LENGTH);
378
379 /* Make sure it's a valid device */
380 if ((PciHeader->VendorID == PCI_INVALID_VENDORID) ||
382 {
383 /* Bail out */
384 return FALSE;
385 }
386
387 /* Make sure interrupt numbers make sense */
388 if (((PciHeader->u.type0.InterruptPin) &&
389 (PciHeader->u.type0.InterruptPin > 4)) ||
390 (PciHeader->u.type0.InterruptLine & 0x70))
391 {
392 /* Bail out */
393 return FALSE;
394 }
395
396 /* Now scan PCI BARs */
397 for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
398 {
399 /* Check what kind of address it is */
400 Address = PciHeader->u.type0.BaseAddresses[i];
402 {
403 /* Highest I/O port is 65535 */
404 if (Address > 0xFFFF) return FALSE;
405 }
406 else
407 {
408 /* MMIO should be higher than 0x80000 */
409 if ((Address > 0xF) && (Address < 0x80000)) return FALSE;
410 }
411
412 /* Is this a 64-bit address? */
413 if (!(Address & PCI_ADDRESS_IO_SPACE) &&
415 {
416 /* Check the next-next entry, since this one 64-bits wide */
417 i++;
418 }
419 }
420
421 /* Header, interrupt and address data all make sense */
422 return TRUE;
423}
424
426
427CODE_SEG("INIT")
429NTAPI
431 IN USHORT DeviceId,
432 IN UCHAR RevisionId,
434{
439 WCHAR Buffer[32];
442
443 /* Setup the object attributes for the key */
445 L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET\\"
446 L"Control\\HAL");
448 &KeyName,
450 NULL,
451 NULL);
452
453 /* Open the key */
454 Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
455 if (!NT_SUCCESS(Status)) return Status;
456
457 /* Query value */
458 swprintf(Buffer, L"%04X%04X", VendorId, DeviceId);
460 Status = ZwQueryValueKey(KeyHandle,
461 &ValueName,
463 &PartialInfo,
464 sizeof(PartialInfo),
465 &ResultLength);
466 if (NT_SUCCESS(Status))
467 {
468 /* Return the flags */
469 DbgPrint("\tFound HackFlags for your chipset\n");
470 *HackFlags = *(PULONG)PartialInfo.Data;
471 DbgPrint("\t\tHack Flags: %lx (Hack Revision: %lx-Your Revision: %lx)\n",
473
474 /* Does it apply to this revision? */
475 if ((RevisionId) && (RevisionId >= (HALP_REVISION_FROM_HACK_FLAGS(*HackFlags))))
476 {
477 /* Read the revision flags */
479 }
480
481 /* Throw out revision data */
483 if (!*HackFlags) DbgPrint("\tNo HackFlags for your chipset's revision!\n");
484 }
485
486 /* Close the handle and return */
488 return Status;
489}
490
491CODE_SEG("INIT")
493NTAPI
495 IN PPCI_COMMON_CONFIG PciData,
496 IN ULONG Flags)
497{
498 ULONG ElementCount, i;
499 PPCI_CARD_DESCRIPTOR CardDescriptor;
500
501 /* How many PCI Cards that we know about? */
502 ElementCount = PciRegistryInfo->ElementCount;
503 if (!ElementCount) return FALSE;
504
505 /* Loop all descriptors */
506 CardDescriptor = &PciRegistryInfo->CardList[0];
507 for (i = 0; i < ElementCount; i++, CardDescriptor++)
508 {
509 /* Check for flag match */
510 if (CardDescriptor->Flags != Flags) continue;
511
512 /* Check for VID-PID match */
513 if ((CardDescriptor->VendorID != PciData->VendorID) ||
514 (CardDescriptor->DeviceID != PciData->DeviceID))
515 {
516 /* Skip */
517 continue;
518 }
519
520 /* Check for revision match, if requested */
521 if ((CardDescriptor->Flags & HALP_CHECK_CARD_REVISION_ID) &&
522 (CardDescriptor->RevisionID != PciData->RevisionID))
523 {
524 /* Skip */
525 continue;
526 }
527
528 /* Check what kind of device this is */
529 switch (PCI_CONFIGURATION_TYPE(PciData))
530 {
531 /* CardBUS Bridge */
533
534 /* This means the real device header is in the device-specific data */
535 PciData = (PPCI_COMMON_CONFIG)PciData->DeviceSpecific;
536
537 /* Normal PCI device */
538 case PCI_DEVICE_TYPE:
539
540 /* Check for subvendor match, if requested */
541 if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBVENDOR_ID) &&
542 (CardDescriptor->SubsystemVendorID != PciData->u.type0.SubVendorID))
543 {
544 /* Skip */
545 continue;
546 }
547
548 /* Check for subsystem match, if requested */
549 if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBSYSTEM_ID) &&
550 (CardDescriptor->SubsystemID != PciData->u.type0.SubSystemID))
551 {
552 /* Skip */
553 continue;
554 }
555
556 /* You made it! */
557 return TRUE;
558
559 /* PCI Bridge -- don't bother */
560 case PCI_BRIDGE_TYPE:
561 default:
562
563 /* Recognize it */
564 return TRUE;
565 }
566 }
567
568 /* This means the card isn't recognized */
569 return FALSE;
570}
571
572CODE_SEG("INIT")
574NTAPI
576{
577 /* Simple test first */
578 if ((PciData->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
579 (PciData->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
580 {
581 /* The device is nice enough to admit it */
582 return TRUE;
583 }
584
585 /* Symphony 82C101 */
586 if (PciData->VendorID == 0x1C1C) return TRUE;
587
588 /* ALi MS4803 or M5219 */
589 if ((PciData->VendorID == 0x10B9) &&
590 ((PciData->DeviceID == 0x5215) || (PciData->DeviceID == 0x5219)))
591 {
592 return TRUE;
593 }
594
595 /* Appian Technology */
596 if ((PciData->VendorID == 0x1097) && (PciData->DeviceID == 0x38)) return TRUE;
597
598 /* Compaq Triflex Dual EIDE Controller */
599 if ((PciData->VendorID == 0xE11) && (PciData->DeviceID == 0xAE33)) return TRUE;
600
601 /* Micron PC Tech RZ1000 */
602 if ((PciData->VendorID == 0x1042) && (PciData->DeviceID == 0x1000)) return TRUE;
603
604 /* SiS 85C601 or 5513 [IDE] */
605 if ((PciData->VendorID == 0x1039) &&
606 ((PciData->DeviceID == 0x601) || (PciData->DeviceID == 0x5513)))
607 {
608 return TRUE;
609 }
610
611 /* Symphony Labs W83769F */
612 if ((PciData->VendorID == 0x10AD) &&
613 ((PciData->DeviceID == 0x1) || (PciData->DeviceID == 0x150)))
614 {
615 return TRUE;
616 }
617
618 /* UMC UM8673F */
619 if ((PciData->VendorID == 0x1060) && (PciData->DeviceID == 0x101)) return TRUE;
620
621 /* You've survived */
622 return FALSE;
623}
624
625CODE_SEG("INIT")
627NTAPI
629{
630 /* Either this is a PCI-to-PCI Bridge, or a CardBUS Bridge */
631 return (((PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE) &&
632 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
633 (PciData->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI)) ||
635 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
636 (PciData->SubClass == PCI_SUBCLASS_BR_CARDBUS)));
637}
638
639CODE_SEG("INIT")
641NTAPI
643 IN PUCHAR BusCount)
644{
645 PCI_SLOT_NUMBER PciSlot;
646 ULONG i, j, k;
647 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
648 PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
649 PBUS_HANDLER BusHandler;
650
651 /* Loop PCI buses */
652 PciSlot.u.bits.Reserved = 0;
653 for (i = 0; i < *BusCount; i++)
654 {
655 /* Get the bus handler */
656 BusHandler = HalHandlerForBus(PCIBus, i);
657
658 /* Loop every device */
659 for (j = 0; j < PCI_MAX_DEVICES; j++)
660 {
661 /* Loop every function */
662 PciSlot.u.bits.DeviceNumber = j;
663 for (k = 0; k < PCI_MAX_FUNCTION; k++)
664 {
665 /* Build the final slot structure */
666 PciSlot.u.bits.FunctionNumber = k;
667
668 /* Read the configuration information */
669 HalpReadPCIConfig(BusHandler,
670 PciSlot,
671 PciData,
672 0,
674
675 /* Skip if this is an invalid function */
676 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
677
678 /* Make sure that this is a PCI bridge or a cardbus bridge */
679 if (!HalpIsBridgeDevice(PciData)) continue;
680
681 /* Not supported */
682 if (!WarningsGiven[2]++)
683 DPRINT1("Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail!\n");
684 continue;
685 }
686 }
687 }
688
689 /* If we exited the loop, then there's no bridge to worry about */
690 return FALSE;
691}
692
693CODE_SEG("INIT")
694VOID
695NTAPI
697{
698 ULONG i;
699 PBUS_HANDLER Bus, ParentBus;
700
701 /* Loop all buses */
702 for (i = 0; i < BusCount; i++)
703 {
704 /* Get PCI bus handler */
705 Bus = HalHandlerForBus(PCIBus, i);
706
707 /* Loop all parent buses */
708 ParentBus = Bus->ParentHandler;
709 while (ParentBus)
710 {
711 /* Should merge addresses */
712 if (!WarningsGiven[0]++)
713 DPRINT1("Found parent bus (indicating PCI Bridge). PCI devices may fail!\n");
714
715 /* Check the next parent */
716 ParentBus = ParentBus->ParentHandler;
717 }
718 }
719
720 /* Loop all buses again */
721 for (i = 0; i < BusCount; i++)
722 {
723 /* Get PCI bus handler */
724 Bus = HalHandlerForBus(PCIBus, i);
725
726 /* Check if this is a PCI 2.2 Bus with Subtractive Decode */
727 if (!((PPCIPBUSDATA)Bus->BusData)->Subtractive)
728 {
729 /* Loop all parent buses */
730 ParentBus = Bus->ParentHandler;
731 while (ParentBus)
732 {
733 /* But check only PCI parent buses specifically */
734 if (ParentBus->InterfaceType == PCIBus)
735 {
736 /* Should trim addresses */
737 if (!WarningsGiven[1]++)
738 DPRINT1("Found parent PCI Bus (indicating PCI-to-PCI Bridge). PCI devices may fail!\n");
739 }
740
741 /* Check the next parent */
742 ParentBus = ParentBus->ParentHandler;
743 }
744 }
745 }
746
747 /* Loop buses one last time */
748 for (i = 0; i < BusCount; i++)
749 {
750 /* Get the PCI bus handler */
751 Bus = HalHandlerForBus(PCIBus, i);
752
753 /* Sort and combine (trim) bus address range information */
754 DPRINT("Warning: Bus addresses not being optimized!\n");
755 }
756}
757
758CODE_SEG("INIT")
759VOID
760NTAPI
762{
763 if (!x) return;
764 DbgPrint(" [size=");
765 if (x < 1024)
766 {
767 DbgPrint("%d", (int) x);
768 }
769 else if (x < 1048576)
770 {
771 DbgPrint("%dK", (int)(x / 1024));
772 }
773 else if (x < 0x80000000)
774 {
775 DbgPrint("%dM", (int)(x / 1048576));
776 }
777 else
778 {
779 DbgPrint("%d", x);
780 }
781 DbgPrint("]");
782}
783
784/*
785 * These includes are required to define
786 * the ClassTable and VendorTable arrays.
787 */
788#define NEWLINE "\n" // "\r\n"
789#include "pci_classes.h"
790#include "pci_vendors.h"
791CODE_SEG("INIT")
792VOID
793NTAPI
795 IN PCI_SLOT_NUMBER PciSlot,
796 IN ULONG i,
797 IN ULONG j,
798 IN ULONG k,
799 IN PPCI_COMMON_CONFIG PciData)
800{
801 PCHAR p, ClassName, Boundary, SubClassName, VendorName, ProductName, SubVendorName;
802 UCHAR HeaderType;
804 CHAR LookupString[16] = "";
805 CHAR bSubClassName[64] = "Unknown";
806 CHAR bVendorName[64] = "";
807 CHAR bProductName[128] = "Unknown device";
808 CHAR bSubVendorName[128] = "Unknown";
809 ULONG Size, Mem, b;
810
811 HeaderType = (PciData->HeaderType & ~PCI_MULTIFUNCTION);
812
813 /* Isolate the class name */
814 sprintf(LookupString, "C %02x ", PciData->BaseClass);
815 ClassName = strstr((PCHAR)ClassTable, LookupString);
816 if (ClassName)
817 {
818 /* Isolate the subclass name */
819 ClassName += strlen("C 00 ");
820 Boundary = strstr(ClassName, NEWLINE "C ");
821 sprintf(LookupString, NEWLINE "\t%02x ", PciData->SubClass);
822 SubClassName = strstr(ClassName, LookupString);
823 if (Boundary && SubClassName > Boundary)
824 {
825 SubClassName = NULL;
826 }
827 if (!SubClassName)
828 {
829 SubClassName = ClassName;
830 }
831 else
832 {
833 SubClassName += strlen(NEWLINE "\t00 ");
834 }
835 /* Copy the subclass into our buffer */
836 p = strpbrk(SubClassName, NEWLINE);
837 Length = p - SubClassName;
838 Length = min(Length, sizeof(bSubClassName) - 1);
839 strncpy(bSubClassName, SubClassName, Length);
840 bSubClassName[Length] = '\0';
841 }
842
843 /* Isolate the vendor name */
844 sprintf(LookupString, NEWLINE "%04x ", PciData->VendorID);
845 VendorName = strstr((PCHAR)VendorTable, LookupString);
846 if (VendorName)
847 {
848 /* Copy the vendor name into our buffer */
849 VendorName += strlen(NEWLINE "0000 ");
851 Length = p - VendorName;
852 Length = min(Length, sizeof(bVendorName) - 1);
853 strncpy(bVendorName, VendorName, Length);
854 bVendorName[Length] = '\0';
855 p += strlen(NEWLINE);
856 while (*p == '\t' || *p == '#')
857 {
858 p = strpbrk(p, NEWLINE);
859 p += strlen(NEWLINE);
860 }
861 Boundary = p;
862
863 /* Isolate the product name */
864 sprintf(LookupString, "\t%04x ", PciData->DeviceID);
865 ProductName = strstr(VendorName, LookupString);
866 if (Boundary && ProductName >= Boundary)
867 {
868 ProductName = NULL;
869 }
870 if (ProductName)
871 {
872 /* Copy the product name into our buffer */
873 ProductName += strlen("\t0000 ");
874 p = strpbrk(ProductName, NEWLINE);
875 Length = p - ProductName;
876 Length = min(Length, sizeof(bProductName) - 1);
877 strncpy(bProductName, ProductName, Length);
878 bProductName[Length] = '\0';
879 p += strlen(NEWLINE);
880 while ((*p == '\t' && *(p + 1) == '\t') || *p == '#')
881 {
882 p = strpbrk(p, NEWLINE);
883 p += strlen(NEWLINE);
884 }
885 Boundary = p;
886 SubVendorName = NULL;
887
888 if (HeaderType == PCI_DEVICE_TYPE)
889 {
890 /* Isolate the subvendor and subsystem name */
891 sprintf(LookupString,
892 "\t\t%04x %04x ",
893 PciData->u.type0.SubVendorID,
894 PciData->u.type0.SubSystemID);
895 SubVendorName = strstr(ProductName, LookupString);
896 if (Boundary && SubVendorName >= Boundary)
897 {
898 SubVendorName = NULL;
899 }
900 }
901 if (SubVendorName)
902 {
903 /* Copy the subvendor name into our buffer */
904 SubVendorName += strlen("\t\t0000 0000 ");
905 p = strpbrk(SubVendorName, NEWLINE);
906 Length = p - SubVendorName;
907 Length = min(Length, sizeof(bSubVendorName) - 1);
908 strncpy(bSubVendorName, SubVendorName, Length);
909 bSubVendorName[Length] = '\0';
910 }
911 }
912 }
913
914 /* Print out the data */
915 DbgPrint("%02x:%02x.%x %s [%02x%02x]: %s %s [%04x:%04x] (rev %02x)\n",
916 i,
917 j,
918 k,
919 bSubClassName,
920 PciData->BaseClass,
921 PciData->SubClass,
922 bVendorName,
923 bProductName,
924 PciData->VendorID,
925 PciData->DeviceID,
926 PciData->RevisionID);
927
928 if (HeaderType == PCI_DEVICE_TYPE)
929 {
930 DbgPrint("\tSubsystem: %s [%04x:%04x]\n",
931 bSubVendorName,
932 PciData->u.type0.SubVendorID,
933 PciData->u.type0.SubSystemID);
934 }
935
936 /* Print out and decode flags */
937 DbgPrint("\tFlags:");
938 if (PciData->Command & PCI_ENABLE_BUS_MASTER) DbgPrint(" bus master,");
939 if (PciData->Status & PCI_STATUS_66MHZ_CAPABLE) DbgPrint(" 66MHz,");
940 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x000) DbgPrint(" fast devsel,");
941 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x200) DbgPrint(" medium devsel,");
942 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x400) DbgPrint(" slow devsel,");
943 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x600) DbgPrint(" unknown devsel,");
944 DbgPrint(" latency %d", PciData->LatencyTimer);
945 if (PciData->u.type0.InterruptPin != 0 &&
946 PciData->u.type0.InterruptLine != 0 &&
947 PciData->u.type0.InterruptLine != 0xFF) DbgPrint(", IRQ %02d", PciData->u.type0.InterruptLine);
948 else if (PciData->u.type0.InterruptPin != 0) DbgPrint(", IRQ assignment required");
949 DbgPrint("\n");
950
951 if (HeaderType == PCI_BRIDGE_TYPE)
952 {
953 DbgPrint("\tBridge:");
954 DbgPrint(" primary bus %d,", PciData->u.type1.PrimaryBus);
955 DbgPrint(" secondary bus %d,", PciData->u.type1.SecondaryBus);
956 DbgPrint(" subordinate bus %d,", PciData->u.type1.SubordinateBus);
957 DbgPrint(" secondary latency %d", PciData->u.type1.SecondaryLatency);
958 DbgPrint("\n");
959 }
960
961 /* Scan addresses */
962 Size = 0;
963 for (b = 0; b < (HeaderType == PCI_DEVICE_TYPE ? PCI_TYPE0_ADDRESSES : PCI_TYPE1_ADDRESSES); b++)
964 {
965 /* Check for a BAR */
966 if (HeaderType != PCI_CARDBUS_BRIDGE_TYPE)
967 Mem = PciData->u.type0.BaseAddresses[b];
968 else
969 Mem = 0;
970 if (Mem)
971 {
972 ULONG PciBar = 0xFFFFFFFF;
973
974 HalpWritePCIConfig(BusHandler,
975 PciSlot,
976 &PciBar,
977 FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[b]),
978 sizeof(ULONG));
979 HalpReadPCIConfig(BusHandler,
980 PciSlot,
981 &PciBar,
982 FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[b]),
983 sizeof(ULONG));
984 HalpWritePCIConfig(BusHandler,
985 PciSlot,
986 &Mem,
987 FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[b]),
988 sizeof(ULONG));
989
990 /* Decode the address type */
991 if (PciBar & PCI_ADDRESS_IO_SPACE)
992 {
993 /* Guess the size */
994 Size = 1 << 2;
995 while (!(PciBar & Size) && (Size)) Size <<= 1;
996
997 /* Print it out */
998 DbgPrint("\tI/O ports at %04lx", Mem & PCI_ADDRESS_IO_ADDRESS_MASK);
999 ShowSize(Size);
1000 }
1001 else
1002 {
1003 /* Guess the size */
1004 Size = 1 << 4;
1005 while (!(PciBar & Size) && (Size)) Size <<= 1;
1006
1007 /* Print it out */
1008 DbgPrint("\tMemory at %08lx (%d-bit, %sprefetchable)",
1010 (Mem & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_32BIT ? 32 : 64,
1011 (Mem & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? "" : "non-");
1012 ShowSize(Size);
1013 }
1014 DbgPrint("\n");
1015 }
1016 }
1017}
1018#endif
1019
1020CODE_SEG("INIT")
1021VOID
1022NTAPI
1024{
1025#ifndef _MINIHAL_
1026 PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
1027 UCHAR PciType;
1028 PCI_SLOT_NUMBER PciSlot;
1029 ULONG i, j, k;
1030 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
1031 PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
1032 PBUS_HANDLER BusHandler;
1034 BOOLEAN ExtendedAddressDecoding = FALSE;
1036
1037 /* Query registry information */
1038 PciRegistryInfo = HalpQueryPciRegistryInfo();
1039 if (!PciRegistryInfo) return;
1040
1041 /* Initialize the PCI configuration lock */
1043
1044 /* Get the type and free the info structure */
1045 PciType = PciRegistryInfo->HardwareMechanism & 0xF;
1046
1047 /* Check if this is a type 2 PCI bus with at least one bus */
1048 if ((PciRegistryInfo->NoBuses) && (PciType == 2))
1049 {
1050 /* Setup the PCI slot */
1051 PciSlot.u.bits.Reserved = 0;
1052 PciSlot.u.bits.FunctionNumber = 0;
1053
1054 /* Loop all slots */
1055 for (i = 0; i < 32; i++)
1056 {
1057 /* Try to setup a Type 2 PCI slot */
1058 PciType = 2;
1059 BusHandler = HalpAllocateAndInitPciBusHandler(2, 0, TRUE);
1060 if (!BusHandler) break;
1061
1062 /* Now check if it's valid */
1063 if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
1064
1065 /* Heh, the BIOS lied... try Type 1 */
1066 PciType = 1;
1067 BusHandler = HalpAllocateAndInitPciBusHandler(1, 0, TRUE);
1068 if (!BusHandler) break;
1069
1070 /* Now check if it's valid */
1071 if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
1072
1073 /* Keep trying */
1074 PciType = 2;
1075 }
1076
1077 /* Now allocate the correct kind of handler */
1079 }
1080
1081 /* Okay, now loop all PCI bridges */
1082 do
1083 {
1084 /* Loop all PCI buses */
1085 for (i = 0; i < PciRegistryInfo->NoBuses; i++)
1086 {
1087 /* Check if we have a handler for it */
1088 if (!HalHandlerForBus(PCIBus, i))
1089 {
1090 /* Allocate it */
1092 }
1093 }
1094 /* Go to the next bridge */
1095 } while (HalpGetPciBridgeConfig(PciType, &PciRegistryInfo->NoBuses));
1096
1097 /* Now build correct address range informaiton */
1098 HalpFixupPciSupportedRanges(PciRegistryInfo->NoBuses);
1099
1100 /* Loop every bus */
1101 DbgPrint("\n====== PCI BUS HARDWARE DETECTION =======\n\n");
1102 PciSlot.u.bits.Reserved = 0;
1103 for (i = 0; i < PciRegistryInfo->NoBuses; i++)
1104 {
1105 /* Get the bus handler */
1106 BusHandler = HalHandlerForBus(PCIBus, i);
1107
1108 /* Loop every device */
1109 for (j = 0; j < 32; j++)
1110 {
1111 /* Loop every function */
1112 PciSlot.u.bits.DeviceNumber = j;
1113 for (k = 0; k < 8; k++)
1114 {
1115 /* Build the final slot structure */
1116 PciSlot.u.bits.FunctionNumber = k;
1117
1118 /* Read the configuration information */
1119 HalpReadPCIConfig(BusHandler,
1120 PciSlot,
1121 PciData,
1122 0,
1124
1125 /* Skip if this is an invalid function */
1126 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
1127
1128 /* Print out the entry */
1129 HalpDebugPciDumpBus(BusHandler, PciSlot, i, j, k, PciData);
1130
1131 /* Check if this is a Cardbus bridge */
1133 {
1134 /* Not supported */
1135 DbgPrint("\tDevice is a PCI Cardbus Bridge. It will not work!\n");
1136 continue;
1137 }
1138
1139 /* Check if this is a PCI device */
1141 {
1142 /* Check if it has an interrupt pin and line registered */
1143 if ((PciData->u.type1.InterruptPin) &&
1144 (PciData->u.type1.InterruptLine))
1145 {
1146 /* Check if this interrupt line is connected to the bus */
1147 if (PciData->u.type1.InterruptLine < 16)
1148 {
1149 /* Is this an IDE device? */
1150 if (!HalpIsIdeDevice(PciData))
1151 {
1152 /* We'll mask out this interrupt then */
1153 DbgPrint("\tDevice is using IRQ %d! ISA Cards using that IRQ may fail!\n",
1154 PciData->u.type1.InterruptLine);
1155 HalpPciIrqMask |= (1 << PciData->u.type1.InterruptLine);
1156 }
1157 }
1158 }
1159 }
1160
1161 /* Check for broken Intel chips */
1162 if (PciData->VendorID == 0x8086)
1163 {
1164 /* Check for broken 82830 PCI controller */
1165 if ((PciData->DeviceID == 0x04A3) &&
1166 (PciData->RevisionID < 0x11))
1167 {
1168 /* Skip */
1169 DbgPrint("\tDevice is a broken Intel 82430 PCI Controller. It will not work!\n\n");
1170 continue;
1171 }
1172
1173 /* Check for broken 82378 PCI-to-ISA Bridge */
1174 if ((PciData->DeviceID == 0x0484) &&
1175 (PciData->RevisionID <= 3))
1176 {
1177 /* Skip */
1178 DbgPrint("\tDevice is a broken Intel 82378 PCI-to-ISA Bridge. It will not work!\n\n");
1179 continue;
1180 }
1181
1182 /* Check for broken 82450 PCI Bridge */
1183 if ((PciData->DeviceID == 0x84C4) &&
1184 (PciData->RevisionID <= 4))
1185 {
1186 DbgPrint("\tDevice is a Intel Orion 82450 PCI Bridge. It will not work!\n\n");
1187 continue;
1188 }
1189 }
1190
1191 /* Do we know this card? */
1192 if (!ExtendedAddressDecoding)
1193 {
1194 /* Check for it */
1195 if (HalpIsRecognizedCard(PciRegistryInfo,
1196 PciData,
1198 {
1199 /* We'll do chipset checks later */
1200 DbgPrint("\tDevice has Extended Address Decoding. It may fail to work on older BIOSes!\n");
1201 ExtendedAddressDecoding = TRUE;
1202 }
1203 }
1204
1205 /* Now check the registry for chipset hacks */
1206 Status = HalpGetChipHacks(PciData->VendorID,
1207 PciData->DeviceID,
1208 PciData->RevisionID,
1209 &HackFlags);
1210 if (NT_SUCCESS(Status))
1211 {
1212 /* Check for broken ACPI routing */
1214 {
1215 DbgPrint("This chipset has broken ACPI IRQ Routing! Be aware!\n\n");
1216 continue;
1217 }
1218
1219 /* Check for broken ACPI timer */
1221 {
1222 DbgPrint("This chipset has a broken ACPI timer! Be aware!\n\n");
1223 continue;
1224 }
1225
1226 /* Check for hibernate-disable */
1228 {
1229 DbgPrint("This chipset has a broken PCI device which is incompatible with hibernation. Be aware!\n\n");
1230 continue;
1231 }
1232
1233 /* Check for USB controllers that generate SMIs */
1235 {
1236 DbgPrint("This chipset has a USB controller which generates SMIs. ReactOS will likely fail to boot!\n\n");
1237 continue;
1238 }
1239 }
1240
1241 /* Terminate the entry */
1242 DbgPrint("\n");
1243 }
1244 }
1245 }
1246
1247 /* Initialize NMI Crash Flag */
1249
1250 /* Free the registry data */
1251 ExFreePoolWithTag(PciRegistryInfo, TAG_HAL);
1252
1253 /* Tell PnP if this hard supports correct decoding */
1254 HalpMarkChipsetDecode(ExtendedAddressDecoding);
1255 DbgPrint("====== PCI BUS DETECTION COMPLETE =======\n\n");
1256#endif
1257}
1258
1259#ifndef _MINIHAL_
1260CODE_SEG("INIT")
1261VOID
1262NTAPI
1264{
1265 /* Register the HAL Bus Handler support */
1267}
1268
1269CODE_SEG("INIT")
1270VOID
1271NTAPI
1273{
1274 /* Register PCI Device Functions */
1277
1278 /* Register memory functions */
1279#ifndef _MINIHAL_
1280#if (NTDDI_VERSION >= NTDDI_VISTA)
1283#else
1286#endif
1287#endif
1288
1289 /* Register ACPI stub */
1291}
1292#endif // _MINIHAL_
1293
1295NTAPI
1304{
1307 PAGED_CODE();
1308 DPRINT1("Slot assignment for %d on bus %u\n", BusType, BusNumber);
1309
1310 /* Find the handler */
1312 if (!Handler) return STATUS_NOT_FOUND;
1313
1314 /* Do the assignment */
1315 Status = Handler->AssignSlotResources(Handler,
1316 Handler,
1321 SlotNumber,
1323
1324 /* Dereference the handler and return */
1326 return Status;
1327}
1328
1329BOOLEAN
1330NTAPI
1335 IN BOOLEAN NextBus)
1336{
1337 PHAL_BUS_HANDLER BusHandler;
1339 PLIST_ENTRY NextEntry;
1340
1341 /* Make sure we have a context */
1342 if (!Context)
1343 return FALSE;
1344
1345 /* If we have data in the context, then this shouldn't be a new lookup */
1346 if ((*Context != 0) && (NextBus != FALSE))
1347 return FALSE;
1348
1349 /* Find the bus handler */
1351 if (!Handler)
1352 return FALSE;
1353
1354 /* Check if this is an ongoing lookup */
1355 if (NextBus)
1356 {
1357 /* Get the HAL bus handler */
1359 NextEntry = &BusHandler->AllHandlers;
1360
1361 /* Get the next one if we were already with one */
1362 if (*Context)
1363 NextEntry = NextEntry->Flink;
1364
1365 /* Start scanning */
1366 while (TRUE)
1367 {
1368 /* Check if this is the last one */
1369 if (NextEntry == &HalpAllBusHandlers)
1370 {
1371 /* Quit */
1372 *Context = 1;
1373 return FALSE;
1374 }
1375
1376 /* Call this translator */
1377 BusHandler = CONTAINING_RECORD(NextEntry, HAL_BUS_HANDLER, AllHandlers);
1379 BusHandler->Handler.BusNumber,
1380 BusAddress,
1383 {
1384 break;
1385 }
1386
1387 /* Try the next one */
1388 NextEntry = NextEntry->Flink;
1389 }
1390
1391 /* If we made it, we're done */
1392 *Context = (ULONG_PTR)&BusHandler->Handler;
1393 return TRUE;
1394 }
1395
1396 /* Try the first one through */
1397 if (!HalTranslateBusAddress(Handler->InterfaceType,
1398 Handler->BusNumber,
1399 BusAddress,
1402 {
1403 return FALSE;
1404 }
1405
1406 /* Remember for next time */
1408 return TRUE;
1409}
1410
1411BOOLEAN
1412NTAPI
1418{
1421
1422 /* Find the handler */
1424 if (!(Handler) || !(Handler->TranslateBusAddress))
1425 {
1426 DPRINT1("No translator Interface: %x, Bus: %x, Handler: %p, BusAddress: %x!\n", InterfaceType, BusNumber, Handler, BusAddress);
1427 return FALSE;
1428 }
1429
1430 /* Do the assignment */
1431 Status = Handler->TranslateBusAddress(Handler,
1432 Handler,
1433 BusAddress,
1436
1437 /* Dereference the handler and return */
1439 return Status;
1440}
1441
1442/* PUBLIC FUNCTIONS **********************************************************/
1443
1444#ifndef _MINIHAL_
1445/*
1446 * @implemented
1447 */
1449NTAPI
1451{
1453 ULONG Status;
1454 PAGED_CODE();
1455
1456 /* Find the handler */
1457 Handler = HalReferenceHandlerForBus((*ResourceList)->InterfaceType,
1458 (*ResourceList)->BusNumber);
1459 if (!Handler) return STATUS_SUCCESS;
1460
1461 /* Do the assignment */
1462 Status = Handler->AdjustResourceList(Handler,
1463 Handler,
1464 ResourceList);
1465
1466 /* Dereference the handler and return */
1468 return Status;
1469}
1470#endif // _MINIHAL_
1471
1472/*
1473 * @implemented
1474 */
1476NTAPI
1485{
1486 PAGED_CODE();
1487
1488 /* Check the bus type */
1489 if (BusType != PCIBus)
1490 {
1491 /* Call our internal handler */
1496 BusType,
1497 BusNumber,
1498 SlotNumber,
1500 }
1501 else
1502 {
1503 /* Call the PCI registered function */
1508 PCIBus,
1509 BusNumber,
1510 SlotNumber,
1512 }
1513}
1514
1515#ifndef _MINIHAL_
1516/*
1517 * @implemented
1518 */
1519ULONG
1520NTAPI
1524 IN PVOID Buffer,
1525 IN ULONG Length)
1526{
1527 /* Call the extended function */
1528 return HalGetBusDataByOffset(BusDataType,
1529 BusNumber,
1530 SlotNumber,
1531 Buffer,
1532 0,
1533 Length);
1534}
1535#endif // _MINIHAL_
1536
1537/*
1538 * @implemented
1539 */
1540ULONG
1541NTAPI
1545 IN PVOID Buffer,
1546 IN ULONG Offset,
1547 IN ULONG Length)
1548{
1550 ULONG Status;
1551
1552 /* Find the handler */
1554 if (!Handler) return 0;
1555
1556 /* Do the assignment */
1557 Status = Handler->GetBusData(Handler,
1558 Handler,
1559 SlotNumber,
1560 Buffer,
1561 Offset,
1562 Length);
1563
1564 /* Dereference the handler and return */
1566 return Status;
1567}
1568
1569#ifndef _MINIHAL_
1570/*
1571 * @implemented
1572 */
1573ULONG
1574NTAPI
1579 OUT PKIRQL Irql,
1581{
1583 ULONG Vector;
1584 PAGED_CODE();
1585
1586 /* Defaults */
1587 *Irql = 0;
1588 *Affinity = 0;
1589
1590 /* Find the handler */
1592 if (!Handler) return 0;
1593
1594 /* Do the assignment */
1595 Vector = Handler->GetInterruptVector(Handler,
1596 Handler,
1599 Irql,
1600 Affinity);
1603 {
1604 DPRINT1("Returning IRQL %lx, Vector %lx for Level/Vector: %lx/%lx\n",
1606 DPRINT1("Old HAL would've returned IRQL %lx and Vector %lx\n",
1609 }
1610
1611 /* Dereference the handler and return */
1613 return Vector;
1614}
1615
1616/*
1617 * @implemented
1618 */
1619ULONG
1620NTAPI
1624 IN PVOID Buffer,
1625 IN ULONG Length)
1626{
1627 /* Call the extended function */
1628 return HalSetBusDataByOffset(BusDataType,
1629 BusNumber,
1630 SlotNumber,
1631 Buffer,
1632 0,
1633 Length);
1634}
1635
1636/*
1637 * @implemented
1638 */
1639ULONG
1640NTAPI
1644 IN PVOID Buffer,
1645 IN ULONG Offset,
1646 IN ULONG Length)
1647{
1649 ULONG Status;
1650
1651 /* Find the handler */
1653 if (!Handler) return 0;
1654
1655 /* Do the assignment */
1656 Status = Handler->SetBusData(Handler,
1657 Handler,
1658 SlotNumber,
1659 Buffer,
1660 Offset,
1661 Length);
1662
1663 /* Dereference the handler and return */
1665 return Status;
1666}
1667#endif // _MINIHAL_
1668
1669/*
1670 * @implemented
1671 */
1672BOOLEAN
1673NTAPI
1679{
1680 /* Look as the bus type */
1681 if (InterfaceType == PCIBus)
1682 {
1683 /* Call the PCI registered function */
1685 BusNumber,
1686 BusAddress,
1689 }
1690 else
1691 {
1692 /* Call the bus handler */
1694 BusNumber,
1695 BusAddress,
1698 }
1699}
1700
1701/* EOF */
#define PAGED_CODE()
#define CODE_SEG(...)
static const char VendorName[]
Definition: ParaNdis-Oid.c:36
unsigned char BOOLEAN
char * strstr(char *String1, char *String2)
Definition: utclib.c:653
ACPI_SIZE strlen(const char *String)
Definition: utclib.c:269
char * strncpy(char *DstString, const char *SrcString, ACPI_SIZE Count)
Definition: utclib.c:427
char * strpbrk(const char *String, const char *Delimiters)
Definition: utclib.c:302
ACPI_PHYSICAL_ADDRESS ACPI_SIZE BOOLEAN Warn UINT32 *TableIdx UINT32 ACPI_TABLE_HEADER *OutTableHeader ACPI_TABLE_HEADER **OutTable ACPI_HANDLE UINT32 ACPI_WALK_CALLBACK ACPI_WALK_CALLBACK void void **ReturnValue UINT32 ACPI_BUFFER *RetPathPtr ACPI_OBJECT_HANDLER Handler
Definition: acpixf.h:672
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
KAFFINITY * PKAFFINITY
Definition: basetsd.h:195
#define PCI_TYPE1_DATA_PORT
Definition: hardware.h:34
#define PCI_TYPE1_ADDRESS_PORT
Definition: hardware.h:33
PBUS_HANDLER FASTCALL HaliReferenceHandlerForConfigSpace(IN BUS_DATA_TYPE ConfigType, IN ULONG BusNumber)
Definition: bushndlr.c:221
ULONG NTAPI HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: pcibus.c:658
NTSTATUS NTAPI HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName OPTIONAL, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject OPTIONAL, IN ULONG Slot, IN OUT PCM_RESOURCE_LIST *pAllocatedResources)
Definition: pcibus.c:798
VOID NTAPI HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciData)
Definition: pcibus.c:680
#define PCI_TYPE2_ADDRESS_BASE
Definition: bus.h:172
#define PCI_TYPE2_CSE_PORT
Definition: bus.h:170
ULONG NTAPI HalpcGetCmosData(_In_ PBUS_HANDLER BusHandler, _In_ PBUS_HANDLER RootHandler, _In_ ULONG SlotNumber, _Out_writes_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
Definition: cmosbus.c:16
BOOLEAN NTAPI HalpTranslateIsaBusAddress(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: isabus.c:21
VOID NTAPI HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciNewData, IN PPCI_COMMON_CONFIG PciOldData)
Definition: pcibus.c:690
NTSTATUS NTAPI HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList)
Definition: pcibus.c:757
NTSTATUS NTAPI HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER PciSlot, OUT PSUPPORTED_RANGE *Range)
Definition: pcibus.c:702
PCI_CONFIG_HANDLER PCIConfigHandler
Definition: pcibus.c:23
VOID NTAPI HalpWritePCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:283
ULONG NTAPI HalpcSetCmosData(_In_ PBUS_HANDLER BusHandler, _In_ PBUS_HANDLER RootHandler, _In_ ULONG SlotNumber, _In_reads_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
Definition: cmosbus.c:38
PCI_CONFIG_HANDLER PCIConfigHandlerType1
Definition: pcibus.c:35
VOID NTAPI HalpReadPCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:257
VOID NTAPI HalpInitBusHandler(VOID)
Definition: bushndlr.c:444
PBUS_HANDLER NTAPI HalpContextToBusHandler(IN ULONG_PTR ContextValue)
Definition: bushndlr.c:230
PPCI_REGISTRY_INFO_INTERNAL NTAPI HalpQueryPciRegistryInfo(VOID)
Definition: pcibus.c:957
ULONG NTAPI HalpNoBusData(_In_ PBUS_HANDLER BusHandler, _In_ PBUS_HANDLER RootHandler, _In_ ULONG SlotNumber, _In_ PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
Handler for buses without configuration space.
Definition: bushndlr.c:111
PCI_CONFIG_HANDLER PCIConfigHandlerType2
Definition: pcibus.c:57
ULONG NTAPI HalpGetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootBusHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:507
BOOLEAN NTAPI HalpTranslateSystemBusAddress(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: sysbus.c:21
ULONG NTAPI HalpGetSystemInterruptVector(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: sysbus.c:115
ULONG HalpBusType
Definition: pcibus.c:18
LIST_ENTRY HalpAllBusHandlers
Definition: bushndlr.c:19
#define PCI_TYPE2_FORWARD_PORT
Definition: bus.h:171
ULONG NTAPI HalpSetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootBusHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:587
struct _PCIPBUSDATA * PPCIPBUSDATA
NTSTATUS NTAPI HalAdjustResourceList(IN PIO_RESOURCE_REQUIREMENTS_LIST *ResourceList)
Definition: bussupp.c:1450
BOOLEAN NTAPI HalpIsIdeDevice(IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:575
ULONG NTAPI HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bussupp.c:1641
BOOLEAN NTAPI HalpGetPciBridgeConfig(IN ULONG PciType, IN PUCHAR BusCount)
Definition: bussupp.c:642
KSPIN_LOCK HalpPCIConfigLock
Definition: pcibus.c:22
VOID NTAPI HalpRegisterKdSupportFunctions(VOID)
Definition: bussupp.c:1272
ULONG HalpPciIrqMask
Definition: bussupp.c:104
BOOLEAN NTAPI HalpIsValidPCIDevice(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot)
Definition: bussupp.c:368
VOID NTAPI HalpInitializePciBus(VOID)
Definition: bussupp.c:1023
BOOLEAN NTAPI HalpIsRecognizedCard(IN PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo, IN PPCI_COMMON_CONFIG PciData, IN ULONG Flags)
Definition: bussupp.c:494
BOOLEAN NTAPI HalpIsBridgeDevice(IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:628
NTSTATUS NTAPI HalpMarkChipsetDecode(IN BOOLEAN OverrideEnable)
VOID NTAPI HalpRegisterInternalBusHandlers(VOID)
Definition: bussupp.c:159
static BOOLEAN WarningsGiven[5]
Definition: bussupp.c:425
VOID NTAPI HalpDebugPciDumpBus(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER PciSlot, IN ULONG i, IN ULONG j, IN ULONG k, IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:794
NTSTATUS NTAPI HalpAssignSlotResources(IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject, IN INTERFACE_TYPE BusType, IN ULONG BusNumber, IN ULONG SlotNumber, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: bussupp.c:1296
VOID NTAPI HalpInitBusHandlers(VOID)
Definition: bussupp.c:1263
NTSTATUS NTAPI HalAssignSlotResources(IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject, IN INTERFACE_TYPE BusType, IN ULONG BusNumber, IN ULONG SlotNumber, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: bussupp.c:1477
#define NEWLINE
Definition: bussupp.c:788
VOID NTAPI ShowSize(IN ULONG Size)
PBUS_HANDLER NTAPI HalpAllocateAndInitPciBusHandler(IN ULONG PciType, IN ULONG BusNo, IN BOOLEAN TestAllocation)
Definition: bussupp.c:283
PBUS_HANDLER NTAPI HalpAllocateBusHandler(IN INTERFACE_TYPE InterfaceType, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN INTERFACE_TYPE ParentBusInterfaceType, IN ULONG ParentBusNumber, IN ULONG BusSpecificData)
Definition: bussupp.c:110
NTSTATUS NTAPI HalpGetChipHacks(IN USHORT VendorId, IN USHORT DeviceId, IN UCHAR RevisionId, IN PULONG HackFlags)
Definition: bussupp.c:430
BOOLEAN NTAPI HaliFindBusAddressTranslation(IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress, IN OUT PULONG_PTR Context, IN BOOLEAN NextBus)
Definition: bussupp.c:1331
BOOLEAN NTAPI HalTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bussupp.c:1674
BOOLEAN NTAPI HaliTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bussupp.c:1413
VOID NTAPI HalpFixupPciSupportedRanges(IN ULONG BusCount)
Definition: bussupp.c:696
ULONG NTAPI HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bussupp.c:1542
ULONG NTAPI HalGetInterruptVector(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: bussupp.c:1575
ULONG NTAPI HalGetBusData(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
Definition: bussupp.c:1521
ULONG NTAPI HalSetBusData(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
Definition: bussupp.c:1621
_In_ ULONG_PTR HackFlags
Definition: cdrom.h:983
Definition: bufpool.h:45
IN PUNICODE_STRING IN POBJECT_ATTRIBUTES ObjectAttributes
Definition: conport.c:36
_Out_ PKIRQL Irql
Definition: csq.h:179
#define NULL
Definition: types.h:112
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:32
#define swprintf
Definition: precomp.h:40
#define ULONG_PTR
Definition: config.h:101
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
ULONG KSPIN_LOCK
Definition: env_spec_w32.h:72
KIRQL * PKIRQL
Definition: env_spec_w32.h:592
#define KeInitializeSpinLock(sl)
Definition: env_spec_w32.h:604
ULONG Handle
Definition: gdb_input.c:15
Status
Definition: gdiplustypes.h:25
GLint GLint GLint GLint GLint x
Definition: gl.h:1548
GLboolean GLboolean GLboolean b
Definition: glext.h:6204
GLfloat GLfloat p
Definition: glext.h:8902
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble * u
Definition: glfuncs.h:240
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
#define DbgPrint
Definition: hal.h:12
PVOID NTAPI HalpMapPhysicalMemory64Vista(IN PHYSICAL_ADDRESS PhysicalAddress, IN PFN_COUNT PageCount, IN BOOLEAN FlushCurrentTLB)
Definition: memory.c:156
VOID NTAPI HalpUnmapVirtualAddress(IN PVOID VirtualAddress, IN PFN_COUNT PageCount)
Definition: memory.c:148
VOID NTAPI HalpUnmapVirtualAddressVista(IN PVOID VirtualAddress, IN PFN_COUNT PageCount, IN BOOLEAN FlushCurrentTLB)
Definition: memory.c:227
PVOID NTAPI HalpMapPhysicalMemory64(IN PHYSICAL_ADDRESS PhysicalAddress, IN PFN_COUNT PageCount)
Definition: memory.c:140
VOID NTAPI HalpCheckPowerButton(VOID)
Definition: misc.c:146
NTSTATUS NTAPI HalpOpenRegistryKey(IN PHANDLE KeyHandle, IN HANDLE RootKey, IN PUNICODE_STRING KeyName, IN ACCESS_MASK DesiredAccess, IN BOOLEAN Create)
Definition: misc.c:104
VOID NTAPI HalpGetNMICrashFlag(VOID)
Definition: usage.c:595
#define TAG_HAL
Definition: hal.h:61
#define VECTOR2IRQL(vector)
Definition: halirq.h:26
#define IRQ2VECTOR(irq)
Definition: halirq.h:27
#define HALP_CHECK_CARD_REVISION_ID
Definition: halp.h:169
#define HALP_CARD_FEATURE_FULL_DECODE
Definition: halp.h:164
#define HALP_HACK_FLAGS(x)
Definition: halp.h:159
#define HALP_CHECK_CARD_SUBVENDOR_ID
Definition: halp.h:170
#define HALP_CHECK_CARD_SUBSYSTEM_ID
Definition: halp.h:171
#define HALP_REVISION_FROM_HACK_FLAGS(x)
Definition: halp.h:157
#define HALP_REVISION_HACK_FLAGS(x)
Definition: halp.h:158
@ InterfaceTypeUndefined
Definition: hwresource.cpp:136
@ PCIBus
Definition: hwresource.cpp:142
@ Internal
Definition: hwresource.cpp:137
@ Isa
Definition: hwresource.cpp:138
enum _INTERFACE_TYPE INTERFACE_TYPE
#define OBJ_CASE_INSENSITIVE
Definition: winternl.h:228
NTSYSAPI void WINAPI RtlInitializeBitMap(PRTL_BITMAP, PULONG, ULONG)
NTSTATUS NTAPI HalpReleasePciDeviceForDebugging(_Inout_ PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Releases the PCI device MMIO mappings previously allocated with HalpSetupPciDeviceForDebugging().
Definition: kdpci.c:421
NTSTATUS NTAPI HalpSetupPciDeviceForDebugging(_In_opt_ PVOID LoaderBlock, _Inout_ PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Finds and fully initializes the PCI device associated with the supplied debug device descriptor.
Definition: kdpci.c:483
#define b
Definition: ke_i.h:79
if(dx< 0)
Definition: linetemp.h:194
#define ASSERT(a)
Definition: mode.c:44
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1109
#define sprintf(buf, format,...)
Definition: sprintf.c:55
#define InitializeObjectAttributes(p, n, a, r, s)
Definition: reg.c:106
#define min(a, b)
Definition: monoChain.cc:55
int k
Definition: mpi.c:3369
_Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PCM_RESOURCE_LIST * AllocatedResources
Definition: ndis.h:4643
_Must_inspect_result_ _Out_ PNDIS_STATUS _In_ NDIS_HANDLE _In_ ULONG _Out_ PNDIS_STRING _Out_ PNDIS_HANDLE KeyHandle
Definition: ndis.h:4715
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1161
#define MACHINE_TYPE_ISA
Definition: ketypes.h:113
#define KdUnmapVirtualAddress
Definition: halfuncs.h:53
#define HalHandlerForBus
Definition: halfuncs.h:35
#define HalRegisterBusHandler
Definition: halfuncs.h:38
#define KdMapPhysicalMemory64
Definition: halfuncs.h:52
#define KdSetupPciDeviceForDebugging
Definition: halfuncs.h:47
#define KdReleasePciDeviceforDebugging
Definition: halfuncs.h:48
#define KdCheckPowerButton
Definition: halfuncs.h:50
#define HalPciTranslateBusAddress
Definition: halfuncs.h:41
#define HalPciAssignSlotResources
Definition: halfuncs.h:42
#define HAL_PCI_CHIP_HACK_BROKEN_ACPI_TIMER
Definition: haltypes.h:263
#define HAL_PCI_CHIP_HACK_DISABLE_ACPI_IRQ_ROUTING
Definition: haltypes.h:265
#define HAL_PCI_CHIP_HACK_USB_SMI_DISABLE
Definition: haltypes.h:266
#define HAL_PCI_CHIP_HACK_DISABLE_HIBERNATE
Definition: haltypes.h:264
#define HAL_SUPPORTED_RANGE_VERSION
Definition: haltypes.h:203
NTSYSAPI NTSTATUS NTAPI ZwClose(_In_ HANDLE Handle)
@ KeyValuePartialInformation
Definition: nt_native.h:1182
#define KEY_ALL_ACCESS
Definition: nt_native.h:1041
#define KEY_READ
Definition: nt_native.h:1023
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:102
_In_opt_ PENTER_STATE_SYSTEM_HANDLER _In_opt_ PVOID _In_ LONG _In_opt_ LONG volatile * Number
Definition: ntpoapi.h:207
#define L(x)
Definition: ntvdm.h:50
unsigned short USHORT
Definition: pedump.c:61
static WCHAR Address[46]
Definition: ping.c:68
#define REG_DWORD
Definition: sdbapi.c:596
@ Cmos
Definition: miniport.h:89
@ ConfigurationSpaceUndefined
Definition: miniport.h:88
@ PCIConfiguration
Definition: miniport.h:93
enum _BUS_DATA_TYPE BUS_DATA_TYPE
#define STATUS_SUCCESS
Definition: shellext.h:65
#define STATUS_NOT_FOUND
Definition: shellext.h:72
#define DPRINT
Definition: sndvol32.h:73
PGETINTERRUPTVECTOR GetInterruptVector
Definition: haltypes.h:248
PGETSETBUSDATA GetBusData
Definition: haltypes.h:244
ULONG BusNumber
Definition: haltypes.h:237
PSUPPORTED_RANGES BusAddresses
Definition: haltypes.h:242
PTRANSLATEBUSADDRESS TranslateBusAddress
Definition: haltypes.h:249
PASSIGNSLOTRESOURCES AssignSlotResources
Definition: haltypes.h:247
struct _BUS_HANDLER * ParentHandler
Definition: haltypes.h:239
PGETSETBUSDATA SetBusData
Definition: haltypes.h:245
INTERFACE_TYPE InterfaceType
Definition: haltypes.h:235
PADJUSTRESOURCELIST AdjustResourceList
Definition: haltypes.h:246
PVOID BusData
Definition: haltypes.h:240
BUS_HANDLER Handler
Definition: bus.h:271
LIST_ENTRY AllHandlers
Definition: bus.h:269
Definition: typedefs.h:120
struct _LIST_ENTRY * Flink
Definition: typedefs.h:121
PciReadWriteConfig WriteConfig
Definition: iotypes.h:5282
PciLine2Pin Line2Pin
Definition: iotypes.h:5284
ULONG Tag
Definition: iotypes.h:5279
PciReadWriteConfig ReadConfig
Definition: iotypes.h:5281
ULONG Version
Definition: iotypes.h:5280
PciPin2Line Pin2Line
Definition: iotypes.h:5283
ULONG ConfiguredBits[PCI_MAX_DEVICES *PCI_MAX_FUNCTION/32]
Definition: bus.h:118
struct _PCIPBUSDATA::@1483::@1485 Type2
PciIrqRange GetIrqRange
Definition: bus.h:111
PCIBUSDATA CommonData
Definition: bus.h:95
union _PCIPBUSDATA::@1483 Config
ULONG MaxDevice
Definition: bus.h:110
RTL_BITMAP DeviceConfigured
Definition: bus.h:117
struct _PCIPBUSDATA::@1483::@1484 Type1
USHORT VendorID
Definition: pci.h:119
USHORT SubsystemID
Definition: pci.h:123
USHORT DeviceID
Definition: pci.h:120
USHORT SubsystemVendorID
Definition: pci.h:122
USHORT RevisionID
Definition: pci.h:121
struct _PCI_SLOT_NUMBER::@4028::@4029 bits
union _PCI_SLOT_NUMBER::@4028 u
SUPPORTED_RANGE Dma
Definition: haltypes.h:225
SUPPORTED_RANGE PrefetchMemory
Definition: haltypes.h:223
SUPPORTED_RANGE Memory
Definition: haltypes.h:221
SUPPORTED_RANGE IO
Definition: haltypes.h:219
ULONG SystemAddressSpace
Definition: haltypes.h:207
LONGLONG Base
Definition: haltypes.h:209
LONGLONG Limit
Definition: haltypes.h:210
uint32_t * PULONG_PTR
Definition: typedefs.h:65
uint32_t * PULONG
Definition: typedefs.h:59
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
#define NTAPI
Definition: typedefs.h:36
void * PVOID
Definition: typedefs.h:50
#define RtlCopyMemory(Destination, Source, Length)
Definition: typedefs.h:263
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
uint32_t ULONG_PTR
Definition: typedefs.h:65
#define IN
Definition: typedefs.h:39
#define CONTAINING_RECORD(address, type, field)
Definition: typedefs.h:260
unsigned char * PUCHAR
Definition: typedefs.h:53
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
_In_ PDEVICE_OBJECT DeviceObject
Definition: wdfdevice.h:2055
_Must_inspect_result_ _In_ WDFDEVICE _In_ DEVICE_REGISTRY_PROPERTY _In_ ULONG _Out_ PULONG ResultLength
Definition: wdfdevice.h:3776
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_DEVICE_PROPERTY_DATA _In_ DEVPROPTYPE _In_ ULONG Size
Definition: wdfdevice.h:4533
_Must_inspect_result_ _In_ WDFDEVICE _In_ PCUNICODE_STRING KeyName
Definition: wdfdevice.h:2699
_Must_inspect_result_ _In_ PDRIVER_OBJECT _In_ PCUNICODE_STRING RegistryPath
Definition: wdfdriver.h:215
_Must_inspect_result_ _In_ PDRIVER_OBJECT DriverObject
Definition: wdfdriver.h:213
_Must_inspect_result_ _In_ WDFDEVICE _In_ LPCGUID InterfaceType
Definition: wdffdo.h:463
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING ValueName
Definition: wdfregistry.h:243
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
Definition: wdfresource.h:309
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
Definition: wdfresource.h:68
_Must_inspect_result_ _In_ ULONG Flags
Definition: wsk.h:170
_In_opt_ PUNICODE_STRING DriverClassName
Definition: halfuncs.h:156
_In_ ULONG _In_ ULONG BusInterruptLevel
Definition: halfuncs.h:171
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE _In_ ULONG BusNumber
Definition: halfuncs.h:160
_In_ ULONG _In_ ULONG _In_ ULONG BusInterruptVector
Definition: halfuncs.h:172
_In_ ULONG _In_ ULONG _In_ ULONG _Out_ PKIRQL _Out_ PKAFFINITY Affinity
Definition: halfuncs.h:174
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE BusType
Definition: halfuncs.h:159
#define HalDereferenceBusHandler
Definition: haltypes.h:299
#define HalReferenceHandlerForBus
Definition: haltypes.h:297
_In_ ULONG _In_ PHYSICAL_ADDRESS BusAddress
Definition: iofuncs.h:2273
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG _Out_ PPHYSICAL_ADDRESS TranslatedAddress
Definition: iofuncs.h:2275
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG AddressSpace
Definition: iofuncs.h:2274
#define PCI_TYPE_64BIT
Definition: iotypes.h:4239
#define PCI_INVALID_VENDORID
Definition: iotypes.h:3601
#define PCI_TYPE_32BIT
Definition: iotypes.h:4237
#define PCI_ADDRESS_IO_ADDRESS_MASK
Definition: iotypes.h:4233
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3618
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3500
#define PCI_DATA_TAG
Definition: iotypes.h:5275
#define PCI_SUBCLASS_BR_PCI_TO_PCI
Definition: iotypes.h:4165
#define PCI_CLASS_MASS_STORAGE_CTLR
Definition: iotypes.h:4104
struct _PCI_COMMON_CONFIG * PPCI_COMMON_CONFIG
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:4230
#define PCI_CONFIGURATION_TYPE(PciData)
Definition: iotypes.h:3609
#define PCI_SUBCLASS_MSC_IDE_CTLR
Definition: iotypes.h:4129
#define PCI_TYPE1_ADDRESSES
Definition: iotypes.h:3501
#define PCI_STATUS_66MHZ_CAPABLE
Definition: iotypes.h:3631
#define PCI_MAX_FUNCTION
Definition: iotypes.h:3599
#define PCI_BRIDGE_TYPE
Definition: iotypes.h:3606
#define PCI_STATUS_DEVSEL
Definition: iotypes.h:3635
#define PCI_ADDRESS_MEMORY_ADDRESS_MASK
Definition: iotypes.h:4234
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3594
#define PCI_CLASS_BRIDGE_DEV
Definition: iotypes.h:4109
#define PCI_SUBCLASS_BR_CARDBUS
Definition: iotypes.h:4168
#define PCI_ADDRESS_MEMORY_PREFETCHABLE
Definition: iotypes.h:4232
#define PCI_MAX_DEVICES
Definition: iotypes.h:3598
#define PCI_ADDRESS_MEMORY_TYPE_MASK
Definition: iotypes.h:4231
#define PCI_DATA_VERSION
Definition: iotypes.h:5276
#define PCI_DEVICE_TYPE
Definition: iotypes.h:3605
#define PCI_CARDBUS_BRIDGE_TYPE
Definition: iotypes.h:3607
@ NonPagedPoolMustSucceed
Definition: ketypes.h:880
unsigned char UCHAR
Definition: xmlstorage.h:181
__wchar_t WCHAR
Definition: xmlstorage.h:180
char CHAR
Definition: xmlstorage.h:175