ReactOS 0.4.17-dev-1190-g4c812f4
bussupp.c
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1/*
2 * PROJECT: ReactOS HAL
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: hal/halx86/legacy/bussupp.c
5 * PURPOSE: HAL Legacy Bus Support Code
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9/* INCLUDES *******************************************************************/
10
11#include <hal.h>
12#define NDEBUG
13#include <debug.h>
14
15/* GLOBALS ********************************************************************/
16
17#ifndef _MINIHAL_
20#endif
21
22/* PRIVATE FUNCTIONS **********************************************************/
23
24#ifndef _MINIHAL_
28 IN BUS_DATA_TYPE BusDataType,
30 IN INTERFACE_TYPE ParentBusInterfaceType,
31 IN ULONG ParentBusNumber,
32 IN ULONG BusSpecificData)
33{
34 PBUS_HANDLER Bus;
35
36 /* Register the bus handler */
38 BusDataType,
40 ParentBusInterfaceType,
41 ParentBusNumber,
42 BusSpecificData,
43 NULL,
44 &Bus);
45 if (!Bus)
46 {
47 return NULL;
48 }
49
50 /* Check for a valid interface */
52 {
53 /* Allocate address ranges and zero them out */
55 sizeof(SUPPORTED_RANGES),
56 TAG_HAL);
58
59 /* Build the data structure */
61 Bus->BusAddresses->Dma.Limit = 7;
62 Bus->BusAddresses->Memory.Limit = 0xFFFFFFFF;
63 Bus->BusAddresses->IO.Limit = 0xFFFF;
66 }
67
68 /* Return the bus address */
69 return Bus;
70}
71
72CODE_SEG("INIT")
73static VOID
76{
77 PBUS_HANDLER Bus;
78
79 /* Only do processor 1 */
80 if (KeGetCurrentPrcb()->Number) return;
81
82 /* Register root support */
84
85 /* Allocate the system bus */
88 0,
90 0,
91 0);
92 if (Bus)
93 {
94 /* Set it up */
97 }
98
99 /* Allocate the CMOS bus */
101 Cmos,
102 0,
104 0,
105 0);
106 if (Bus)
107 {
108 /* Set it up */
111 }
112
113 /* Allocate the CMOS bus */
115 Cmos,
116 1,
118 0,
119 0);
120 if (Bus)
121 {
122 /* Set it up */
125 }
126
127 /* Allocate ISA bus */
130 0,
131 Internal,
132 0,
133 0);
134 if (Bus)
135 {
136 /* Set it up */
138 Bus->BusAddresses->Memory.Limit = 0xFFFFFF;
140 }
141
142 /* No support for EISA or MCA */
144}
145
146CODE_SEG("INIT")
147static NTSTATUS
148NTAPI
150{
152 UNICODE_STRING KeyString;
153 ULONG Data = OverrideEnable;
155
156 /* Open CCS key */
157 RtlInitUnicodeString(&KeyString,
158 L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET");
160 if (NT_SUCCESS(Status))
161 {
162 /* Open PNP Bios key */
163 RtlInitUnicodeString(&KeyString, L"Control\\Biosinfo\\PNPBios");
165 Handle,
166 &KeyString,
168 TRUE);
169
170 /* Close root key */
172
173 /* Check if PNP BIOS key exists */
174 if (NT_SUCCESS(Status))
175 {
176 /* Set the override value */
177 RtlInitUnicodeString(&KeyString, L"FullDecodeChipsetOverride");
178 Status = ZwSetValueKey(KeyHandle,
179 &KeyString,
180 0,
181 REG_DWORD,
182 &Data,
183 sizeof(Data));
184
185 /* Close subkey */
187 }
188 }
189
190 /* Return status */
191 return Status;
192}
193
194CODE_SEG("INIT")
195static PBUS_HANDLER
196NTAPI
198 IN ULONG BusNo,
199 IN BOOLEAN TestAllocation)
200{
201 PBUS_HANDLER Bus;
202 PPCIPBUSDATA BusData;
203
204 /* Allocate the bus handler */
207 BusNo,
208 Internal,
209 0,
210 sizeof(PCIPBUSDATA));
211
212 /* Set it up */
218 Bus->BusAddresses->Dma.Limit = 0;
219
220 /* Get our custom bus data */
221 BusData = (PPCIPBUSDATA)Bus->BusData;
222
223 /* Setup custom bus data */
224 BusData->CommonData.Tag = PCI_DATA_TAG;
230 BusData->MaxDevice = PCI_MAX_DEVICES;
232
233 /* Initialize the bitmap */
234 RtlInitializeBitMap(&BusData->DeviceConfigured, BusData->ConfiguredBits, 256);
235
236 /* Check the type of PCI bus */
237 switch (PciType)
238 {
239 /* Type 1 PCI Bus */
240 case 1:
241
242 /* Copy the Type 1 handler data */
245 sizeof(PCIConfigHandler));
246
247 /* Set correct I/O Ports */
248 BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
249 BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
250 break;
251
252 /* Type 2 PCI Bus */
253 case 2:
254
255 /* Copy the Type 1 handler data */
258 sizeof (PCIConfigHandler));
259
260 /* Set correct I/O Ports */
261 BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
262 BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
263 BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
264
265 /* Only 16 devices supported, not 32 */
266 BusData->MaxDevice = 16;
267 break;
268
269 default:
270
271 /* Invalid type */
272 DbgPrint("HAL: Unknown PCI type\n");
273 }
274
275 /* Return the bus handler */
276 return Bus;
277}
278
279CODE_SEG("INIT")
280static BOOLEAN
281NTAPI
283 IN PCI_SLOT_NUMBER Slot)
284{
285 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
286 PPCI_COMMON_CONFIG PciHeader = (PVOID)DataBuffer;
287 ULONG i;
289
290 /* Read the PCI header */
291 HalpReadPCIConfig(BusHandler, Slot, PciHeader, 0, PCI_COMMON_HDR_LENGTH);
292
293 /* Make sure it's a valid device */
294 if ((PciHeader->VendorID == PCI_INVALID_VENDORID) ||
296 {
297 /* Bail out */
298 return FALSE;
299 }
300
301 /* Make sure interrupt numbers make sense */
302 if (((PciHeader->u.type0.InterruptPin) &&
303 (PciHeader->u.type0.InterruptPin > 4)) ||
304 (PciHeader->u.type0.InterruptLine & 0x70))
305 {
306 /* Bail out */
307 return FALSE;
308 }
309
310 /* Now scan PCI BARs */
311 for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
312 {
313 /* Check what kind of address it is */
314 Address = PciHeader->u.type0.BaseAddresses[i];
316 {
317 /* Highest I/O port is 65535 */
318 if (Address > 0xFFFF) return FALSE;
319 }
320 else
321 {
322 /* MMIO should be higher than 0x80000 */
323 if ((Address > 0xF) && (Address < 0x80000)) return FALSE;
324 }
325
326 /* Is this a 64-bit address? */
327 if (!(Address & PCI_ADDRESS_IO_SPACE) &&
329 {
330 /* Check the next-next entry, since this one 64-bits wide */
331 i++;
332 }
333 }
334
335 /* Header, interrupt and address data all make sense */
336 return TRUE;
337}
338
339CODE_SEG("INIT")
340static NTSTATUS
341NTAPI
343 IN USHORT DeviceId,
344 IN UCHAR RevisionId,
346{
351 WCHAR Buffer[32];
354
355 /* Setup the object attributes for the key */
357 L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET\\"
358 L"Control\\HAL");
360 &KeyName,
362 NULL,
363 NULL);
364
365 /* Open the key */
366 Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
367 if (!NT_SUCCESS(Status)) return Status;
368
369 /* Query value */
370 _swprintf(Buffer, L"%04X%04X", VendorId, DeviceId);
372 Status = ZwQueryValueKey(KeyHandle,
373 &ValueName,
375 &PartialInfo,
376 sizeof(PartialInfo),
377 &ResultLength);
378 if (NT_SUCCESS(Status))
379 {
380 /* Return the flags */
381 DbgPrint("\tFound HackFlags for your chipset\n");
382 *HackFlags = *(PULONG)PartialInfo.Data;
383 DbgPrint("\t\tHack Flags: %lx (Hack Revision: %lx-Your Revision: %lx)\n",
385
386 /* Does it apply to this revision? */
387 if ((RevisionId) && (RevisionId >= (HALP_REVISION_FROM_HACK_FLAGS(*HackFlags))))
388 {
389 /* Read the revision flags */
391 }
392
393 /* Throw out revision data */
395 if (!*HackFlags) DbgPrint("\tNo HackFlags for your chipset's revision!\n");
396 }
397
398 /* Close the handle and return */
400 return Status;
401}
402
403CODE_SEG("INIT")
404static BOOLEAN
405NTAPI
407 IN PPCI_COMMON_CONFIG PciData,
408 IN ULONG Flags)
409{
410 ULONG ElementCount, i;
411 PPCI_CARD_DESCRIPTOR CardDescriptor;
412
413 /* How many PCI Cards that we know about? */
414 ElementCount = PciRegistryInfo->ElementCount;
415 if (!ElementCount) return FALSE;
416
417 /* Loop all descriptors */
418 CardDescriptor = &PciRegistryInfo->CardList[0];
419 for (i = 0; i < ElementCount; i++, CardDescriptor++)
420 {
421 /* Check for flag match */
422 if (CardDescriptor->Flags != Flags) continue;
423
424 /* Check for VID-PID match */
425 if ((CardDescriptor->VendorID != PciData->VendorID) ||
426 (CardDescriptor->DeviceID != PciData->DeviceID))
427 {
428 /* Skip */
429 continue;
430 }
431
432 /* Check for revision match, if requested */
433 if ((CardDescriptor->Flags & HALP_CHECK_CARD_REVISION_ID) &&
434 (CardDescriptor->RevisionID != PciData->RevisionID))
435 {
436 /* Skip */
437 continue;
438 }
439
440 /* Check what kind of device this is */
441 switch (PCI_CONFIGURATION_TYPE(PciData))
442 {
443 /* CardBus bridge */
445
446 /* This means the real device header is in the device-specific data */
447 PciData = (PPCI_COMMON_CONFIG)PciData->DeviceSpecific;
448
449 /* Normal PCI device */
450 case PCI_DEVICE_TYPE:
451
452 /* Check for subvendor match, if requested */
453 if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBVENDOR_ID) &&
454 (CardDescriptor->SubsystemVendorID != PciData->u.type0.SubVendorID))
455 {
456 /* Skip */
457 continue;
458 }
459
460 /* Check for subsystem match, if requested */
461 if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBSYSTEM_ID) &&
462 (CardDescriptor->SubsystemID != PciData->u.type0.SubSystemID))
463 {
464 /* Skip */
465 continue;
466 }
467
468 /* You made it! */
469 return TRUE;
470
471 /* PCI bridge -- don't bother */
472 case PCI_BRIDGE_TYPE:
473 default:
474
475 /* Recognize it */
476 return TRUE;
477 }
478 }
479
480 /* This means the card isn't recognized */
481 return FALSE;
482}
483
484CODE_SEG("INIT")
485static BOOLEAN
486NTAPI
488{
489 /* Simple test first */
490 if ((PciData->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
491 (PciData->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
492 {
493 /* The device is nice enough to admit it */
494 return TRUE;
495 }
496
497 /* Symphony 82C101 */
498 if (PciData->VendorID == 0x1C1C) return TRUE;
499
500 /* ALi MS4803 or M5219 */
501 if ((PciData->VendorID == 0x10B9) &&
502 ((PciData->DeviceID == 0x5215) || (PciData->DeviceID == 0x5219)))
503 {
504 return TRUE;
505 }
506
507 /* Appian Technology */
508 if ((PciData->VendorID == 0x1097) && (PciData->DeviceID == 0x38)) return TRUE;
509
510 /* Compaq Triflex Dual EIDE Controller */
511 if ((PciData->VendorID == 0xE11) && (PciData->DeviceID == 0xAE33)) return TRUE;
512
513 /* Micron PC Tech RZ1000 */
514 if ((PciData->VendorID == 0x1042) && (PciData->DeviceID == 0x1000)) return TRUE;
515
516 /* SiS 85C601 or 5513 [IDE] */
517 if ((PciData->VendorID == 0x1039) &&
518 ((PciData->DeviceID == 0x601) || (PciData->DeviceID == 0x5513)))
519 {
520 return TRUE;
521 }
522
523 /* Symphony Labs W83769F */
524 if ((PciData->VendorID == 0x10AD) &&
525 ((PciData->DeviceID == 0x1) || (PciData->DeviceID == 0x150)))
526 {
527 return TRUE;
528 }
529
530 /* UMC UM8673F */
531 if ((PciData->VendorID == 0x1060) && (PciData->DeviceID == 0x101)) return TRUE;
532
533 /* You've survived */
534 return FALSE;
535}
536
537CODE_SEG("INIT")
538static BOOLEAN
539NTAPI
541{
542 /* Either this is a PCI-to-PCI bridge, or a CardBus bridge */
543 return (((PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE) &&
544 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
545 (PciData->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI)) ||
547 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
548 (PciData->SubClass == PCI_SUBCLASS_BR_CARDBUS)));
549}
550
552
553CODE_SEG("INIT")
554static BOOLEAN
555NTAPI
557 _In_ ULONG PciType,
558 _Inout_ PUSHORT BusCount)
559{
561 ULONG i, j, k;
562 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
563 PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
564 PBUS_HANDLER BusHandler;
565
566 /* Loop PCI buses */
567 PciSlot.u.bits.Reserved = 0;
568 for (i = 0; i < *BusCount; i++)
569 {
570 /* Get the bus handler */
571 BusHandler = HalHandlerForBus(PCIBus, i);
572
573 /* Loop every device */
574 for (j = 0; j < PCI_MAX_DEVICES; j++)
575 {
576 /* Loop every function */
577 PciSlot.u.bits.DeviceNumber = j;
578 for (k = 0; k < PCI_MAX_FUNCTION; k++)
579 {
580 /* Build the final slot structure */
581 PciSlot.u.bits.FunctionNumber = k;
582
583 /* Read the configuration information */
584 HalpReadPCIConfig(BusHandler,
585 PciSlot,
586 PciData,
587 0,
589
590 /* Skip if this is an invalid function */
591 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
592
593 /* Make sure that this is a PCI bridge or a CardBus bridge */
594 if (!HalpIsBridgeDevice(PciData)) continue;
595
596 // FIXME TODO: Implement
597 if (!WarningsGiven[2]++)
598 DPRINT1("UNIMPLEMENTED: Your machine has a PCI-to-PCI or CardBus bridge. PCI devices may fail!\n");
599 continue;
600 }
601 }
602 }
603
604 /* If we exited the loop, then there's no bridge to worry about */
605 return FALSE;
606}
607
608CODE_SEG("INIT")
609static VOID
610NTAPI
612 _In_ USHORT BusCount)
613{
614 ULONG i;
615 PBUS_HANDLER Bus, ParentBus;
616
617 /* Loop all buses */
618 for (i = 0; i < BusCount; i++)
619 {
620 /* Get PCI bus handler */
621 Bus = HalHandlerForBus(PCIBus, i);
622
623 /* Loop all parent buses */
624 ParentBus = Bus->ParentHandler;
625 while (ParentBus)
626 {
627 // FIXME TODO: Should merge addresses
628 if (!WarningsGiven[0]++)
629 DPRINT1("UNIMPLEMENTED: Found parent bus (indicating PCI bridge). PCI devices may fail!\n");
630
631 /* Check the next parent */
632 ParentBus = ParentBus->ParentHandler;
633 }
634 }
635
636 /* Loop all buses again */
637 for (i = 0; i < BusCount; i++)
638 {
639 /* Get PCI bus handler */
640 Bus = HalHandlerForBus(PCIBus, i);
641
642 /* Check if this is a PCI 2.2 Bus with Subtractive Decode */
643 if (!((PPCIPBUSDATA)Bus->BusData)->Subtractive)
644 {
645 /* Loop all parent buses */
646 ParentBus = Bus->ParentHandler;
647 while (ParentBus)
648 {
649 /* But check only PCI parent buses specifically */
650 if (ParentBus->InterfaceType == PCIBus)
651 {
652 // FIXME TODO: Should trim addresses
653 if (!WarningsGiven[1]++)
654 DPRINT1("UNIMPLEMENTED: Found parent PCI bus (indicating PCI-to-PCI bridge). PCI devices may fail!\n");
655 }
656
657 /* Check the next parent */
658 ParentBus = ParentBus->ParentHandler;
659 }
660 }
661 }
662
663 /* Loop buses one last time */
664 for (i = 0; i < BusCount; i++)
665 {
666 /* Get the PCI bus handler */
667 Bus = HalHandlerForBus(PCIBus, i);
668
669 /* Sort and combine (trim) bus address range information */
670 // TODO: Implement
671 DPRINT("Warning: Bus addresses not being optimized!\n");
672 }
673}
674
675CODE_SEG("INIT")
676static VOID
678{
679 if (!x) return;
680 DbgPrint(" [size=");
681 if (x < 1024)
682 {
683 DbgPrint("%d", (int) x);
684 }
685 else if (x < 1048576)
686 {
687 DbgPrint("%dK", (int)(x / 1024));
688 }
689 else if (x < 0x80000000)
690 {
691 DbgPrint("%dM", (int)(x / 1048576));
692 }
693 else
694 {
695 DbgPrint("%d", x);
696 }
697 DbgPrint("]");
698}
699
700/*
701 * These includes are required to define
702 * the ClassTable and VendorTable arrays.
703 */
704#define NEWLINE "\n" // "\r\n"
705#include "pci_classes.h"
706#include "pci_vendors.h"
707CODE_SEG("INIT")
708VOID
709NTAPI
712 IN ULONG i,
713 IN ULONG j,
714 IN ULONG k,
715 IN PPCI_COMMON_CONFIG PciData)
716{
717 PCHAR p, ClassName, Boundary, SubClassName, VendorName, ProductName, SubVendorName;
718 UCHAR HeaderType;
720 CHAR LookupString[16] = "";
721 CHAR bSubClassName[64] = "Unknown";
722 CHAR bVendorName[64] = "";
723 CHAR bProductName[128] = "Unknown device";
724 CHAR bSubVendorName[128] = "Unknown";
725 ULONG Size, Mem, b;
726
727 HeaderType = PCI_CONFIGURATION_TYPE(PciData);
728
729 /* Isolate the class name */
730 sprintf(LookupString, "C %02x ", PciData->BaseClass);
731 ClassName = strstr((PCHAR)ClassTable, LookupString);
732 if (ClassName)
733 {
734 /* Isolate the subclass name */
735 ClassName += strlen("C 00 ");
736 Boundary = strstr(ClassName, NEWLINE "C ");
737 sprintf(LookupString, NEWLINE "\t%02x ", PciData->SubClass);
738 SubClassName = strstr(ClassName, LookupString);
739 if (Boundary && SubClassName > Boundary)
740 {
741 SubClassName = NULL;
742 }
743 if (!SubClassName)
744 {
745 SubClassName = ClassName;
746 }
747 else
748 {
749 SubClassName += strlen(NEWLINE "\t00 ");
750 }
751 /* Copy the subclass into our buffer */
752 p = strpbrk(SubClassName, NEWLINE);
753 Length = p - SubClassName;
754 Length = min(Length, sizeof(bSubClassName) - 1);
755 strncpy(bSubClassName, SubClassName, Length);
756 bSubClassName[Length] = '\0';
757 }
758
759 /* Isolate the vendor name */
760 sprintf(LookupString, NEWLINE "%04x ", PciData->VendorID);
761 VendorName = strstr((PCHAR)VendorTable, LookupString);
762 if (VendorName)
763 {
764 /* Copy the vendor name into our buffer */
765 VendorName += strlen(NEWLINE "0000 ");
767 Length = p - VendorName;
768 Length = min(Length, sizeof(bVendorName) - 1);
769 strncpy(bVendorName, VendorName, Length);
770 bVendorName[Length] = '\0';
771 p += strlen(NEWLINE);
772 while (*p == '\t' || *p == '#')
773 {
774 p = strpbrk(p, NEWLINE);
775 p += strlen(NEWLINE);
776 }
777 Boundary = p;
778
779 /* Isolate the product name */
780 sprintf(LookupString, "\t%04x ", PciData->DeviceID);
781 ProductName = strstr(VendorName, LookupString);
782 if (Boundary && ProductName >= Boundary)
783 {
784 ProductName = NULL;
785 }
786 if (ProductName)
787 {
788 /* Copy the product name into our buffer */
789 ProductName += strlen("\t0000 ");
790 p = strpbrk(ProductName, NEWLINE);
791 Length = p - ProductName;
792 Length = min(Length, sizeof(bProductName) - 1);
793 strncpy(bProductName, ProductName, Length);
794 bProductName[Length] = '\0';
795 p += strlen(NEWLINE);
796 while ((*p == '\t' && *(p + 1) == '\t') || *p == '#')
797 {
798 p = strpbrk(p, NEWLINE);
799 p += strlen(NEWLINE);
800 }
801 Boundary = p;
802 SubVendorName = NULL;
803
804 if (HeaderType == PCI_DEVICE_TYPE)
805 {
806 /* Isolate the subvendor and subsystem name */
807 sprintf(LookupString,
808 "\t\t%04x %04x ",
809 PciData->u.type0.SubVendorID,
810 PciData->u.type0.SubSystemID);
811 SubVendorName = strstr(ProductName, LookupString);
812 if (Boundary && SubVendorName >= Boundary)
813 {
814 SubVendorName = NULL;
815 }
816 }
817 if (SubVendorName)
818 {
819 /* Copy the subvendor name into our buffer */
820 SubVendorName += strlen("\t\t0000 0000 ");
821 p = strpbrk(SubVendorName, NEWLINE);
822 Length = p - SubVendorName;
823 Length = min(Length, sizeof(bSubVendorName) - 1);
824 strncpy(bSubVendorName, SubVendorName, Length);
825 bSubVendorName[Length] = '\0';
826 }
827 }
828 }
829
830 /* Print out the data */
831 DbgPrint("%02x:%02x.%x %s [%02x%02x]: %s %s [%04x:%04x] (rev %02x)\n",
832 i,
833 j,
834 k,
835 bSubClassName,
836 PciData->BaseClass,
837 PciData->SubClass,
838 bVendorName,
839 bProductName,
840 PciData->VendorID,
841 PciData->DeviceID,
842 PciData->RevisionID);
843
844 if (HeaderType == PCI_DEVICE_TYPE)
845 {
846 DbgPrint("\tSubsystem: %s [%04x:%04x]\n",
847 bSubVendorName,
848 PciData->u.type0.SubVendorID,
849 PciData->u.type0.SubSystemID);
850 }
851
852 /* Print out and decode flags */
853 DbgPrint("\tFlags:");
854 if (PciData->Command & PCI_ENABLE_BUS_MASTER) DbgPrint(" bus master,");
855 if (PciData->Status & PCI_STATUS_66MHZ_CAPABLE) DbgPrint(" 66MHz,");
856 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x000) DbgPrint(" fast devsel,");
857 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x200) DbgPrint(" medium devsel,");
858 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x400) DbgPrint(" slow devsel,");
859 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x600) DbgPrint(" unknown devsel,");
860 DbgPrint(" latency %d", PciData->LatencyTimer);
861 if (PciData->u.type0.InterruptPin != 0 &&
862 PciData->u.type0.InterruptLine != 0 &&
863 PciData->u.type0.InterruptLine != 0xFF) DbgPrint(", IRQ %02d", PciData->u.type0.InterruptLine);
864 else if (PciData->u.type0.InterruptPin != 0) DbgPrint(", IRQ assignment required");
865 DbgPrint("\n");
866
867 if (HeaderType == PCI_BRIDGE_TYPE)
868 {
869 DbgPrint("\tBridge:");
870 DbgPrint(" primary bus %d,", PciData->u.type1.PrimaryBus);
871 DbgPrint(" secondary bus %d,", PciData->u.type1.SecondaryBus);
872 DbgPrint(" subordinate bus %d,", PciData->u.type1.SubordinateBus);
873 DbgPrint(" secondary latency %d", PciData->u.type1.SecondaryLatency);
874 DbgPrint("\n");
875 }
876
877 /* Scan addresses */
878 Size = 0;
879 for (b = 0; b < (HeaderType == PCI_DEVICE_TYPE ? PCI_TYPE0_ADDRESSES : PCI_TYPE1_ADDRESSES); b++)
880 {
881 /* Check for a BAR */
882 if (HeaderType != PCI_CARDBUS_BRIDGE_TYPE)
883 Mem = PciData->u.type0.BaseAddresses[b];
884 else
885 Mem = 0;
886 if (Mem)
887 {
888 ULONG PciBar = 0xFFFFFFFF;
889
890 HalpWritePCIConfig(BusHandler,
891 PciSlot,
892 &PciBar,
893 FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[b]),
894 sizeof(ULONG));
895 HalpReadPCIConfig(BusHandler,
896 PciSlot,
897 &PciBar,
898 FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[b]),
899 sizeof(ULONG));
900 HalpWritePCIConfig(BusHandler,
901 PciSlot,
902 &Mem,
903 FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[b]),
904 sizeof(ULONG));
905
906 /* Decode the address type */
907 if (PciBar & PCI_ADDRESS_IO_SPACE)
908 {
909 /* Guess the size */
910 Size = 1 << 2;
911 while (!(PciBar & Size) && (Size)) Size <<= 1;
912
913 /* Print it out */
914 DbgPrint("\tI/O ports at %04lx", Mem & PCI_ADDRESS_IO_ADDRESS_MASK);
915 ShowSize(Size);
916 }
917 else
918 {
919 /* Guess the size */
920 Size = 1 << 4;
921 while (!(PciBar & Size) && (Size)) Size <<= 1;
922
923 /* Print it out */
924 DbgPrint("\tMemory at %08lx (%d-bit, %sprefetchable)",
926 (Mem & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_32BIT ? 32 : 64,
927 (Mem & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? "" : "non-");
928 ShowSize(Size);
929 }
930 DbgPrint("\n");
931 }
932 }
933}
934#endif // !_MINIHAL_
935
936CODE_SEG("INIT")
937VOID
938NTAPI
940{
941#ifndef _MINIHAL_
942 PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
943 UCHAR PciType;
945 ULONG i, j, k;
946 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
947 PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
948 PBUS_HANDLER BusHandler;
950 BOOLEAN ExtendedAddressDecoding = FALSE;
952
953 /* Query registry information */
954 PciRegistryInfo = HalpQueryPciRegistryInfo();
955 if (!PciRegistryInfo) return;
956
957 /* Initialize the PCI configuration lock */
959
960 /* Get the type */
961 PciType = PciRegistryInfo->HardwareMechanism & 0xF;
962
963 /* Check if this is a type 2 PCI bus with at least one bus */
964 if (PciRegistryInfo->NoBuses && (PciType == 2))
965 {
966 /* Setup the PCI slot */
967 PciSlot.u.bits.Reserved = 0;
968 PciSlot.u.bits.FunctionNumber = 0;
969
970 /* Loop all slots */
971 for (i = 0; i < PCI_MAX_DEVICES; i++)
972 {
973 /* Try to setup a Type 2 PCI slot */
974 PciType = 2;
975 BusHandler = HalpAllocateAndInitPciBusHandler(2, 0, TRUE);
976 if (!BusHandler) break;
977
978 /* Now check if it's valid */
979 if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
980
981 /* Heh, the BIOS lied... try Type 1 */
982 PciType = 1;
983 BusHandler = HalpAllocateAndInitPciBusHandler(1, 0, TRUE);
984 if (!BusHandler) break;
985
986 /* Now check if it's valid */
987 if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
988
989 /* Keep trying */
990 PciType = 2;
991 }
992
993 /* Now allocate the correct kind of handler */
995 }
996
997 /* Okay, now loop all PCI bridges */
998 do
999 {
1000 /* Loop all PCI buses */
1001 for (i = 0; i < PciRegistryInfo->NoBuses; i++)
1002 {
1003 /* Check if we have a handler for it */
1004 if (!HalHandlerForBus(PCIBus, i))
1005 {
1006 /* Allocate it */
1008 }
1009 }
1010 /* Go to the next bridge */
1011 } while (HalpGetPciBridgeConfig(PciType, &PciRegistryInfo->NoBuses));
1012
1013 /* Now build correct address range information */
1014 HalpFixupPciSupportedRanges(PciRegistryInfo->NoBuses);
1015
1016 /* Loop every bus */
1017 DbgPrint("\n====== PCI BUS HARDWARE DETECTION =======\n\n");
1018 PciSlot.u.bits.Reserved = 0;
1019 for (i = 0; i < PciRegistryInfo->NoBuses; i++)
1020 {
1021 /* Get the bus handler */
1022 BusHandler = HalHandlerForBus(PCIBus, i);
1023
1024 /* Loop every device */
1025 for (j = 0; j < PCI_MAX_DEVICES; j++)
1026 {
1027 /* Loop every function */
1028 PciSlot.u.bits.DeviceNumber = j;
1029 for (k = 0; k < PCI_MAX_FUNCTION; k++)
1030 {
1031 /* Build the final slot structure */
1032 PciSlot.u.bits.FunctionNumber = k;
1033
1034 /* Read the configuration information */
1035 HalpReadPCIConfig(BusHandler,
1036 PciSlot,
1037 PciData,
1038 0,
1040
1041 /* Skip if this is an invalid function */
1042 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
1043
1044 /* Print out the entry */
1045 HalpDebugPciDumpBus(BusHandler, PciSlot, i, j, k, PciData);
1046
1047 /* Check if this is a CardBus bridge */
1049 {
1050 // FIXME TODO: Implement
1051 DbgPrint("\tDevice is a PCI CardBus bridge. It will not work!\n");
1052 continue;
1053 }
1054
1055 /* Check if this is a PCI device */
1057 {
1058 /* Check if it has an interrupt pin and line registered */
1059 if ((PciData->u.type1.InterruptPin) &&
1060 (PciData->u.type1.InterruptLine))
1061 {
1062 /* Check if this interrupt line is connected to the bus */
1063 if (PciData->u.type1.InterruptLine < 16)
1064 {
1065 /* Is this an IDE device? */
1066 if (!HalpIsIdeDevice(PciData))
1067 {
1068 /* We'll mask out this interrupt then */
1069 DbgPrint("\tDevice is using IRQ %d! ISA Cards using that IRQ may fail!\n",
1070 PciData->u.type1.InterruptLine);
1071 HalpPciIrqMask |= (1 << PciData->u.type1.InterruptLine);
1072 }
1073 }
1074 }
1075 }
1076
1077 /* Check for broken Intel chips */
1078 if (PciData->VendorID == 0x8086)
1079 {
1080 /* Check for broken 82830 PCI controller */
1081 if ((PciData->DeviceID == 0x04A3) &&
1082 (PciData->RevisionID < 0x11))
1083 {
1084 /* Skip */
1085 DbgPrint("\tDevice is a broken Intel 82430 PCI Controller. It will not work!\n\n");
1086 continue;
1087 }
1088
1089 /* Check for broken 82378 PCI-to-ISA bridge */
1090 if ((PciData->DeviceID == 0x0484) &&
1091 (PciData->RevisionID <= 3))
1092 {
1093 /* Skip */
1094 DbgPrint("\tDevice is a broken Intel 82378 PCI-to-ISA bridge. It will not work!\n\n");
1095 continue;
1096 }
1097
1098 /* Check for broken 82450 PCI bridge */
1099 if ((PciData->DeviceID == 0x84C4) &&
1100 (PciData->RevisionID <= 4))
1101 {
1102 DbgPrint("\tDevice is a Intel Orion 82450 PCI bridge. It will not work!\n\n");
1103 continue;
1104 }
1105 }
1106
1107 /* Do we know this card? */
1108 if (!ExtendedAddressDecoding)
1109 {
1110 /* Check for it */
1111 if (HalpIsRecognizedCard(PciRegistryInfo,
1112 PciData,
1114 {
1115 /* We'll do chipset checks later */
1116 DbgPrint("\tDevice has Extended Address Decoding. It may fail to work on older BIOSes!\n");
1117 ExtendedAddressDecoding = TRUE;
1118 }
1119 }
1120
1121 /* Now check the registry for chipset hacks */
1122 Status = HalpGetChipHacks(PciData->VendorID,
1123 PciData->DeviceID,
1124 PciData->RevisionID,
1125 &HackFlags);
1126 if (NT_SUCCESS(Status))
1127 {
1128 /* Check for broken ACPI routing */
1130 {
1131 DbgPrint("This chipset has broken ACPI IRQ Routing! Be aware!\n\n");
1132 continue;
1133 }
1134
1135 /* Check for broken ACPI timer */
1137 {
1138 DbgPrint("This chipset has a broken ACPI timer! Be aware!\n\n");
1139 continue;
1140 }
1141
1142 /* Check for hibernate-disable */
1144 {
1145 DbgPrint("This chipset has a broken PCI device which is incompatible with hibernation. Be aware!\n\n");
1146 continue;
1147 }
1148
1149 /* Check for USB controllers that generate SMIs */
1151 {
1152 DbgPrint("This chipset has a USB controller which generates SMIs. ReactOS will likely fail to boot!\n\n");
1153 continue;
1154 }
1155 }
1156
1157 /* Terminate the entry */
1158 DbgPrint("\n");
1159 }
1160 }
1161 }
1162
1163 /* Initialize NMI Crash Flag */
1165
1166 /* Free the registry data */
1167 ExFreePoolWithTag(PciRegistryInfo, TAG_HAL);
1168
1169 /* Tell PnP if this hard supports correct decoding */
1170 HalpMarkChipsetDecode(ExtendedAddressDecoding);
1171 DbgPrint("====== PCI BUS DETECTION COMPLETE =======\n\n");
1172#endif // !_MINIHAL_
1173}
1174
1175#ifndef _MINIHAL_
1176CODE_SEG("INIT")
1177VOID
1178NTAPI
1180{
1181 /* Register the HAL Bus Handler support */
1183}
1184
1185CODE_SEG("INIT")
1186VOID
1187NTAPI
1189{
1190 /* Register PCI Device Functions */
1193
1194 /* Register memory functions */
1195#if (NTDDI_VERSION >= NTDDI_VISTA)
1198#else
1201#endif
1202
1203 /* Register ACPI stub */
1205}
1206#endif // !_MINIHAL_
1207
1209NTAPI
1218{
1221 PAGED_CODE();
1222 DPRINT1("Slot assignment for %d on bus %u\n", BusType, BusNumber);
1223
1224 /* Find the handler */
1226 if (!Handler) return STATUS_NOT_FOUND;
1227
1228 /* Do the assignment */
1229 Status = Handler->AssignSlotResources(Handler,
1230 Handler,
1235 SlotNumber,
1237
1238 /* Dereference the handler and return */
1240 return Status;
1241}
1242
1243BOOLEAN
1244NTAPI
1249 IN BOOLEAN NextBus)
1250{
1251 PHAL_BUS_HANDLER BusHandler;
1253 PLIST_ENTRY NextEntry;
1254
1255 /* Make sure we have a context */
1256 if (!Context)
1257 return FALSE;
1258
1259 /* If we have data in the context, then this shouldn't be a new lookup */
1260 if ((*Context != 0) && (NextBus != FALSE))
1261 return FALSE;
1262
1263 /* Find the bus handler */
1265 if (!Handler)
1266 return FALSE;
1267
1268 /* Check if this is an ongoing lookup */
1269 if (NextBus)
1270 {
1271 /* Get the HAL bus handler */
1273 NextEntry = &BusHandler->AllHandlers;
1274
1275 /* Get the next one if we were already with one */
1276 if (*Context)
1277 NextEntry = NextEntry->Flink;
1278
1279 /* Start scanning */
1280 while (TRUE)
1281 {
1282 /* Check if this is the last one */
1283 if (NextEntry == &HalpAllBusHandlers)
1284 {
1285 /* Quit */
1286 *Context = 1;
1287 return FALSE;
1288 }
1289
1290 /* Call this translator */
1291 BusHandler = CONTAINING_RECORD(NextEntry, HAL_BUS_HANDLER, AllHandlers);
1293 BusHandler->Handler.BusNumber,
1294 BusAddress,
1297 {
1298 break;
1299 }
1300
1301 /* Try the next one */
1302 NextEntry = NextEntry->Flink;
1303 }
1304
1305 /* If we made it, we're done */
1306 *Context = (ULONG_PTR)&BusHandler->Handler;
1307 return TRUE;
1308 }
1309
1310 /* Try the first one through */
1311 if (!HalTranslateBusAddress(Handler->InterfaceType,
1312 Handler->BusNumber,
1313 BusAddress,
1316 {
1317 return FALSE;
1318 }
1319
1320 /* Remember for next time */
1322 return TRUE;
1323}
1324
1325BOOLEAN
1326NTAPI
1332{
1335
1336 /* Find the handler */
1338 if (!(Handler) || !(Handler->TranslateBusAddress))
1339 {
1340 DPRINT1("No translator Interface: %x, Bus: %x, Handler: %p, BusAddress: %x!\n", InterfaceType, BusNumber, Handler, BusAddress);
1341 return FALSE;
1342 }
1343
1344 /* Do the assignment */
1345 Status = Handler->TranslateBusAddress(Handler,
1346 Handler,
1347 BusAddress,
1350
1351 /* Dereference the handler and return */
1353 return Status;
1354}
1355
1356/* PUBLIC FUNCTIONS **********************************************************/
1357
1358#ifndef _MINIHAL_
1359/*
1360 * @implemented
1361 */
1363NTAPI
1365{
1367 ULONG Status;
1368 PAGED_CODE();
1369
1370 /* Find the handler */
1371 Handler = HalReferenceHandlerForBus((*ResourceList)->InterfaceType,
1372 (*ResourceList)->BusNumber);
1373 if (!Handler) return STATUS_SUCCESS;
1374
1375 /* Do the assignment */
1376 Status = Handler->AdjustResourceList(Handler,
1377 Handler,
1378 ResourceList);
1379
1380 /* Dereference the handler and return */
1382 return Status;
1383}
1384#endif // !_MINIHAL_
1385
1386/*
1387 * @implemented
1388 */
1390NTAPI
1399{
1400 PAGED_CODE();
1401
1402 /* Check the bus type */
1403 if (BusType != PCIBus)
1404 {
1405 /* Call our internal handler */
1410 BusType,
1411 BusNumber,
1412 SlotNumber,
1414 }
1415 else
1416 {
1417 /* Call the PCI registered function */
1422 PCIBus,
1423 BusNumber,
1424 SlotNumber,
1426 }
1427}
1428
1429#ifndef _MINIHAL_
1430/*
1431 * @implemented
1432 */
1433ULONG
1434NTAPI
1438 IN PVOID Buffer,
1439 IN ULONG Length)
1440{
1441 /* Call the extended function */
1442 return HalGetBusDataByOffset(BusDataType,
1443 BusNumber,
1444 SlotNumber,
1445 Buffer,
1446 0,
1447 Length);
1448}
1449#endif // !_MINIHAL_
1450
1451/*
1452 * @implemented
1453 */
1454ULONG
1455NTAPI
1459 IN PVOID Buffer,
1460 IN ULONG Offset,
1461 IN ULONG Length)
1462{
1464 ULONG Status;
1465
1466 /* Find the handler */
1468 if (!Handler) return 0;
1469
1470 /* Do the assignment */
1471 Status = Handler->GetBusData(Handler,
1472 Handler,
1473 SlotNumber,
1474 Buffer,
1475 Offset,
1476 Length);
1477
1478 /* Dereference the handler and return */
1480 return Status;
1481}
1482
1483#ifndef _MINIHAL_
1484/*
1485 * @implemented
1486 */
1487ULONG
1488NTAPI
1493 OUT PKIRQL Irql,
1495{
1497 ULONG Vector;
1498 PAGED_CODE();
1499
1500 /* Defaults */
1501 *Irql = 0;
1502 *Affinity = 0;
1503
1504 /* Find the handler */
1506 if (!Handler) return 0;
1507
1508 /* Do the assignment */
1509 Vector = Handler->GetInterruptVector(Handler,
1510 Handler,
1513 Irql,
1514 Affinity);
1517 {
1518 DPRINT1("Returning IRQL %lx, Vector %lx for Level/Vector: %lx/%lx\n",
1520 DPRINT1("Old HAL would've returned IRQL %lx and Vector %lx\n",
1523 }
1524
1525 /* Dereference the handler and return */
1527 return Vector;
1528}
1529
1530/*
1531 * @implemented
1532 */
1533ULONG
1534NTAPI
1538 IN PVOID Buffer,
1539 IN ULONG Length)
1540{
1541 /* Call the extended function */
1542 return HalSetBusDataByOffset(BusDataType,
1543 BusNumber,
1544 SlotNumber,
1545 Buffer,
1546 0,
1547 Length);
1548}
1549
1550/*
1551 * @implemented
1552 */
1553ULONG
1554NTAPI
1558 IN PVOID Buffer,
1559 IN ULONG Offset,
1560 IN ULONG Length)
1561{
1563 ULONG Status;
1564
1565 /* Find the handler */
1567 if (!Handler) return 0;
1568
1569 /* Do the assignment */
1570 Status = Handler->SetBusData(Handler,
1571 Handler,
1572 SlotNumber,
1573 Buffer,
1574 Offset,
1575 Length);
1576
1577 /* Dereference the handler and return */
1579 return Status;
1580}
1581#endif // !_MINIHAL_
1582
1583/*
1584 * @implemented
1585 */
1586BOOLEAN
1587NTAPI
1593{
1594 /* Look as the bus type */
1595 if (InterfaceType == PCIBus)
1596 {
1597 /* Call the PCI registered function */
1599 BusNumber,
1600 BusAddress,
1603 }
1604 else
1605 {
1606 /* Call the bus handler */
1608 BusNumber,
1609 BusAddress,
1612 }
1613}
1614
1615/* EOF */
#define PAGED_CODE()
#define CODE_SEG(...)
static const char VendorName[]
Definition: ParaNdis-Oid.c:36
ACPI_PHYSICAL_ADDRESS ACPI_SIZE BOOLEAN Warn UINT32 *TableIdx UINT32 ACPI_TABLE_HEADER *OutTableHeader ACPI_TABLE_HEADER **OutTable ACPI_HANDLE UINT32 ACPI_WALK_CALLBACK ACPI_WALK_CALLBACK void void **ReturnValue UINT32 ACPI_BUFFER *RetPathPtr ACPI_OBJECT_HANDLER Handler
Definition: acpixf.h:672
unsigned char BOOLEAN
Definition: actypes.h:127
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
KAFFINITY * PKAFFINITY
Definition: basetsd.h:189
#define PCI_TYPE1_DATA_PORT
Definition: hardware.h:45
#define PCI_TYPE1_ADDRESS_PORT
Definition: hardware.h:44
PBUS_HANDLER FASTCALL HaliReferenceHandlerForConfigSpace(IN BUS_DATA_TYPE ConfigType, IN ULONG BusNumber)
Definition: bushndlr.c:221
ULONG NTAPI HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: pcibus.c:658
NTSTATUS NTAPI HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName OPTIONAL, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject OPTIONAL, IN ULONG Slot, IN OUT PCM_RESOURCE_LIST *pAllocatedResources)
Definition: pcibus.c:798
VOID NTAPI HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciData)
Definition: pcibus.c:680
#define PCI_TYPE2_ADDRESS_BASE
Definition: bus.h:172
#define PCI_TYPE2_CSE_PORT
Definition: bus.h:170
const PCI_CONFIG_HANDLER PCIConfigHandlerType1
Definition: pcibus.c:35
ULONG NTAPI HalpcGetCmosData(_In_ PBUS_HANDLER BusHandler, _In_ PBUS_HANDLER RootHandler, _In_ ULONG SlotNumber, _Out_writes_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
Definition: cmosbus.c:16
BOOLEAN NTAPI HalpTranslateIsaBusAddress(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: isabus.c:21
VOID NTAPI HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciNewData, IN PPCI_COMMON_CONFIG PciOldData)
Definition: pcibus.c:690
NTSTATUS NTAPI HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList)
Definition: pcibus.c:757
NTSTATUS NTAPI HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER PciSlot, OUT PSUPPORTED_RANGE *Range)
Definition: pcibus.c:702
PCI_CONFIG_HANDLER PCIConfigHandler
Definition: pcibus.c:23
VOID NTAPI HalpWritePCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:283
ULONG NTAPI HalpcSetCmosData(_In_ PBUS_HANDLER BusHandler, _In_ PBUS_HANDLER RootHandler, _In_ ULONG SlotNumber, _In_reads_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
Definition: cmosbus.c:38
const PCI_CONFIG_HANDLER PCIConfigHandlerType2
Definition: pcibus.c:57
VOID NTAPI HalpReadPCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:257
VOID NTAPI HalpInitBusHandler(VOID)
Definition: bushndlr.c:444
PBUS_HANDLER NTAPI HalpContextToBusHandler(IN ULONG_PTR ContextValue)
Definition: bushndlr.c:230
PPCI_REGISTRY_INFO_INTERNAL NTAPI HalpQueryPciRegistryInfo(VOID)
Definition: pcibus.c:978
ULONG NTAPI HalpNoBusData(_In_ PBUS_HANDLER BusHandler, _In_ PBUS_HANDLER RootHandler, _In_ ULONG SlotNumber, _In_ PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
Handler for buses without configuration space.
Definition: bushndlr.c:111
ULONG NTAPI HalpGetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootBusHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:507
BOOLEAN NTAPI HalpTranslateSystemBusAddress(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: sysbus.c:21
ULONG NTAPI HalpGetSystemInterruptVector(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: sysbus.c:115
ULONG HalpBusType
Definition: pcibus.c:18
LIST_ENTRY HalpAllBusHandlers
Definition: bushndlr.c:19
#define PCI_TYPE2_FORWARD_PORT
Definition: bus.h:171
ULONG NTAPI HalpSetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootBusHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:587
struct _PCIPBUSDATA * PPCIPBUSDATA
static BOOLEAN NTAPI HalpIsValidPCIDevice(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot)
Definition: bussupp.c:282
static PBUS_HANDLER NTAPI HalpAllocateAndInitPciBusHandler(IN ULONG PciType, IN ULONG BusNo, IN BOOLEAN TestAllocation)
Definition: bussupp.c:197
NTSTATUS NTAPI HalAdjustResourceList(IN PIO_RESOURCE_REQUIREMENTS_LIST *ResourceList)
Definition: bussupp.c:1364
ULONG NTAPI HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bussupp.c:1555
static NTSTATUS NTAPI HalpGetChipHacks(IN USHORT VendorId, IN USHORT DeviceId, IN UCHAR RevisionId, IN PULONG HackFlags)
Definition: bussupp.c:342
KSPIN_LOCK HalpPCIConfigLock
Definition: pcibus.c:22
VOID NTAPI HalpRegisterKdSupportFunctions(VOID)
Definition: bussupp.c:1188
ULONG HalpPciIrqMask
Definition: bussupp.c:19
VOID NTAPI HalpInitializePciBus(VOID)
Definition: bussupp.c:939
static BOOLEAN NTAPI HalpGetPciBridgeConfig(_In_ ULONG PciType, _Inout_ PUSHORT BusCount)
Definition: bussupp.c:556
static BOOLEAN WarningsGiven[5]
Definition: bussupp.c:551
static BOOLEAN NTAPI HalpIsRecognizedCard(IN PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo, IN PPCI_COMMON_CONFIG PciData, IN ULONG Flags)
Definition: bussupp.c:406
VOID NTAPI HalpDebugPciDumpBus(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER PciSlot, IN ULONG i, IN ULONG j, IN ULONG k, IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:710
static NTSTATUS NTAPI HalpMarkChipsetDecode(IN BOOLEAN OverrideEnable)
Definition: bussupp.c:149
NTSTATUS NTAPI HalpAssignSlotResources(IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject, IN INTERFACE_TYPE BusType, IN ULONG BusNumber, IN ULONG SlotNumber, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: bussupp.c:1210
VOID NTAPI HalpInitBusHandlers(VOID)
Definition: bussupp.c:1179
NTSTATUS NTAPI HalAssignSlotResources(IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject, IN INTERFACE_TYPE BusType, IN ULONG BusNumber, IN ULONG SlotNumber, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: bussupp.c:1391
static VOID NTAPI HalpRegisterInternalBusHandlers(VOID)
Definition: bussupp.c:75
#define NEWLINE
Definition: bussupp.c:704
static VOID NTAPI HalpFixupPciSupportedRanges(_In_ USHORT BusCount)
Definition: bussupp.c:611
PBUS_HANDLER NTAPI HalpAllocateBusHandler(IN INTERFACE_TYPE InterfaceType, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN INTERFACE_TYPE ParentBusInterfaceType, IN ULONG ParentBusNumber, IN ULONG BusSpecificData)
Definition: bussupp.c:27
static VOID ShowSize(IN ULONG x)
Definition: bussupp.c:677
BOOLEAN NTAPI HaliFindBusAddressTranslation(IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress, IN OUT PULONG_PTR Context, IN BOOLEAN NextBus)
Definition: bussupp.c:1245
BOOLEAN NTAPI HalTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bussupp.c:1588
BOOLEAN NTAPI HaliTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bussupp.c:1327
ULONG NTAPI HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bussupp.c:1456
static BOOLEAN NTAPI HalpIsBridgeDevice(IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:540
ULONG NTAPI HalGetInterruptVector(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: bussupp.c:1489
static BOOLEAN NTAPI HalpIsIdeDevice(IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:487
ULONG NTAPI HalGetBusData(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
Definition: bussupp.c:1435
ULONG NTAPI HalSetBusData(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
Definition: bussupp.c:1535
_In_ ULONG_PTR HackFlags
Definition: cdrom.h:983
Definition: bufpool.h:45
IN PUNICODE_STRING IN POBJECT_ATTRIBUTES ObjectAttributes
Definition: conport.c:36
_Out_ PKIRQL Irql
Definition: csq.h:179
#define RtlInitializeBitMap
Definition: dbgbitmap.h:326
_In_ D3DDDI_VIDEO_PRESENT_TARGET_ID _In_ ULONG _In_ ULONG Flags
Definition: dispmprt.h:245
#define NULL
Definition: types.h:112
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:33
_ACRTIMP size_t __cdecl strlen(const char *)
Definition: string.c:1597
_ACRTIMP char *__cdecl strstr(const char *, const char *)
Definition: string.c:3420
_ACRTIMP char *__cdecl strpbrk(const char *, const char *)
Definition: string.c:3530
#define L(x)
Definition: resources.c:13
static const uint32_t k[]
Definition: sha256.c:24
#define ULONG_PTR
Definition: config.h:101
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
ULONG KSPIN_LOCK
Definition: env_spec_w32.h:72
KIRQL * PKIRQL
Definition: env_spec_w32.h:592
#define KeInitializeSpinLock(sl)
Definition: env_spec_w32.h:604
ULONG Handle
Definition: gdb_input.c:15
Status
Definition: gdiplustypes.h:24
GLint GLint GLint GLint GLint x
Definition: gl.h:1548
GLboolean GLboolean GLboolean b
Definition: glext.h:6204
GLfloat GLfloat p
Definition: glext.h:8902
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble * u
Definition: glfuncs.h:240
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
#define DbgPrint
Definition: hal.h:12
PVOID NTAPI HalpMapPhysicalMemory64Vista(IN PHYSICAL_ADDRESS PhysicalAddress, IN PFN_COUNT PageCount, IN BOOLEAN FlushCurrentTLB)
Definition: memory.c:156
VOID NTAPI HalpUnmapVirtualAddress(IN PVOID VirtualAddress, IN PFN_COUNT PageCount)
Definition: memory.c:148
VOID NTAPI HalpUnmapVirtualAddressVista(IN PVOID VirtualAddress, IN PFN_COUNT PageCount, IN BOOLEAN FlushCurrentTLB)
Definition: memory.c:227
PVOID NTAPI HalpMapPhysicalMemory64(IN PHYSICAL_ADDRESS PhysicalAddress, IN PFN_COUNT PageCount)
Definition: memory.c:140
VOID NTAPI HalpCheckPowerButton(VOID)
Definition: misc.c:150
NTSTATUS NTAPI HalpOpenRegistryKey(IN PHANDLE KeyHandle, IN HANDLE RootKey, IN PUNICODE_STRING KeyName, IN ACCESS_MASK DesiredAccess, IN BOOLEAN Create)
Definition: misc.c:108
VOID NTAPI HalpGetNMICrashFlag(VOID)
Definition: usage.c:605
#define TAG_HAL
Definition: hal.h:61
#define VECTOR2IRQL(vector)
Definition: halirq.h:26
#define IRQ2VECTOR(irq)
Definition: halirq.h:27
#define HALP_CHECK_CARD_REVISION_ID
Definition: halp.h:179
#define HALP_CARD_FEATURE_FULL_DECODE
Definition: halp.h:174
#define HALP_HACK_FLAGS(x)
Definition: halp.h:169
#define HALP_CHECK_CARD_SUBVENDOR_ID
Definition: halp.h:180
#define HALP_CHECK_CARD_SUBSYSTEM_ID
Definition: halp.h:181
#define HALP_REVISION_FROM_HACK_FLAGS(x)
Definition: halp.h:167
#define HALP_REVISION_HACK_FLAGS(x)
Definition: halp.h:168
NTSTATUS NTAPI HalpReleasePciDeviceForDebugging(_Inout_ PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Releases the PCI device MMIO mappings previously allocated with HalpSetupPciDeviceForDebugging().
Definition: kdpci.c:421
NTSTATUS NTAPI HalpSetupPciDeviceForDebugging(_In_opt_ PVOID LoaderBlock, _Inout_ PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Finds and fully initializes the PCI device associated with the supplied debug device descriptor.
Definition: kdpci.c:483
#define b
Definition: ke_i.h:79
_In_ PIRP _In_ PIO_COMPLETION_ROUTINE _In_ PVOID Context
Definition: kse.h:81
if(dx< 0)
Definition: linetemp.h:194
#define ASSERT(a)
Definition: mode.c:44
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1109
#define sprintf
Definition: sprintf.c:45
#define _swprintf(buf, format,...)
Definition: sprintf.c:56
#define InitializeObjectAttributes(p, n, a, r, s)
Definition: reg.c:115
#define min(a, b)
Definition: monoChain.cc:55
_Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PCM_RESOURCE_LIST * AllocatedResources
Definition: ndis.h:4643
_Must_inspect_result_ _Out_ PNDIS_STATUS _In_ NDIS_HANDLE _In_ ULONG _Out_ PNDIS_STRING _Out_ PNDIS_HANDLE KeyHandle
Definition: ndis.h:4715
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1197
#define MACHINE_TYPE_ISA
Definition: ketypes.h:107
#define KdUnmapVirtualAddress
Definition: halfuncs.h:56
#define HalHandlerForBus
Definition: halfuncs.h:35
#define HalRegisterBusHandler
Definition: halfuncs.h:38
#define KdMapPhysicalMemory64
Definition: halfuncs.h:55
#define KdSetupPciDeviceForDebugging
Definition: halfuncs.h:50
#define KdReleasePciDeviceforDebugging
Definition: halfuncs.h:51
#define KdCheckPowerButton
Definition: halfuncs.h:53
#define HalPciTranslateBusAddress
Definition: halfuncs.h:41
#define HalPciAssignSlotResources
Definition: halfuncs.h:42
_In_ ULONG Number
Definition: haltypes.h:1940
#define HAL_PCI_CHIP_HACK_BROKEN_ACPI_TIMER
Definition: haltypes.h:2088
#define HAL_PCI_CHIP_HACK_DISABLE_ACPI_IRQ_ROUTING
Definition: haltypes.h:2090
#define HAL_PCI_CHIP_HACK_USB_SMI_DISABLE
Definition: haltypes.h:2091
#define HAL_PCI_CHIP_HACK_DISABLE_HIBERNATE
Definition: haltypes.h:2089
#define HAL_SUPPORTED_RANGE_VERSION
Definition: haltypes.h:2028
NTSYSAPI NTSTATUS NTAPI ZwClose(_In_ HANDLE Handle)
#define _Inout_
Definition: no_sal2.h:162
#define _In_
Definition: no_sal2.h:158
@ KeyValuePartialInformation
Definition: nt_native.h:1185
#define KEY_ALL_ACCESS
Definition: nt_native.h:1044
#define KEY_READ
Definition: nt_native.h:1026
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:102
_In_ ULONG _In_ PCI_SLOT_NUMBER PciSlot
Definition: pciidex.h:66
_In_ ULONG BusNumber
Definition: pciidex.h:65
short WCHAR
Definition: pedump.c:58
unsigned short USHORT
Definition: pedump.c:61
char CHAR
Definition: pedump.c:57
static WCHAR Address[46]
Definition: ping.c:68
#define OBJ_CASE_INSENSITIVE
Definition: winternl.h:228
@ InterfaceTypeUndefined
Definition: restypes.h:121
@ PCIBus
Definition: restypes.h:127
@ Internal
Definition: restypes.h:122
@ Isa
Definition: restypes.h:123
enum _INTERFACE_TYPE INTERFACE_TYPE
#define REG_DWORD
Definition: sdbapi.c:615
@ Cmos
Definition: miniport.h:89
@ ConfigurationSpaceUndefined
Definition: miniport.h:88
@ PCIConfiguration
Definition: miniport.h:93
enum _BUS_DATA_TYPE BUS_DATA_TYPE
strncpy
Definition: string.h:335
#define STATUS_SUCCESS
Definition: shellext.h:65
#define STATUS_NOT_FOUND
Definition: shellext.h:72
#define DPRINT
Definition: sndvol32.h:73
PGETINTERRUPTVECTOR GetInterruptVector
Definition: haltypes.h:2073
PGETSETBUSDATA GetBusData
Definition: haltypes.h:2069
ULONG BusNumber
Definition: haltypes.h:2062
PSUPPORTED_RANGES BusAddresses
Definition: haltypes.h:2067
PTRANSLATEBUSADDRESS TranslateBusAddress
Definition: haltypes.h:2074
PASSIGNSLOTRESOURCES AssignSlotResources
Definition: haltypes.h:2072
struct _BUS_HANDLER * ParentHandler
Definition: haltypes.h:2064
PGETSETBUSDATA SetBusData
Definition: haltypes.h:2070
INTERFACE_TYPE InterfaceType
Definition: haltypes.h:2060
PADJUSTRESOURCELIST AdjustResourceList
Definition: haltypes.h:2071
PVOID BusData
Definition: haltypes.h:2065
BUS_HANDLER Handler
Definition: bus.h:271
LIST_ENTRY AllHandlers
Definition: bus.h:269
Definition: typedefs.h:120
struct _LIST_ENTRY * Flink
Definition: typedefs.h:121
PciReadWriteConfig WriteConfig
Definition: iotypes.h:5298
PciLine2Pin Line2Pin
Definition: iotypes.h:5300
ULONG Tag
Definition: iotypes.h:5295
PciReadWriteConfig ReadConfig
Definition: iotypes.h:5297
ULONG Version
Definition: iotypes.h:5296
PciPin2Line Pin2Line
Definition: iotypes.h:5299
ULONG ConfiguredBits[PCI_MAX_DEVICES *PCI_MAX_FUNCTION/32]
Definition: bus.h:118
PciIrqRange GetIrqRange
Definition: bus.h:111
PCIBUSDATA CommonData
Definition: bus.h:95
ULONG MaxDevice
Definition: bus.h:110
union _PCIPBUSDATA::@1725 Config
RTL_BITMAP DeviceConfigured
Definition: bus.h:117
struct _PCIPBUSDATA::@1725::@1727 Type2
struct _PCIPBUSDATA::@1725::@1726 Type1
USHORT VendorID
Definition: pci.h:137
USHORT SubsystemID
Definition: pci.h:141
USHORT DeviceID
Definition: pci.h:138
USHORT SubsystemVendorID
Definition: pci.h:140
USHORT RevisionID
Definition: pci.h:139
struct _PCI_SLOT_NUMBER::@5064::@5065 bits
union _PCI_SLOT_NUMBER::@5064 u
SUPPORTED_RANGE Dma
Definition: haltypes.h:2050
SUPPORTED_RANGE PrefetchMemory
Definition: haltypes.h:2048
SUPPORTED_RANGE Memory
Definition: haltypes.h:2046
SUPPORTED_RANGE IO
Definition: haltypes.h:2044
ULONG SystemAddressSpace
Definition: haltypes.h:2032
LONGLONG Base
Definition: haltypes.h:2034
LONGLONG Limit
Definition: haltypes.h:2035
uint32_t * PULONG_PTR
Definition: typedefs.h:65
uint32_t * PULONG
Definition: typedefs.h:59
unsigned char UCHAR
Definition: typedefs.h:53
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
#define NTAPI
Definition: typedefs.h:36
void * PVOID
Definition: typedefs.h:50
uint16_t * PUSHORT
Definition: typedefs.h:56
#define RtlCopyMemory(Destination, Source, Length)
Definition: typedefs.h:263
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
uint32_t ULONG_PTR
Definition: typedefs.h:65
#define IN
Definition: typedefs.h:39
#define CONTAINING_RECORD(address, type, field)
Definition: typedefs.h:260
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
_In_ PGUID _In_ ULONG _Out_ PULONG ResultLength
Definition: ucxcontroller.h:83
_In_ PDEVICE_OBJECT DeviceObject
Definition: wdfdevice.h:2061
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_DEVICE_PROPERTY_DATA _In_ DEVPROPTYPE _In_ ULONG Size
Definition: wdfdevice.h:4539
_Must_inspect_result_ _In_ WDFDEVICE _In_ PCUNICODE_STRING KeyName
Definition: wdfdevice.h:2705
_Must_inspect_result_ _In_ PDRIVER_OBJECT _In_ PCUNICODE_STRING RegistryPath
Definition: wdfdriver.h:215
_Must_inspect_result_ _In_ PDRIVER_OBJECT DriverObject
Definition: wdfdriver.h:213
_Must_inspect_result_ _In_ WDFDEVICE _In_ LPCGUID InterfaceType
Definition: wdffdo.h:463
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING ValueName
Definition: wdfregistry.h:243
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
Definition: wdfresource.h:309
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
Definition: wdfresource.h:68
_In_opt_ PUNICODE_STRING DriverClassName
Definition: halfuncs.h:156
_In_ ULONG _In_ ULONG BusInterruptLevel
Definition: halfuncs.h:171
_In_ ULONG _In_ ULONG _In_ ULONG BusInterruptVector
Definition: halfuncs.h:172
_In_ ULONG _In_ ULONG _In_ ULONG _Out_ PKIRQL _Out_ PKAFFINITY Affinity
Definition: halfuncs.h:174
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE BusType
Definition: halfuncs.h:159
#define HalDereferenceBusHandler
Definition: haltypes.h:309
#define HalReferenceHandlerForBus
Definition: haltypes.h:307
_In_ ULONG _In_ PHYSICAL_ADDRESS BusAddress
Definition: iofuncs.h:2273
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG _Out_ PPHYSICAL_ADDRESS TranslatedAddress
Definition: iofuncs.h:2275
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG AddressSpace
Definition: iofuncs.h:2274
#define PCI_TYPE_64BIT
Definition: iotypes.h:4255
#define PCI_INVALID_VENDORID
Definition: iotypes.h:3616
#define PCI_TYPE_32BIT
Definition: iotypes.h:4253
#define PCI_ADDRESS_IO_ADDRESS_MASK
Definition: iotypes.h:4249
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3633
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3515
#define PCI_DATA_TAG
Definition: iotypes.h:5291
#define PCI_SUBCLASS_BR_PCI_TO_PCI
Definition: iotypes.h:4181
#define PCI_CLASS_MASS_STORAGE_CTLR
Definition: iotypes.h:4119
struct _PCI_COMMON_CONFIG * PPCI_COMMON_CONFIG
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:4246
#define PCI_CONFIGURATION_TYPE(PciData)
Definition: iotypes.h:3624
#define PCI_SUBCLASS_MSC_IDE_CTLR
Definition: iotypes.h:4144
#define PCI_TYPE1_ADDRESSES
Definition: iotypes.h:3516
#define PCI_STATUS_66MHZ_CAPABLE
Definition: iotypes.h:3646
#define PCI_MAX_FUNCTION
Definition: iotypes.h:3614
#define PCI_BRIDGE_TYPE
Definition: iotypes.h:3621
#define PCI_STATUS_DEVSEL
Definition: iotypes.h:3650
#define PCI_ADDRESS_MEMORY_ADDRESS_MASK
Definition: iotypes.h:4250
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3609
#define PCI_CLASS_BRIDGE_DEV
Definition: iotypes.h:4124
#define PCI_SUBCLASS_BR_CARDBUS
Definition: iotypes.h:4184
#define PCI_ADDRESS_MEMORY_PREFETCHABLE
Definition: iotypes.h:4248
#define PCI_MAX_DEVICES
Definition: iotypes.h:3613
#define PCI_ADDRESS_MEMORY_TYPE_MASK
Definition: iotypes.h:4247
#define PCI_DATA_VERSION
Definition: iotypes.h:5292
#define PCI_DEVICE_TYPE
Definition: iotypes.h:3620
#define PCI_CARDBUS_BRIDGE_TYPE
Definition: iotypes.h:3622
@ NonPagedPoolMustSucceed
Definition: ketypes.h:948