ReactOS  0.4.15-dev-2534-geba00d1
bussupp.c
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1 /*
2  * PROJECT: ReactOS HAL
3  * LICENSE: BSD - See COPYING.ARM in the top level directory
4  * FILE: hal/halx86/legacy/bussupp.c
5  * PURPOSE: HAL Legacy Bus Support Code
6  * PROGRAMMERS: ReactOS Portable Systems Group
7  */
8 
9 /* INCLUDES *******************************************************************/
10 
11 #include <hal.h>
12 #define NDEBUG
13 #include <debug.h>
14 
15 CODE_SEG("INIT")
17 NTAPI
19  IN ULONG PciType,
20  IN ULONG BusNo,
21  IN BOOLEAN TestAllocation
22 );
23 
24 CODE_SEG("INIT")
25 VOID
26 NTAPI
28  IN ULONG BusCount
29 );
30 
31 CODE_SEG("INIT")
33 NTAPI
35  IN USHORT VendorId,
36  IN USHORT DeviceId,
37  IN UCHAR RevisionId,
39 );
40 
41 CODE_SEG("INIT")
42 BOOLEAN
43 NTAPI
45  IN ULONG PciType,
46  IN PUCHAR BusCount
47 );
48 
49 CODE_SEG("INIT")
50 BOOLEAN
51 NTAPI
53  IN PPCI_COMMON_CONFIG PciData
54 );
55 
56 CODE_SEG("INIT")
57 BOOLEAN
58 NTAPI
60  IN PPCI_COMMON_CONFIG PciData
61 );
62 
63 CODE_SEG("INIT")
64 BOOLEAN
65 NTAPI
67  IN PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo,
68  IN PPCI_COMMON_CONFIG PciData,
69  IN ULONG Flags
70 );
71 
72 CODE_SEG("INIT")
73 BOOLEAN
74 NTAPI
76  IN PBUS_HANDLER BusHandler,
77  IN PCI_SLOT_NUMBER Slot
78 );
79 
80 CODE_SEG("INIT")
82 NTAPI
84  IN BOOLEAN OverrideEnable
85 );
86 
87 CODE_SEG("INIT")
88 VOID
89 NTAPI
91  VOID
92 );
93 
94 CODE_SEG("INIT")
95 VOID
96 NTAPI
97 ShowSize(
98  IN ULONG Size
99 );
100 
101 /* GLOBALS ********************************************************************/
102 
105 
106 /* PRIVATE FUNCTIONS **********************************************************/
107 
109 NTAPI
111  IN BUS_DATA_TYPE BusDataType,
113  IN INTERFACE_TYPE ParentBusInterfaceType,
114  IN ULONG ParentBusNumber,
115  IN ULONG BusSpecificData)
116 {
117  PBUS_HANDLER Bus;
118 
119  /* Register the bus handler */
121  BusDataType,
122  BusNumber,
123  ParentBusInterfaceType,
124  ParentBusNumber,
125  BusSpecificData,
126  NULL,
127  &Bus);
128  if (!Bus)
129  {
130  return NULL;
131  }
132 
133  /* Check for a valid interface */
135  {
136  /* Allocate address ranges and zero them out */
138  sizeof(SUPPORTED_RANGES),
139  TAG_HAL);
141 
142  /* Build the data structure */
144  Bus->BusAddresses->Dma.Limit = 7;
145  Bus->BusAddresses->Memory.Limit = 0xFFFFFFFF;
146  Bus->BusAddresses->IO.Limit = 0xFFFF;
148  Bus->BusAddresses->PrefetchMemory.Base = 1;
149  }
150 
151  /* Return the bus address */
152  return Bus;
153 }
154 
155 CODE_SEG("INIT")
156 VOID
157 NTAPI
159 {
160  PBUS_HANDLER Bus;
161 
162  /* Only do processor 1 */
163  if (KeGetCurrentPrcb()->Number) return;
164 
165  /* Register root support */
167 
168  /* Allocate the system bus */
171  0,
173  0,
174  0);
175  if (Bus)
176  {
177  /* Set it up */
180  }
181 
182  /* Allocate the CMOS bus */
184  Cmos,
185  0,
187  0,
188  0);
189  if (Bus)
190  {
191  /* Set it up */
194  }
195 
196  /* Allocate the CMOS bus */
198  Cmos,
199  1,
201  0,
202  0);
203  if (Bus)
204  {
205  /* Set it up */
208  }
209 
210  /* Allocate ISA bus */
213  0,
214  Internal,
215  0,
216  0);
217  if (Bus)
218  {
219  /* Set it up */
220  Bus->GetBusData = HalpNoBusData;
221  Bus->BusAddresses->Memory.Limit = 0xFFFFFF;
223  }
224 
225  /* No support for EISA or MCA */
227 }
228 
229 #ifndef _MINIHAL_
230 CODE_SEG("INIT")
231 NTSTATUS
232 NTAPI
234 {
236  UNICODE_STRING KeyString;
237  ULONG Data = OverrideEnable;
239 
240  /* Open CCS key */
241  RtlInitUnicodeString(&KeyString,
242  L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET");
244  if (NT_SUCCESS(Status))
245  {
246  /* Open PNP Bios key */
247  RtlInitUnicodeString(&KeyString, L"Control\\Biosinfo\\PNPBios");
249  Handle,
250  &KeyString,
252  TRUE);
253 
254  /* Close root key */
255  ZwClose(Handle);
256 
257  /* Check if PNP BIOS key exists */
258  if (NT_SUCCESS(Status))
259  {
260  /* Set the override value */
261  RtlInitUnicodeString(&KeyString, L"FullDecodeChipsetOverride");
262  Status = ZwSetValueKey(KeyHandle,
263  &KeyString,
264  0,
265  REG_DWORD,
266  &Data,
267  sizeof(Data));
268 
269  /* Close subkey */
271  }
272  }
273 
274  /* Return status */
275  return Status;
276 }
277 
278 CODE_SEG("INIT")
280 NTAPI
282  IN ULONG BusNo,
283  IN BOOLEAN TestAllocation)
284 {
285  PBUS_HANDLER Bus;
286  PPCIPBUSDATA BusData;
287 
288  /* Allocate the bus handler */
291  BusNo,
292  Internal,
293  0,
294  sizeof(PCIPBUSDATA));
295 
296  /* Set it up */
297  Bus->GetBusData = HalpGetPCIData;
298  Bus->SetBusData = HalpSetPCIData;
302  Bus->BusAddresses->Dma.Limit = 0;
303 
304  /* Get our custom bus data */
305  BusData = (PPCIPBUSDATA)Bus->BusData;
306 
307  /* Setup custom bus data */
308  BusData->CommonData.Tag = PCI_DATA_TAG;
314  BusData->MaxDevice = PCI_MAX_DEVICES;
316 
317  /* Initialize the bitmap */
318  RtlInitializeBitMap(&BusData->DeviceConfigured, BusData->ConfiguredBits, 256);
319 
320  /* Check the type of PCI bus */
321  switch (PciType)
322  {
323  /* Type 1 PCI Bus */
324  case 1:
325 
326  /* Copy the Type 1 handler data */
329  sizeof(PCIConfigHandler));
330 
331  /* Set correct I/O Ports */
332  BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
333  BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
334  break;
335 
336  /* Type 2 PCI Bus */
337  case 2:
338 
339  /* Copy the Type 1 handler data */
342  sizeof (PCIConfigHandler));
343 
344  /* Set correct I/O Ports */
345  BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
346  BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
347  BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
348 
349  /* Only 16 devices supported, not 32 */
350  BusData->MaxDevice = 16;
351  break;
352 
353  default:
354 
355  /* Invalid type */
356  DbgPrint("HAL: Unnkown PCI type\n");
357  }
358 
359  /* Return the bus handler */
360  return Bus;
361 }
362 
363 CODE_SEG("INIT")
364 BOOLEAN
365 NTAPI
367  IN PCI_SLOT_NUMBER Slot)
368 {
369  UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
370  PPCI_COMMON_CONFIG PciHeader = (PVOID)DataBuffer;
371  ULONG i;
373 
374  /* Read the PCI header */
375  HalpReadPCIConfig(BusHandler, Slot, PciHeader, 0, PCI_COMMON_HDR_LENGTH);
376 
377  /* Make sure it's a valid device */
378  if ((PciHeader->VendorID == PCI_INVALID_VENDORID) ||
379  (PCI_CONFIGURATION_TYPE(PciHeader) != PCI_DEVICE_TYPE))
380  {
381  /* Bail out */
382  return FALSE;
383  }
384 
385  /* Make sure interrupt numbers make sense */
386  if (((PciHeader->u.type0.InterruptPin) &&
387  (PciHeader->u.type0.InterruptPin > 4)) ||
388  (PciHeader->u.type0.InterruptLine & 0x70))
389  {
390  /* Bail out */
391  return FALSE;
392  }
393 
394  /* Now scan PCI BARs */
395  for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
396  {
397  /* Check what kind of address it is */
398  Address = PciHeader->u.type0.BaseAddresses[i];
400  {
401  /* Highest I/O port is 65535 */
402  if (Address > 0xFFFF) return FALSE;
403  }
404  else
405  {
406  /* MMIO should be higher than 0x80000 */
407  if ((Address > 0xF) && (Address < 0x80000)) return FALSE;
408  }
409 
410  /* Is this a 64-bit address? */
411  if (!(Address & PCI_ADDRESS_IO_SPACE) &&
413  {
414  /* Check the next-next entry, since this one 64-bits wide */
415  i++;
416  }
417  }
418 
419  /* Header, interrupt and address data all make sense */
420  return TRUE;
421 }
422 
424 
425 CODE_SEG("INIT")
426 NTSTATUS
427 NTAPI
429  IN USHORT DeviceId,
430  IN UCHAR RevisionId,
432 {
437  WCHAR Buffer[32];
438  KEY_VALUE_PARTIAL_INFORMATION PartialInfo;
440 
441  /* Setup the object attributes for the key */
443  L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET\\"
444  L"Control\\HAL");
446  &KeyName,
448  NULL,
449  NULL);
450 
451  /* Open the key */
452  Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
453  if (!NT_SUCCESS(Status)) return Status;
454 
455  /* Query value */
456  swprintf(Buffer, L"%04X%04X", VendorId, DeviceId);
458  Status = ZwQueryValueKey(KeyHandle,
459  &ValueName,
461  &PartialInfo,
462  sizeof(PartialInfo),
463  &ResultLength);
464  if (NT_SUCCESS(Status))
465  {
466  /* Return the flags */
467  DbgPrint("\tFound HackFlags for your chipset\n");
468  *HackFlags = *(PULONG)PartialInfo.Data;
469  DbgPrint("\t\tHack Flags: %lx (Hack Revision: %lx-Your Revision: %lx)\n",
471 
472  /* Does it apply to this revision? */
473  if ((RevisionId) && (RevisionId >= (HALP_REVISION_FROM_HACK_FLAGS(*HackFlags))))
474  {
475  /* Read the revision flags */
477  }
478 
479  /* Throw out revision data */
481  if (!*HackFlags) DbgPrint("\tNo HackFlags for your chipset's revision!\n");
482  }
483 
484  /* Close the handle and return */
486  return Status;
487 }
488 
489 CODE_SEG("INIT")
490 BOOLEAN
491 NTAPI
493  IN PPCI_COMMON_CONFIG PciData,
494  IN ULONG Flags)
495 {
496  ULONG ElementCount, i;
497  PPCI_CARD_DESCRIPTOR CardDescriptor;
498 
499  /* How many PCI Cards that we know about? */
500  ElementCount = PciRegistryInfo->ElementCount;
501  if (!ElementCount) return FALSE;
502 
503  /* Loop all descriptors */
504  CardDescriptor = &PciRegistryInfo->CardList[0];
505  for (i = 0; i < ElementCount; i++, CardDescriptor++)
506  {
507  /* Check for flag match */
508  if (CardDescriptor->Flags != Flags) continue;
509 
510  /* Check for VID-PID match */
511  if ((CardDescriptor->VendorID != PciData->VendorID) ||
512  (CardDescriptor->DeviceID != PciData->DeviceID))
513  {
514  /* Skip */
515  continue;
516  }
517 
518  /* Check for revision match, if requested */
519  if ((CardDescriptor->Flags & HALP_CHECK_CARD_REVISION_ID) &&
520  (CardDescriptor->RevisionID != PciData->RevisionID))
521  {
522  /* Skip */
523  continue;
524  }
525 
526  /* Check what kind of device this is */
527  switch (PCI_CONFIGURATION_TYPE(PciData))
528  {
529  /* CardBUS Bridge */
531 
532  /* This means the real device header is in the device-specific data */
533  PciData = (PPCI_COMMON_CONFIG)PciData->DeviceSpecific;
534 
535  /* Normal PCI device */
536  case PCI_DEVICE_TYPE:
537 
538  /* Check for subvendor match, if requested */
539  if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBVENDOR_ID) &&
540  (CardDescriptor->SubsystemVendorID != PciData->u.type0.SubVendorID))
541  {
542  /* Skip */
543  continue;
544  }
545 
546  /* Check for subsystem match, if requested */
547  if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBSYSTEM_ID) &&
548  (CardDescriptor->SubsystemID != PciData->u.type0.SubSystemID))
549  {
550  /* Skip */
551  continue;
552  }
553 
554  /* You made it! */
555  return TRUE;
556 
557  /* PCI Bridge -- don't bother */
558  case PCI_BRIDGE_TYPE:
559  default:
560 
561  /* Recognize it */
562  return TRUE;
563  }
564  }
565 
566  /* This means the card isn't recognized */
567  return FALSE;
568 }
569 
570 CODE_SEG("INIT")
571 BOOLEAN
572 NTAPI
574 {
575  /* Simple test first */
576  if ((PciData->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
577  (PciData->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
578  {
579  /* The device is nice enough to admit it */
580  return TRUE;
581  }
582 
583  /* Symphony 82C101 */
584  if (PciData->VendorID == 0x1C1C) return TRUE;
585 
586  /* ALi MS4803 or M5219 */
587  if ((PciData->VendorID == 0x10B9) &&
588  ((PciData->DeviceID == 0x5215) || (PciData->DeviceID == 0x5219)))
589  {
590  return TRUE;
591  }
592 
593  /* Appian Technology */
594  if ((PciData->VendorID == 0x1097) && (PciData->DeviceID == 0x38)) return TRUE;
595 
596  /* Compaq Triflex Dual EIDE Controller */
597  if ((PciData->VendorID == 0xE11) && (PciData->DeviceID == 0xAE33)) return TRUE;
598 
599  /* Micron PC Tech RZ1000 */
600  if ((PciData->VendorID == 0x1042) && (PciData->DeviceID == 0x1000)) return TRUE;
601 
602  /* SiS 85C601 or 5513 [IDE] */
603  if ((PciData->VendorID == 0x1039) &&
604  ((PciData->DeviceID == 0x601) || (PciData->DeviceID == 0x5513)))
605  {
606  return TRUE;
607  }
608 
609  /* Symphony Labs W83769F */
610  if ((PciData->VendorID == 0x10AD) &&
611  ((PciData->DeviceID == 0x1) || (PciData->DeviceID == 0x150)))
612  {
613  return TRUE;
614  }
615 
616  /* UMC UM8673F */
617  if ((PciData->VendorID == 0x1060) && (PciData->DeviceID == 0x101)) return TRUE;
618 
619  /* You've survived */
620  return FALSE;
621 }
622 
623 CODE_SEG("INIT")
624 BOOLEAN
625 NTAPI
627 {
628  /* Either this is a PCI-to-PCI Bridge, or a CardBUS Bridge */
629  return (((PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE) &&
630  (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
631  (PciData->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI)) ||
633  (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
634  (PciData->SubClass == PCI_SUBCLASS_BR_CARDBUS)));
635 }
636 
637 CODE_SEG("INIT")
638 BOOLEAN
639 NTAPI
641  IN PUCHAR BusCount)
642 {
643  PCI_SLOT_NUMBER PciSlot;
644  ULONG i, j, k;
645  UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
646  PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
647  PBUS_HANDLER BusHandler;
648 
649  /* Loop PCI buses */
650  PciSlot.u.bits.Reserved = 0;
651  for (i = 0; i < *BusCount; i++)
652  {
653  /* Get the bus handler */
654  BusHandler = HalHandlerForBus(PCIBus, i);
655 
656  /* Loop every device */
657  for (j = 0; j < PCI_MAX_DEVICES; j++)
658  {
659  /* Loop every function */
660  PciSlot.u.bits.DeviceNumber = j;
661  for (k = 0; k < PCI_MAX_FUNCTION; k++)
662  {
663  /* Build the final slot structure */
664  PciSlot.u.bits.FunctionNumber = k;
665 
666  /* Read the configuration information */
667  HalpReadPCIConfig(BusHandler,
668  PciSlot,
669  PciData,
670  0,
672 
673  /* Skip if this is an invalid function */
674  if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
675 
676  /* Make sure that this is a PCI bridge or a cardbus bridge */
677  if (!HalpIsBridgeDevice(PciData)) continue;
678 
679  /* Not supported */
680  if (!WarningsGiven[2]++) DPRINT1("Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail!\n");
681  continue;
682  }
683  }
684  }
685 
686  /* If we exited the loop, then there's no bridge to worry about */
687  return FALSE;
688 }
689 
690 CODE_SEG("INIT")
691 VOID
692 NTAPI
694 {
695  ULONG i;
696  PBUS_HANDLER Bus, ParentBus;
697 
698  /* Loop all buses */
699  for (i = 0; i < BusCount; i++)
700  {
701  /* Get PCI bus handler */
702  Bus = HalHandlerForBus(PCIBus, i);
703 
704  /* Loop all parent buses */
705  ParentBus = Bus->ParentHandler;
706  while (ParentBus)
707  {
708  /* Should merge addresses */
709  if (!WarningsGiven[0]++) DPRINT1("Found parent bus (indicating PCI Bridge). PCI devices may fail!\n");
710 
711  /* Check the next parent */
712  ParentBus = ParentBus->ParentHandler;
713  }
714  }
715 
716  /* Loop all buses again */
717  for (i = 0; i < BusCount; i++)
718  {
719  /* Get PCI bus handler */
720  Bus = HalHandlerForBus(PCIBus, i);
721 
722  /* Check if this is a PCI 2.2 Bus with Subtractive Decode */
723  if (!((PPCIPBUSDATA)Bus->BusData)->Subtractive)
724  {
725  /* Loop all parent buses */
726  ParentBus = Bus->ParentHandler;
727  while (ParentBus)
728  {
729  /* But check only PCI parent buses specifically */
730  if (ParentBus->InterfaceType == PCIBus)
731  {
732  /* Should trim addresses */
733  if (!WarningsGiven[1]++) DPRINT1("Found parent PCI Bus (indicating PCI-to-PCI Bridge). PCI devices may fail!\n");
734  }
735 
736  /* Check the next parent */
737  ParentBus = ParentBus->ParentHandler;
738  }
739  }
740  }
741 
742  /* Loop buses one last time */
743  for (i = 0; i < BusCount; i++)
744  {
745  /* Get the PCI bus handler */
746  Bus = HalHandlerForBus(PCIBus, i);
747 
748  /* Sort and combine (trim) bus address range information */
749  DPRINT("Warning: Bus addresses not being optimized!\n");
750  }
751 }
752 
753 CODE_SEG("INIT")
754 VOID
755 NTAPI
757 {
758  if (!x) return;
759  DbgPrint(" [size=");
760  if (x < 1024)
761  {
762  DbgPrint("%d", (int) x);
763  }
764  else if (x < 1048576)
765  {
766  DbgPrint("%dK", (int)(x / 1024));
767  }
768  else if (x < 0x80000000)
769  {
770  DbgPrint("%dM", (int)(x / 1048576));
771  }
772  else
773  {
774  DbgPrint("%d", x);
775  }
776  DbgPrint("]");
777 }
778 
779 /*
780  * These includes are required to define
781  * the ClassTable and VendorTable arrays.
782  */
783 #include "pci_classes.h"
784 #include "pci_vendors.h"
785 CODE_SEG("INIT")
786 VOID
787 NTAPI
789  IN ULONG j,
790  IN ULONG k,
791  IN PPCI_COMMON_CONFIG PciData)
792 {
793  PCHAR p, ClassName, Boundary, SubClassName, VendorName, ProductName, SubVendorName;
794  ULONG Length;
795  CHAR LookupString[16] = "";
796  CHAR bSubClassName[64] = "Unknown";
797  CHAR bVendorName[64] = "";
798  CHAR bProductName[128] = "Unknown device";
799  CHAR bSubVendorName[128] = "Unknown";
800  ULONG Size, Mem, b;
801 
802  /* Isolate the class name */
803  sprintf(LookupString, "C %02x ", PciData->BaseClass);
804  ClassName = strstr((PCHAR)ClassTable, LookupString);
805  if (ClassName)
806  {
807  /* Isolate the subclass name */
808  ClassName += strlen("C 00 ");
809  Boundary = strstr(ClassName, "\nC ");
810  sprintf(LookupString, "\n\t%02x ", PciData->SubClass);
811  SubClassName = strstr(ClassName, LookupString);
812  if (Boundary && SubClassName > Boundary)
813  {
814  SubClassName = NULL;
815  }
816  if (!SubClassName)
817  {
818  SubClassName = ClassName;
819  }
820  else
821  {
822  SubClassName += strlen("\n\t00 ");
823  }
824  /* Copy the subclass into our buffer */
825  p = strpbrk(SubClassName, "\r\n");
826  Length = p - SubClassName;
827  if (Length >= sizeof(bSubClassName)) Length = sizeof(bSubClassName) - 1;
828  strncpy(bSubClassName, SubClassName, Length);
829  bSubClassName[Length] = '\0';
830  }
831 
832  /* Isolate the vendor name */
833  sprintf(LookupString, "\r\n%04x ", PciData->VendorID);
834  VendorName = strstr((PCHAR)VendorTable, LookupString);
835  if (VendorName)
836  {
837  /* Copy the vendor name into our buffer */
838  VendorName += strlen("\r\n0000 ");
839  p = strpbrk(VendorName, "\r\n");
840  Length = p - VendorName;
841  if (Length >= sizeof(bVendorName)) Length = sizeof(bVendorName) - 1;
842  strncpy(bVendorName, VendorName, Length);
843  bVendorName[Length] = '\0';
844  p += strlen("\r\n");
845  while (*p == '\t' || *p == '#')
846  {
847  p = strpbrk(p, "\r\n");
848  p += strlen("\r\n");
849  }
850  Boundary = p;
851 
852  /* Isolate the product name */
853  sprintf(LookupString, "\t%04x ", PciData->DeviceID);
854  ProductName = strstr(VendorName, LookupString);
855  if (Boundary && ProductName >= Boundary)
856  {
857  ProductName = NULL;
858  }
859  if (ProductName)
860  {
861  /* Copy the product name into our buffer */
862  ProductName += strlen("\t0000 ");
863  p = strpbrk(ProductName, "\r\n");
864  Length = p - ProductName;
865  if (Length >= sizeof(bProductName)) Length = sizeof(bProductName) - 1;
866  strncpy(bProductName, ProductName, Length);
867  bProductName[Length] = '\0';
868  p += strlen("\r\n");
869  while ((*p == '\t' && *(p + 1) == '\t') || *p == '#')
870  {
871  p = strpbrk(p, "\r\n");
872  p += strlen("\r\n");
873  }
874  Boundary = p;
875 
876  /* Isolate the subvendor and subsystem name */
877  sprintf(LookupString,
878  "\t\t%04x %04x ",
879  PciData->u.type0.SubVendorID,
880  PciData->u.type0.SubSystemID);
881  SubVendorName = strstr(ProductName, LookupString);
882  if (Boundary && SubVendorName >= Boundary)
883  {
884  SubVendorName = NULL;
885  }
886  if (SubVendorName)
887  {
888  /* Copy the subvendor name into our buffer */
889  SubVendorName += strlen("\t\t0000 0000 ");
890  p = strpbrk(SubVendorName, "\r\n");
891  Length = p - SubVendorName;
892  if (Length >= sizeof(bSubVendorName)) Length = sizeof(bSubVendorName) - 1;
893  strncpy(bSubVendorName, SubVendorName, Length);
894  bSubVendorName[Length] = '\0';
895  }
896  }
897  }
898 
899  /* Print out the data */
900  DbgPrint("%02x:%02x.%x %s [%02x%02x]: %s %s [%04x:%04x] (rev %02x)\n"
901  "\tSubsystem: %s [%04x:%04x]\n",
902  i,
903  j,
904  k,
905  bSubClassName,
906  PciData->BaseClass,
907  PciData->SubClass,
908  bVendorName,
909  bProductName,
910  PciData->VendorID,
911  PciData->DeviceID,
912  PciData->RevisionID,
913  bSubVendorName,
914  PciData->u.type0.SubVendorID,
915  PciData->u.type0.SubSystemID);
916 
917  /* Print out and decode flags */
918  DbgPrint("\tFlags:");
919  if (PciData->Command & PCI_ENABLE_BUS_MASTER) DbgPrint(" bus master,");
920  if (PciData->Status & PCI_STATUS_66MHZ_CAPABLE) DbgPrint(" 66MHz,");
921  if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x000) DbgPrint(" fast devsel,");
922  if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x200) DbgPrint(" medium devsel,");
923  if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x400) DbgPrint(" slow devsel,");
924  if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x600) DbgPrint(" unknown devsel,");
925  DbgPrint(" latency %d", PciData->LatencyTimer);
926  if (PciData->u.type0.InterruptPin != 0 &&
927  PciData->u.type0.InterruptLine != 0 &&
928  PciData->u.type0.InterruptLine != 0xFF) DbgPrint(", IRQ %02d", PciData->u.type0.InterruptLine);
929  else if (PciData->u.type0.InterruptPin != 0) DbgPrint(", IRQ assignment required");
930  DbgPrint("\n");
931 
932  /* Scan addresses */
933  Size = 0;
934  for (b = 0; b < PCI_TYPE0_ADDRESSES; b++)
935  {
936  /* Check for a BAR */
937  Mem = PciData->u.type0.BaseAddresses[b];
938  if (Mem)
939  {
940  /* Decode the address type */
941  if (Mem & PCI_ADDRESS_IO_SPACE)
942  {
943  /* Guess the size */
944  Size = 1 << 2;
945  while (!(Mem & Size) && (Size)) Size <<= 1;
946 
947  /* Print it out */
948  DbgPrint("\tI/O ports at %04lx", Mem & PCI_ADDRESS_IO_ADDRESS_MASK);
949  ShowSize(Size);
950  }
951  else
952  {
953  /* Guess the size */
954  Size = 1 << 8;
955  while (!(Mem & Size) && (Size)) Size <<= 1;
956 
957  /* Print it out */
958  DbgPrint("\tMemory at %08lx (%d-bit, %sprefetchable)",
960  (Mem & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_32BIT ? 32 : 64,
961  (Mem & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? "" : "non-");
962  ShowSize(Size);
963  }
964  DbgPrint("\n");
965  }
966  }
967 }
968 #endif
969 
970 CODE_SEG("INIT")
971 VOID
972 NTAPI
974 {
975 #ifndef _MINIHAL_
976  PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
977  UCHAR PciType;
978  PCI_SLOT_NUMBER PciSlot;
979  ULONG i, j, k;
980  UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
981  PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
982  PBUS_HANDLER BusHandler;
984  BOOLEAN ExtendedAddressDecoding = FALSE;
986 
987  /* Query registry information */
988  PciRegistryInfo = HalpQueryPciRegistryInfo();
989  if (!PciRegistryInfo) return;
990 
991  /* Initialize the PCI configuration lock */
993 
994  /* Get the type and free the info structure */
995  PciType = PciRegistryInfo->HardwareMechanism & 0xF;
996 
997  /* Check if this is a type 2 PCI bus with at least one bus */
998  if ((PciRegistryInfo->NoBuses) && (PciType == 2))
999  {
1000  /* Setup the PCI slot */
1001  PciSlot.u.bits.Reserved = 0;
1002  PciSlot.u.bits.FunctionNumber = 0;
1003 
1004  /* Loop all slots */
1005  for (i = 0; i < 32; i++)
1006  {
1007  /* Try to setup a Type 2 PCI slot */
1008  PciType = 2;
1009  BusHandler = HalpAllocateAndInitPciBusHandler(2, 0, TRUE);
1010  if (!BusHandler) break;
1011 
1012  /* Now check if it's valid */
1013  if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
1014 
1015  /* Heh, the BIOS lied... try Type 1 */
1016  PciType = 1;
1017  BusHandler = HalpAllocateAndInitPciBusHandler(1, 0, TRUE);
1018  if (!BusHandler) break;
1019 
1020  /* Now check if it's valid */
1021  if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
1022 
1023  /* Keep trying */
1024  PciType = 2;
1025  }
1026 
1027  /* Now allocate the correct kind of handler */
1029  }
1030 
1031  /* Okay, now loop all PCI bridges */
1032  do
1033  {
1034  /* Loop all PCI buses */
1035  for (i = 0; i < PciRegistryInfo->NoBuses; i++)
1036  {
1037  /* Check if we have a handler for it */
1038  if (!HalHandlerForBus(PCIBus, i))
1039  {
1040  /* Allocate it */
1042  }
1043  }
1044  /* Go to the next bridge */
1045  } while (HalpGetPciBridgeConfig(PciType, &PciRegistryInfo->NoBuses));
1046 
1047  /* Now build correct address range informaiton */
1048  HalpFixupPciSupportedRanges(PciRegistryInfo->NoBuses);
1049 
1050  /* Loop every bus */
1051  DbgPrint("\n====== PCI BUS HARDWARE DETECTION =======\n\n");
1052  PciSlot.u.bits.Reserved = 0;
1053  for (i = 0; i < PciRegistryInfo->NoBuses; i++)
1054  {
1055  /* Get the bus handler */
1056  BusHandler = HalHandlerForBus(PCIBus, i);
1057 
1058  /* Loop every device */
1059  for (j = 0; j < 32; j++)
1060  {
1061  /* Loop every function */
1062  PciSlot.u.bits.DeviceNumber = j;
1063  for (k = 0; k < 8; k++)
1064  {
1065  /* Build the final slot structure */
1066  PciSlot.u.bits.FunctionNumber = k;
1067 
1068  /* Read the configuration information */
1069  HalpReadPCIConfig(BusHandler,
1070  PciSlot,
1071  PciData,
1072  0,
1074 
1075  /* Skip if this is an invalid function */
1076  if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
1077 
1078  /* Print out the entry */
1079  HalpDebugPciDumpBus(i, j, k, PciData);
1080 
1081  /* Check if this is a Cardbus bridge */
1083  {
1084  /* Not supported */
1085  DbgPrint("\tDevice is a PCI Cardbus Bridge. It will not work!\n");
1086  continue;
1087  }
1088 
1089  /* Check if this is a PCI device */
1090  if (PCI_CONFIGURATION_TYPE(PciData) != PCI_BRIDGE_TYPE)
1091  {
1092  /* Check if it has an interrupt pin and line registered */
1093  if ((PciData->u.type1.InterruptPin) &&
1094  (PciData->u.type1.InterruptLine))
1095  {
1096  /* Check if this interrupt line is connected to the bus */
1097  if (PciData->u.type1.InterruptLine < 16)
1098  {
1099  /* Is this an IDE device? */
1100  if (!HalpIsIdeDevice(PciData))
1101  {
1102  /* We'll mask out this interrupt then */
1103  DbgPrint("\tDevice is using IRQ %d! ISA Cards using that IRQ may fail!\n",
1104  PciData->u.type1.InterruptLine);
1105  HalpPciIrqMask |= (1 << PciData->u.type1.InterruptLine);
1106  }
1107  }
1108  }
1109  }
1110 
1111  /* Check for broken Intel chips */
1112  if (PciData->VendorID == 0x8086)
1113  {
1114  /* Check for broken 82830 PCI controller */
1115  if ((PciData->DeviceID == 0x04A3) &&
1116  (PciData->RevisionID < 0x11))
1117  {
1118  /* Skip */
1119  DbgPrint("\tDevice is a broken Intel 82430 PCI Controller. It will not work!\n\n");
1120  continue;
1121  }
1122 
1123  /* Check for broken 82378 PCI-to-ISA Bridge */
1124  if ((PciData->DeviceID == 0x0484) &&
1125  (PciData->RevisionID <= 3))
1126  {
1127  /* Skip */
1128  DbgPrint("\tDevice is a broken Intel 82378 PCI-to-ISA Bridge. It will not work!\n\n");
1129  continue;
1130  }
1131 
1132  /* Check for broken 82450 PCI Bridge */
1133  if ((PciData->DeviceID == 0x84C4) &&
1134  (PciData->RevisionID <= 4))
1135  {
1136  DbgPrint("\tDevice is a Intel Orion 82450 PCI Bridge. It will not work!\n\n");
1137  continue;
1138  }
1139  }
1140 
1141  /* Do we know this card? */
1142  if (!ExtendedAddressDecoding)
1143  {
1144  /* Check for it */
1145  if (HalpIsRecognizedCard(PciRegistryInfo,
1146  PciData,
1148  {
1149  /* We'll do chipset checks later */
1150  DbgPrint("\tDevice has Extended Address Decoding. It may fail to work on older BIOSes!\n");
1151  ExtendedAddressDecoding = TRUE;
1152  }
1153  }
1154 
1155  /* Now check the registry for chipset hacks */
1156  Status = HalpGetChipHacks(PciData->VendorID,
1157  PciData->DeviceID,
1158  PciData->RevisionID,
1159  &HackFlags);
1160  if (NT_SUCCESS(Status))
1161  {
1162  /* Check for broken ACPI routing */
1164  {
1165  DbgPrint("This chipset has broken ACPI IRQ Routing! Be aware!\n\n");
1166  continue;
1167  }
1168 
1169  /* Check for broken ACPI timer */
1171  {
1172  DbgPrint("This chipset has a broken ACPI timer! Be aware!\n\n");
1173  continue;
1174  }
1175 
1176  /* Check for hibernate-disable */
1178  {
1179  DbgPrint("This chipset has a broken PCI device which is incompatible with hibernation. Be aware!\n\n");
1180  continue;
1181  }
1182 
1183  /* Check for USB controllers that generate SMIs */
1185  {
1186  DbgPrint("This chipset has a USB controller which generates SMIs. ReactOS will likely fail to boot!\n\n");
1187  continue;
1188  }
1189  }
1190 
1191  /* Terminate the entry */
1192  DbgPrint("\n");
1193  }
1194  }
1195  }
1196 
1197  /* Initialize NMI Crash Flag */
1199 
1200  /* Free the registry data */
1201  ExFreePoolWithTag(PciRegistryInfo, TAG_HAL);
1202 
1203  /* Tell PnP if this hard supports correct decoding */
1204  HalpMarkChipsetDecode(ExtendedAddressDecoding);
1205  DbgPrint("====== PCI BUS DETECTION COMPLETE =======\n\n");
1206 #endif
1207 }
1208 
1209 CODE_SEG("INIT")
1210 VOID
1211 NTAPI
1213 {
1214  /* Register the HAL Bus Handler support */
1216 }
1217 
1218 CODE_SEG("INIT")
1219 VOID
1220 NTAPI
1222 {
1223  /* Register PCI Device Functions */
1226 
1227  /* Register memory functions */
1228 #ifndef _MINIHAL_
1229 #if (NTDDI_VERSION >= NTDDI_VISTA)
1232 #else
1235 #endif
1236 #endif
1237 
1238  /* Register ACPI stub */
1240 }
1241 
1242 NTSTATUS
1243 NTAPI
1249  IN ULONG BusNumber,
1252 {
1254  NTSTATUS Status;
1255  PAGED_CODE();
1256  DPRINT1("Slot assignment for %d on bus %u\n", BusType, BusNumber);
1257 
1258  /* Find the handler */
1260  if (!Handler) return STATUS_NOT_FOUND;
1261 
1262  /* Do the assignment */
1263  Status = Handler->AssignSlotResources(Handler,
1264  Handler,
1265  RegistryPath,
1267  DriverObject,
1268  DeviceObject,
1269  SlotNumber,
1271 
1272  /* Dereference the handler and return */
1274  return Status;
1275 }
1276 
1277 BOOLEAN
1278 NTAPI
1283  IN BOOLEAN NextBus)
1284 {
1285  PHAL_BUS_HANDLER BusHandler;
1287  PLIST_ENTRY NextEntry;
1288  ULONG ContextValue;
1289 
1290  /* Make sure we have a context */
1291  if (!Context) return FALSE;
1292  ASSERT((*Context) || (NextBus == TRUE));
1293 
1294  /* Read the context */
1295  ContextValue = *Context;
1296 
1297  /* Find the bus handler */
1298  Handler = HalpContextToBusHandler(ContextValue);
1299  if (!Handler) return FALSE;
1300 
1301  /* Check if this is an ongoing lookup */
1302  if (NextBus)
1303  {
1304  /* Get the HAL bus handler */
1306  NextEntry = &BusHandler->AllHandlers;
1307 
1308  /* Get the next one if we were already with one */
1309  if (ContextValue) NextEntry = NextEntry->Flink;
1310 
1311  /* Start scanning */
1312  while (TRUE)
1313  {
1314  /* Check if this is the last one */
1315  if (NextEntry == &HalpAllBusHandlers)
1316  {
1317  /* Quit */
1318  *Context = 1;
1319  return FALSE;
1320  }
1321 
1322  /* Call this translator */
1323  BusHandler = CONTAINING_RECORD(NextEntry, HAL_BUS_HANDLER, AllHandlers);
1325  BusHandler->Handler.BusNumber,
1326  BusAddress,
1327  AddressSpace,
1328  TranslatedAddress)) break;
1329 
1330  /* Try the next one */
1331  NextEntry = NextEntry->Flink;
1332  }
1333 
1334  /* If we made it, we're done */
1335  *Context = (ULONG_PTR)&BusHandler->Handler;
1336  return TRUE;
1337  }
1338 
1339  /* Try the first one through */
1340  if (!HalTranslateBusAddress(Handler->InterfaceType,
1341  Handler->BusNumber,
1342  BusAddress,
1343  AddressSpace,
1344  TranslatedAddress)) return FALSE;
1345 
1346  /* Remember for next time */
1348  return TRUE;
1349 }
1350 
1351 BOOLEAN
1352 NTAPI
1354  IN ULONG BusNumber,
1358 {
1360  BOOLEAN Status;
1361 
1362  /* Find the handler */
1364  if (!(Handler) || !(Handler->TranslateBusAddress))
1365  {
1366  DPRINT1("No translator Interface: %x, Bus: %x, Handler: %p, BusAddress: %x!\n", InterfaceType, BusNumber, Handler, BusAddress);
1367  return FALSE;
1368  }
1369 
1370  /* Do the assignment */
1371  Status = Handler->TranslateBusAddress(Handler,
1372  Handler,
1373  BusAddress,
1374  AddressSpace,
1376 
1377  /* Dereference the handler and return */
1379  return Status;
1380 }
1381 
1382 /* PUBLIC FUNCTIONS **********************************************************/
1383 
1384 /*
1385  * @implemented
1386  */
1387 NTSTATUS
1388 NTAPI
1390 {
1392  ULONG Status;
1393  PAGED_CODE();
1394 
1395  /* Find the handler */
1396  Handler = HalReferenceHandlerForBus((*ResourceList)->InterfaceType,
1397  (*ResourceList)->BusNumber);
1398  if (!Handler) return STATUS_SUCCESS;
1399 
1400  /* Do the assignment */
1401  Status = Handler->AdjustResourceList(Handler,
1402  Handler,
1403  ResourceList);
1404 
1405  /* Dereference the handler and return */
1407  return Status;
1408 }
1409 
1410 /*
1411  * @implemented
1412  */
1413 NTSTATUS
1414 NTAPI
1420  IN ULONG BusNumber,
1423 {
1424  PAGED_CODE();
1425 
1426  /* Check the bus type */
1427  if (BusType != PCIBus)
1428  {
1429  /* Call our internal handler */
1432  DriverObject,
1433  DeviceObject,
1434  BusType,
1435  BusNumber,
1436  SlotNumber,
1438  }
1439  else
1440  {
1441  /* Call the PCI registered function */
1444  DriverObject,
1445  DeviceObject,
1446  PCIBus,
1447  BusNumber,
1448  SlotNumber,
1450  }
1451 }
1452 
1453 /*
1454  * @implemented
1455  */
1456 ULONG
1457 NTAPI
1459  IN ULONG BusNumber,
1461  IN PVOID Buffer,
1462  IN ULONG Length)
1463 {
1464  /* Call the extended function */
1465  return HalGetBusDataByOffset(BusDataType,
1466  BusNumber,
1467  SlotNumber,
1468  Buffer,
1469  0,
1470  Length);
1471 }
1472 
1473 /*
1474  * @implemented
1475  */
1476 ULONG
1477 NTAPI
1479  IN ULONG BusNumber,
1481  IN PVOID Buffer,
1482  IN ULONG Offset,
1483  IN ULONG Length)
1484 {
1486  ULONG Status;
1487 
1488  /* Find the handler */
1490  if (!Handler) return 0;
1491 
1492  /* Do the assignment */
1493  Status = Handler->GetBusData(Handler,
1494  Handler,
1495  SlotNumber,
1496  Buffer,
1497  Offset,
1498  Length);
1499 
1500  /* Dereference the handler and return */
1502  return Status;
1503 }
1504 
1505 /*
1506  * @implemented
1507  */
1508 ULONG
1509 NTAPI
1511  IN ULONG BusNumber,
1514  OUT PKIRQL Irql,
1516 {
1518  ULONG Vector;
1519  PAGED_CODE();
1520 
1521  /* Defaults */
1522  *Irql = 0;
1523  *Affinity = 0;
1524 
1525  /* Find the handler */
1527  if (!Handler) return 0;
1528 
1529  /* Do the assignment */
1530  Vector = Handler->GetInterruptVector(Handler,
1531  Handler,
1534  Irql,
1535  Affinity);
1536  if ((Vector != IRQ2VECTOR(BusInterruptLevel)) ||
1538  {
1539  DPRINT1("Returning IRQL %lx, Vector %lx for Level/Vector: %lx/%lx\n",
1541  DPRINT1("Old HAL would've returned IRQL %lx and Vector %lx\n",
1544  }
1545 
1546  /* Dereference the handler and return */
1548  return Vector;
1549 }
1550 
1551 /*
1552  * @implemented
1553  */
1554 ULONG
1555 NTAPI
1557  IN ULONG BusNumber,
1559  IN PVOID Buffer,
1560  IN ULONG Length)
1561 {
1562  /* Call the extended function */
1563  return HalSetBusDataByOffset(BusDataType,
1564  BusNumber,
1565  SlotNumber,
1566  Buffer,
1567  0,
1568  Length);
1569 }
1570 
1571 /*
1572  * @implemented
1573  */
1574 ULONG
1575 NTAPI
1577  IN ULONG BusNumber,
1579  IN PVOID Buffer,
1580  IN ULONG Offset,
1581  IN ULONG Length)
1582 {
1584  ULONG Status;
1585 
1586  /* Find the handler */
1588  if (!Handler) return 0;
1589 
1590  /* Do the assignment */
1591  Status = Handler->SetBusData(Handler,
1592  Handler,
1593  SlotNumber,
1594  Buffer,
1595  Offset,
1596  Length);
1597 
1598  /* Dereference the handler and return */
1600  return Status;
1601 }
1602 
1603 /*
1604  * @implemented
1605  */
1606 BOOLEAN
1607 NTAPI
1609  IN ULONG BusNumber,
1613 {
1614  /* Look as the bus type */
1615  if (InterfaceType == PCIBus)
1616  {
1617  /* Call the PCI registered function */
1619  BusNumber,
1620  BusAddress,
1621  AddressSpace,
1623  }
1624  else
1625  {
1626  /* Call the bus handler */
1628  BusNumber,
1629  BusAddress,
1630  AddressSpace,
1632  }
1633 }
1634 
1635 /* EOF */
PVOID NTAPI HalpMapPhysicalMemory64Vista(IN PHYSICAL_ADDRESS PhysicalAddress, IN PFN_COUNT PageCount, IN BOOLEAN FlushCurrentTLB)
Definition: memory.c:156
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
Definition: wdfresource.h:65
#define HalReferenceHandlerForBus
Definition: haltypes.h:286
signed char * PCHAR
Definition: retypes.h:7
PSUPPORTED_RANGES BusAddresses
Definition: haltypes.h:231
IN PUNICODE_STRING IN POBJECT_ATTRIBUTES ObjectAttributes
Definition: conport.c:35
#define HalRegisterBusHandler
Definition: halfuncs.h:38
_In_ ULONG _In_ ULONG BusInterruptLevel
Definition: halfuncs.h:170
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3499
ULONG NTAPI HalpcSetCmosData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: cmosbus.c:34
#define IN
Definition: typedefs.h:39
VOID NTAPI HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciNewData, IN PPCI_COMMON_CONFIG PciOldData)
Definition: pcibus.c:563
NTSTATUS NTAPI HalpAssignSlotResources(IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject, IN INTERFACE_TYPE BusType, IN ULONG BusNumber, IN ULONG SlotNumber, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: bussupp.c:1244
LONGLONG Limit
Definition: haltypes.h:199
PCI_CONFIG_HANDLER PCIConfigHandlerType2
Definition: pci.c:54
#define HalPciTranslateBusAddress
Definition: halfuncs.h:41
#define PCI_ADDRESS_IO_ADDRESS_MASK
Definition: iotypes.h:4232
_In_ ULONG _In_ PHYSICAL_ADDRESS BusAddress
Definition: iofuncs.h:2272
VOID NTAPI HalpCheckPowerButton(VOID)
Definition: misc.c:20
ULONG NTAPI HalpNoBusData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bushndlr.c:108
#define HALP_REVISION_FROM_HACK_FLAGS(x)
Definition: halp.h:143
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:101
VOID NTAPI HalpInitBusHandler(VOID)
Definition: bushndlr.c:420
enum _INTERFACE_TYPE INTERFACE_TYPE
#define PCI_TYPE2_FORWARD_PORT
Definition: bus.h:171
ULONG MaxDevice
Definition: bus.h:100
VOID NTAPI HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciData)
Definition: pcibus.c:553
SUPPORTED_RANGE IO
Definition: haltypes.h:208
#define OBJ_CASE_INSENSITIVE
Definition: winternl.h:228
_Must_inspect_result_ _Out_ PNDIS_STATUS _In_ NDIS_HANDLE _In_ ULONG _Out_ PNDIS_STRING _Out_ PNDIS_HANDLE KeyHandle
Definition: ndis.h:4711
#define DbgPrint
Definition: loader.c:25
#define KdUnmapVirtualAddress
Definition: halfuncs.h:53
#define HALP_CHECK_CARD_SUBSYSTEM_ID
Definition: halp.h:157
ACPI_SIZE strlen(const char *String)
Definition: utclib.c:269
char * strpbrk(const char *String, const char *Delimiters)
Definition: utclib.c:302
_Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PCM_RESOURCE_LIST * AllocatedResources
Definition: ndis.h:4640
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE BusType
Definition: halfuncs.h:156
ULONG NTAPI HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bussupp.c:1576
#define KEY_READ
Definition: nt_native.h:1023
#define TRUE
Definition: types.h:120
ULONG HalpPciIrqMask
Definition: bussupp.c:104
NTSYSAPI NTSTATUS NTAPI ZwClose(_In_ HANDLE Handle)
char * strstr(char *String1, char *String2)
Definition: utclib.c:653
enum _BUS_DATA_TYPE BUS_DATA_TYPE
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG AddressSpace
Definition: iofuncs.h:2272
char * strncpy(char *DstString, const char *SrcString, ACPI_SIZE Count)
Definition: utclib.c:427
unsigned char * PUCHAR
Definition: retypes.h:3
#define PCI_TYPE1_ADDRESS_PORT
Definition: bus.h:164
char CHAR
Definition: xmlstorage.h:175
_In_ CLIPOBJ _In_ BRUSHOBJ _In_ LONG x1
Definition: winddi.h:3706
struct _PCIPBUSDATA::@1433::@1435 Type2
LONGLONG Base
Definition: haltypes.h:198
NTSYSAPI void WINAPI RtlInitializeBitMap(PRTL_BITMAP, PULONG, ULONG)
LONG NTSTATUS
Definition: precomp.h:26
_Must_inspect_result_ _In_ PDRIVER_OBJECT _In_ PCUNICODE_STRING RegistryPath
Definition: wdfdriver.h:213
NTSTATUS NTAPI HalpMarkChipsetDecode(IN BOOLEAN OverrideEnable)
struct _PCI_COMMON_CONFIG * PPCI_COMMON_CONFIG
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1079
#define PCI_ADDRESS_MEMORY_TYPE_MASK
Definition: iotypes.h:4230
IN PVOID IN PVOID IN USHORT IN USHORT Size
Definition: pci.h:361
ULONG Tag
Definition: iotypes.h:5278
GLint GLint GLint GLint GLint x
Definition: gl.h:1548
#define HALP_CHECK_CARD_SUBVENDOR_ID
Definition: halp.h:156
#define PCI_DATA_TAG
Definition: iotypes.h:5274
union _PCI_SLOT_NUMBER::@3802 u
USHORT SubsystemVendorID
Definition: pci.h:122
PciReadWriteConfig WriteConfig
Definition: iotypes.h:5281
SUPPORTED_RANGE PrefetchMemory
Definition: haltypes.h:212
VOID NTAPI HalpWritePCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pci.c:281
#define swprintf
Definition: precomp.h:40
union _PCIPBUSDATA::@1433 Config
_In_ ULONG _In_ ULONG _In_ ULONG BusInterruptVector
Definition: halfuncs.h:170
if(dx==0 &&dy==0)
Definition: linetemp.h:174
#define HalDereferenceBusHandler
Definition: haltypes.h:288
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG _Out_ PPHYSICAL_ADDRESS TranslatedAddress
Definition: iofuncs.h:2272
KSPIN_LOCK HalpPCIConfigLock
Definition: pci.c:19
#define HAL_PCI_CHIP_HACK_DISABLE_ACPI_IRQ_ROUTING
Definition: haltypes.h:254
_Out_ PKIRQL Irql
Definition: csq.h:179
ULONG NTAPI HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bussupp.c:1478
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
Definition: wdfresource.h:304
VOID NTAPI HalpRegisterInternalBusHandlers(VOID)
Definition: bussupp.c:158
#define PCI_TYPE_32BIT
Definition: iotypes.h:4236
#define HAL_SUPPORTED_RANGE_VERSION
Definition: haltypes.h:192
PCIBUSDATA CommonData
Definition: bus.h:85
#define HAL_PCI_CHIP_HACK_DISABLE_HIBERNATE
Definition: haltypes.h:253
BOOLEAN NTAPI HalpIsValidPCIDevice(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot)
Definition: bussupp.c:366
_In_opt_ PUNICODE_STRING DriverClassName
Definition: halfuncs.h:156
USHORT SubsystemID
Definition: pci.h:123
uint32_t ULONG_PTR
Definition: typedefs.h:65
#define sprintf(buf, format,...)
Definition: sprintf.c:55
#define PCI_SUBCLASS_BR_CARDBUS
Definition: iotypes.h:4167
BOOLEAN NTAPI HaliTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bussupp.c:1353
_In_ PDEVICE_OBJECT DeviceObject
Definition: wdfdevice.h:2055
NTSTATUS NTAPI HalpSetupPciDeviceForDebugging(IN PVOID LoaderBlock, IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Definition: pci.c:473
ULONG NTAPI HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: pcibus.c:532
#define PCI_STATUS_DEVSEL
Definition: iotypes.h:3634
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
BOOLEAN NTAPI HalpTranslateIsaBusAddress(PBUS_HANDLER BusHandler, ULONG BusNumber, PHYSICAL_ADDRESS BusAddress, PULONG AddressSpace, PPHYSICAL_ADDRESS TranslatedAddress)
Definition: isa.c:37
#define FALSE
Definition: types.h:117
ULONG SystemAddressSpace
Definition: haltypes.h:196
PVOID NTAPI HalpMapPhysicalMemory64(IN PHYSICAL_ADDRESS PhysicalAddress, IN ULONG NumberPage)
Definition: misc.c:28
#define PCI_ADDRESS_MEMORY_ADDRESS_MASK
Definition: iotypes.h:4233
NTSTATUS NTAPI HalpOpenRegistryKey(IN PHANDLE KeyHandle, IN HANDLE RootKey, IN PUNICODE_STRING KeyName, IN ACCESS_MASK DesiredAccess, IN BOOLEAN Create)
Definition: misc.c:104
BOOLEAN NTAPI HalpTranslateSystemBusAddress(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: sysbus.c:21
VOID NTAPI HalpUnmapVirtualAddressVista(IN PVOID VirtualAddress, IN PFN_COUNT PageCount, IN BOOLEAN FlushCurrentTLB)
Definition: memory.c:227
PciPin2Line Pin2Line
Definition: iotypes.h:5282
NTSTATUS NTAPI HalAssignSlotResources(IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject, IN INTERFACE_TYPE BusType, IN ULONG BusNumber, IN ULONG SlotNumber, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: bussupp.c:1415
NTSTATUS NTAPI HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER PciSlot, OUT PSUPPORTED_RANGE *Range)
Definition: pcibus.c:574
FORCEINLINE VOID KeInitializeSpinLock(_Out_ PKSPIN_LOCK SpinLock)
Definition: kefuncs.h:238
#define HALP_HACK_FLAGS(x)
Definition: halp.h:145
KAFFINITY * PKAFFINITY
Definition: basetsd.h:197
VOID NTAPI HalpInitBusHandlers(VOID)
Definition: bussupp.c:1212
unsigned char BOOLEAN
VOID NTAPI HalpGetNMICrashFlag(VOID)
Definition: usage.c:587
static WCHAR Address[46]
Definition: ping.c:68
Definition: bufpool.h:45
#define VECTOR2IRQL(vector)
Definition: halirq.h:26
CODE_SEG("INIT")
Definition: Interface.c:1810
void * PVOID
Definition: retypes.h:9
_Must_inspect_result_ _In_ WDFDEVICE _In_ PCUNICODE_STRING KeyName
Definition: wdfdevice.h:2697
ULONG NTAPI HalGetInterruptVector(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: bussupp.c:1510
struct _BUS_HANDLER * ParentHandler
Definition: haltypes.h:228
PFLT_MESSAGE_WAITER_QUEUE CONTAINING_RECORD(Csq, DEVICE_EXTENSION, IrpQueue)) -> WaiterQ.mLock) _IRQL_raises_(DISPATCH_LEVEL) VOID NTAPI FltpAcquireMessageWaiterLock(_In_ PIO_CSQ Csq, _Out_ PKIRQL Irql)
Definition: Messaging.c:560
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE _In_ ULONG BusNumber
Definition: halfuncs.h:156
#define b
Definition: ke_i.h:79
PCI_CONFIG_HANDLER PCIConfigHandlerType1
Definition: pci.c:32
_Must_inspect_result_ _In_ PDRIVER_OBJECT DriverObject
Definition: wdfdriver.h:213
#define PCI_TYPE1_DATA_PORT
Definition: bus.h:165
VOID NTAPI HalpDebugPciDumpBus(IN ULONG i, IN ULONG j, IN ULONG k, IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:788
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
#define HAL_PCI_CHIP_HACK_BROKEN_ACPI_TIMER
Definition: haltypes.h:252
Status
Definition: gdiplustypes.h:24
struct _LIST_ENTRY * Flink
Definition: typedefs.h:121
#define HALP_CARD_FEATURE_FULL_DECODE
Definition: halp.h:150
#define STATUS_NOT_FOUND
Definition: shellext.h:72
#define HAL_PCI_CHIP_HACK_USB_SMI_DISABLE
Definition: haltypes.h:255
GLboolean GLboolean GLboolean b
Definition: glext.h:6204
VOID NTAPI HalpReadPCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pci.c:255
_Must_inspect_result_ _In_ ULONG Flags
Definition: wsk.h:170
ULONG HalpBusType
Definition: bus.c:17
#define PCI_INVALID_VENDORID
Definition: iotypes.h:3600
ULONG BusNumber
Definition: haltypes.h:226
Definition: miniport.h:89
PBUS_HANDLER FASTCALL HaliReferenceHandlerForConfigSpace(IN BUS_DATA_TYPE ConfigType, IN ULONG BusNumber)
Definition: bushndlr.c:197
#define ASSERT(a)
Definition: mode.c:45
BOOLEAN NTAPI HaliFindBusAddressTranslation(IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress, IN OUT PULONG_PTR Context, IN BOOLEAN NextBus)
Definition: bussupp.c:1279
__wchar_t WCHAR
Definition: xmlstorage.h:180
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:32
PciReadWriteConfig ReadConfig
Definition: iotypes.h:5280
static BOOLEAN WarningsGiven[5]
Definition: bussupp.c:423
VOID NTAPI HalpRegisterKdSupportFunctions(VOID)
Definition: bussupp.c:1221
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3617
#define PCI_MAX_DEVICES
Definition: iotypes.h:3597
#define MACHINE_TYPE_ISA
Definition: ketypes.h:52
PBUS_HANDLER NTAPI HalpAllocateBusHandler(IN INTERFACE_TYPE InterfaceType, IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN INTERFACE_TYPE ParentBusInterfaceType, IN ULONG ParentBusNumber, IN ULONG BusSpecificData)
Definition: bussupp.c:110
PTRANSLATEBUSADDRESS TranslateBusAddress
Definition: haltypes.h:238
#define PCI_DEVICE_TYPE
Definition: iotypes.h:3604
_In_ ULONG _In_ ULONG _In_ ULONG _Out_ PKIRQL _Out_ PKAFFINITY Affinity
Definition: halfuncs.h:170
struct _PCI_SLOT_NUMBER::@3802::@3803 bits
#define HALP_CHECK_CARD_REVISION_ID
Definition: halp.h:155
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING ValueName
Definition: wdfregistry.h:240
unsigned char UCHAR
Definition: xmlstorage.h:181
#define PCI_STATUS_66MHZ_CAPABLE
Definition: iotypes.h:3630
#define PCI_DATA_VERSION
Definition: iotypes.h:5275
VOID NTAPI ShowSize(IN ULONG Size)
PASSIGNSLOTRESOURCES AssignSlotResources
Definition: haltypes.h:236
static const WCHAR L[]
Definition: oid.c:1250
#define TAG_HAL
Definition: hal.h:61
BOOLEAN NTAPI HalpIsBridgeDevice(IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:626
#define KdMapPhysicalMemory64
Definition: halfuncs.h:52
KIRQL * PKIRQL
Definition: env_spec_w32.h:592
#define PCI_SUBCLASS_BR_PCI_TO_PCI
Definition: iotypes.h:4164
NTSTATUS NTAPI HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList)
Definition: pcibus.c:675
Definition: typedefs.h:119
BOOLEAN NTAPI HalpIsIdeDevice(IN PPCI_COMMON_CONFIG PciData)
Definition: bussupp.c:573
VOID NTAPI HalpUnmapVirtualAddress(IN PVOID VirtualAddress, IN ULONG NumberPages)
Definition: misc.c:39
#define PCI_SUBCLASS_MSC_IDE_CTLR
Definition: iotypes.h:4128
PPCI_REGISTRY_INFO_INTERNAL NTAPI HalpQueryPciRegistryInfo(VOID)
Definition: pci.c:543
_In_opt_ PENTER_STATE_SYSTEM_HANDLER _In_opt_ PVOID _In_ LONG _In_opt_ LONG volatile * Number
Definition: ntpoapi.h:204
#define PCI_TYPE2_CSE_PORT
Definition: bus.h:170
ACPI_PHYSICAL_ADDRESS ACPI_SIZE BOOLEAN Warn BOOLEAN Physical UINT32 ACPI_TABLE_HEADER *OutTableHeader ACPI_TABLE_HEADER **OutTable ACPI_HANDLE UINT32 ACPI_WALK_CALLBACK ACPI_WALK_CALLBACK void void **ReturnValue UINT32 ACPI_BUFFER *RetPathPtr ACPI_OBJECT_HANDLER Handler
Definition: acpixf.h:668
#define KdSetupPciDeviceForDebugging
Definition: halfuncs.h:47
ULONG NTAPI HalSetBusData(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
Definition: bussupp.c:1556
struct _PCIPBUSDATA::@1433::@1434 Type1
NTSTATUS NTAPI HalAdjustResourceList(IN PIO_RESOURCE_REQUIREMENTS_LIST *ResourceList)
Definition: bussupp.c:1389
ULONG NTAPI HalpGetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER Slot, IN PUCHAR Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pci.c:338
#define PCI_MAX_FUNCTION
Definition: iotypes.h:3598
NTSTATUS NTAPI HalpGetChipHacks(IN USHORT VendorId, IN USHORT DeviceId, IN UCHAR RevisionId, IN PULONG HackFlags)
Definition: bussupp.c:428
ULONG NTAPI HalpSetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER Slot, IN PUCHAR Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pci.c:409
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
NTSTATUS NTAPI HalpReleasePciDeviceForDebugging(IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Definition: pci.c:482
BUS_HANDLER Handler
Definition: bus.h:274
ULONG NTAPI HalpGetSystemInterruptVector(IN ULONG BusNumber, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
Definition: bus.c:84
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
#define PCI_TYPE_64BIT
Definition: iotypes.h:4238
unsigned short USHORT
Definition: pedump.c:61
#define KEY_ALL_ACCESS
Definition: nt_native.h:1041
_In_ PKSERVICE_ROUTINE _In_opt_ PVOID _In_opt_ PKSPIN_LOCK _In_ ULONG Vector
Definition: iofuncs.h:800
VOID NTAPI HalpInitializePciBus(VOID)
Definition: bussupp.c:973
PBUS_HANDLER NTAPI HalpAllocateAndInitPciBusHandler(IN ULONG PciType, IN ULONG BusNo, IN BOOLEAN TestAllocation)
Definition: bussupp.c:281
NTSTATUS NTAPI HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName OPTIONAL, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject OPTIONAL, IN ULONG Slot, IN OUT PCM_RESOURCE_LIST *pAllocatedResources)
Definition: pci.c:490
ULONG KSPIN_LOCK
Definition: env_spec_w32.h:72
PGETSETBUSDATA SetBusData
Definition: haltypes.h:234
PGETINTERRUPTVECTOR GetInterruptVector
Definition: haltypes.h:237
BOOLEAN NTAPI HalTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bussupp.c:1608
ULONG NTAPI HalpcGetCmosData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: cmosbus.c:21
BOOLEAN NTAPI HalpIsRecognizedCard(IN PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo, IN PPCI_COMMON_CONFIG PciData, IN ULONG Flags)
Definition: bussupp.c:492
ULONG Version
Definition: iotypes.h:5279
PciLine2Pin Line2Pin
Definition: iotypes.h:5283
unsigned int * PULONG
Definition: retypes.h:1
#define NULL
Definition: types.h:112
VOID NTAPI HalpFixupPciSupportedRanges(IN ULONG BusCount)
Definition: bussupp.c:693
#define DPRINT1
Definition: precomp.h:8
PBUS_HANDLER NTAPI HalpContextToBusHandler(IN ULONG_PTR ContextValue)
Definition: bushndlr.c:206
#define KdCheckPowerButton
Definition: halfuncs.h:50
static const char VendorName[]
Definition: ParaNdis-Oid.c:36
SUPPORTED_RANGE Memory
Definition: haltypes.h:210
#define HALP_REVISION_HACK_FLAGS(x)
Definition: halp.h:144
struct _PCIPBUSDATA * PPCIPBUSDATA
_In_ HANDLE Handle
Definition: extypes.h:390
struct tagContext Context
Definition: acpixf.h:1034
#define OUT
Definition: typedefs.h:40
#define KdReleasePciDeviceforDebugging
Definition: halfuncs.h:48
#define PCI_ADDRESS_MEMORY_PREFETCHABLE
Definition: iotypes.h:4231
INTERFACE_TYPE InterfaceType
Definition: haltypes.h:224
#define PCI_CONFIGURATION_TYPE(PciData)
Definition: iotypes.h:3608
unsigned int ULONG
Definition: retypes.h:1
LIST_ENTRY HalpAllBusHandlers
Definition: bushndlr.c:19
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
#define HalPciAssignSlotResources
Definition: halfuncs.h:42
#define ULONG_PTR
Definition: config.h:101
uint32_t * PULONG_PTR
Definition: typedefs.h:65
#define InitializeObjectAttributes(p, n, a, r, s)
Definition: reg.c:106
#define RtlCopyMemory(Destination, Source, Length)
Definition: typedefs.h:263
_Must_inspect_result_ _In_ WDFDEVICE _In_ DEVICE_REGISTRY_PROPERTY _In_ ULONG _Out_ PULONG ResultLength
Definition: wdfdevice.h:3776
PGETSETBUSDATA GetBusData
Definition: haltypes.h:233
PADJUSTRESOURCELIST AdjustResourceList
Definition: haltypes.h:235
#define PCI_CLASS_BRIDGE_DEV
Definition: iotypes.h:4108
RTL_BITMAP DeviceConfigured
Definition: bus.h:117
#define STATUS_SUCCESS
Definition: shellext.h:65
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1099
#define IRQ2VECTOR(irq)
Definition: halirq.h:27
LIST_ENTRY AllHandlers
Definition: bus.h:272
_In_ ULONG_PTR HackFlags
Definition: cdrom.h:983
GLfloat GLfloat p
Definition: glext.h:8902
#define DPRINT
Definition: sndvol32.h:71
SUPPORTED_RANGE Dma
Definition: haltypes.h:214
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:4229
#define HalHandlerForBus
Definition: halfuncs.h:35
USHORT DeviceID
Definition: pci.h:120
#define REG_DWORD
Definition: sdbapi.c:596
PciIrqRange GetIrqRange
Definition: bus.h:111
#define PCI_TYPE2_ADDRESS_BASE
Definition: bus.h:172
int k
Definition: mpi.c:3369
BOOLEAN NTAPI HalpGetPciBridgeConfig(IN ULONG PciType, IN PUCHAR BusCount)
Definition: bussupp.c:640
PVOID BusData
Definition: haltypes.h:229
ULONG NTAPI HalGetBusData(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Length)
Definition: bussupp.c:1458
_Must_inspect_result_ _In_ WDFDEVICE _In_ LPCGUID InterfaceType
Definition: wdffdo.h:461
USHORT VendorID
Definition: pci.h:119
#define PCI_CARDBUS_BRIDGE_TYPE
Definition: iotypes.h:3606
ULONG ConfiguredBits[PCI_MAX_DEVICES *PCI_MAX_FUNCTION/32]
Definition: bus.h:118
#define PCI_CLASS_MASS_STORAGE_CTLR
Definition: iotypes.h:4103
#define PAGED_CODE()
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3593
USHORT RevisionID
Definition: pci.h:121
#define PCI_BRIDGE_TYPE
Definition: iotypes.h:3605
PCI_CONFIG_HANDLER PCIConfigHandler
Definition: pci.c:20