ReactOS  0.4.14-dev-583-g2a1ba2c
pcibus.c
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1 /*
2  * PROJECT: ReactOS HAL
3  * LICENSE: GPL - See COPYING in the top level directory
4  * FILE: hal/halx86/legacy/bus/pcibus.c
5  * PURPOSE: PCI Bus Support (Configuration Space, Resource Allocation)
6  * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
7  */
8 
9 /* INCLUDES ******************************************************************/
10 
11 #include <hal.h>
12 #define NDEBUG
13 #include <debug.h>
14 
15 #if defined(ALLOC_PRAGMA) && !defined(_MINIHAL_)
16 #pragma alloc_text(INIT, HalpInitializePciStubs)
17 #pragma alloc_text(INIT, HalpQueryPciRegistryInfo)
18 #pragma alloc_text(INIT, HalpRegisterPciDebuggingDeviceInfo)
19 #pragma alloc_text(INIT, HalpReleasePciDeviceForDebugging)
20 #pragma alloc_text(INIT, HalpSetupPciDeviceForDebugging)
21 #endif
22 
23 /* GLOBALS *******************************************************************/
24 
27 
29 
34 
35 /* PCI Operation Matrix */
36 UCHAR PCIDeref[4][4] =
37 {
38  {0, 1, 2, 2}, // ULONG-aligned offset
39  {1, 1, 1, 1}, // UCHAR-aligned offset
40  {2, 1, 2, 2}, // USHORT-aligned offset
41  {1, 1, 1, 1} // UCHAR-aligned offset
42 };
43 
44 /* Type 1 PCI Bus */
46 {
47  /* Synchronization */
50 
51  /* Read */
52  {
53  (FncConfigIO)HalpPCIReadUlongType1,
54  (FncConfigIO)HalpPCIReadUcharType1,
55  (FncConfigIO)HalpPCIReadUshortType1
56  },
57 
58  /* Write */
59  {
60  (FncConfigIO)HalpPCIWriteUlongType1,
61  (FncConfigIO)HalpPCIWriteUcharType1,
62  (FncConfigIO)HalpPCIWriteUshortType1
63  }
64 };
65 
66 /* Type 2 PCI Bus */
68 {
69  /* Synchronization */
72 
73  /* Read */
74  {
75  (FncConfigIO)HalpPCIReadUlongType2,
76  (FncConfigIO)HalpPCIReadUcharType2,
77  (FncConfigIO)HalpPCIReadUshortType2
78  },
79 
80  /* Write */
81  {
82  (FncConfigIO)HalpPCIWriteUlongType2,
83  (FncConfigIO)HalpPCIWriteUcharType2,
84  (FncConfigIO)HalpPCIWriteUshortType2
85  }
86 };
87 
89 {
90  {
95  NULL,
96  NULL,
97  {{{0, 0, 0}}},
98  {0, 0, 0, 0}
99  },
100  {{0, 0}},
101  32,
102 };
103 
105 {
106  1,
107  PCIBus,
109  0,
110  NULL,
111  NULL,
113  0,
114  NULL,
115  {0, 0, 0, 0},
118  NULL,
120  NULL,
121  NULL
122 };
123 
124 /* TYPE 1 FUNCTIONS **********************************************************/
125 
126 VOID
127 NTAPI
129  IN PCI_SLOT_NUMBER Slot,
130  IN PKIRQL Irql,
131  IN PPCI_TYPE1_CFG_BITS PciCfg1)
132 {
133  /* Setup the PCI Configuration Register */
134  PciCfg1->u.AsULONG = 0;
135  PciCfg1->u.bits.BusNumber = BusHandler->BusNumber;
136  PciCfg1->u.bits.DeviceNumber = Slot.u.bits.DeviceNumber;
137  PciCfg1->u.bits.FunctionNumber = Slot.u.bits.FunctionNumber;
138  PciCfg1->u.bits.Enable = TRUE;
139 
140  /* Acquire the lock */
143 }
144 
145 VOID
146 NTAPI
148  IN KIRQL Irql)
149 {
150  PCI_TYPE1_CFG_BITS PciCfg1;
151 
152  /* Clear the PCI Configuration Register */
153  PciCfg1.u.AsULONG = 0;
154  WRITE_PORT_ULONG(((PPCIPBUSDATA)BusHandler->BusData)->Config.Type1.Address,
155  PciCfg1.u.AsULONG);
156 
157  /* Release the lock */
159  KeLowerIrql(Irql);
160 }
161 
162 TYPE1_READ(HalpPCIReadUcharType1, UCHAR)
163 TYPE1_READ(HalpPCIReadUshortType1, USHORT)
164 TYPE1_READ(HalpPCIReadUlongType1, ULONG)
165 TYPE1_WRITE(HalpPCIWriteUcharType1, UCHAR)
166 TYPE1_WRITE(HalpPCIWriteUshortType1, USHORT)
167 TYPE1_WRITE(HalpPCIWriteUlongType1, ULONG)
168 
169 /* TYPE 2 FUNCTIONS **********************************************************/
170 
171 VOID
172 NTAPI
174  IN PCI_SLOT_NUMBER Slot,
175  IN PKIRQL Irql,
177 {
178  PCI_TYPE2_CSE_BITS PciCfg2Cse;
179  PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
180 
181  /* Setup the configuration register */
182  PciCfg->u.AsUSHORT = 0;
183  PciCfg->u.bits.Agent = (USHORT)Slot.u.bits.DeviceNumber;
184  PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
185 
186  /* Acquire the lock */
189 
190  /* Setup the CSE Register */
191  PciCfg2Cse.u.AsUCHAR = 0;
192  PciCfg2Cse.u.bits.Enable = TRUE;
193  PciCfg2Cse.u.bits.FunctionNumber = (UCHAR)Slot.u.bits.FunctionNumber;
194  PciCfg2Cse.u.bits.Key = -1;
195 
196  /* Write the bus number and CSE */
197  WRITE_PORT_UCHAR(BusData->Config.Type2.Forward,
198  (UCHAR)BusHandler->BusNumber);
199  WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
200 }
201 
202 VOID
203 NTAPI
205  IN KIRQL Irql)
206 {
207  PCI_TYPE2_CSE_BITS PciCfg2Cse;
208  PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
209 
210  /* Clear CSE and bus number */
211  PciCfg2Cse.u.AsUCHAR = 0;
212  WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
213  WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
214 
215  /* Release the lock */
217  KeLowerIrql(Irql);
218 }
219 
220 TYPE2_READ(HalpPCIReadUcharType2, UCHAR)
221 TYPE2_READ(HalpPCIReadUshortType2, USHORT)
222 TYPE2_READ(HalpPCIReadUlongType2, ULONG)
223 TYPE2_WRITE(HalpPCIWriteUcharType2, UCHAR)
224 TYPE2_WRITE(HalpPCIWriteUshortType2, USHORT)
225 TYPE2_WRITE(HalpPCIWriteUlongType2, ULONG)
226 
227 /* PCI CONFIGURATION SPACE ***************************************************/
228 
229 VOID
230 NTAPI
232  IN PCI_SLOT_NUMBER Slot,
233  IN PUCHAR Buffer,
234  IN ULONG Offset,
235  IN ULONG Length,
236  IN FncConfigIO *ConfigIO)
237 {
238  KIRQL OldIrql;
239  ULONG i;
240  UCHAR State[20];
241 
242  /* Synchronize the operation */
243  PCIConfigHandler.Synchronize(BusHandler, Slot, &OldIrql, State);
244 
245  /* Loop every increment */
246  while (Length)
247  {
248  /* Find out the type of read/write we need to do */
249  i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
250 
251  /* Do the read/write and return the number of bytes */
252  i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
253  State,
254  Buffer,
255  Offset);
256 
257  /* Increment the buffer position and offset, and decrease the length */
258  Offset += i;
259  Buffer += i;
260  Length -= i;
261  }
262 
263  /* Release the lock and PCI bus */
265 }
266 
267 VOID
268 NTAPI
270  IN PCI_SLOT_NUMBER Slot,
271  IN PVOID Buffer,
272  IN ULONG Offset,
273  IN ULONG Length)
274 {
275  /* Validate the PCI Slot */
276  if (!HalpValidPCISlot(BusHandler, Slot))
277  {
278  /* Fill the buffer with invalid data */
280  }
281  else
282  {
283  /* Send the request */
284  HalpPCIConfig(BusHandler,
285  Slot,
286  Buffer,
287  Offset,
288  Length,
290  }
291 }
292 
293 VOID
294 NTAPI
296  IN PCI_SLOT_NUMBER Slot,
297  IN PVOID Buffer,
298  IN ULONG Offset,
299  IN ULONG Length)
300 {
301  /* Validate the PCI Slot */
302  if (HalpValidPCISlot(BusHandler, Slot))
303  {
304  /* Send the request */
305  HalpPCIConfig(BusHandler,
306  Slot,
307  Buffer,
308  Offset,
309  Length,
311  }
312 }
313 
314 #ifdef SARCH_XBOX
315 BOOLEAN
316 NTAPI
317 HalpXboxBlacklistedPCISlot(IN PBUS_HANDLER BusHandler,
318  IN PCI_SLOT_NUMBER Slot)
319 {
320  /* Trying to get PCI config data from devices 0:0:1 and 0:0:2 will completely
321  * hang the Xbox. Also, the device number doesn't seem to be decoded for the
322  * video card, so it appears to be present on 1:0:0 - 1:31:0.
323  * We hack around these problems by indicating "device not present" for devices
324  * 0:0:1, 0:0:2, 1:1:0, 1:2:0, 1:3:0, ...., 1:31:0 */
325  if ((BusHandler->BusNumber == 0 && Slot.u.bits.DeviceNumber == 0 &&
326  (Slot.u.bits.FunctionNumber == 1 || Slot.u.bits.FunctionNumber == 2)) ||
327  (BusHandler->BusNumber == 1 && Slot.u.bits.DeviceNumber != 0))
328  {
329  DPRINT("Blacklisted PCI slot (%d:%d:%d)\n", BusHandler->BusNumber, Slot.u.bits.DeviceNumber, Slot.u.bits.FunctionNumber);
330  return TRUE;
331  }
332 
333  /* Temporary hack to avoid stack overflow in kernel, see CORE-16319 */
334  if (BusHandler->BusNumber == 0 && Slot.u.bits.DeviceNumber == 8 && Slot.u.bits.FunctionNumber == 0)
335  {
336  DPRINT("Blacklisted PCI-to-PCI bridge (00:08.0 - PCI\\VEN_10DE&DEV_01B8, see CORE-16319)\n");
337  return TRUE;
338  }
339 
340  return FALSE;
341 }
342 #endif
343 
344 BOOLEAN
345 NTAPI
347  IN PCI_SLOT_NUMBER Slot)
348 {
349  PCI_SLOT_NUMBER MultiSlot;
350  PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
351  UCHAR HeaderType;
352  //ULONG Device;
353 
354  /* Simple validation */
355  if (Slot.u.bits.Reserved) return FALSE;
356  if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice) return FALSE;
357 
358 #ifdef SARCH_XBOX
359  if (HalpXboxBlacklistedPCISlot(BusHandler, Slot)) return FALSE;
360 #endif
361 
362  /* Function 0 doesn't need checking */
363  if (!Slot.u.bits.FunctionNumber) return TRUE;
364 
365  /* Functions 0+ need Multi-Function support, so check the slot */
366  //Device = Slot.u.bits.DeviceNumber;
367  MultiSlot = Slot;
368  MultiSlot.u.bits.FunctionNumber = 0;
369 
370  /* Send function 0 request to get the header back */
371  HalpReadPCIConfig(BusHandler,
372  MultiSlot,
373  &HeaderType,
374  FIELD_OFFSET(PCI_COMMON_CONFIG, HeaderType),
375  sizeof(UCHAR));
376 
377  /* Now make sure the header is multi-function */
378  if (!(HeaderType & PCI_MULTIFUNCTION) || (HeaderType == 0xFF)) return FALSE;
379  return TRUE;
380 }
381 
382 /* HAL PCI CALLBACKS *********************************************************/
383 
384 ULONG
385 NTAPI
387  IN PBUS_HANDLER RootHandler,
389  IN PVOID Buffer,
390  IN ULONG Offset,
391  IN ULONG Length)
392 {
393  PCI_SLOT_NUMBER Slot;
394  UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
395  PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
396  ULONG Len = 0;
397 
398  Slot.u.AsULONG = SlotNumber;
399 #ifdef SARCH_XBOX
400  if (HalpXboxBlacklistedPCISlot(BusHandler, Slot))
401  {
402  if (Offset == 0 && Length >= sizeof(USHORT))
403  {
405  return sizeof(USHORT);
406  }
407  return 0;
408  }
409 #endif
410 
411  /* Normalize the length */
412  if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
413 
414  /* Check if this is a vendor-specific read */
416  {
417  /* Read the header */
418  HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
419 
420  /* Make sure the vendor is valid */
421  if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
422  }
423  else
424  {
425  /* Read the entire header */
427  HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
428 
429  /* Validate the vendor ID */
430  if (PciConfig->VendorID == PCI_INVALID_VENDORID)
431  {
432  /* It's invalid, but we want to return this much */
433  Len = sizeof(USHORT);
434  }
435 
436  /* Now check if there's space left */
437  if (Len < Offset) return 0;
438 
439  /* There is, so return what's after the offset and normalize */
440  Len -= Offset;
441  if (Len > Length) Len = Length;
442 
443  /* Copy the data into the caller's buffer */
444  RtlMoveMemory(Buffer, PciBuffer + Offset, Len);
445 
446  /* Update buffer and offset, decrement total length */
447  Offset += Len;
448  Buffer = (PVOID)((ULONG_PTR)Buffer + Len);
449  Length -= Len;
450  }
451 
452  /* Now we still have something to copy */
453  if (Length)
454  {
455  /* Check if it's vendor-specific data */
457  {
458  /* Read it now */
459  HalpReadPCIConfig(BusHandler, Slot, Buffer, Offset, Length);
460  Len += Length;
461  }
462  }
463 
464  /* Update the total length read */
465  return Len;
466 }
467 
468 ULONG
469 NTAPI
471  IN PBUS_HANDLER RootHandler,
473  IN PVOID Buffer,
474  IN ULONG Offset,
475  IN ULONG Length)
476 {
477  PCI_SLOT_NUMBER Slot;
478  UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
479  PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
480  ULONG Len = 0;
481 
482  Slot.u.AsULONG = SlotNumber;
483 #ifdef SARCH_XBOX
484  if (HalpXboxBlacklistedPCISlot(BusHandler, Slot)) return 0;
485 #endif
486 
487  /* Normalize the length */
488  if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
489 
490  /* Check if this is a vendor-specific read */
492  {
493  /* Read the header */
494  HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
495 
496  /* Make sure the vendor is valid */
497  if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
498  }
499  else
500  {
501  /* Read the entire header and validate the vendor ID */
503  HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
504  if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
505 
506  /* Return what's after the offset and normalize */
507  Len -= Offset;
508  if (Len > Length) Len = Length;
509 
510  /* Copy the specific caller data */
511  RtlMoveMemory(PciBuffer + Offset, Buffer, Len);
512 
513  /* Write the actual configuration data */
514  HalpWritePCIConfig(BusHandler, Slot, PciBuffer + Offset, Offset, Len);
515 
516  /* Update buffer and offset, decrement total length */
517  Offset += Len;
518  Buffer = (PVOID)((ULONG_PTR)Buffer + Len);
519  Length -= Len;
520  }
521 
522  /* Now we still have something to copy */
523  if (Length)
524  {
525  /* Check if it's vendor-specific data */
527  {
528  /* Read it now */
529  HalpWritePCIConfig(BusHandler, Slot, Buffer, Offset, Length);
530  Len += Length;
531  }
532  }
533 
534  /* Update the total length read */
535  return Len;
536 }
537 
538 ULONG
539 NTAPI
541  IN PBUS_HANDLER RootHandler,
544  OUT PKIRQL Irql,
546 {
547  /* Validate the level first */
548  if (BusInterruptLevel < 1) return 0;
549 
550  /* PCI has its IRQs on top of ISA IRQs, so pass it on to the ISA handler */
551  return HalGetInterruptVector(Isa,
552  0,
554  0,
555  Irql,
556  Affinity);
557 }
558 
559 VOID
560 NTAPI
562  IN PBUS_HANDLER RootHandler,
564  IN PPCI_COMMON_CONFIG PciData)
565 {
567 }
568 
569 VOID
570 NTAPI
572  IN PBUS_HANDLER RootHandler,
574  IN PPCI_COMMON_CONFIG PciNewData,
575  IN PPCI_COMMON_CONFIG PciOldData)
576 {
578 }
579 
580 NTSTATUS
581 NTAPI
583  IN PBUS_HANDLER RootHandler,
584  IN PCI_SLOT_NUMBER PciSlot,
586 {
587  PCI_COMMON_HEADER PciData;
588 
589  /* Read PCI configuration data */
591  BusHandler->BusNumber,
592  PciSlot.u.AsULONG,
593  &PciData,
595 
596  /* Make sure it's a real device */
597  if (PciData.VendorID == PCI_INVALID_VENDORID) return STATUS_UNSUCCESSFUL;
598 
599  /* Allocate the supported range structure */
601  if (!*Range) return STATUS_INSUFFICIENT_RESOURCES;
602 
603  /* Set it up */
605  (*Range)->Base = 1;
606 
607  /* If the PCI device has no IRQ, nothing to do */
608  if (!PciData.u.type0.InterruptPin) return STATUS_SUCCESS;
609 
610  /* FIXME: The PCI IRQ Routing Miniport should be called */
611 
612  /* Also if the INT# seems bogus, nothing to do either */
613  if ((PciData.u.type0.InterruptLine == 0) ||
614  (PciData.u.type0.InterruptLine == 255))
615  {
616  /* Fake success */
617  return STATUS_SUCCESS;
618  }
619 
620  /* Otherwise, the INT# should be valid, return it to the caller */
621  (*Range)->Base = PciData.u.type0.InterruptLine;
622  (*Range)->Limit = PciData.u.type0.InterruptLine;
623  return STATUS_SUCCESS;
624 }
625 
626 INIT_FUNCTION
627 NTSTATUS
628 NTAPI
630  IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
631 {
632  DPRINT1("Unimplemented!\n");
633  return STATUS_NOT_IMPLEMENTED;
634 }
635 
636 INIT_FUNCTION
637 NTSTATUS
638 NTAPI
640 {
641  DPRINT1("Unimplemented!\n");
642  return STATUS_NOT_IMPLEMENTED;
643 }
644 
645 INIT_FUNCTION
646 VOID
647 NTAPI
649 {
650  BOOLEAN Found = FALSE;
651  ULONG i;
652  PAGED_CODE();
653 
654  /* Loop PCI debugging devices */
655  for (i = 0; i < 2; i++)
656  {
657  /* Reserved bit is set if we found one */
658  if (HalpPciDebuggingDevice[i].u.bits.Reserved1)
659  {
660  Found = TRUE;
661  break;
662  }
663  }
664 
665  /* Bail out if there aren't any */
666  if (!Found) return;
667 
668  /* FIXME: TODO */
669  UNIMPLEMENTED_DBGBREAK("You have implemented the KD routines for searching PCI debugger"
670  "devices, but you have forgotten to implement this routine\n");
671 }
672 
673 static ULONG NTAPI
675 {
676  ULONG Size = Mask & Base; /* Find the significant bits */
677  Size = Size & ~(Size - 1); /* Get the lowest of them to find the decode size */
678  return Size;
679 }
680 
681 NTSTATUS
682 NTAPI
684  IN PBUS_HANDLER RootHandler,
685  IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList)
686 {
687  PPCIPBUSDATA BusData;
689  PSUPPORTED_RANGE Interrupt;
691 
692  /* Get PCI bus data */
693  BusData = BusHandler->BusData;
694  SlotNumber.u.AsULONG = (*pResourceList)->SlotNumber;
695 
696  /* Get the IRQ supported range */
697  Status = BusData->GetIrqRange(BusHandler, RootHandler, SlotNumber, &Interrupt);
698  if (!NT_SUCCESS(Status)) return Status;
699 #ifndef _MINIHAL_
700  /* Handle the /PCILOCK feature */
702  {
703  /* /PCILOCK is not yet supported */
704  UNIMPLEMENTED_DBGBREAK("/PCILOCK boot switch is not yet supported.");
705  }
706 #endif
707  /* Now create the correct resource list based on the supported bus ranges */
708 #if 0
709  Status = HaliAdjustResourceListRange(BusHandler->BusAddresses,
710  Interrupt,
711  pResourceList);
712 #else
713  DPRINT1("HAL: No PCI Resource Adjustment done! Hardware may malfunction\n");
715 #endif
716 
717  /* Return to caller */
718  ExFreePool(Interrupt);
719  return Status;
720 }
721 
722 NTSTATUS
723 NTAPI
725  IN PBUS_HANDLER RootHandler,
730  IN ULONG Slot,
732 {
733  PCI_COMMON_CONFIG PciConfig;
734  SIZE_T Address;
738  UCHAR Offset;
742  DPRINT1("WARNING: PCI Slot Resource Assignment is FOOBAR\n");
743 
744  /* FIXME: Should handle 64-bit addresses */
745 
746  /* Read configuration data */
747  SlotNumber.u.AsULONG = Slot;
748  HalpReadPCIConfig(BusHandler, SlotNumber, &PciConfig, 0, PCI_COMMON_HDR_LENGTH);
749 
750  /* Check if we read it correctly */
751  if (PciConfig.VendorID == PCI_INVALID_VENDORID)
752  return STATUS_NO_SUCH_DEVICE;
753 
754  /* Read the PCI configuration space for the device and store base address and
755  size information in temporary storage. Count the number of valid base addresses */
756  ResourceCount = 0;
758  {
759  if (0xffffffff == PciConfig.u.type0.BaseAddresses[Address])
760  PciConfig.u.type0.BaseAddresses[Address] = 0;
761 
762  /* Memory resource */
763  if (0 != PciConfig.u.type0.BaseAddresses[Address])
764  {
765  ResourceCount++;
766 
767  Offset = (UCHAR)FIELD_OFFSET(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
768 
769  /* Write 0xFFFFFFFF there */
770  WriteBuffer = 0xffffffff;
771  HalpWritePCIConfig(BusHandler, SlotNumber, &WriteBuffer, Offset, sizeof(ULONG));
772 
773  /* Read that figure back from the config space */
774  HalpReadPCIConfig(BusHandler, SlotNumber, &Size[Address], Offset, sizeof(ULONG));
775 
776  /* Write back initial value */
777  HalpWritePCIConfig(BusHandler, SlotNumber, &PciConfig.u.type0.BaseAddresses[Address], Offset, sizeof(ULONG));
778  }
779  }
780 
781  /* Interrupt resource */
782  if (0 != PciConfig.u.type0.InterruptPin &&
783  0 != PciConfig.u.type0.InterruptLine &&
784  0xFF != PciConfig.u.type0.InterruptLine)
785  ResourceCount++;
786 
787  /* Allocate output buffer and initialize */
789  PagedPool,
790  sizeof(CM_RESOURCE_LIST) +
792  TAG_HAL);
793 
794  if (NULL == *AllocatedResources)
795  return STATUS_NO_MEMORY;
796 
797  (*AllocatedResources)->Count = 1;
798  (*AllocatedResources)->List[0].InterfaceType = PCIBus;
799  (*AllocatedResources)->List[0].BusNumber = BusHandler->BusNumber;
800  (*AllocatedResources)->List[0].PartialResourceList.Version = 1;
801  (*AllocatedResources)->List[0].PartialResourceList.Revision = 1;
802  (*AllocatedResources)->List[0].PartialResourceList.Count = ResourceCount;
803  Descriptor = (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
804 
805  /* Store configuration information */
807  {
808  if (0 != PciConfig.u.type0.BaseAddresses[Address])
809  {
811  (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
812  {
814  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
815  Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE; /* FIXME Just a guess */
816  Descriptor->u.Memory.Start.QuadPart = (PciConfig.u.type0.BaseAddresses[Address] & PCI_ADDRESS_MEMORY_ADDRESS_MASK);
818  }
819  else if (PCI_ADDRESS_IO_SPACE ==
820  (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
821  {
823  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
824  Descriptor->Flags = CM_RESOURCE_PORT_IO; /* FIXME Just a guess */
825  Descriptor->u.Port.Start.QuadPart = PciConfig.u.type0.BaseAddresses[Address] &= PCI_ADDRESS_IO_ADDRESS_MASK;
826  Descriptor->u.Port.Length = PciSize(Size[Address], PCI_ADDRESS_IO_ADDRESS_MASK & 0xffff);
827  }
828  else
829  {
830  ASSERT(FALSE);
831  return STATUS_UNSUCCESSFUL;
832  }
833  Descriptor++;
834  }
835  }
836 
837  if (0 != PciConfig.u.type0.InterruptPin &&
838  0 != PciConfig.u.type0.InterruptLine &&
839  0xFF != PciConfig.u.type0.InterruptLine)
840  {
842  Descriptor->ShareDisposition = CmResourceShareShared; /* FIXME Just a guess */
843  Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE; /* FIXME Just a guess */
844  Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
845  Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
846  Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
847 
848  Descriptor++;
849  }
850 
851  ASSERT(Descriptor == (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors + ResourceCount);
852 
853  /* FIXME: Should store the resources in the registry resource map */
854 
855  return Status;
856 }
857 
858 ULONG
859 NTAPI
863  IN PVOID Buffer,
864  IN ULONG Offset,
865  IN ULONG Length)
866 {
867  BUS_HANDLER BusHandler;
868 
869  /* Setup fake PCI Bus handler */
870  RtlCopyMemory(&BusHandler, &HalpFakePciBusHandler, sizeof(BUS_HANDLER));
871  BusHandler.BusNumber = BusNumber;
872 
873  /* Read configuration data */
875 
876  /* Return length */
877  return Length;
878 }
879 
880 INIT_FUNCTION
882 NTAPI
884 {
885 #ifndef _MINIHAL_
886  WCHAR NameBuffer[8];
888  UNICODE_STRING KeyName, ConfigName, IdentName;
889  HANDLE KeyHandle, BusKeyHandle, CardListHandle;
891  UCHAR KeyBuffer[sizeof(CM_FULL_RESOURCE_DESCRIPTOR) + 100];
892  PKEY_VALUE_FULL_INFORMATION ValueInfo = (PVOID)KeyBuffer;
893  UCHAR PartialKeyBuffer[sizeof(KEY_VALUE_PARTIAL_INFORMATION) +
894  sizeof(PCI_CARD_DESCRIPTOR)];
895  PKEY_VALUE_PARTIAL_INFORMATION PartialValueInfo = (PVOID)PartialKeyBuffer;
896  KEY_FULL_INFORMATION KeyInformation;
898  PWSTR Tag;
899  ULONG i, ElementCount;
900  PCM_FULL_RESOURCE_DESCRIPTOR FullDescriptor;
901  PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptor;
902  PPCI_REGISTRY_INFO PciRegInfo;
903  PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
904  PPCI_CARD_DESCRIPTOR CardDescriptor;
905 
906  /* Setup the object attributes for the key */
908  L"\\Registry\\Machine\\Hardware\\Description\\"
909  L"System\\MultiFunctionAdapter");
911  &KeyName,
913  NULL,
914  NULL);
915 
916  /* Open the key */
917  Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
918  if (!NT_SUCCESS(Status)) return NULL;
919 
920  /* Setup the receiving string */
921  KeyName.Buffer = NameBuffer;
922  KeyName.MaximumLength = sizeof(NameBuffer);
923 
924  /* Setup the configuration and identifier key names */
925  RtlInitUnicodeString(&ConfigName, L"Configuration Data");
926  RtlInitUnicodeString(&IdentName, L"Identifier");
927 
928  /* Keep looping for each ID */
929  for (i = 0; TRUE; i++)
930  {
931  /* Setup the key name */
934  &KeyName,
936  KeyHandle,
937  NULL);
938 
939  /* Open it */
940  Status = ZwOpenKey(&BusKeyHandle, KEY_READ, &ObjectAttributes);
941  if (!NT_SUCCESS(Status))
942  {
943  /* None left, fail */
945  return NULL;
946  }
947 
948  /* Read the registry data */
949  Status = ZwQueryValueKey(BusKeyHandle,
950  &IdentName,
952  ValueInfo,
953  sizeof(KeyBuffer),
954  &ResultLength);
955  if (!NT_SUCCESS(Status))
956  {
957  /* Failed, try the next one */
958  ZwClose(BusKeyHandle);
959  continue;
960  }
961 
962  /* Get the PCI Tag and validate it */
963  Tag = (PWSTR)((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
964  if ((Tag[0] != L'P') ||
965  (Tag[1] != L'C') ||
966  (Tag[2] != L'I') ||
967  (Tag[3]))
968  {
969  /* Not a valid PCI entry, skip it */
970  ZwClose(BusKeyHandle);
971  continue;
972  }
973 
974  /* Now read our PCI structure */
975  Status = ZwQueryValueKey(BusKeyHandle,
976  &ConfigName,
978  ValueInfo,
979  sizeof(KeyBuffer),
980  &ResultLength);
981  ZwClose(BusKeyHandle);
982  if (!NT_SUCCESS(Status)) continue;
983 
984  /* We read it OK! Get the actual resource descriptors */
985  FullDescriptor = (PCM_FULL_RESOURCE_DESCRIPTOR)
986  ((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
987  PartialDescriptor = (PCM_PARTIAL_RESOURCE_DESCRIPTOR)
988  ((ULONG_PTR)FullDescriptor->
989  PartialResourceList.PartialDescriptors);
990 
991  /* Check if this is our PCI Registry Information */
992  if (PartialDescriptor->Type == CmResourceTypeDeviceSpecific)
993  {
994  /* It is, stop searching */
995  break;
996  }
997  }
998 
999  /* Close the key */
1000  ZwClose(KeyHandle);
1001 
1002  /* Save the PCI information for later */
1003  PciRegInfo = (PPCI_REGISTRY_INFO)(PartialDescriptor + 1);
1004 
1005  /* Assume no Card List entries */
1006  ElementCount = 0;
1007 
1008  /* Set up for checking the PCI Card List key */
1010  L"\\Registry\\Machine\\System\\CurrentControlSet\\"
1011  L"Control\\PnP\\PCI\\CardList");
1013  &KeyName,
1015  NULL,
1016  NULL);
1017 
1018  /* Attempt to open it */
1019  Status = ZwOpenKey(&CardListHandle, KEY_READ, &ObjectAttributes);
1020  if (NT_SUCCESS(Status))
1021  {
1022  /* It exists, so let's query it */
1023  Status = ZwQueryKey(CardListHandle,
1025  &KeyInformation,
1026  sizeof(KEY_FULL_INFORMATION),
1027  &ResultLength);
1028  if (!NT_SUCCESS(Status))
1029  {
1030  /* Failed to query, so no info */
1031  PciRegistryInfo = NULL;
1032  }
1033  else
1034  {
1035  /* Allocate the full structure */
1036  PciRegistryInfo =
1038  sizeof(PCI_REGISTRY_INFO_INTERNAL) +
1039  (KeyInformation.Values *
1040  sizeof(PCI_CARD_DESCRIPTOR)),
1041  TAG_HAL);
1042  if (PciRegistryInfo)
1043  {
1044  /* Get the first card descriptor entry */
1045  CardDescriptor = (PPCI_CARD_DESCRIPTOR)(PciRegistryInfo + 1);
1046 
1047  /* Loop all the values */
1048  for (i = 0; i < KeyInformation.Values; i++)
1049  {
1050  /* Attempt to get the value */
1051  Status = ZwEnumerateValueKey(CardListHandle,
1052  i,
1054  PartialValueInfo,
1055  sizeof(PartialKeyBuffer),
1056  &ResultLength);
1057  if (!NT_SUCCESS(Status))
1058  {
1059  /* Something went wrong, stop the search */
1060  break;
1061  }
1062 
1063  /* Make sure it is correctly sized */
1064  if (PartialValueInfo->DataLength == sizeof(PCI_CARD_DESCRIPTOR))
1065  {
1066  /* Sure is, copy it over */
1067  *CardDescriptor = *(PPCI_CARD_DESCRIPTOR)
1068  PartialValueInfo->Data;
1069 
1070  /* One more Card List entry */
1071  ElementCount++;
1072 
1073  /* Move to the next descriptor */
1074  CardDescriptor = (CardDescriptor + 1);
1075  }
1076  }
1077  }
1078  }
1079 
1080  /* Close the Card List key */
1081  ZwClose(CardListHandle);
1082  }
1083  else
1084  {
1085  /* No key, no Card List */
1086  PciRegistryInfo = NULL;
1087  }
1088 
1089  /* Check if we failed to get the full structure */
1090  if (!PciRegistryInfo)
1091  {
1092  /* Just allocate the basic structure then */
1093  PciRegistryInfo = ExAllocatePoolWithTag(NonPagedPool,
1095  TAG_HAL);
1096  if (!PciRegistryInfo) return NULL;
1097  }
1098 
1099  /* Save the info we got */
1100  PciRegistryInfo->MajorRevision = PciRegInfo->MajorRevision;
1101  PciRegistryInfo->MinorRevision = PciRegInfo->MinorRevision;
1102  PciRegistryInfo->NoBuses = PciRegInfo->NoBuses;
1103  PciRegistryInfo->HardwareMechanism = PciRegInfo->HardwareMechanism;
1104  PciRegistryInfo->ElementCount = ElementCount;
1105 
1106  /* Return it */
1107  return PciRegistryInfo;
1108 #else
1109  return NULL;
1110 #endif
1111 }
1112 
1113 INIT_FUNCTION
1114 VOID
1115 NTAPI
1117 {
1118  PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
1119  UCHAR PciType;
1121  ULONG i;
1123  ULONG VendorId = 0;
1124  ULONG MaxPciBusNumber;
1125 
1126  /* Query registry information */
1127  PciRegistryInfo = HalpQueryPciRegistryInfo();
1128  if (!PciRegistryInfo)
1129  {
1130  /* Assume type 1 */
1131  PciType = 1;
1132 
1133  /* Force a manual bus scan later */
1134  MaxPciBusNumber = MAXULONG;
1135  }
1136  else
1137  {
1138  /* Get the PCI type */
1139  PciType = PciRegistryInfo->HardwareMechanism & 0xF;
1140 
1141  /* Get MaxPciBusNumber and make it 0-based */
1142  MaxPciBusNumber = PciRegistryInfo->NoBuses - 1;
1143 
1144  /* Free the info structure */
1145  ExFreePoolWithTag(PciRegistryInfo, TAG_HAL);
1146  }
1147 
1148  /* Initialize the PCI lock */
1150 
1151  /* Check the type of PCI bus */
1152  switch (PciType)
1153  {
1154  /* Type 1 PCI Bus */
1155  case 1:
1156 
1157  /* Copy the Type 1 handler data */
1160  sizeof(PCIConfigHandler));
1161 
1162  /* Set correct I/O Ports */
1163  BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
1164  BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
1165  break;
1166 
1167  /* Type 2 PCI Bus */
1168  case 2:
1169 
1170  /* Copy the Type 2 handler data */
1173  sizeof (PCIConfigHandler));
1174 
1175  /* Set correct I/O Ports */
1176  BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
1177  BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
1178  BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
1179 
1180  /* Only 16 devices supported, not 32 */
1181  BusData->MaxDevice = 16;
1182  break;
1183 
1184  default:
1185 
1186  /* Invalid type */
1187  DbgPrint("HAL: Unknown PCI type\n");
1188  }
1189 
1190  /* Run a forced bus scan if needed */
1191  if (MaxPciBusNumber == MAXULONG)
1192  {
1193  /* Initialize the max bus number to 0xFF */
1194  HalpMaxPciBus = 0xFF;
1195 
1196  /* Initialize the counter */
1197  MaxPciBusNumber = 0;
1198 
1199  /* Loop all possible buses */
1200  for (i = 0; i < HalpMaxPciBus; i++)
1201  {
1202  /* Loop all devices */
1203  for (j.u.AsULONG = 0; j.u.AsULONG < BusData->MaxDevice; j.u.AsULONG++)
1204  {
1205  /* Query the interface */
1207  i,
1208  j,
1209  &VendorId,
1210  0,
1211  sizeof(ULONG)))
1212  {
1213  /* Validate the vendor ID */
1214  if ((VendorId & 0xFFFF) != PCI_INVALID_VENDORID)
1215  {
1216  /* Set this as the maximum ID */
1217  MaxPciBusNumber = i;
1218  break;
1219  }
1220  }
1221  }
1222  }
1223  }
1224 
1225  /* Set the real max bus number */
1226  HalpMaxPciBus = MaxPciBusNumber;
1227 
1228  /* We're done */
1230 }
1231 
1232 /* EOF */
1233 
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble * u
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IN CINT OUT PVOID IN ULONG OUT PULONG ResultLength
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IN PUNICODE_STRING IN POBJECT_ATTRIBUTES ObjectAttributes
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_In_ ULONG _In_ ULONG BusInterruptLevel
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_Must_inspect_result_ _Out_ PNDIS_STATUS _In_ NDIS_HANDLE _In_ ULONG _Out_ PNDIS_STRING KeyName
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#define IN
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struct _CM_PARTIAL_RESOURCE_DESCRIPTOR * PCM_PARTIAL_RESOURCE_DESCRIPTOR
#define KeRaiseIrql(irql, oldIrql)
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#define PCI_ADDRESS_IO_ADDRESS_MASK
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#define TRUE
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NTSYSAPI VOID NTAPI RtlCopyMemory(VOID UNALIGNED *Destination, CONST VOID UNALIGNED *Source, ULONG Length)
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_In_ ULONG _In_ ULONG _In_ ULONG BusInterruptVector
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_Out_ PKIRQL Irql
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_In_opt_ PUNICODE_STRING DriverClassName
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FncReleaseSync ReleaseSynchronzation
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FncConfigIO ConfigRead[3]
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uint32_t ULONG_PTR
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GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
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_In_ ULONG _In_ ULONG Offset
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#define PCI_TYPE1_DATA_PORT
Definition: bus.h:165
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
NTSYSAPI NTSTATUS NTAPI RtlIntegerToUnicodeString(ULONG Value, ULONG Base, PUNICODE_STRING String)
PCI_CONFIG_HANDLER PCIConfigHandler
Definition: pcibus.c:33
#define PCI_INVALID_VENDORID
Definition: iotypes.h:3245
ULONG BusNumber
Definition: haltypes.h:226
PCIPBUSDATA HalpFakePciBusData
Definition: pcibus.c:88
if(!(yy_init))
Definition: macro.lex.yy.c:714
INIT_FUNCTION VOID NTAPI HalpInitializePciStubs(VOID)
Definition: pcibus.c:1116
__wchar_t WCHAR
Definition: xmlstorage.h:180
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:32
#define STATUS_NO_SUCH_DEVICE
Definition: udferr_usr.h:136
INIT_FUNCTION NTSTATUS NTAPI HalpReleasePciDeviceForDebugging(IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Definition: pcibus.c:639
union _PCI_SLOT_NUMBER::@3659 u
_In_ ULONG _In_ ULONG _In_ ULONG _Out_ PKIRQL _Out_ PKAFFINITY Affinity
Definition: halfuncs.h:170
VOID NTAPI HalpPCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PUCHAR Buffer, IN ULONG Offset, IN ULONG Length, IN FncConfigIO *ConfigIO)
Definition: pcibus.c:231
#define Len
Definition: deflate.h:82
KSPIN_LOCK HalpPCIConfigLock
Definition: pcibus.c:32
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:101
#define OBJ_CASE_INSENSITIVE
Definition: winternl.h:228
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel) ?(CompletionRoutine !=NULL) :TRUE)
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
INIT_FUNCTION VOID NTAPI HalpRegisterPciDebuggingDeviceInfo(VOID)
Definition: pcibus.c:648
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE _In_ ULONG _In_ ULONG SlotNumber
Definition: halfuncs.h:156
static ULONG ResourceCount
Definition: inbv.c:95
unsigned char UCHAR
Definition: xmlstorage.h:181
#define PCI_DATA_VERSION
Definition: iotypes.h:4920
static const WCHAR L[]
Definition: oid.c:1250
#define TAG_HAL
Definition: hal.h:55
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:803
union _PCIPBUSDATA::@1420 Config
KIRQL * PKIRQL
Definition: env_spec_w32.h:592
PCI_CONFIG_HANDLER PCIConfigHandlerType2
Definition: pcibus.c:67
struct _PCIPBUSDATA::@1420::@1422 Type2
Definition: range.c:39
IN PVOID IN PVOID IN USHORT IN USHORT Size
Definition: pci.h:359
#define PCI_TYPE2_CSE_PORT
Definition: bus.h:170
BUS_HANDLER HalpFakePciBusHandler
Definition: pcibus.c:104
VOID NTAPI HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler, IN KIRQL Irql)
Definition: pcibus.c:204
Status
Definition: gdiplustypes.h:24
#define MAXULONG
Definition: typedefs.h:250
IN PDEVICE_OBJECT DeviceObject
Definition: fatprocs.h:1560
ULONG_PTR SIZE_T
Definition: typedefs.h:78
#define HIGH_LEVEL
Definition: env_spec_w32.h:703
FncSync Synchronize
Definition: bus.h:127
#define CM_RESOURCE_PORT_IO
Definition: cmtypes.h:109
VOID NTAPI HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PKIRQL Irql, IN PPCI_TYPE1_CFG_BITS PciCfg1)
Definition: pcibus.c:128
unsigned short USHORT
Definition: pedump.c:61
VOID NTAPI HalpWritePCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:295
NTSTATUS NTAPI HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList)
Definition: pcibus.c:683
struct _KEY_VALUE_PARTIAL_INFORMATION KEY_VALUE_PARTIAL_INFORMATION
#define STATUS_NO_MEMORY
Definition: ntstatus.h:246
VOID FASTCALL KiAcquireSpinLock(IN PKSPIN_LOCK SpinLock)
Definition: ntoskrnl.c:32
ULONG KSPIN_LOCK
Definition: env_spec_w32.h:72
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:254
PCI_CONFIG_HANDLER PCIConfigHandlerType1
Definition: pcibus.c:45
ULONG HalpMinPciBus
Definition: pcibus.c:31
#define CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
Definition: cmtypes.h:143
#define CmResourceTypeInterrupt
Definition: hwresource.cpp:124
ULONG(NTAPI * FncConfigIO)(IN PPCIPBUSDATA BusData, IN PVOID State, IN PUCHAR Buffer, IN ULONG Offset)
Definition: bus.h:104
union _PCI_TYPE2_CSE_BITS::@1461 u
#define UNIMPLEMENTED_DBGBREAK(...)
Definition: debug.h:57
#define DPRINT1
Definition: precomp.h:8
IN ULONG IN ULONG Tag
Definition: evtlib.h:159
UCHAR NoBuses
Definition: pci.h:109
BOOLEAN HalpPCIConfigInitialized
Definition: pcibus.c:30
struct _PCIPBUSDATA * PPCIPBUSDATA
#define OUT
Definition: typedefs.h:39
UCHAR AsUCHAR
Definition: bus.h:210
VOID NTAPI HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PKIRQL Irql, IN PPCI_TYPE2_ADDRESS_BITS PciCfg)
Definition: pcibus.c:173
struct _PCI_SLOT_NUMBER::@3659::@3660 bits
unsigned int ULONG
Definition: retypes.h:1
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
NTHALAPI ULONG NTAPI HalGetBusData(BUS_DATA_TYPE, ULONG, ULONG, PVOID, ULONG)
void WRITE_PORT_UCHAR(PUCHAR Address, UCHAR Value)
Definition: mach.c:532
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:261
#define InitializeObjectAttributes(p, n, a, r, s)
Definition: reg.c:106
_In_ PUNICODE_STRING RegistryPath
Definition: wmip.h:27
ULONG NTAPI HaliPciInterfaceReadConfig(IN PBUS_HANDLER RootBusHandler, IN ULONG BusNumber, IN PCI_SLOT_NUMBER SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:860
VOID NTAPI HalpReadPCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:269
ULONG NTAPI HalpSetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:470
static ULONG NTAPI PciSize(ULONG Base, ULONG Mask)
Definition: pcibus.c:674
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1099
struct _PCI_REGISTRY_INFO * PPCI_REGISTRY_INFO
#define CmResourceTypeMemory
Definition: hwresource.cpp:125
struct _PCI_TYPE2_CSE_BITS::@1461::@1462 bits
return STATUS_SUCCESS
Definition: btrfs.c:2938
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:3874
INIT_FUNCTION NTSTATUS NTAPI HalpSetupPciDeviceForDebugging(IN PVOID LoaderBlock, IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
Definition: pcibus.c:629
NTSTATUS NTAPI HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName OPTIONAL, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject OPTIONAL, IN ULONG Slot, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: pcibus.c:724
#define RtlFillMemory(Dest, Length, Fill)
Definition: winternl.h:593
ULONG AsULONG
Definition: bus.h:192
PciIrqRange GetIrqRange
Definition: bus.h:111
#define PCI_TYPE2_ADDRESS_BASE
Definition: bus.h:172
FncConfigIO ConfigWrite[3]
Definition: bus.h:130
PVOID BusData
Definition: haltypes.h:229
unsigned short * PUSHORT
Definition: retypes.h:2
#define WriteBuffer(BaseIoAddress, Buffer, Count)
Definition: atapi.h:344
#define ExFreePool(addr)
Definition: env_spec_w32.h:352
ULONG HalpMaxPciBus
Definition: pcibus.c:31
#define TYPE1_WRITE(x, y)
Definition: bus.h:51
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3238
_In_ PSTORAGE_PROPERTY_ID _Outptr_ PSTORAGE_DESCRIPTOR_HEADER * Descriptor
Definition: classpnp.h:966
PULONG MinorVersion OPTIONAL
Definition: CrossNt.h:68