ReactOS 0.4.15-dev-5672-gf73ac17
pcibus.c File Reference
#include <hal.h>
#include <debug.h>
Include dependency graph for pcibus.c:

Go to the source code of this file.

Macros

#define NDEBUG
 

Functions

VOID NTAPI HalpPCISynchronizeType1 (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, OUT PKIRQL OldIrql, OUT PPCI_TYPE1_CFG_BITS PciCfg1)
 
VOID NTAPI HalpPCIReleaseSynchronzationType1 (IN PBUS_HANDLER BusHandler, IN KIRQL OldIrql)
 
VOID NTAPI HalpPCISynchronizeType2 (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, OUT PKIRQL OldIrql, OUT PPCI_TYPE2_ADDRESS_BITS PciCfg)
 
VOID NTAPI HalpPCIReleaseSynchronizationType2 (IN PBUS_HANDLER BusHandler, IN KIRQL OldIrql)
 
VOID NTAPI HalpPCIConfig (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PUCHAR Buffer, IN ULONG Offset, IN ULONG Length, IN FncConfigIO *ConfigIO)
 
VOID NTAPI HalpReadPCIConfig (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
 
VOID NTAPI HalpWritePCIConfig (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
 
BOOLEAN NTAPI HalpValidPCISlot (IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot)
 
ULONG HalpPhase0GetPciDataByOffset (_In_ ULONG Bus, _In_ PCI_SLOT_NUMBER PciSlot, _Out_writes_bytes_all_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
 
ULONG HalpPhase0SetPciDataByOffset (_In_ ULONG Bus, _In_ PCI_SLOT_NUMBER PciSlot, _In_reads_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
 
ULONG NTAPI HalpGetPCIData (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
 
ULONG NTAPI HalpSetPCIData (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
 
ULONG NTAPI HalpGetPCIIntOnISABus (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)
 
VOID NTAPI HalpPCIPin2ISALine (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciData)
 
VOID NTAPI HalpPCIISALine2Pin (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER SlotNumber, IN PPCI_COMMON_CONFIG PciNewData, IN PPCI_COMMON_CONFIG PciOldData)
 
NTSTATUS NTAPI HalpGetISAFixedPCIIrq (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PCI_SLOT_NUMBER PciSlot, OUT PSUPPORTED_RANGE *Range)
 
static ULONG NTAPI PciSize (ULONG Base, ULONG Mask)
 
NTSTATUS NTAPI HalpAdjustPCIResourceList (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList)
 
NTSTATUS NTAPI HalpAssignPCISlotResources (IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName OPTIONAL, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject OPTIONAL, IN ULONG Slot, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
 
ULONG NTAPI HaliPciInterfaceReadConfig (IN PBUS_HANDLER RootBusHandler, IN ULONG BusNumber, IN PCI_SLOT_NUMBER SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
 
PPCI_REGISTRY_INFO_INTERNAL NTAPI HalpQueryPciRegistryInfo (VOID)
 
VOID NTAPI HalpInitializePciStubs (VOID)
 

Variables

BOOLEAN HalpPciLockSettings
 
ULONG HalpBusType
 
BOOLEAN HalpPCIConfigInitialized
 
ULONG HalpMinPciBus
 
ULONG HalpMaxPciBus
 
KSPIN_LOCK HalpPCIConfigLock
 
PCI_CONFIG_HANDLER PCIConfigHandler
 
UCHAR PCIDeref [4][4]
 
PCI_CONFIG_HANDLER PCIConfigHandlerType1
 
PCI_CONFIG_HANDLER PCIConfigHandlerType2
 
PCIPBUSDATA HalpFakePciBusData
 
BUS_HANDLER HalpFakePciBusHandler
 

Macro Definition Documentation

◆ NDEBUG

#define NDEBUG

Definition at line 12 of file pcibus.c.

Function Documentation

◆ HaliPciInterfaceReadConfig()

ULONG NTAPI HaliPciInterfaceReadConfig ( IN PBUS_HANDLER  RootBusHandler,
IN ULONG  BusNumber,
IN PCI_SLOT_NUMBER  SlotNumber,
IN PVOID  Buffer,
IN ULONG  Offset,
IN ULONG  Length 
)

Definition at line 934 of file pcibus.c.

940{
941 BUS_HANDLER BusHandler;
942
943 /* Setup fake PCI Bus handler */
944 RtlCopyMemory(&BusHandler, &HalpFakePciBusHandler, sizeof(BUS_HANDLER));
945 BusHandler.BusNumber = BusNumber;
946
947 /* Read configuration data */
949
950 /* Return length */
951 return Length;
952}
Definition: bufpool.h:45
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:102
BUS_HANDLER HalpFakePciBusHandler
Definition: pcibus.c:94
VOID NTAPI HalpReadPCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:257
ULONG BusNumber
Definition: haltypes.h:237
#define RtlCopyMemory(Destination, Source, Length)
Definition: typedefs.h:263
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
Definition: wdfresource.h:68
_In_opt_ PUNICODE_STRING _In_ PDRIVER_OBJECT _In_ PDEVICE_OBJECT _In_ INTERFACE_TYPE _In_ ULONG BusNumber
Definition: halfuncs.h:160

Referenced by HalpInitializePciStubs().

◆ HalpAdjustPCIResourceList()

NTSTATUS NTAPI HalpAdjustPCIResourceList ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN OUT PIO_RESOURCE_REQUIREMENTS_LIST pResourceList 
)

Definition at line 757 of file pcibus.c.

760{
761 PPCIPBUSDATA BusData;
765
766 /* Get PCI bus data */
767 BusData = BusHandler->BusData;
768 SlotNumber.u.AsULONG = (*pResourceList)->SlotNumber;
769
770 /* Get the IRQ supported range */
771 Status = BusData->GetIrqRange(BusHandler, RootHandler, SlotNumber, &Interrupt);
772 if (!NT_SUCCESS(Status)) return Status;
773#ifndef _MINIHAL_
774 /* Handle the /PCILOCK feature */
776 {
777 /* /PCILOCK is not yet supported */
778 UNIMPLEMENTED_DBGBREAK("/PCILOCK boot switch is not yet supported.");
779 }
780#endif
781 /* Now create the correct resource list based on the supported bus ranges */
782#if 0
783 Status = HaliAdjustResourceListRange(BusHandler->BusAddresses,
784 Interrupt,
785 pResourceList);
786#else
787 DPRINT1("HAL: No PCI Resource Adjustment done! Hardware may malfunction\n");
789#endif
790
791 /* Return to caller */
793 return Status;
794}
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:32
#define UNIMPLEMENTED_DBGBREAK(...)
Definition: debug.h:57
#define ExFreePool(addr)
Definition: env_spec_w32.h:352
Status
Definition: gdiplustypes.h:25
BOOLEAN HalpPciLockSettings
Definition: halinit.c:17
#define STATUS_SUCCESS
Definition: shellext.h:65
PciIrqRange GetIrqRange
Definition: bus.h:111
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_INTERRUPT_CONFIG _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFINTERRUPT * Interrupt
Definition: wdfinterrupt.h:379

Referenced by HalpAllocateAndInitPciBusHandler().

◆ HalpAssignPCISlotResources()

NTSTATUS NTAPI HalpAssignPCISlotResources ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN PUNICODE_STRING  RegistryPath,
IN PUNICODE_STRING DriverClassName  OPTIONAL,
IN PDRIVER_OBJECT  DriverObject,
IN PDEVICE_OBJECT DeviceObject  OPTIONAL,
IN ULONG  Slot,
IN OUT PCM_RESOURCE_LIST AllocatedResources 
)

Definition at line 798 of file pcibus.c.

806{
807 PCI_COMMON_CONFIG PciConfig;
816 DPRINT1("WARNING: PCI Slot Resource Assignment is FOOBAR\n");
817
818 /* FIXME: Should handle 64-bit addresses */
819
820 /* Read configuration data */
821 SlotNumber.u.AsULONG = Slot;
822 HalpReadPCIConfig(BusHandler, SlotNumber, &PciConfig, 0, PCI_COMMON_HDR_LENGTH);
823
824 /* Check if we read it correctly */
825 if (PciConfig.VendorID == PCI_INVALID_VENDORID)
827
828 /* Read the PCI configuration space for the device and store base address and
829 size information in temporary storage. Count the number of valid base addresses */
830 ResourceCount = 0;
832 {
833 if (0xffffffff == PciConfig.u.type0.BaseAddresses[Address])
834 PciConfig.u.type0.BaseAddresses[Address] = 0;
835
836 /* Memory resource */
837 if (0 != PciConfig.u.type0.BaseAddresses[Address])
838 {
840
841 Offset = (UCHAR)FIELD_OFFSET(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
842
843 /* Write 0xFFFFFFFF there */
844 WriteBuffer = 0xffffffff;
845 HalpWritePCIConfig(BusHandler, SlotNumber, &WriteBuffer, Offset, sizeof(ULONG));
846
847 /* Read that figure back from the config space */
848 HalpReadPCIConfig(BusHandler, SlotNumber, &Size[Address], Offset, sizeof(ULONG));
849
850 /* Write back initial value */
851 HalpWritePCIConfig(BusHandler, SlotNumber, &PciConfig.u.type0.BaseAddresses[Address], Offset, sizeof(ULONG));
852 }
853 }
854
855 /* Interrupt resource */
856 if (0 != PciConfig.u.type0.InterruptPin &&
857 0 != PciConfig.u.type0.InterruptLine &&
858 0xFF != PciConfig.u.type0.InterruptLine)
860
861 /* Allocate output buffer and initialize */
863 PagedPool,
864 sizeof(CM_RESOURCE_LIST) +
866 TAG_HAL);
867
868 if (NULL == *AllocatedResources)
869 return STATUS_NO_MEMORY;
870
871 (*AllocatedResources)->Count = 1;
872 (*AllocatedResources)->List[0].InterfaceType = PCIBus;
873 (*AllocatedResources)->List[0].BusNumber = BusHandler->BusNumber;
874 (*AllocatedResources)->List[0].PartialResourceList.Version = 1;
875 (*AllocatedResources)->List[0].PartialResourceList.Revision = 1;
876 (*AllocatedResources)->List[0].PartialResourceList.Count = ResourceCount;
877 Descriptor = (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
878
879 /* Store configuration information */
881 {
882 if (0 != PciConfig.u.type0.BaseAddresses[Address])
883 {
885 (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
886 {
888 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
889 Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE; /* FIXME Just a guess */
890 Descriptor->u.Memory.Start.QuadPart = (PciConfig.u.type0.BaseAddresses[Address] & PCI_ADDRESS_MEMORY_ADDRESS_MASK);
892 }
893 else if (PCI_ADDRESS_IO_SPACE ==
894 (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
895 {
897 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
898 Descriptor->Flags = CM_RESOURCE_PORT_IO; /* FIXME Just a guess */
899 Descriptor->u.Port.Start.QuadPart = PciConfig.u.type0.BaseAddresses[Address] &= PCI_ADDRESS_IO_ADDRESS_MASK;
900 Descriptor->u.Port.Length = PciSize(Size[Address], PCI_ADDRESS_IO_ADDRESS_MASK & 0xffff);
901 }
902 else
903 {
904 ASSERT(FALSE);
905 return STATUS_UNSUCCESSFUL;
906 }
907 Descriptor++;
908 }
909 }
910
911 if (0 != PciConfig.u.type0.InterruptPin &&
912 0 != PciConfig.u.type0.InterruptLine &&
913 0xFF != PciConfig.u.type0.InterruptLine)
914 {
916 Descriptor->ShareDisposition = CmResourceShareShared; /* FIXME Just a guess */
917 Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE; /* FIXME Just a guess */
918 Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
919 Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
920 Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
921
922 Descriptor++;
923 }
924
925 ASSERT(Descriptor == (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors + ResourceCount);
926
927 /* FIXME: Should store the resources in the registry resource map */
928
929 return Status;
930}
#define WriteBuffer(BaseIoAddress, Buffer, Count)
Definition: atapi.h:344
#define PCI_ADDRESS_MEMORY_SPACE
Definition: bus.h:3
#define NULL
Definition: types.h:112
#define FALSE
Definition: types.h:117
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
#define PagedPool
Definition: env_spec_w32.h:308
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble * u
Definition: glfuncs.h:240
#define TAG_HAL
Definition: hal.h:61
#define CmResourceTypeMemory
Definition: hwresource.cpp:125
@ PCIBus
Definition: hwresource.cpp:142
#define CmResourceTypePort
Definition: hwresource.cpp:123
#define CmResourceTypeInterrupt
Definition: hwresource.cpp:124
static ULONG ResourceCount
Definition: inbv.c:50
#define ASSERT(a)
Definition: mode.c:44
_Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PDEVICE_OBJECT _Inout_opt_ PCM_RESOURCE_LIST * AllocatedResources
Definition: ndis.h:4643
#define CM_RESOURCE_PORT_IO
Definition: cmtypes.h:109
#define CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
Definition: cmtypes.h:143
#define CM_RESOURCE_MEMORY_READ_WRITE
Definition: cmtypes.h:120
#define STATUS_NO_MEMORY
Definition: ntstatus.h:260
VOID NTAPI HalpWritePCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:283
static ULONG NTAPI PciSize(ULONG Base, ULONG Mask)
Definition: pcibus.c:748
static WCHAR Address[46]
Definition: ping.c:68
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
ULONG_PTR SIZE_T
Definition: typedefs.h:80
uint32_t ULONG
Definition: typedefs.h:59
#define STATUS_NO_SUCH_DEVICE
Definition: udferr_usr.h:136
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_DEVICE_PROPERTY_DATA _In_ DEVPROPTYPE _In_ ULONG Size
Definition: wdfdevice.h:4533
_Must_inspect_result_ _In_ WDFIORESLIST _In_ PIO_RESOURCE_DESCRIPTOR Descriptor
Definition: wdfresource.h:342
@ CmResourceShareDeviceExclusive
Definition: cmtypes.h:241
@ CmResourceShareShared
Definition: cmtypes.h:243
#define PCI_INVALID_VENDORID
Definition: iotypes.h:3601
#define PCI_ADDRESS_IO_ADDRESS_MASK
Definition: iotypes.h:4233
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3500
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:4230
#define PCI_ADDRESS_MEMORY_ADDRESS_MASK
Definition: iotypes.h:4234
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3594
unsigned char UCHAR
Definition: xmlstorage.h:181

Referenced by HalpAllocateAndInitPciBusHandler(), and HalpAssignSlotResources().

◆ HalpGetISAFixedPCIIrq()

NTSTATUS NTAPI HalpGetISAFixedPCIIrq ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN PCI_SLOT_NUMBER  PciSlot,
OUT PSUPPORTED_RANGE Range 
)

Definition at line 702 of file pcibus.c.

706{
707 PCI_COMMON_HEADER PciData;
708
709 /* Read PCI configuration data */
711 BusHandler->BusNumber,
712 PciSlot.u.AsULONG,
713 &PciData,
715
716 /* Make sure it's a real device */
717 if (PciData.VendorID == PCI_INVALID_VENDORID) return STATUS_UNSUCCESSFUL;
718
719 /* Allocate the supported range structure */
722
723 /* Set it up */
725 (*Range)->Base = 1;
726
727 /* If the PCI device has no IRQ, nothing to do */
728 if (!PciData.u.type0.InterruptPin) return STATUS_SUCCESS;
729
730 /* FIXME: The PCI IRQ Routing Miniport should be called */
731
732 /* Also if the INT# seems bogus, nothing to do either */
733 if ((PciData.u.type0.InterruptLine == 0) ||
734 (PciData.u.type0.InterruptLine == 255))
735 {
736 /* Fake success */
737 return STATUS_SUCCESS;
738 }
739
740 /* Otherwise, the INT# should be valid, return it to the caller */
741 (*Range)->Base = PciData.u.type0.InterruptLine;
742 (*Range)->Limit = PciData.u.type0.InterruptLine;
743 return STATUS_SUCCESS;
744}
NTHALAPI ULONG NTAPI HalGetBusData(BUS_DATA_TYPE, ULONG, ULONG, PVOID, ULONG)
@ PCIConfiguration
Definition: miniport.h:93
Definition: range.c:39
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
#define STATUS_INSUFFICIENT_RESOURCES
Definition: udferr_usr.h:158

Referenced by HalpAllocateAndInitPciBusHandler().

◆ HalpGetPCIData()

ULONG NTAPI HalpGetPCIData ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN ULONG  SlotNumber,
IN PVOID  Buffer,
IN ULONG  Offset,
IN ULONG  Length 
)

Definition at line 507 of file pcibus.c.

513{
514 PCI_SLOT_NUMBER Slot;
515 UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
516 PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
517 ULONG Len = 0;
518
519 Slot.u.AsULONG = SlotNumber;
520#ifdef SARCH_XBOX
521 if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
522 {
524 return Length;
525 }
526#endif
527
528 /* Normalize the length */
529 if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
530
531 /* Check if this is a vendor-specific read */
533 {
534 /* Read the header */
535 HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
536
537 /* Make sure the vendor is valid */
538 if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
539 }
540 else
541 {
542 /* Read the entire header */
544 HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
545
546 /* Validate the vendor ID */
547 if (PciConfig->VendorID == PCI_INVALID_VENDORID)
548 {
549 /* It's invalid, but we want to return this much */
550 Len = sizeof(USHORT);
551 }
552
553 /* Now check if there's space left */
554 if (Len < Offset) return 0;
555
556 /* There is, so return what's after the offset and normalize */
557 Len -= Offset;
558 if (Len > Length) Len = Length;
559
560 /* Copy the data into the caller's buffer */
561 RtlMoveMemory(Buffer, PciBuffer + Offset, Len);
562
563 /* Update buffer and offset, decrement total length */
564 Offset += Len;
566 Length -= Len;
567 }
568
569 /* Now we still have something to copy */
570 if (Length)
571 {
572 /* Check if it's vendor-specific data */
574 {
575 /* Read it now */
576 HalpReadPCIConfig(BusHandler, Slot, Buffer, Offset, Length);
577 Len += Length;
578 }
579 }
580
581 /* Update the total length read */
582 return Len;
583}
#define Len
Definition: deflate.h:82
#define RtlFillMemory(Dest, Length, Fill)
Definition: winternl.h:593
unsigned short USHORT
Definition: pedump.c:61
union _PCI_SLOT_NUMBER::@3816 u
void * PVOID
Definition: typedefs.h:50
uint32_t ULONG_PTR
Definition: typedefs.h:65
#define RtlMoveMemory(Destination, Source, Length)
Definition: typedefs.h:264
struct _PCI_COMMON_CONFIG * PPCI_COMMON_CONFIG
struct _PCI_COMMON_CONFIG PCI_COMMON_CONFIG

Referenced by HalGetBusDataByOffset(), and HalpAllocateAndInitPciBusHandler().

◆ HalpGetPCIIntOnISABus()

ULONG NTAPI HalpGetPCIIntOnISABus ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN ULONG  BusInterruptLevel,
IN ULONG  BusInterruptVector,
OUT PKIRQL  Irql,
OUT PKAFFINITY  Affinity 
)

Definition at line 658 of file pcibus.c.

664{
665 /* Validate the level first */
666 if (BusInterruptLevel < 1) return 0;
667
668 /* PCI has its IRQs on top of ISA IRQs, so pass it on to the ISA handler */
670 0,
672 0,
673 Irql,
674 Affinity);
675}
_Out_ PKIRQL Irql
Definition: csq.h:179
NTHALAPI ULONG NTAPI HalGetInterruptVector(INTERFACE_TYPE, ULONG, ULONG, ULONG, PKIRQL, PKAFFINITY)
@ Isa
Definition: hwresource.cpp:138
_In_ ULONG _In_ ULONG BusInterruptLevel
Definition: halfuncs.h:171
_In_ ULONG _In_ ULONG _In_ ULONG _Out_ PKIRQL _Out_ PKAFFINITY Affinity
Definition: halfuncs.h:174

Referenced by HalpAllocateAndInitPciBusHandler().

◆ HalpInitializePciStubs()

VOID NTAPI HalpInitializePciStubs ( VOID  )

Definition at line 1190 of file pcibus.c.

1191{
1192 PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
1193 UCHAR PciType;
1195 ULONG i;
1197 ULONG VendorId = 0;
1198 ULONG MaxPciBusNumber;
1199
1200 /* Query registry information */
1201 PciRegistryInfo = HalpQueryPciRegistryInfo();
1202 if (!PciRegistryInfo)
1203 {
1204 /* Assume type 1 */
1205 PciType = 1;
1206
1207 /* Force a manual bus scan later */
1208 MaxPciBusNumber = MAXULONG;
1209 }
1210 else
1211 {
1212 /* Get the PCI type */
1213 PciType = PciRegistryInfo->HardwareMechanism & 0xF;
1214
1215 /* Get MaxPciBusNumber and make it 0-based */
1216 MaxPciBusNumber = PciRegistryInfo->NoBuses - 1;
1217
1218 /* Free the info structure */
1219 ExFreePoolWithTag(PciRegistryInfo, TAG_HAL);
1220 }
1221
1222 /* Initialize the PCI lock */
1224
1225 /* Check the type of PCI bus */
1226 switch (PciType)
1227 {
1228 /* Type 1 PCI Bus */
1229 case 1:
1230
1231 /* Copy the Type 1 handler data */
1234 sizeof(PCIConfigHandler));
1235
1236 /* Set correct I/O Ports */
1237 BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
1238 BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
1239 break;
1240
1241 /* Type 2 PCI Bus */
1242 case 2:
1243
1244 /* Copy the Type 2 handler data */
1247 sizeof (PCIConfigHandler));
1248
1249 /* Set correct I/O Ports */
1250 BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
1251 BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
1252 BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
1253
1254 /* Only 16 devices supported, not 32 */
1255 BusData->MaxDevice = 16;
1256 break;
1257
1258 default:
1259
1260 /* Invalid type */
1261 DbgPrint("HAL: Unknown PCI type\n");
1262 }
1263
1264 /* Run a forced bus scan if needed */
1265 if (MaxPciBusNumber == MAXULONG)
1266 {
1267 /* Initialize the max bus number to 0xFF */
1268 HalpMaxPciBus = 0xFF;
1269
1270 /* Initialize the counter */
1271 MaxPciBusNumber = 0;
1272
1273 /* Loop all possible buses */
1274 for (i = 0; i < HalpMaxPciBus; i++)
1275 {
1276 /* Loop all devices */
1277 for (j.u.AsULONG = 0; j.u.AsULONG < BusData->MaxDevice; j.u.AsULONG++)
1278 {
1279 /* Query the interface */
1281 i,
1282 j,
1283 &VendorId,
1284 0,
1285 sizeof(ULONG)))
1286 {
1287 /* Validate the vendor ID */
1288 if ((VendorId & 0xFFFF) != PCI_INVALID_VENDORID)
1289 {
1290 /* Set this as the maximum ID */
1291 MaxPciBusNumber = i;
1292 break;
1293 }
1294 }
1295 }
1296 }
1297 }
1298
1299 /* Set the real max bus number */
1300 HalpMaxPciBus = MaxPciBusNumber;
1301
1302 /* We're done */
1304}
#define PCI_TYPE1_DATA_PORT
Definition: hardware.h:34
#define PCI_TYPE1_ADDRESS_PORT
Definition: hardware.h:33
#define PCI_TYPE2_ADDRESS_BASE
Definition: bus.h:172
#define PCI_TYPE2_CSE_PORT
Definition: bus.h:170
#define PCI_TYPE2_FORWARD_PORT
Definition: bus.h:171
struct _PCIPBUSDATA * PPCIPBUSDATA
#define TRUE
Definition: types.h:120
#define KeInitializeSpinLock(sl)
Definition: env_spec_w32.h:604
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
#define DbgPrint
Definition: hal.h:12
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1099
ULONG NTAPI HaliPciInterfaceReadConfig(IN PBUS_HANDLER RootBusHandler, IN ULONG BusNumber, IN PCI_SLOT_NUMBER SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:934
KSPIN_LOCK HalpPCIConfigLock
Definition: pcibus.c:22
ULONG HalpMaxPciBus
Definition: pcibus.c:21
PCI_CONFIG_HANDLER PCIConfigHandler
Definition: pcibus.c:23
PCI_CONFIG_HANDLER PCIConfigHandlerType1
Definition: pcibus.c:35
BOOLEAN HalpPCIConfigInitialized
Definition: pcibus.c:20
PPCI_REGISTRY_INFO_INTERNAL NTAPI HalpQueryPciRegistryInfo(VOID)
Definition: pcibus.c:957
PCI_CONFIG_HANDLER PCIConfigHandlerType2
Definition: pcibus.c:57
PVOID BusData
Definition: haltypes.h:240
union _PCIPBUSDATA::@1460 Config
ULONG MaxDevice
Definition: bus.h:110
struct _PCIPBUSDATA::@1460::@1462 Type2
struct _PCIPBUSDATA::@1460::@1461 Type1
#define MAXULONG
Definition: typedefs.h:251

Referenced by HalpInitializePciBus(), HalReportResourceUsage(), and LoadBootDeviceDriver().

◆ HalpPCIConfig()

VOID NTAPI HalpPCIConfig ( IN PBUS_HANDLER  BusHandler,
IN PCI_SLOT_NUMBER  Slot,
IN PUCHAR  Buffer,
IN ULONG  Offset,
IN ULONG  Length,
IN FncConfigIO ConfigIO 
)

Definition at line 219 of file pcibus.c.

225{
227 ULONG i;
228 UCHAR State[20];
229
230 /* Synchronize the operation */
231 PCIConfigHandler.Synchronize(BusHandler, Slot, &OldIrql, State);
232
233 /* Loop every increment */
234 while (Length)
235 {
236 /* Find out the type of read/write we need to do */
237 i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
238
239 /* Do the read/write and return the number of bytes */
240 i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
241 State,
242 Buffer,
243 Offset);
244
245 /* Increment the buffer position and offset, and decrease the length */
246 Offset += i;
247 Buffer += i;
248 Length -= i;
249 }
250
251 /* Release the lock and PCI bus */
253}
UCHAR KIRQL
Definition: env_spec_w32.h:591
UCHAR PCIDeref[4][4]
Definition: pcibus.c:26
FncReleaseSync ReleaseSynchronzation
Definition: bus.h:146
FncSync Synchronize
Definition: bus.h:145
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:792

Referenced by HalpReadPCIConfig(), and HalpWritePCIConfig().

◆ HalpPCIISALine2Pin()

VOID NTAPI HalpPCIISALine2Pin ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN PCI_SLOT_NUMBER  SlotNumber,
IN PPCI_COMMON_CONFIG  PciNewData,
IN PPCI_COMMON_CONFIG  PciOldData 
)

Definition at line 690 of file pcibus.c.

695{
697}

Referenced by HalpAllocateAndInitPciBusHandler().

◆ HalpPCIPin2ISALine()

VOID NTAPI HalpPCIPin2ISALine ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN PCI_SLOT_NUMBER  SlotNumber,
IN PPCI_COMMON_CONFIG  PciData 
)

Definition at line 680 of file pcibus.c.

684{
686}

Referenced by HalpAllocateAndInitPciBusHandler().

◆ HalpPCIReleaseSynchronizationType2()

VOID NTAPI HalpPCIReleaseSynchronizationType2 ( IN PBUS_HANDLER  BusHandler,
IN KIRQL  OldIrql 
)

Definition at line 193 of file pcibus.c.

195{
196 PCI_TYPE2_CSE_BITS PciCfg2Cse;
197 PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
198
199 /* Clear CSE and bus number */
200 PciCfg2Cse.u.AsUCHAR = 0;
201 WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
202 WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
203
204 /* Release the lock */
206}
#define KeReleaseSpinLock(sl, irql)
Definition: env_spec_w32.h:627
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:21
union _PCI_TYPE2_CSE_BITS::@1465 u
UCHAR AsUCHAR
Definition: bus.h:210

◆ HalpPCIReleaseSynchronzationType1()

VOID NTAPI HalpPCIReleaseSynchronzationType1 ( IN PBUS_HANDLER  BusHandler,
IN KIRQL  OldIrql 
)

Definition at line 137 of file pcibus.c.

139{
140 PCI_TYPE1_CFG_BITS PciCfg1;
141
142 /* Clear the PCI Configuration Register */
143 PciCfg1.u.AsULONG = 0;
144 WRITE_PORT_ULONG(((PPCIPBUSDATA)BusHandler->BusData)->Config.Type1.Address,
145 PciCfg1.u.AsULONG);
146
147 /* Release the lock */
149}
VOID NTAPI WRITE_PORT_ULONG(IN PULONG Port, IN ULONG Value)
Definition: portio.c:123
union _PCI_TYPE1_CFG_BITS::@153 u

◆ HalpPCISynchronizeType1()

VOID NTAPI HalpPCISynchronizeType1 ( IN PBUS_HANDLER  BusHandler,
IN PCI_SLOT_NUMBER  Slot,
OUT PKIRQL  OldIrql,
OUT PPCI_TYPE1_CFG_BITS  PciCfg1 
)

Definition at line 118 of file pcibus.c.

122{
123 /* Setup the PCI Configuration Register */
124 PciCfg1->u.AsULONG = 0;
125 PciCfg1->u.bits.BusNumber = BusHandler->BusNumber;
126 PciCfg1->u.bits.DeviceNumber = Slot.u.bits.DeviceNumber;
127 PciCfg1->u.bits.FunctionNumber = Slot.u.bits.FunctionNumber;
128 PciCfg1->u.bits.Enable = TRUE;
129
130 /* Acquire the lock */
133}
#define KeRaiseIrql(irql, oldIrql)
Definition: env_spec_w32.h:597
#define HIGH_LEVEL
Definition: env_spec_w32.h:703
#define KeAcquireSpinLockAtDpcLevel(SpinLock)
Definition: ke.h:125

◆ HalpPCISynchronizeType2()

VOID NTAPI HalpPCISynchronizeType2 ( IN PBUS_HANDLER  BusHandler,
IN PCI_SLOT_NUMBER  Slot,
OUT PKIRQL  OldIrql,
OUT PPCI_TYPE2_ADDRESS_BITS  PciCfg 
)

Definition at line 162 of file pcibus.c.

166{
167 PCI_TYPE2_CSE_BITS PciCfg2Cse;
168 PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
169
170 /* Setup the configuration register */
171 PciCfg->u.AsUSHORT = 0;
172 PciCfg->u.bits.Agent = (USHORT)Slot.u.bits.DeviceNumber;
173 PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
174
175 /* Acquire the lock */
178
179 /* Setup the CSE Register */
180 PciCfg2Cse.u.AsUCHAR = 0;
181 PciCfg2Cse.u.bits.Enable = TRUE;
182 PciCfg2Cse.u.bits.FunctionNumber = (UCHAR)Slot.u.bits.FunctionNumber;
183 PciCfg2Cse.u.bits.Key = -1;
184
185 /* Write the bus number and CSE */
186 WRITE_PORT_UCHAR(BusData->Config.Type2.Forward,
187 (UCHAR)BusHandler->BusNumber);
188 WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
189}
struct _PCI_TYPE2_CSE_BITS::@1465::@1466 bits

◆ HalpPhase0GetPciDataByOffset()

ULONG HalpPhase0GetPciDataByOffset ( _In_ ULONG  Bus,
_In_ PCI_SLOT_NUMBER  PciSlot,
_Out_writes_bytes_all_(Length) PVOID  Buffer,
_In_ ULONG  Offset,
_In_ ULONG  Length 
)

Definition at line 368 of file pcibus.c.

374{
375 ULONG BytesLeft = Length;
376 PUCHAR BufferPtr = Buffer;
377 PCI_TYPE1_CFG_BITS PciCfg;
378
379#ifdef SARCH_XBOX
380 if (HalpXboxBlacklistedPCISlot(Bus, PciSlot))
381 {
383 return Length;
384 }
385#endif
386
387 PciCfg.u.AsULONG = 0;
388 PciCfg.u.bits.BusNumber = Bus;
389 PciCfg.u.bits.DeviceNumber = PciSlot.u.bits.DeviceNumber;
390 PciCfg.u.bits.FunctionNumber = PciSlot.u.bits.FunctionNumber;
391 PciCfg.u.bits.Enable = TRUE;
392
393 while (BytesLeft)
394 {
395 ULONG i;
396
397 PciCfg.u.bits.RegisterNumber = Offset / sizeof(ULONG);
399
400 i = PCIDeref[Offset % sizeof(ULONG)][BytesLeft % sizeof(ULONG)];
401 switch (i)
402 {
403 case 0:
404 {
406
407 /* Number of bytes read */
408 i = sizeof(ULONG);
409 break;
410 }
411 case 1:
412 {
414 Offset % sizeof(ULONG)));
415 break;
416 }
417 case 2:
418 {
420 Offset % sizeof(ULONG)));
421 break;
422 }
423
425 }
426
427 Offset += i;
428 BufferPtr += i;
429 BytesLeft -= i;
430 }
431
432 return Length;
433}
ULONG NTAPI READ_PORT_ULONG(IN PULONG Port)
Definition: portio.c:70
USHORT NTAPI READ_PORT_USHORT(IN PUSHORT Port)
Definition: portio.c:63
#define DEFAULT_UNREACHABLE
#define READ_PORT_UCHAR(p)
Definition: pc98vid.h:22
struct _PCI_TYPE1_CFG_BITS::@153::@154 bits
uint32_t * PULONG
Definition: typedefs.h:59
uint16_t * PUSHORT
Definition: typedefs.h:56
unsigned char * PUCHAR
Definition: typedefs.h:53

Referenced by HalpConfigureDebuggingDevice(), and HalpFindMatchingDebuggingDevice().

◆ HalpPhase0SetPciDataByOffset()

ULONG HalpPhase0SetPciDataByOffset ( _In_ ULONG  Bus,
_In_ PCI_SLOT_NUMBER  PciSlot,
_In_reads_bytes_(Length) PVOID  Buffer,
_In_ ULONG  Offset,
_In_ ULONG  Length 
)

Definition at line 437 of file pcibus.c.

443{
444 ULONG BytesLeft = Length;
445 PUCHAR BufferPtr = Buffer;
446 PCI_TYPE1_CFG_BITS PciCfg;
447
448#ifdef SARCH_XBOX
449 if (HalpXboxBlacklistedPCISlot(Bus, PciSlot))
450 {
451 return 0;
452 }
453#endif
454
455 PciCfg.u.AsULONG = 0;
456 PciCfg.u.bits.BusNumber = Bus;
457 PciCfg.u.bits.DeviceNumber = PciSlot.u.bits.DeviceNumber;
458 PciCfg.u.bits.FunctionNumber = PciSlot.u.bits.FunctionNumber;
459 PciCfg.u.bits.Enable = TRUE;
460
461 while (BytesLeft)
462 {
463 ULONG i;
464
465 PciCfg.u.bits.RegisterNumber = Offset / sizeof(ULONG);
467
468 i = PCIDeref[Offset % sizeof(ULONG)][BytesLeft % sizeof(ULONG)];
469 switch (i)
470 {
471 case 0:
472 {
474
475 /* Number of bytes written */
476 i = sizeof(ULONG);
477 break;
478 }
479 case 1:
480 {
482 *BufferPtr);
483 break;
484 }
485 case 2:
486 {
488 *(PUSHORT)BufferPtr);
489 break;
490 }
491
493 }
494
495 Offset += i;
496 BufferPtr += i;
497 BytesLeft -= i;
498 }
499
500 return Length;
501}
VOID NTAPI WRITE_PORT_USHORT(IN PUSHORT Port, IN USHORT Value)
Definition: portio.c:115

Referenced by HalpConfigureDebuggingDevice().

◆ HalpQueryPciRegistryInfo()

PPCI_REGISTRY_INFO_INTERNAL NTAPI HalpQueryPciRegistryInfo ( VOID  )

Definition at line 957 of file pcibus.c.

958{
959#ifndef _MINIHAL_
960 WCHAR NameBuffer[8];
962 UNICODE_STRING KeyName, ConfigName, IdentName;
963 HANDLE KeyHandle, BusKeyHandle, CardListHandle;
965 UCHAR KeyBuffer[sizeof(CM_FULL_RESOURCE_DESCRIPTOR) + 100];
966 PKEY_VALUE_FULL_INFORMATION ValueInfo = (PVOID)KeyBuffer;
967 UCHAR PartialKeyBuffer[sizeof(KEY_VALUE_PARTIAL_INFORMATION) +
968 sizeof(PCI_CARD_DESCRIPTOR)];
969 PKEY_VALUE_PARTIAL_INFORMATION PartialValueInfo = (PVOID)PartialKeyBuffer;
970 KEY_FULL_INFORMATION KeyInformation;
972 PWSTR Tag;
973 ULONG i, ElementCount;
974 PCM_FULL_RESOURCE_DESCRIPTOR FullDescriptor;
975 PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptor;
976 PPCI_REGISTRY_INFO PciRegInfo;
977 PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
978 PPCI_CARD_DESCRIPTOR CardDescriptor;
979
980 /* Setup the object attributes for the key */
982 L"\\Registry\\Machine\\Hardware\\Description\\"
983 L"System\\MultiFunctionAdapter");
985 &KeyName,
987 NULL,
988 NULL);
989
990 /* Open the key */
991 Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
992 if (!NT_SUCCESS(Status)) return NULL;
993
994 /* Setup the receiving string */
995 KeyName.Buffer = NameBuffer;
996 KeyName.MaximumLength = sizeof(NameBuffer);
997
998 /* Setup the configuration and identifier key names */
999 RtlInitUnicodeString(&ConfigName, L"Configuration Data");
1000 RtlInitUnicodeString(&IdentName, L"Identifier");
1001
1002 /* Keep looping for each ID */
1003 for (i = 0; TRUE; i++)
1004 {
1005 /* Setup the key name */
1008 &KeyName,
1010 KeyHandle,
1011 NULL);
1012
1013 /* Open it */
1014 Status = ZwOpenKey(&BusKeyHandle, KEY_READ, &ObjectAttributes);
1015 if (!NT_SUCCESS(Status))
1016 {
1017 /* None left, fail */
1019 return NULL;
1020 }
1021
1022 /* Read the registry data */
1023 Status = ZwQueryValueKey(BusKeyHandle,
1024 &IdentName,
1026 ValueInfo,
1027 sizeof(KeyBuffer),
1028 &ResultLength);
1029 if (!NT_SUCCESS(Status))
1030 {
1031 /* Failed, try the next one */
1032 ZwClose(BusKeyHandle);
1033 continue;
1034 }
1035
1036 /* Get the PCI Tag and validate it */
1037 Tag = (PWSTR)((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
1038 if ((Tag[0] != L'P') ||
1039 (Tag[1] != L'C') ||
1040 (Tag[2] != L'I') ||
1041 (Tag[3]))
1042 {
1043 /* Not a valid PCI entry, skip it */
1044 ZwClose(BusKeyHandle);
1045 continue;
1046 }
1047
1048 /* Now read our PCI structure */
1049 Status = ZwQueryValueKey(BusKeyHandle,
1050 &ConfigName,
1052 ValueInfo,
1053 sizeof(KeyBuffer),
1054 &ResultLength);
1055 ZwClose(BusKeyHandle);
1056 if (!NT_SUCCESS(Status)) continue;
1057
1058 /* We read it OK! Get the actual resource descriptors */
1059 FullDescriptor = (PCM_FULL_RESOURCE_DESCRIPTOR)
1060 ((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
1061 PartialDescriptor = (PCM_PARTIAL_RESOURCE_DESCRIPTOR)
1062 ((ULONG_PTR)FullDescriptor->
1063 PartialResourceList.PartialDescriptors);
1064
1065 /* Check if this is our PCI Registry Information */
1066 if (PartialDescriptor->Type == CmResourceTypeDeviceSpecific)
1067 {
1068 /* It is, stop searching */
1069 break;
1070 }
1071 }
1072
1073 /* Close the key */
1075
1076 /* Save the PCI information for later */
1077 PciRegInfo = (PPCI_REGISTRY_INFO)(PartialDescriptor + 1);
1078
1079 /* Assume no Card List entries */
1080 ElementCount = 0;
1081
1082 /* Set up for checking the PCI Card List key */
1084 L"\\Registry\\Machine\\System\\CurrentControlSet\\"
1085 L"Control\\PnP\\PCI\\CardList");
1087 &KeyName,
1089 NULL,
1090 NULL);
1091
1092 /* Attempt to open it */
1093 Status = ZwOpenKey(&CardListHandle, KEY_READ, &ObjectAttributes);
1094 if (NT_SUCCESS(Status))
1095 {
1096 /* It exists, so let's query it */
1097 Status = ZwQueryKey(CardListHandle,
1099 &KeyInformation,
1100 sizeof(KEY_FULL_INFORMATION),
1101 &ResultLength);
1102 if (!NT_SUCCESS(Status))
1103 {
1104 /* Failed to query, so no info */
1105 PciRegistryInfo = NULL;
1106 }
1107 else
1108 {
1109 /* Allocate the full structure */
1110 PciRegistryInfo =
1113 (KeyInformation.Values *
1114 sizeof(PCI_CARD_DESCRIPTOR)),
1115 TAG_HAL);
1116 if (PciRegistryInfo)
1117 {
1118 /* Get the first card descriptor entry */
1119 CardDescriptor = (PPCI_CARD_DESCRIPTOR)(PciRegistryInfo + 1);
1120
1121 /* Loop all the values */
1122 for (i = 0; i < KeyInformation.Values; i++)
1123 {
1124 /* Attempt to get the value */
1125 Status = ZwEnumerateValueKey(CardListHandle,
1126 i,
1128 PartialValueInfo,
1129 sizeof(PartialKeyBuffer),
1130 &ResultLength);
1131 if (!NT_SUCCESS(Status))
1132 {
1133 /* Something went wrong, stop the search */
1134 break;
1135 }
1136
1137 /* Make sure it is correctly sized */
1138 if (PartialValueInfo->DataLength == sizeof(PCI_CARD_DESCRIPTOR))
1139 {
1140 /* Sure is, copy it over */
1141 *CardDescriptor = *(PPCI_CARD_DESCRIPTOR)
1142 PartialValueInfo->Data;
1143
1144 /* One more Card List entry */
1145 ElementCount++;
1146
1147 /* Move to the next descriptor */
1148 CardDescriptor = (CardDescriptor + 1);
1149 }
1150 }
1151 }
1152 }
1153
1154 /* Close the Card List key */
1155 ZwClose(CardListHandle);
1156 }
1157 else
1158 {
1159 /* No key, no Card List */
1160 PciRegistryInfo = NULL;
1161 }
1162
1163 /* Check if we failed to get the full structure */
1164 if (!PciRegistryInfo)
1165 {
1166 /* Just allocate the basic structure then */
1167 PciRegistryInfo = ExAllocatePoolWithTag(NonPagedPool,
1169 TAG_HAL);
1170 if (!PciRegistryInfo) return NULL;
1171 }
1172
1173 /* Save the info we got */
1174 PciRegistryInfo->MajorRevision = PciRegInfo->MajorRevision;
1175 PciRegistryInfo->MinorRevision = PciRegInfo->MinorRevision;
1176 PciRegistryInfo->NoBuses = PciRegInfo->NoBuses;
1177 PciRegistryInfo->HardwareMechanism = PciRegInfo->HardwareMechanism;
1178 PciRegistryInfo->ElementCount = ElementCount;
1179
1180 /* Return it */
1181 return PciRegistryInfo;
1182#else
1183 return NULL;
1184#endif
1185}
IN PUNICODE_STRING IN POBJECT_ATTRIBUTES ObjectAttributes
Definition: conport.c:36
#define NonPagedPool
Definition: env_spec_w32.h:307
struct _CM_FULL_RESOURCE_DESCRIPTOR CM_FULL_RESOURCE_DESCRIPTOR
struct _CM_FULL_RESOURCE_DESCRIPTOR * PCM_FULL_RESOURCE_DESCRIPTOR
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR * PCM_PARTIAL_RESOURCE_DESCRIPTOR
#define CmResourceTypeDeviceSpecific
Definition: hwresource.cpp:127
#define OBJ_CASE_INSENSITIVE
Definition: winternl.h:228
#define InitializeObjectAttributes(p, n, a, r, s)
Definition: reg.c:106
_Must_inspect_result_ _Out_ PNDIS_STATUS _In_ NDIS_HANDLE _In_ ULONG _Out_ PNDIS_STRING _Out_ PNDIS_HANDLE KeyHandle
Definition: ndis.h:4715
NTSYSAPI NTSTATUS NTAPI ZwClose(_In_ HANDLE Handle)
@ KeyFullInformation
Definition: nt_native.h:1133
@ KeyValuePartialInformation
Definition: nt_native.h:1182
@ KeyValueFullInformation
Definition: nt_native.h:1181
#define KEY_READ
Definition: nt_native.h:1023
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
struct _KEY_VALUE_PARTIAL_INFORMATION KEY_VALUE_PARTIAL_INFORMATION
NTSYSAPI NTSTATUS NTAPI RtlIntegerToUnicodeString(ULONG Value, ULONG Base, PUNICODE_STRING String)
#define L(x)
Definition: ntvdm.h:50
struct _PCI_CARD_DESCRIPTOR * PPCI_CARD_DESCRIPTOR
struct _PCI_REGISTRY_INFO * PPCI_REGISTRY_INFO
UCHAR MajorRevision
Definition: pci.h:107
UCHAR NoBuses
Definition: pci.h:109
UCHAR HardwareMechanism
Definition: pci.h:110
UCHAR MinorRevision
Definition: pci.h:108
uint16_t * PWSTR
Definition: typedefs.h:56
_Must_inspect_result_ _In_ WDFDEVICE _In_ DEVICE_REGISTRY_PROPERTY _In_ ULONG _Out_ PULONG ResultLength
Definition: wdfdevice.h:3776
_Must_inspect_result_ _In_ WDFDEVICE _In_ BOOLEAN _In_opt_ PVOID Tag
Definition: wdfdevice.h:4065
_Must_inspect_result_ _In_ WDFDEVICE _In_ PCUNICODE_STRING KeyName
Definition: wdfdevice.h:2699
__wchar_t WCHAR
Definition: xmlstorage.h:180

Referenced by HalpInitializePciBus(), and HalpInitializePciStubs().

◆ HalpReadPCIConfig()

VOID NTAPI HalpReadPCIConfig ( IN PBUS_HANDLER  BusHandler,
IN PCI_SLOT_NUMBER  Slot,
IN PVOID  Buffer,
IN ULONG  Offset,
IN ULONG  Length 
)

Definition at line 257 of file pcibus.c.

262{
263 /* Validate the PCI Slot */
264 if (!HalpValidPCISlot(BusHandler, Slot))
265 {
266 /* Fill the buffer with invalid data */
268 }
269 else
270 {
271 /* Send the request */
272 HalpPCIConfig(BusHandler,
273 Slot,
274 Buffer,
275 Offset,
276 Length,
278 }
279}
BOOLEAN NTAPI HalpValidPCISlot(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot)
Definition: pcibus.c:329
VOID NTAPI HalpPCIConfig(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PUCHAR Buffer, IN ULONG Offset, IN ULONG Length, IN FncConfigIO *ConfigIO)
Definition: pcibus.c:219
FncConfigIO ConfigRead[3]
Definition: bus.h:147

Referenced by HaliPciInterfaceReadConfig(), HalpAllocateAndInitPciBusHandler(), HalpAssignPCISlotResources(), HalpDebugPciDumpBus(), HalpGetPciBridgeConfig(), HalpGetPCIData(), HalpInitializePciBus(), HalpIsValidPCIDevice(), HalpSetPCIData(), and HalpValidPCISlot().

◆ HalpSetPCIData()

ULONG NTAPI HalpSetPCIData ( IN PBUS_HANDLER  BusHandler,
IN PBUS_HANDLER  RootHandler,
IN ULONG  SlotNumber,
IN PVOID  Buffer,
IN ULONG  Offset,
IN ULONG  Length 
)

Definition at line 587 of file pcibus.c.

593{
594 PCI_SLOT_NUMBER Slot;
595 UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
596 PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
597 ULONG Len = 0;
598
599 Slot.u.AsULONG = SlotNumber;
600#ifdef SARCH_XBOX
601 if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
602 return 0;
603#endif
604
605 /* Normalize the length */
606 if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
607
608 /* Check if this is a vendor-specific read */
610 {
611 /* Read the header */
612 HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
613
614 /* Make sure the vendor is valid */
615 if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
616 }
617 else
618 {
619 /* Read the entire header and validate the vendor ID */
621 HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
622 if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
623
624 /* Return what's after the offset and normalize */
625 Len -= Offset;
626 if (Len > Length) Len = Length;
627
628 /* Copy the specific caller data */
629 RtlMoveMemory(PciBuffer + Offset, Buffer, Len);
630
631 /* Write the actual configuration data */
632 HalpWritePCIConfig(BusHandler, Slot, PciBuffer + Offset, Offset, Len);
633
634 /* Update buffer and offset, decrement total length */
635 Offset += Len;
637 Length -= Len;
638 }
639
640 /* Now we still have something to copy */
641 if (Length)
642 {
643 /* Check if it's vendor-specific data */
645 {
646 /* Read it now */
647 HalpWritePCIConfig(BusHandler, Slot, Buffer, Offset, Length);
648 Len += Length;
649 }
650 }
651
652 /* Update the total length read */
653 return Len;
654}

Referenced by HalpAllocateAndInitPciBusHandler(), and HalSetBusDataByOffset().

◆ HalpValidPCISlot()

BOOLEAN NTAPI HalpValidPCISlot ( IN PBUS_HANDLER  BusHandler,
IN PCI_SLOT_NUMBER  Slot 
)

Definition at line 329 of file pcibus.c.

331{
332 PCI_SLOT_NUMBER MultiSlot;
333 PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
334 UCHAR HeaderType;
335 //ULONG Device;
336
337 /* Simple validation */
338 if (Slot.u.bits.Reserved) return FALSE;
339 if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice) return FALSE;
340
341#ifdef SARCH_XBOX
342 if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
343 return FALSE;
344#endif
345
346 /* Function 0 doesn't need checking */
347 if (!Slot.u.bits.FunctionNumber) return TRUE;
348
349 /* Functions 0+ need Multi-Function support, so check the slot */
350 //Device = Slot.u.bits.DeviceNumber;
351 MultiSlot = Slot;
352 MultiSlot.u.bits.FunctionNumber = 0;
353
354 /* Send function 0 request to get the header back */
355 HalpReadPCIConfig(BusHandler,
356 MultiSlot,
357 &HeaderType,
358 FIELD_OFFSET(PCI_COMMON_CONFIG, HeaderType),
359 sizeof(UCHAR));
360
361 /* Now make sure the header is multi-function */
362 if (!(HeaderType & PCI_MULTIFUNCTION) || (HeaderType == 0xFF)) return FALSE;
363 return TRUE;
364}
if(dx< 0)
Definition: linetemp.h:194
struct _PCI_SLOT_NUMBER::@3816::@3817 bits
#define PCI_MULTIFUNCTION
Definition: iotypes.h:3604

Referenced by HalpReadPCIConfig(), and HalpWritePCIConfig().

◆ HalpWritePCIConfig()

VOID NTAPI HalpWritePCIConfig ( IN PBUS_HANDLER  BusHandler,
IN PCI_SLOT_NUMBER  Slot,
IN PVOID  Buffer,
IN ULONG  Offset,
IN ULONG  Length 
)

Definition at line 283 of file pcibus.c.

288{
289 /* Validate the PCI Slot */
290 if (HalpValidPCISlot(BusHandler, Slot))
291 {
292 /* Send the request */
293 HalpPCIConfig(BusHandler,
294 Slot,
295 Buffer,
296 Offset,
297 Length,
299 }
300}
FncConfigIO ConfigWrite[3]
Definition: bus.h:148

Referenced by HalpAllocateAndInitPciBusHandler(), HalpAssignPCISlotResources(), HalpDebugPciDumpBus(), and HalpSetPCIData().

◆ PciSize()

static ULONG NTAPI PciSize ( ULONG  Base,
ULONG  Mask 
)
static

Definition at line 748 of file pcibus.c.

749{
750 ULONG Size = Mask & Base; /* Find the significant bits */
751 Size = Size & ~(Size - 1); /* Get the lowest of them to find the decode size */
752 return Size;
753}
unsigned int Mask
Definition: fpcontrol.c:82
_In_opt_ ULONG Base
Definition: rtlfuncs.h:2427

Referenced by HalpAssignPCISlotResources().

Variable Documentation

◆ HalpBusType

◆ HalpFakePciBusData

PCIPBUSDATA HalpFakePciBusData
Initial value:
=
{
{
{{{0, 0, 0}}},
{0, 0, 0, 0}
},
{{0, 0}},
32,
}
#define PCI_DATA_TAG
Definition: iotypes.h:5275
#define PCI_DATA_VERSION
Definition: iotypes.h:5276

Definition at line 78 of file pcibus.c.

◆ HalpFakePciBusHandler

BUS_HANDLER HalpFakePciBusHandler
Initial value:
=
{
1,
0,
0,
{0, 0, 0, 0},
}
ULONG(NTAPI * PGETSETBUSDATA)(_In_ PBUS_HANDLER BusHandler, _In_ PBUS_HANDLER RootHandler, _In_ ULONG SlotNumber, _Out_ PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)
Definition: haltypes.h:125
ULONG NTAPI HalpGetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:507
ULONG NTAPI HalpSetPCIData(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: pcibus.c:587
NTSTATUS NTAPI HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler, IN PBUS_HANDLER RootHandler, IN PUNICODE_STRING RegistryPath, IN PUNICODE_STRING DriverClassName OPTIONAL, IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT DeviceObject OPTIONAL, IN ULONG Slot, IN OUT PCM_RESOURCE_LIST *AllocatedResources)
Definition: pcibus.c:798
PCIPBUSDATA HalpFakePciBusData
Definition: pcibus.c:78

Definition at line 94 of file pcibus.c.

Referenced by HalGetBusDataByOffset(), HaliPciInterfaceReadConfig(), HalpAssignSlotResources(), HalpInitializePciStubs(), and HalSetBusDataByOffset().

◆ HalpMaxPciBus

ULONG HalpMaxPciBus

Definition at line 21 of file pcibus.c.

Referenced by HalpInitializePciStubs().

◆ HalpMinPciBus

ULONG HalpMinPciBus

Definition at line 21 of file pcibus.c.

Referenced by HalGetBusDataByOffset().

◆ HalpPCIConfigInitialized

BOOLEAN HalpPCIConfigInitialized

Definition at line 20 of file pcibus.c.

Referenced by HalGetBusDataByOffset(), HalpInitializePciStubs(), and HalSetBusDataByOffset().

◆ HalpPCIConfigLock

◆ HalpPciLockSettings

BOOLEAN HalpPciLockSettings
extern

Definition at line 17 of file halinit.c.

Referenced by HalpAdjustPCIResourceList(), and HalpGetParameters().

◆ PCIConfigHandler

◆ PCIConfigHandlerType1

PCI_CONFIG_HANDLER PCIConfigHandlerType1
Initial value:
=
{
{
(FncConfigIO)HalpPCIReadUlongType1,
(FncConfigIO)HalpPCIReadUcharType1,
(FncConfigIO)HalpPCIReadUshortType1
},
{
(FncConfigIO)HalpPCIWriteUlongType1,
(FncConfigIO)HalpPCIWriteUcharType1,
(FncConfigIO)HalpPCIWriteUshortType1
}
}
ULONG(NTAPI * FncConfigIO)(IN PPCIPBUSDATA BusData, IN PVOID State, IN PUCHAR Buffer, IN ULONG Offset)
Definition: bus.h:122
VOID(NTAPI * FncSync)(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, IN PKIRQL Irql, IN PVOID State)
Definition: bus.h:130
VOID(NTAPI * FncReleaseSync)(IN PBUS_HANDLER BusHandler, IN KIRQL Irql)
Definition: bus.h:138
VOID NTAPI HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, OUT PKIRQL OldIrql, OUT PPCI_TYPE1_CFG_BITS PciCfg1)
Definition: pcibus.c:118
VOID NTAPI HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler, IN KIRQL OldIrql)
Definition: pcibus.c:137

Definition at line 35 of file pcibus.c.

Referenced by HalpAllocateAndInitPciBusHandler(), and HalpInitializePciStubs().

◆ PCIConfigHandlerType2

PCI_CONFIG_HANDLER PCIConfigHandlerType2
Initial value:
=
{
{
(FncConfigIO)HalpPCIReadUlongType2,
(FncConfigIO)HalpPCIReadUcharType2,
(FncConfigIO)HalpPCIReadUshortType2
},
{
(FncConfigIO)HalpPCIWriteUlongType2,
(FncConfigIO)HalpPCIWriteUcharType2,
(FncConfigIO)HalpPCIWriteUshortType2
}
}
VOID NTAPI HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler, IN PCI_SLOT_NUMBER Slot, OUT PKIRQL OldIrql, OUT PPCI_TYPE2_ADDRESS_BITS PciCfg)
Definition: pcibus.c:162
VOID NTAPI HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler, IN KIRQL OldIrql)
Definition: pcibus.c:193

Definition at line 57 of file pcibus.c.

Referenced by HalpAllocateAndInitPciBusHandler(), and HalpInitializePciStubs().

◆ PCIDeref

UCHAR PCIDeref[4][4]
Initial value:
=
{
{0, 1, 2, 2},
{1, 1, 1, 1},
{2, 1, 2, 2},
{1, 1, 1, 1}
}

Definition at line 26 of file pcibus.c.

Referenced by HalpPCIConfig(), HalpPhase0GetPciDataByOffset(), and HalpPhase0SetPciDataByOffset().