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#define | KF_SMEP 0x00000001 |
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#define | KF_RDTSC 0x00000002 |
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#define | KF_CR4 0x00000004 |
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#define | KF_CMOV 0x00000008 |
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#define | KF_GLOBAL_PAGE 0x00000010 |
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#define | KF_LARGE_PAGE 0x00000020 |
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#define | KF_MTRR 0x00000040 |
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#define | KF_CMPXCHG8B 0x00000080 |
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#define | KF_MMX 0x00000100 |
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#define | KF_DTS 0x00000200 |
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#define | KF_PAT 0x00000400 |
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#define | KF_FXSR 0x00000800 |
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#define | KF_FAST_SYSCALL 0x00001000 |
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#define | KF_XMMI 0x00002000 |
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#define | KF_3DNOW 0x00004000 |
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#define | KF_AMDK6MTRR 0x00008000 |
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#define | KF_XSAVEOPT 0x00008000 |
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#define | KF_XMMI64 0x00010000 |
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#define | KF_BRANCH 0x00020000 |
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#define | KF_00040000 0x00040000 |
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#define | KF_SSE3 0x00080000 |
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#define | KF_CMPXCHG16B 0x00100000 |
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#define | KF_AUTHENTICAMD 0x00200000 |
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#define | KF_ACNT2 0x00400000 |
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#define | KF_XSTATE 0x00800000 |
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#define | KF_GENUINE_INTEL 0x01000000 |
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#define | KF_02000000 0x02000000 |
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#define | KF_SLAT 0x04000000 |
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#define | KF_VIRT_FIRMWARE_ENABLED 0x08000000 |
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#define | KF_RDWRFSGSBASE 0x10000000 |
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#define | KF_NX_BIT 0x20000000 |
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#define | KF_NX_DISABLED 0x40000000 |
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#define | KF_NX_ENABLED 0x80000000 |
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#define | KF_RDRAND 0x0000000100000000ULL |
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#define | KF_SMAP 0x0000000200000000ULL |
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#define | KF_RDTSCP 0x0000000400000000ULL |
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#define | KF_HUGEPAGE 0x0000002000000000ULL |
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#define | KF_XSAVES 0x0000004000000000ULL |
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#define | KF_FPU_LEAKAGE 0x0000020000000000ULL |
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#define | KF_CAT 0x0000100000000000ULL |
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#define | KF_CET_SS 0x0000400000000000ULL |
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#define | KF_SSSE3 0x0000800000000000ULL |
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#define | KF_SSE4_1 0x0001000000000000ULL |
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#define | KF_SSE4_2 0x0002000000000000ULL |
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#define | KF_XSAVEOPT_BIT 15 |
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#define | KF_XSTATE_BIT 23 |
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#define | KF_RDWRFSGSBASE_BIT 28 |
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#define | KF_XSAVES_BIT 38 |
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#define | KF_FPU_LEAKAGE_BIT 41 |
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#define | KF_CAT_BIT 44 |
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#define | DOUBLE_FAULT_STACK_SIZE 0x2000 |
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#define | MACHINE_TYPE_ISA 0x0000 |
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#define | MACHINE_TYPE_EISA 0x0001 |
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#define | MACHINE_TYPE_MCA 0x0002 |
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#define | I386_TASK_GATE 0x5 |
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#define | I386_TSS 0x9 |
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#define | I386_ACTIVE_TSS 0xB |
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#define | I386_CALL_GATE 0xC |
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#define | I386_INTERRUPT_GATE 0xE |
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#define | I386_TRAP_GATE 0xF |
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#define | RPL_MASK 0x0003 |
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#define | MODE_MASK 0x0001 |
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#define | KGDT64_NULL 0x0000 |
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#define | KGDT64_R0_CODE 0x0010 |
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#define | KGDT64_R0_DATA 0x0018 |
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#define | KGDT64_R3_CMCODE 0x0020 |
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#define | KGDT64_R3_DATA 0x0028 |
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#define | KGDT64_R3_CODE 0x0030 |
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#define | KGDT64_SYS_TSS 0x0040 |
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#define | KGDT64_R3_CMTEB 0x0050 |
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#define | KGDT64_R0_LDT 0x0060 |
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#define | CR0_PE 0x00000001 |
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#define | CR0_MP 0x00000002 |
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#define | CR0_EM 0x00000004 |
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#define | CR0_TS 0x00000008 |
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#define | CR0_ET 0x00000010 |
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#define | CR0_NE 0x00000020 |
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#define | CR0_WP 0x00010000 |
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#define | CR0_AM 0x00040000 |
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#define | CR0_NW 0x20000000 |
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#define | CR0_CD 0x40000000 |
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#define | CR0_PG 0x80000000 |
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#define | CR4_VME 0x1 |
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#define | CR4_PVI 0x2 |
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#define | CR4_TSD 0x4 |
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#define | CR4_DE 0x8 |
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#define | CR4_PSE 0x10 |
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#define | CR4_PAE 0x20 |
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#define | CR4_MCE 0x40 |
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#define | CR4_PGE 0x80 |
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#define | CR4_FXSR 0x200 |
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#define | CR4_XMMEXCPT 0x400 |
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#define | CR4_CHANNELS 0x800 |
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#define | CR4_XSAVE 0x40000 |
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#define | DR7_LEGAL 0xFFFF0355 |
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#define | DR7_ACTIVE 0x00000355 |
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#define | DR7_TRACE_BRANCH 0x00000200 |
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#define | DR7_LAST_BRANCH 0x00000100 |
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#define | DEBUG_ACTIVE_DR7 0x0001 |
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#define | DEBUG_ACTIVE_INSTRUMENTED 0x0002 |
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#define | DEBUG_ACTIVE_DBG_INSTRUMENTED 0x0003 |
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#define | DEBUG_ACTIVE_MINIMAL_THREAD 0x0004 |
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#define | DEBUG_ACTIVE_PRIMARY_THREAD 0x0080 |
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#define | DEBUG_ACTIVE_PRIMARY_THREAD_BIT 0x0007 |
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#define | DEBUG_ACTIVE_PRIMARY_THREAD_LOCK_BIT 0x001F |
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#define | DEBUG_ACTIVE_SCHEDULED_THREAD 0x0040 |
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#define | DEBUG_ACTIVE_SCHEDULED_THREAD_BIT 0x0006 |
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#define | DEBUG_ACTIVE_SCHEDULED_THREAD_LOCK_BIT 0x001E |
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#define | DEBUG_ACTIVE_SCHEDULED_THREAD_LOCK 0x40000000 |
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#define | EFLAGS_CF 0x01L |
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#define | EFLAGS_ZF 0x40L |
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#define | EFLAGS_TF 0x100L |
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#define | EFLAGS_INTERRUPT_MASK 0x200L |
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#define | EFLAGS_DF 0x400L |
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#define | EFLAGS_IOPL 0x3000L |
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#define | EFLAGS_NESTED_TASK 0x4000L |
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#define | EFLAGS_RF 0x10000 |
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#define | EFLAGS_V86_MASK 0x20000 |
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#define | EFLAGS_ALIGN_CHECK 0x40000 |
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#define | EFLAGS_VIF 0x80000 |
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#define | EFLAGS_VIP 0x100000 |
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#define | EFLAGS_ID 0x200000 |
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#define | EFLAGS_USER_SANITIZE 0x3F4DD7 |
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#define | EFLAG_SIGN 0x8000 |
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#define | EFLAG_ZERO 0x4000 |
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#define | EFLAGS_TF_MASK 0x0100 |
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#define | EFLAGS_TF_SHIFT 0x0008 |
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#define | EFLAGS_ID_MASK 0x200000 |
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#define | EFLAGS_IF_MASK 0x0200 |
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#define | EFLAGS_IF_SHIFT 0x0009 |
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#define | XSW_INVALID_OPERATION 0x0001 |
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#define | XSW_DENORMAL 0x0002 |
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#define | XSW_ZERO_DIVIDE 0x0004 |
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#define | XSW_OVERFLOW 0x0008 |
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#define | XSW_UNDERFLOW 0x0010 |
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#define | XSW_PRECISION 0x0020 |
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#define | XCW_INVALID_OPERATION 0x0080 |
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#define | XCW_DENORMAL 0x0100 |
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#define | XCW_ZERO_DIVIDE 0x0200 |
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#define | XCW_OVERFLOW 0x0400 |
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#define | XCW_UNDERFLOW 0x0800 |
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#define | XCW_PRECISION 0x1000 |
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#define | XCW_ROUND_CONTROL 0x6000 |
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#define | XCW_FLUSH_ZERO 0x8000 |
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#define | XSW_ERROR_MASK 0x003F |
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#define | XSW_ERROR_SHIFT 7 |
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#define | FSW_INVALID_OPERATION 0x0001 |
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#define | FSW_DENORMAL 0x0002 |
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#define | FSW_ZERO_DIVIDE 0x0004 |
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#define | FSW_OVERFLOW 0x0008 |
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#define | FSW_UNDERFLOW 0x0010 |
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#define | FSW_PRECISION 0x0020 |
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#define | FSW_STACK_FAULT 0x0040 |
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#define | FSW_ERROR_SUMMARY 0x0080 |
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#define | FSW_CONDITION_CODE_0 0x0100 |
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#define | FSW_CONDITION_CODE_1 0x0200 |
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#define | FSW_CONDITION_CODE_2 0x0400 |
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#define | FSW_CONDITION_CODE_3 0x4000 |
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#define | FSW_ERROR_MASK 0x003F |
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#define | MSR_EFER 0xC0000080 |
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#define | MSR_STAR 0xC0000081 |
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#define | MSR_LSTAR 0xC0000082 |
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#define | MSR_CSTAR 0xC0000083 |
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#define | MSR_SYSCALL_MASK 0xC0000084 |
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#define | MSR_FS_BASE 0xC0000100 |
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#define | MSR_GS_BASE 0xC0000101 |
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#define | MSR_GS_SWAP 0xC0000102 |
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#define | MSR_MCG_STATUS 0x017A |
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#define | MSR_AMD_ACCESS 0x9C5A203A |
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#define | MSR_IA32_MISC_ENABLE 0x000001A0 |
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#define | MSR_LAST_BRANCH_FROM 0x01DB |
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#define | MSR_LAST_BRANCH_TO 0x01DC |
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#define | MSR_LAST_EXCEPTION_FROM 0x01DD |
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#define | MSR_LAST_EXCEPTION_TO 0x01DE |
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#define | PAT_UC 0ULL |
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#define | PAT_WC 1ULL |
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#define | PAT_WT 4ULL |
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#define | PAT_WP 5ULL |
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#define | PAT_WB 6ULL |
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#define | PAT_UCM 7ULL |
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#define | MSR_SCE 0x0001 |
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#define | MSR_LME 0x0100 |
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#define | MSR_LMA 0x0400 |
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#define | MSR_NXE 0x0800 |
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#define | MSR_PAT 0x0277 |
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#define | MSR_DEBUG_CTL 0x01D9 |
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#define | MSR_XD_ENABLE_MASK 0xFFFFFFFB |
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#define | MSR_DEBUG_CTL_LBR 0x0001 |
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#define | MSR_DEBUG_CTL_BTF 0x0002 |
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#define | IPI_APC 1 |
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#define | IPI_DPC 2 |
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#define | IPI_FREEZE 4 |
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#define | IPI_PACKET_READY 8 |
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#define | IPI_SYNCH_REQUEST 16 |
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#define | IPI_FROZEN_STATE_RUNNING 0 |
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#define | IPI_FROZEN_STATE_FROZEN 2 |
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#define | IPI_FROZEN_STATE_THAW 3 |
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#define | IPI_FROZEN_STATE_OWNER 4 |
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#define | IPI_FROZEN_STATE_TARGET_FREEZE 5 |
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#define | IPI_FROZEN_FLAG_ACTIVE 0x20 |
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#define | PRCB_MINOR_VERSION 1 |
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#define | PRCB_MAJOR_VERSION 1 |
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#define | PRCB_BUILD_DEBUG 1 |
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#define | PRCB_BUILD_UNIPROCESSOR 2 |
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#define | KEXCEPTION_ACTIVE_INTERRUPT_FRAME 0x0000 |
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#define | KEXCEPTION_ACTIVE_EXCEPTION_FRAME 0x0001 |
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#define | KEXCEPTION_ACTIVE_SERVICE_FRAME 0x0002 |
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#define | PRIMARY_VECTOR_BASE 0x30 |
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#define | MAXIMUM_IDTVECTOR 0xFF |
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#define | INITIAL_STALL_COUNT 100 |
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#define | MM_HAL_VA_START 0xFFFFFFFFFFC00000ULL /* This is Vista+ */ |
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#define | MM_HAL_VA_END 0xFFFFFFFFFFFFFFFFULL |
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#define | APIC_BASE 0xFFFFFFFFFFFE0000ULL |
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#define | IO_ACCESS_MAP_NONE 0 |
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#define | IOPM_OFFSET FIELD_OFFSET(KTSS, IoMaps[0].IoMap) |
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#define | KiComputeIopmOffset(MapNumber) |
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#define | KSEG0_BASE 0xfffff80000000000ULL |
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#define | NMI_STACK_SIZE 0x2000 |
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#define | ISR_STACK_SIZE 0x6000 |
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#define | MAX_SYSCALL_PARAM_SIZE (16 * 8) |
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#define | SYNCH_LEVEL DISPATCH_LEVEL |
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#define | NUMBER_POOL_LOOKASIDE_LISTS 32 |
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#define | _LDT_ENTRY_DEFINED |
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#define | KGDTENTRY KGDTENTRY64 |
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#define | PKGDTENTRY PKGDTENTRY64 |
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#define | KIDTENTRY KIDTENTRY64 |
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#define | PKIDTENTRY PKIDTENTRY64 |
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#define | KTSS KTSS64 |
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#define | PKTSS PKTSS64 |
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#define | PROCESSOR_START_FLAG_FORCE_ENABLE_NX 0x0001 |
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