ReactOS 0.4.15-dev-5858-g16decc6
cpu.c
Go to the documentation of this file.
1/*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/amd64/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
7 * Timo Kreuzer (timo.kreuzer@reactos.org)
8 */
9
10/* INCLUDES *****************************************************************/
11
12#include <ntoskrnl.h>
13#define NDEBUG
14#include <debug.h>
15
16/* GLOBALS *******************************************************************/
17
18/* The Boot TSS */
20
21/* CPU Features and Flags */
29
30/* Flush data */
32
33/* CPU Signatures */
34static const CHAR CmpIntelID[] = "GenuineIntel";
35static const CHAR CmpAmdID[] = "AuthenticAMD";
36static const CHAR CmpCentaurID[] = "CentaurHauls";
37
38typedef union _CPU_SIGNATURE
39{
40 struct
41 {
49 };
52
53/* FUNCTIONS *****************************************************************/
54
58{
59 PKPRCB Prcb = KeGetCurrentPrcb();
60 CPU_INFO CpuInfo;
61
62 /* Get the Vendor ID and null-terminate it */
63 KiCpuId(&CpuInfo, 0);
64
65 /* Copy it to the PRCB and null-terminate it */
66 *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
67 *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
68 *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
69 Prcb->VendorString[12] = 0;
70
71 /* Now check the CPU Type */
73 {
74 Prcb->CpuVendor = CPU_INTEL;
75 }
76 else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
77 {
78 Prcb->CpuVendor = CPU_AMD;
79 }
80 else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
81 {
82 DPRINT1("VIA CPUs not fully supported\n");
83 Prcb->CpuVendor = CPU_VIA;
84 }
85 else
86 {
87 /* Invalid CPU */
88 DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
89 Prcb->CpuVendor = CPU_UNKNOWN;
90 }
91
92 return Prcb->CpuVendor;
93}
94
95VOID
98{
99 CPU_INFO CpuInfo;
100 CPU_SIGNATURE CpuSignature;
101 BOOLEAN ExtendModel;
102 ULONG Stepping, Type, Vendor;
103
104 /* This initializes Prcb->CpuVendor */
105 Vendor = KiGetCpuVendor();
106
107 /* Do CPUID 1 now */
108 KiCpuId(&CpuInfo, 1);
109
110 /*
111 * Get the Stepping and Type. The stepping contains both the
112 * Model and the Step, while the Type contains the returned Family.
113 *
114 * For the stepping, we convert this: zzzzzzxy into this: x0y
115 */
116 CpuSignature.AsULONG = CpuInfo.Eax;
117 Stepping = CpuSignature.Model;
118 ExtendModel = (CpuSignature.Family == 15);
119#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
120 if (CpuSignature.Family == 6)
121 {
122 ExtendModel |= (Vendor == CPU_INTEL);
123#if (NTDDI_VERSION >= NTDDI_WIN8)
124 ExtendModel |= (Vendor == CPU_CENTAUR);
125#endif
126 }
127#endif
128 if (ExtendModel)
129 {
130 /* Add ExtendedModel to distinguish from non-extended values. */
131 Stepping |= (CpuSignature.ExtendedModel << 4);
132 }
133 Stepping = (Stepping << 8) | CpuSignature.Step;
134 Type = CpuSignature.Family;
135 if (CpuSignature.Family == 15)
136 {
137 /* Add ExtendedFamily to distinguish from non-extended values.
138 * It must not be larger than 0xF0 to avoid overflow. */
139 Type += min(CpuSignature.ExtendedFamily, 0xF0);
140 }
141
142 /* Save them in the PRCB */
143 KeGetCurrentPrcb()->CpuID = TRUE;
144 KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
145 KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
146}
147
148ULONG
149NTAPI
151{
152 PKPRCB Prcb = KeGetCurrentPrcb();
153 ULONG Vendor;
154 ULONG FeatureBits = KF_WORKING_PTE;
155 CPU_INFO CpuInfo;
156
157 /* Get the Vendor ID */
158 Vendor = Prcb->CpuVendor;
159
160 /* Make sure we got a valid vendor ID at least. */
161 if (!Vendor) return FeatureBits;
162
163 /* Get the CPUID Info. */
164 KiCpuId(&CpuInfo, 1);
165
166 /* Set the initial APIC ID */
167 Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
168
169 /* Convert all CPUID Feature bits into our format */
170 if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4;
171 if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
172 if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC;
173 if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B;
174 if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL;
175 if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR;
176 if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
177 if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV;
178 if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT;
179 if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS;
180 if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX;
181 if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR;
182 if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI;
183 if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64;
184
185 if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3;
186 //if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR;
187 //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP;
188 if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B;
189 //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41;
190 //if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT;
191 if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE;
192
193 /* Check if the CPU has hyper-threading */
194 if (CpuInfo.Edx & X86_FEATURE_HT)
195 {
196 /* Set the number of logical CPUs */
197 Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
199 {
200 /* We're on dual-core */
202 }
203 }
204 else
205 {
206 /* We only have a single CPU */
208 }
209
210 /* Check extended cpuid features */
211 KiCpuId(&CpuInfo, 0x80000000);
212 if ((CpuInfo.Eax & 0xffffff00) == 0x80000000)
213 {
214 /* Check if CPUID 0x80000001 is supported */
215 if (CpuInfo.Eax >= 0x80000001)
216 {
217 /* Check which extended features are available. */
218 KiCpuId(&CpuInfo, 0x80000001);
219
220 /* Check if NX-bit is supported */
221 if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT;
222
223 /* Now handle each features for each CPU Vendor */
224 switch (Vendor)
225 {
226 case CPU_AMD:
227 if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW;
228 break;
229 }
230 }
231 }
232
233 /* Return the Feature Bits */
234 return FeatureBits;
235}
236
237VOID
238NTAPI
240{
241 PKIPCR Pcr = (PKIPCR)KeGetPcr();
242 ULONG Vendor;
243 ULONG CacheRequests = 0, i;
244 ULONG CurrentRegister;
245 UCHAR RegisterByte;
246 BOOLEAN FirstPass = TRUE;
247 CPU_INFO CpuInfo;
248
249 /* Set default L2 size */
250 Pcr->SecondLevelCacheSize = 0;
251
252 /* Get the Vendor ID and make sure we support CPUID */
253 Vendor = KiGetCpuVendor();
254 if (!Vendor) return;
255
256 /* Check the Vendor ID */
257 switch (Vendor)
258 {
259 /* Handle Intel case */
260 case CPU_INTEL:
261
262 /*Check if we support CPUID 2 */
263 KiCpuId(&CpuInfo, 0);
264 if (CpuInfo.Eax >= 2)
265 {
266 /* We need to loop for the number of times CPUID will tell us to */
267 do
268 {
269 /* Do the CPUID call */
270 KiCpuId(&CpuInfo, 2);
271
272 /* Check if it was the first call */
273 if (FirstPass)
274 {
275 /*
276 * The number of times to loop is the first byte. Read
277 * it and then destroy it so we don't get confused.
278 */
279 CacheRequests = CpuInfo.Eax & 0xFF;
280 CpuInfo.Eax &= 0xFFFFFF00;
281
282 /* Don't go over this again */
283 FirstPass = FALSE;
284 }
285
286 /* Loop all 4 registers */
287 for (i = 0; i < 4; i++)
288 {
289 /* Get the current register */
290 CurrentRegister = CpuInfo.AsUINT32[i];
291
292 /*
293 * If the upper bit is set, then this register should
294 * be skipped.
295 */
296 if (CurrentRegister & 0x80000000) continue;
297
298 /* Keep looping for every byte inside this register */
299 while (CurrentRegister)
300 {
301 /* Read a byte, skip a byte. */
302 RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
303 CurrentRegister >>= 8;
304 if (!RegisterByte) continue;
305
306 /*
307 * Valid values are from 0x40 (0 bytes) to 0x49
308 * (32MB), or from 0x80 to 0x89 (same size but
309 * 8-way associative.
310 */
311 if (((RegisterByte > 0x40) &&
312 (RegisterByte <= 0x49)) ||
313 ((RegisterByte > 0x80) &&
314 (RegisterByte <= 0x89)))
315 {
316 /* Mask out only the first nibble */
317 RegisterByte &= 0x0F;
318
319 /* Set the L2 Cache Size */
320 Pcr->SecondLevelCacheSize = 0x10000 <<
321 RegisterByte;
322 }
323 }
324 }
325 } while (--CacheRequests);
326 }
327 break;
328
329 case CPU_AMD:
330
331 /* Check if we support CPUID 0x80000006 */
332 KiCpuId(&CpuInfo, 0x80000000);
333 if (CpuInfo.Eax >= 6)
334 {
335 /* Get 2nd level cache and tlb size */
336 KiCpuId(&CpuInfo, 0x80000006);
337
338 /* Set the L2 Cache Size */
339 Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
340 }
341 break;
342 }
343}
344
345VOID
346NTAPI
348{
349 /* Flush the TLB by resetting CR3 */
351}
352
353VOID
354NTAPI
356{
357 /* Restore the CR registers */
358 __writecr0(ProcessorState->SpecialRegisters.Cr0);
359// __writecr2(ProcessorState->SpecialRegisters.Cr2);
360 __writecr3(ProcessorState->SpecialRegisters.Cr3);
361 __writecr4(ProcessorState->SpecialRegisters.Cr4);
362 __writecr8(ProcessorState->SpecialRegisters.Cr8);
363
364 /* Restore the DR registers */
365 __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
366 __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
367 __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
368 __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
369 __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
370 __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
371
372 /* Restore GDT, IDT, LDT and TSS */
373 __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
374// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
375// __ltr(&ProcessorState->SpecialRegisters.Tr);
376 __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
377
378 _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
379// ProcessorState->SpecialRegisters.DebugControl
380// ProcessorState->SpecialRegisters.LastBranchToRip
381// ProcessorState->SpecialRegisters.LastBranchFromRip
382// ProcessorState->SpecialRegisters.LastExceptionToRip
383// ProcessorState->SpecialRegisters.LastExceptionFromRip
384
385 /* Restore MSRs */
392
393}
394
395VOID
396NTAPI
398{
399 /* Save the CR registers */
400 ProcessorState->SpecialRegisters.Cr0 = __readcr0();
401 ProcessorState->SpecialRegisters.Cr2 = __readcr2();
402 ProcessorState->SpecialRegisters.Cr3 = __readcr3();
403 ProcessorState->SpecialRegisters.Cr4 = __readcr4();
404 ProcessorState->SpecialRegisters.Cr8 = __readcr8();
405
406 /* Save the DR registers */
407 ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
408 ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
409 ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
410 ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
411 ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
412 ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
413
414 /* Save GDT, IDT, LDT and TSS */
415 __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
416 __sldt(&ProcessorState->SpecialRegisters.Ldtr);
417 __str(&ProcessorState->SpecialRegisters.Tr);
418 __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
419
420 ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
421// ProcessorState->SpecialRegisters.DebugControl =
422// ProcessorState->SpecialRegisters.LastBranchToRip =
423// ProcessorState->SpecialRegisters.LastBranchFromRip =
424// ProcessorState->SpecialRegisters.LastExceptionToRip =
425// ProcessorState->SpecialRegisters.LastExceptionFromRip =
426
427 /* Save MSRs */
428 ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
429 ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
430 ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
431 ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
432 ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
433 ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
434}
435
436VOID
437NTAPI
439 IN BOOLEAN AllProcessors)
440{
442
443 // FIXME: halfplemented
444 /* Raise the IRQL for the TB Flush */
446
447 /* Flush the TB for the Current CPU, and update the flush stamp */
449
450 /* Update the flush stamp and return to original IRQL */
453
454}
455
457NTAPI
459{
460 PAGED_CODE();
461
462 /* Simply return the number of active processors */
463 return KeActiveProcessors;
464}
465
467NTAPI
469{
470 UNREFERENCED_PARAMETER(FloatingState);
471 return STATUS_SUCCESS;
472}
473
475NTAPI
477{
478 UNREFERENCED_PARAMETER(FloatingState);
479 return STATUS_SUCCESS;
480}
481
483NTAPI
485{
486 /* Invalidate all caches */
487 __wbinvd();
488 return TRUE;
489}
490
491/*
492 * @implemented
493 */
494ULONG
495NTAPI
497{
498 /* Return the global variable */
499 return KeLargestCacheLine;
500}
501
502/*
503 * @implemented
504 */
505VOID
508{
509 /* Capture the context */
510 RtlCaptureContext(&State->ContextFrame);
511
512 /* Capture the control state */
514}
515
516/*
517 * @implemented
518 */
519VOID
520NTAPI
522{
523 /* Save the coherency globally */
524 KiDmaIoCoherency = Coherency;
525}
#define PAGED_CODE()
unsigned char BOOLEAN
Type
Definition: Type.h:7
int strcmp(const char *String1, const char *String2)
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#define __cdecl
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@ Invalid
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LONG NTSTATUS
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#define DPRINT1
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#define TRUE
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#define FALSE
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ULONG_PTR KAFFINITY
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UCHAR KIRQL
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#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
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#define InterlockedExchangeAdd
Definition: interlocked.h:181
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759
__INTRIN_INLINE unsigned long __readcr3(void)
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__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2018
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
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__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1825
__INTRIN_INLINE unsigned long __readcr0(void)
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__INTRIN_INLINE void __writecr3(unsigned int Data)
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__INTRIN_INLINE unsigned long __readcr2(void)
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__INTRIN_INLINE void __writecr0(unsigned int Data)
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__INTRIN_INLINE void __sidt(void *Destination)
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__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1799
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
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if(dx< 0)
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#define min(a, b)
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FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1080
struct _KIPCR * PKIPCR
@ CPU_VIA
Definition: ketypes.h:46
@ CPU_INTEL
Definition: ketypes.h:45
@ CPU_UNKNOWN
Definition: ketypes.h:43
@ CPU_AMD
Definition: ketypes.h:44
@ CPU_CENTAUR
Definition: ketypes.h:47
#define KF_WORKING_PTE
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#define KF_MTRR
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#define KF_XSTATE
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#define KF_DTS
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#define KF_RDTSC
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#define KF_FAST_SYSCALL
Definition: ketypes.h:155
#define KF_3DNOW
Definition: ketypes.h:157
#define KF_NX_BIT
Definition: ketypes.h:165
#define KF_FXSR
Definition: ketypes.h:154
#define KF_V86_VIS
Definition: ketypes.h:143
#define KF_LARGE_PAGE
Definition: ketypes.h:148
#define KF_XMMI
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#define KF_MMX
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#define KF_SSE3
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#define KF_PAT
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#define KF_GLOBAL_PAGE
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NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)
#define UNREFERENCED_PARAMETER(P)
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#define X86_MSR_CSTAR
Definition: ke.h:75
#define X86_FEATURE_TSC
Definition: ke.h:34
#define X86_FEATURE_HT
Definition: ke.h:47
#define X86_FEATURE_SSE2
Definition: ke.h:46
#define X86_FEATURE_SSE
Definition: ke.h:45
#define X86_FEATURE_PGE
Definition: ke.h:39
#define X86_FEATURE_XSAVE
Definition: ke.h:60
#define X86_FEATURE_DS
Definition: ke.h:42
#define X86_FEATURE_VME
Definition: ke.h:31
#define X86_FEATURE_MMX
Definition: ke.h:43
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Definition: ke.h:70
#define X86_FEATURE_PSE
Definition: ke.h:33
#define X86_MSR_LSTAR
Definition: ke.h:74
#define X86_FEATURE_SSE3
Definition: ke.h:50
#define X86_FEATURE_PAT
Definition: ke.h:41
#define X86_FEATURE_MTTR
Definition: ke.h:38
#define X86_FEATURE_CMOV
Definition: ke.h:40
#define X86_FEATURE_CX8
Definition: ke.h:36
#define X86_FEATURE_SYSCALL
Definition: ke.h:37
#define X86_MSR_SFMASK
Definition: ke.h:76
#define X86_FEATURE_NX
Definition: ke.h:63
#define X86_FEATURE_FXSR
Definition: ke.h:44
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:71
#define X86_MSR_STAR
Definition: ke.h:73
#define X86_FEATURE_CX16
Definition: ke.h:55
KAFFINITY KeActiveProcessors
Definition: krnlinit.c:23
ULONG NTAPI KeGetRecommendedSharedDataAlignment(VOID)
Definition: cpu.c:496
VOID NTAPI KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:355
ULONG KeI386NpxPresent
Definition: cpu.c:25
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:347
VOID NTAPI KiSetProcessorType(VOID)
Definition: cpu.c:97
ULONG KeI386MachineType
Definition: cpu.c:24
VOID NTAPI KeFlushEntireTb(IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
Definition: cpu.c:438
ULONG KeLargestCacheLine
Definition: cpu.c:26
VOID __cdecl KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
Definition: cpu.c:507
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:28
BOOLEAN NTAPI KeInvalidateAllCaches(VOID)
Definition: cpu.c:484
NTSTATUS NTAPI KxRestoreFloatingPointState(IN PKFLOATING_SAVE FloatingState)
Definition: cpu.c:476
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:57
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:31
VOID NTAPI KeSetDmaIoCoherency(IN ULONG Coherency)
Definition: cpu.c:521
KTSS64 KiBootTss
Definition: cpu.c:19
ULONG KeI386CpuType
Definition: cpu.c:22
NTSTATUS NTAPI KxSaveFloatingPointState(OUT PKFLOATING_SAVE FloatingState)
Definition: cpu.c:468
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:397
static const CHAR CmpIntelID[]
Definition: cpu.c:34
static const CHAR CmpAmdID[]
Definition: cpu.c:35
ULONG NTAPI KiGetFeatureBits(VOID)
Definition: cpu.c:150
static const CHAR CmpCentaurID[]
Definition: cpu.c:36
ULONG KiDmaIoCoherency
Definition: cpu.c:27
VOID NTAPI KiGetCacheInformation(VOID)
Definition: cpu.c:239
union _CPU_SIGNATURE CPU_SIGNATURE
KAFFINITY NTAPI KeQueryActiveProcessors(VOID)
Definition: cpu.c:458
ULONG KeI386CpuStep
Definition: cpu.c:23
long LONG
Definition: pedump.c:60
unsigned short USHORT
Definition: pedump.c:61
#define KeGetPcr()
Definition: ke.h:26
#define STATUS_SUCCESS
Definition: shellext.h:65
USHORT Limit
Definition: ketypes.h:396
ULONG SecondLevelCacheSize
Definition: ketypes.h:886
UCHAR VendorString[13]
Definition: ketypes.h:802
UCHAR CpuVendor
Definition: ketypes.h:605
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:706
ULONG InitialApicId
Definition: ketypes.h:622
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:535
ULONG64 KernelDr0
Definition: ketypes.h:505
ULONG64 KernelDr7
Definition: ketypes.h:510
ULONG64 MsrLStar
Definition: ketypes.h:525
KDESCRIPTOR Gdtr
Definition: ketypes.h:511
ULONG64 KernelDr2
Definition: ketypes.h:507
ULONG64 MsrGsBase
Definition: ketypes.h:522
KDESCRIPTOR Idtr
Definition: ketypes.h:512
ULONG64 KernelDr1
Definition: ketypes.h:506
ULONG64 MsrCStar
Definition: ketypes.h:526
ULONG64 MsrSyscallMask
Definition: ketypes.h:527
ULONG64 MsrGsSwap
Definition: ketypes.h:523
ULONG64 KernelDr3
Definition: ketypes.h:508
ULONG64 KernelDr6
Definition: ketypes.h:509
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
ULONG Ebx
Definition: ketypes.h:302
ULONG Eax
Definition: ketypes.h:301
UINT32 AsUINT32[4]
Definition: ketypes.h:298
ULONG Ecx
Definition: ketypes.h:303
ULONG Edx
Definition: ketypes.h:304
ULONG Unused
Definition: cpu.c:45
ULONG ExtendedFamily
Definition: cpu.c:47
ULONG Model
Definition: cpu.c:43
ULONG Unused2
Definition: cpu.c:48
ULONG Family
Definition: cpu.c:44
ULONG AsULONG
Definition: cpu.c:50
ULONG Step
Definition: cpu.c:42
ULONG ExtendedModel
Definition: cpu.c:46
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:792
unsigned char UCHAR
Definition: xmlstorage.h:181
char CHAR
Definition: xmlstorage.h:175
void _mm_setcsr(unsigned int a)
Definition: xmmintrin.h:542
unsigned int _mm_getcsr(void)
Definition: xmmintrin.h:535