ReactOS 0.4.15-dev-7906-g1b85a5f
cpu.c
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1/*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/amd64/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
7 * Timo Kreuzer (timo.kreuzer@reactos.org)
8 */
9
10/* INCLUDES *****************************************************************/
11
12#include <ntoskrnl.h>
13#include <x86x64/Cpuid.h>
14#include <x86x64/Msr.h>
15#define NDEBUG
16#include <debug.h>
17
18/* GLOBALS *******************************************************************/
19
20/* The Boot TSS */
22
23/* CPU Features and Flags */
31
32/* Flush data */
34
35/* CPU Signatures */
36static const CHAR CmpIntelID[] = "GenuineIntel";
37static const CHAR CmpAmdID[] = "AuthenticAMD";
38static const CHAR CmpCentaurID[] = "CentaurHauls";
39
40typedef union _CPU_SIGNATURE
41{
42 struct
43 {
51 };
54
55/* FUNCTIONS *****************************************************************/
56
60{
61 PKPRCB Prcb = KeGetCurrentPrcb();
62 CPU_INFO CpuInfo;
63
64 /* Get the Vendor ID and null-terminate it */
65 KiCpuId(&CpuInfo, 0);
66
67 /* Copy it to the PRCB and null-terminate it */
68 *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
69 *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
70 *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
71 Prcb->VendorString[12] = 0;
72
73 /* Now check the CPU Type */
75 {
76 Prcb->CpuVendor = CPU_INTEL;
77 }
78 else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
79 {
80 Prcb->CpuVendor = CPU_AMD;
81 }
82 else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
83 {
84 DPRINT1("VIA CPUs not fully supported\n");
85 Prcb->CpuVendor = CPU_VIA;
86 }
87 else
88 {
89 /* Invalid CPU */
90 DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
91 Prcb->CpuVendor = CPU_UNKNOWN;
92 }
93
94 return Prcb->CpuVendor;
95}
96
97VOID
100{
101 CPU_INFO CpuInfo;
102 CPU_SIGNATURE CpuSignature;
103 BOOLEAN ExtendModel;
104 ULONG Stepping, Type, Vendor;
105
106 /* This initializes Prcb->CpuVendor */
107 Vendor = KiGetCpuVendor();
108
109 /* Do CPUID 1 now */
110 KiCpuId(&CpuInfo, 1);
111
112 /*
113 * Get the Stepping and Type. The stepping contains both the
114 * Model and the Step, while the Type contains the returned Family.
115 *
116 * For the stepping, we convert this: zzzzzzxy into this: x0y
117 */
118 CpuSignature.AsULONG = CpuInfo.Eax;
119 Stepping = CpuSignature.Model;
120 ExtendModel = (CpuSignature.Family == 15);
121#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
122 if (CpuSignature.Family == 6)
123 {
124 ExtendModel |= (Vendor == CPU_INTEL);
125#if (NTDDI_VERSION >= NTDDI_WIN8)
126 ExtendModel |= (Vendor == CPU_CENTAUR);
127#endif
128 }
129#endif
130 if (ExtendModel)
131 {
132 /* Add ExtendedModel to distinguish from non-extended values. */
133 Stepping |= (CpuSignature.ExtendedModel << 4);
134 }
135 Stepping = (Stepping << 8) | CpuSignature.Step;
136 Type = CpuSignature.Family;
137 if (CpuSignature.Family == 15)
138 {
139 /* Add ExtendedFamily to distinguish from non-extended values.
140 * It must not be larger than 0xF0 to avoid overflow. */
141 Type += min(CpuSignature.ExtendedFamily, 0xF0);
142 }
143
144 /* Save them in the PRCB */
145 KeGetCurrentPrcb()->CpuID = TRUE;
146 KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
147 KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
148}
149
164NTAPI
166{
167 PKPRCB Prcb = KeGetCurrentPrcb();
168 ULONG Vendor;
169 ULONG64 FeatureBits = 0;
170 CPUID_SIGNATURE_REGS signature;
172 CPUID_EXTENDED_FUNCTION_REGS extendedFunction;
173
174 /* Get the Vendor ID */
175 Vendor = Prcb->CpuVendor;
176
177 /* Make sure we got a valid vendor ID at least. */
178 if (Vendor == CPU_UNKNOWN) return FeatureBits;
179
180 /* Get signature CPUID for the maximum function */
181 __cpuid(signature.AsInt32, CPUID_SIGNATURE);
182
183 /* Get the CPUID Info. */
185
186 /* Set the initial APIC ID */
187 Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId;
188
189 /* Convert all CPUID Feature bits into our format */
190 if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4;
191 if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
192 if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC;
193 if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B;
194 if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL;
195 if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR;
196 if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
197 if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV;
198 if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT;
199 if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS;
200 if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX;
201 if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR;
202 if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI;
203 if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64;
204
205 if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3;
206 if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3;
207 if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B;
208 if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1;
209 if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE;
210 if (VersionInfo.Ecx.Bits.RDRAND) FeatureBits |= KF_RDRAND;
211
212 /* Check if the CPU has hyper-threading */
213 if (VersionInfo.Edx.Bits.HTT)
214 {
215 /* Set the number of logical CPUs */
217 VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors;
219 {
220 /* We're on dual-core */
222 }
223 }
224 else
225 {
226 /* We only have a single CPU */
228 }
229
230 /* Check if CPUID_THERMAL_POWER_MANAGEMENT (0x06) is supported */
232 {
233 /* Read CPUID_THERMAL_POWER_MANAGEMENT */
236
237 if (PowerInfo.Undoc.Ecx.ACNT2) FeatureBits |= KF_ACNT2;
238 }
239
240 /* Check if CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) is supported */
242 {
243 /* Read CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS */
245 __cpuidex(ExtFlags.AsInt32,
248
249 if (ExtFlags.Ebx.Bits.SMEP) FeatureBits |= KF_SMEP;
250 if (ExtFlags.Ebx.Bits.FSGSBASE) FeatureBits |= KF_RDWRFSGSBASE;
251 if (ExtFlags.Ebx.Bits.SMAP) FeatureBits |= KF_SMAP;
252 }
253
254 /* Check if CPUID_EXTENDED_STATE (0x0D) is supported */
255 if (signature.MaxLeaf >= CPUID_EXTENDED_STATE)
256 {
257 /* Read CPUID_EXTENDED_STATE */
259 __cpuidex(ExtStateSub.AsInt32,
262
263 if (ExtStateSub.Eax.Bits.XSAVEOPT) FeatureBits |= KF_XSAVEOPT;
264 if (ExtStateSub.Eax.Bits.XSAVES) FeatureBits |= KF_XSAVES;
265 }
266
267 /* Check extended cpuid features */
268 __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION);
269 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
270 {
271 /* Check if CPUID_EXTENDED_CPU_SIG (0x80000001) is supported */
272 if (extendedFunction.MaxLeaf >= CPUID_EXTENDED_CPU_SIG)
273 {
274 /* Read CPUID_EXTENDED_CPU_SIG */
277
278 /* Check if NX-bit is supported */
279 if (ExtSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT;
280 if (ExtSig.Intel.Edx.Bits.Page1GB) FeatureBits |= KF_HUGEPAGE;
281 if (ExtSig.Intel.Edx.Bits.RDTSCP) FeatureBits |= KF_RDTSCP;
282
283 /* AMD specific */
284 if (Vendor == CPU_AMD)
285 {
286 if (ExtSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW;
287 }
288 }
289 }
290
291 /* Vendor specific */
292 if (Vendor == CPU_INTEL)
293 {
294 FeatureBits |= KF_GENUINE_INTEL;
295
296 /* Check for models that support LBR */
297 if (VersionInfo.Eax.Bits.FamilyId == 6)
298 {
299 if ((VersionInfo.Eax.Bits.Model == 15) ||
300 (VersionInfo.Eax.Bits.Model == 22) ||
301 (VersionInfo.Eax.Bits.Model == 23) ||
302 (VersionInfo.Eax.Bits.Model == 26))
303 {
304 FeatureBits |= KF_BRANCH;
305 }
306 }
307
308 /* Check if VMX is available */
309 if (VersionInfo.Ecx.Bits.VMX)
310 {
311 /* Read PROCBASED ctls and check if secondary are allowed */
314 if (ProcBasedCtls.Bits.Allowed1.ActivateSecondaryControls)
315 {
316 /* Read secondary controls and check if EPT is allowed */
319 if (ProcBasedCtls2.Bits.Allowed1.EPT)
320 FeatureBits |= KF_SLAT;
321 }
322 }
323 }
324 else if (Vendor == CPU_AMD)
325 {
326 FeatureBits |= KF_AUTHENTICAMD;
327 FeatureBits |= KF_BRANCH;
328
329 /* Check extended cpuid features */
330 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
331 {
332 /* Check if CPUID_AMD_SVM_FEATURES (0x8000000A) is supported */
333 if (extendedFunction.MaxLeaf >= CPUID_AMD_SVM_FEATURES)
334 {
335 /* Read CPUID_AMD_SVM_FEATURES and check if Nested Paging is available */
336 CPUID_AMD_SVM_FEATURES_REGS SvmFeatures;
338 if (SvmFeatures.Edx.Bits.NP) FeatureBits |= KF_SLAT;
339 }
340 }
341 }
342
343 /* Return the Feature Bits */
344 return FeatureBits;
345}
346
347#if DBG
348VOID
349KiReportCpuFeatures(IN PKPRCB Prcb)
350{
351 ULONG CpuFeatures = 0;
352 CPU_INFO CpuInfo;
353
354 if (Prcb->CpuVendor)
355 {
356 KiCpuId(&CpuInfo, 1);
357 CpuFeatures = CpuInfo.Edx;
358 }
359
360 DPRINT1("Supported CPU features: ");
361
362#define print_kf_bit(kf_value) if (Prcb->FeatureBits & kf_value) DbgPrint(#kf_value " ")
363 print_kf_bit(KF_SMEP);
364 print_kf_bit(KF_RDTSC);
365 print_kf_bit(KF_CR4);
366 print_kf_bit(KF_CMOV);
367 print_kf_bit(KF_GLOBAL_PAGE);
368 print_kf_bit(KF_LARGE_PAGE);
369 print_kf_bit(KF_MTRR);
370 print_kf_bit(KF_CMPXCHG8B);
371 print_kf_bit(KF_MMX);
372 print_kf_bit(KF_DTS);
373 print_kf_bit(KF_PAT);
374 print_kf_bit(KF_FXSR);
375 print_kf_bit(KF_FAST_SYSCALL);
376 print_kf_bit(KF_XMMI);
377 print_kf_bit(KF_3DNOW);
378 print_kf_bit(KF_XSAVEOPT);
379 print_kf_bit(KF_XMMI64);
380 print_kf_bit(KF_BRANCH);
381 print_kf_bit(KF_00040000);
382 print_kf_bit(KF_SSE3);
383 print_kf_bit(KF_CMPXCHG16B);
384 print_kf_bit(KF_AUTHENTICAMD);
385 print_kf_bit(KF_ACNT2);
386 print_kf_bit(KF_XSTATE);
387 print_kf_bit(KF_GENUINE_INTEL);
388 print_kf_bit(KF_SLAT);
389 print_kf_bit(KF_VIRT_FIRMWARE_ENABLED);
390 print_kf_bit(KF_RDWRFSGSBASE);
391 print_kf_bit(KF_NX_BIT);
392 print_kf_bit(KF_NX_DISABLED);
393 print_kf_bit(KF_NX_ENABLED);
394 print_kf_bit(KF_RDRAND);
395 print_kf_bit(KF_SMAP);
396 print_kf_bit(KF_RDTSCP);
397 print_kf_bit(KF_HUGEPAGE);
398 print_kf_bit(KF_XSAVES);
399 print_kf_bit(KF_FPU_LEAKAGE);
400 print_kf_bit(KF_CAT);
401 print_kf_bit(KF_CET_SS);
402 print_kf_bit(KF_SSSE3);
403 print_kf_bit(KF_SSE4_1);
404 print_kf_bit(KF_SSE4_2);
405#undef print_kf_bit
406
407#define print_cf(cpu_flag) if (CpuFeatures & cpu_flag) DbgPrint(#cpu_flag " ")
408 print_cf(X86_FEATURE_PAE);
409 print_cf(X86_FEATURE_HT);
410#undef print_cf
411
412 DbgPrint("\n");
413}
414#endif // DBG
415
416VOID
417NTAPI
419{
420 PKIPCR Pcr = (PKIPCR)KeGetPcr();
421 ULONG Vendor;
422 ULONG CacheRequests = 0, i;
423 ULONG CurrentRegister;
424 UCHAR RegisterByte;
425 BOOLEAN FirstPass = TRUE;
426 CPU_INFO CpuInfo;
427
428 /* Set default L2 size */
429 Pcr->SecondLevelCacheSize = 0;
430
431 /* Get the Vendor ID and make sure we support CPUID */
432 Vendor = KiGetCpuVendor();
433 if (!Vendor) return;
434
435 /* Check the Vendor ID */
436 switch (Vendor)
437 {
438 /* Handle Intel case */
439 case CPU_INTEL:
440
441 /*Check if we support CPUID 2 */
442 KiCpuId(&CpuInfo, 0);
443 if (CpuInfo.Eax >= 2)
444 {
445 /* We need to loop for the number of times CPUID will tell us to */
446 do
447 {
448 /* Do the CPUID call */
449 KiCpuId(&CpuInfo, 2);
450
451 /* Check if it was the first call */
452 if (FirstPass)
453 {
454 /*
455 * The number of times to loop is the first byte. Read
456 * it and then destroy it so we don't get confused.
457 */
458 CacheRequests = CpuInfo.Eax & 0xFF;
459 CpuInfo.Eax &= 0xFFFFFF00;
460
461 /* Don't go over this again */
462 FirstPass = FALSE;
463 }
464
465 /* Loop all 4 registers */
466 for (i = 0; i < 4; i++)
467 {
468 /* Get the current register */
469 CurrentRegister = CpuInfo.AsUINT32[i];
470
471 /*
472 * If the upper bit is set, then this register should
473 * be skipped.
474 */
475 if (CurrentRegister & 0x80000000) continue;
476
477 /* Keep looping for every byte inside this register */
478 while (CurrentRegister)
479 {
480 /* Read a byte, skip a byte. */
481 RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
482 CurrentRegister >>= 8;
483 if (!RegisterByte) continue;
484
485 /*
486 * Valid values are from 0x40 (0 bytes) to 0x49
487 * (32MB), or from 0x80 to 0x89 (same size but
488 * 8-way associative.
489 */
490 if (((RegisterByte > 0x40) &&
491 (RegisterByte <= 0x49)) ||
492 ((RegisterByte > 0x80) &&
493 (RegisterByte <= 0x89)))
494 {
495 /* Mask out only the first nibble */
496 RegisterByte &= 0x0F;
497
498 /* Set the L2 Cache Size */
499 Pcr->SecondLevelCacheSize = 0x10000 <<
500 RegisterByte;
501 }
502 }
503 }
504 } while (--CacheRequests);
505 }
506 break;
507
508 case CPU_AMD:
509
510 /* Check if we support CPUID 0x80000006 */
511 KiCpuId(&CpuInfo, 0x80000000);
512 if (CpuInfo.Eax >= 6)
513 {
514 /* Get 2nd level cache and tlb size */
515 KiCpuId(&CpuInfo, 0x80000006);
516
517 /* Set the L2 Cache Size */
518 Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
519 }
520 break;
521 }
522}
523
524VOID
525NTAPI
527{
528 /* Flush the TLB by resetting CR3 */
530}
531
532VOID
533NTAPI
535{
536 /* Restore the CR registers */
537 __writecr0(ProcessorState->SpecialRegisters.Cr0);
538// __writecr2(ProcessorState->SpecialRegisters.Cr2);
539 __writecr3(ProcessorState->SpecialRegisters.Cr3);
540 __writecr4(ProcessorState->SpecialRegisters.Cr4);
541 __writecr8(ProcessorState->SpecialRegisters.Cr8);
542
543 /* Restore the DR registers */
544 __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
545 __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
546 __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
547 __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
548 __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
549 __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
550
551 /* Restore GDT, IDT, LDT and TSS */
552 __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
553// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
554// __ltr(&ProcessorState->SpecialRegisters.Tr);
555 __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
556
557 _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
558// ProcessorState->SpecialRegisters.DebugControl
559// ProcessorState->SpecialRegisters.LastBranchToRip
560// ProcessorState->SpecialRegisters.LastBranchFromRip
561// ProcessorState->SpecialRegisters.LastExceptionToRip
562// ProcessorState->SpecialRegisters.LastExceptionFromRip
563
564 /* Restore MSRs */
571
572}
573
574VOID
575NTAPI
577{
578 /* Save the CR registers */
579 ProcessorState->SpecialRegisters.Cr0 = __readcr0();
580 ProcessorState->SpecialRegisters.Cr2 = __readcr2();
581 ProcessorState->SpecialRegisters.Cr3 = __readcr3();
582 ProcessorState->SpecialRegisters.Cr4 = __readcr4();
583 ProcessorState->SpecialRegisters.Cr8 = __readcr8();
584
585 /* Save the DR registers */
586 ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
587 ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
588 ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
589 ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
590 ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
591 ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
592
593 /* Save GDT, IDT, LDT and TSS */
594 __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
595 __sldt(&ProcessorState->SpecialRegisters.Ldtr);
596 __str(&ProcessorState->SpecialRegisters.Tr);
597 __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
598
599 ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
600// ProcessorState->SpecialRegisters.DebugControl =
601// ProcessorState->SpecialRegisters.LastBranchToRip =
602// ProcessorState->SpecialRegisters.LastBranchFromRip =
603// ProcessorState->SpecialRegisters.LastExceptionToRip =
604// ProcessorState->SpecialRegisters.LastExceptionFromRip =
605
606 /* Save MSRs */
607 ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
608 ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
609 ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
610 ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
611 ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
612 ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
613}
614
615VOID
616NTAPI
618 IN BOOLEAN AllProcessors)
619{
621
622 // FIXME: halfplemented
623 /* Raise the IRQL for the TB Flush */
625
626 /* Flush the TB for the Current CPU, and update the flush stamp */
628
629 /* Update the flush stamp and return to original IRQL */
632
633}
634
636NTAPI
638{
639 PAGED_CODE();
640
641 /* Simply return the number of active processors */
642 return KeActiveProcessors;
643}
644
646NTAPI
648{
649 UNREFERENCED_PARAMETER(FloatingState);
650 return STATUS_SUCCESS;
651}
652
654NTAPI
656{
657 UNREFERENCED_PARAMETER(FloatingState);
658 return STATUS_SUCCESS;
659}
660
662NTAPI
664{
665 /* Invalidate all caches */
666 __wbinvd();
667 return TRUE;
668}
669
670/*
671 * @implemented
672 */
673ULONG
674NTAPI
676{
677 /* Return the global variable */
678 return KeLargestCacheLine;
679}
680
681/*
682 * @implemented
683 */
684VOID
687{
688 /* Capture the context */
689 RtlCaptureContext(&State->ContextFrame);
690
691 /* Capture the control state */
693}
694
695/*
696 * @implemented
697 */
698VOID
699NTAPI
701{
702 /* Save the coherency globally */
703 KiDmaIoCoherency = Coherency;
704}
#define MSR_IA32_VMX_PROCBASED_CTLS
#define MSR_IA32_VMX_PROCBASED_CTLS2
#define PAGED_CODE()
#define CPUID_AMD_SVM_FEATURES
Definition: Cpuid.h:146
#define CPUID_EXTENDED_FUNCTION
Definition: Cpuid.h:3745
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
Definition: Cpuid.h:1301
#define CPUID_SIGNATURE
Definition: Cpuid.h:45
#define CPUID_VERSION_INFO
Definition: Cpuid.h:81
#define CPUID_EXTENDED_STATE
Definition: Cpuid.h:1918
#define CPUID_THERMAL_POWER_MANAGEMENT
Definition: Cpuid.h:1114
#define CPUID_EXTENDED_STATE_SUB_LEAF
Definition: Cpuid.h:2033
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
Definition: Cpuid.h:1306
#define CPUID_EXTENDED_CPU_SIG
Definition: Cpuid.h:3768
unsigned char BOOLEAN
Type
Definition: Type.h:7
int strcmp(const char *String1, const char *String2)
Definition: utclib.c:469
#define __cdecl
Definition: accygwin.h:79
@ Invalid
Definition: asmpp.cpp:30
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
OSVERSIONINFOW VersionInfo
Definition: wkssvc.c:40
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
ULONG_PTR KAFFINITY
Definition: compat.h:85
UCHAR KIRQL
Definition: env_spec_w32.h:591
#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
Definition: pic.c:156
#define DbgPrint
Definition: hal.h:12
#define InterlockedExchangeAdd
Definition: interlocked.h:181
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
PPC_QUAL void __cpuid(int CPUInfo[], const int InfoType)
Definition: intrin_ppc.h:682
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1818
__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2018
__INTRIN_INLINE void __cpuidex(int CPUInfo[4], int InfoType, int ECXValue)
Definition: intrin_x86.h:1649
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
Definition: intrin_x86.h:1902
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1825
__INTRIN_INLINE unsigned long __readcr0(void)
Definition: intrin_x86.h:1804
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1794
__INTRIN_INLINE unsigned long __readcr2(void)
Definition: intrin_x86.h:1811
__INTRIN_INLINE void __writecr0(unsigned int Data)
Definition: intrin_x86.h:1789
__INTRIN_INLINE void __sidt(void *Destination)
Definition: intrin_x86.h:2023
__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1799
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
Definition: intrin_x86.h:1935
if(dx< 0)
Definition: linetemp.h:194
unsigned __int64 ULONG64
Definition: imports.h:198
#define min(a, b)
Definition: monoChain.cc:55
#define KF_SSE4_2
Definition: ketypes.h:74
#define KF_SMEP
Definition: ketypes.h:31
#define KF_FPU_LEAKAGE
Definition: ketypes.h:69
#define KF_SSSE3
Definition: ketypes.h:72
#define KF_MTRR
Definition: ketypes.h:37
#define KF_HUGEPAGE
Definition: ketypes.h:67
#define KF_XSTATE
Definition: ketypes.h:55
#define KF_DTS
Definition: ketypes.h:40
#define KF_VIRT_FIRMWARE_ENABLED
Definition: ketypes.h:59
#define KF_CMPXCHG16B
Definition: ketypes.h:52
#define KF_CET_SS
Definition: ketypes.h:71
#define KF_NX_DISABLED
Definition: ketypes.h:62
#define KF_CR4
Definition: ketypes.h:33
#define KF_AUTHENTICAMD
Definition: ketypes.h:53
#define KF_XMMI64
Definition: ketypes.h:48
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1146
#define KF_CMOV
Definition: ketypes.h:34
#define KF_ACNT2
Definition: ketypes.h:54
#define KF_SSE4_1
Definition: ketypes.h:73
#define KF_RDWRFSGSBASE
Definition: ketypes.h:60
#define KF_00040000
Definition: ketypes.h:50
#define KF_CMPXCHG8B
Definition: ketypes.h:38
#define KF_NX_ENABLED
Definition: ketypes.h:63
#define KF_RDTSC
Definition: ketypes.h:32
#define KF_FAST_SYSCALL
Definition: ketypes.h:43
#define KF_3DNOW
Definition: ketypes.h:45
struct _KIPCR * PKIPCR
#define KF_NX_BIT
Definition: ketypes.h:61
#define KF_FXSR
Definition: ketypes.h:42
#define KF_RDRAND
Definition: ketypes.h:64
#define KF_CAT
Definition: ketypes.h:70
@ CPU_VIA
Definition: ketypes.h:107
@ CPU_INTEL
Definition: ketypes.h:106
@ CPU_UNKNOWN
Definition: ketypes.h:104
@ CPU_AMD
Definition: ketypes.h:105
#define KF_XSAVES
Definition: ketypes.h:68
#define KF_LARGE_PAGE
Definition: ketypes.h:36
#define KF_BRANCH
Definition: ketypes.h:49
#define KF_GENUINE_INTEL
Definition: ketypes.h:56
#define KF_XMMI
Definition: ketypes.h:44
#define KF_MMX
Definition: ketypes.h:39
#define KF_XSAVEOPT
Definition: ketypes.h:47
#define KF_SSE3
Definition: ketypes.h:51
#define KF_SLAT
Definition: ketypes.h:58
#define KF_PAT
Definition: ketypes.h:41
#define KF_RDTSCP
Definition: ketypes.h:66
#define KF_GLOBAL_PAGE
Definition: ketypes.h:35
#define KF_SMAP
Definition: ketypes.h:65
#define KeGetPcr()
Definition: ketypes.h:81
@ CPU_CENTAUR
Definition: ketypes.h:95
NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317
#define X86_MSR_CSTAR
Definition: ke.h:75
#define X86_FEATURE_HT
Definition: ke.h:47
#define X86_MSR_GSBASE
Definition: ke.h:70
#define X86_MSR_LSTAR
Definition: ke.h:74
#define X86_FEATURE_PAE
Definition: ke.h:35
#define X86_MSR_SFMASK
Definition: ke.h:76
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:71
#define X86_MSR_STAR
Definition: ke.h:73
KAFFINITY KeActiveProcessors
Definition: krnlinit.c:23
ULONG NTAPI KeGetRecommendedSharedDataAlignment(VOID)
Definition: cpu.c:675
VOID NTAPI KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:534
ULONG KeI386NpxPresent
Definition: cpu.c:27
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:526
VOID NTAPI KiSetProcessorType(VOID)
Definition: cpu.c:99
ULONG KeI386MachineType
Definition: cpu.c:26
VOID NTAPI KeFlushEntireTb(IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
Definition: cpu.c:617
ULONG KeLargestCacheLine
Definition: cpu.c:28
VOID __cdecl KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
Definition: cpu.c:686
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:30
ULONG64 NTAPI KiGetFeatureBits(VOID)
Evaluates the KeFeatureFlag bits for the current CPU.
Definition: cpu.c:165
BOOLEAN NTAPI KeInvalidateAllCaches(VOID)
Definition: cpu.c:663
NTSTATUS NTAPI KxRestoreFloatingPointState(IN PKFLOATING_SAVE FloatingState)
Definition: cpu.c:655
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:59
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:33
VOID NTAPI KeSetDmaIoCoherency(IN ULONG Coherency)
Definition: cpu.c:700
KTSS64 KiBootTss
Definition: cpu.c:21
ULONG KeI386CpuType
Definition: cpu.c:24
NTSTATUS NTAPI KxSaveFloatingPointState(OUT PKFLOATING_SAVE FloatingState)
Definition: cpu.c:647
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:576
static const CHAR CmpIntelID[]
Definition: cpu.c:36
static const CHAR CmpAmdID[]
Definition: cpu.c:37
static const CHAR CmpCentaurID[]
Definition: cpu.c:38
ULONG KiDmaIoCoherency
Definition: cpu.c:29
VOID NTAPI KiGetCacheInformation(VOID)
Definition: cpu.c:418
union _CPU_SIGNATURE CPU_SIGNATURE
KAFFINITY NTAPI KeQueryActiveProcessors(VOID)
Definition: cpu.c:637
ULONG KeI386CpuStep
Definition: cpu.c:25
long LONG
Definition: pedump.c:60
unsigned short USHORT
Definition: pedump.c:61
#define STATUS_SUCCESS
Definition: shellext.h:65
USHORT Limit
Definition: ketypes.h:449
ULONG SecondLevelCacheSize
Definition: ketypes.h:953
UCHAR VendorString[13]
Definition: ketypes.h:866
UCHAR CpuVendor
Definition: ketypes.h:669
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:759
ULONG InitialApicId
Definition: ketypes.h:686
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:600
ULONG64 KernelDr0
Definition: ketypes.h:570
ULONG64 KernelDr7
Definition: ketypes.h:575
ULONG64 MsrLStar
Definition: ketypes.h:590
KDESCRIPTOR Gdtr
Definition: ketypes.h:576
ULONG64 KernelDr2
Definition: ketypes.h:572
ULONG64 MsrGsBase
Definition: ketypes.h:587
KDESCRIPTOR Idtr
Definition: ketypes.h:577
ULONG64 KernelDr1
Definition: ketypes.h:571
ULONG64 MsrCStar
Definition: ketypes.h:591
ULONG64 MsrSyscallMask
Definition: ketypes.h:592
ULONG64 MsrGsSwap
Definition: ketypes.h:588
ULONG64 KernelDr3
Definition: ketypes.h:573
ULONG64 KernelDr6
Definition: ketypes.h:574
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
struct CPUID_AMD_SVM_FEATURES_EDX::@3728 Bits
CPUID_AMD_SVM_FEATURES_EDX Edx
Definition: Cpuid.h:206
struct CPUID_EXTENDED_CPU_SIG_REGS::@3725 Intel
struct CPUID_EXTENDED_CPU_SIG_REGS::@3726 Amd
CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax
Definition: Cpuid.h:107
struct CPUID_EXTENDED_STATE_SUB_LEAF_EAX::@3823 Bits
UINT32 MaxLeaf
Definition: Cpuid.h:19
INT32 AsInt32[4]
Definition: Cpuid.h:16
struct CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::@3813 Bits
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx
Definition: Cpuid.h:80
struct CPUID_THERMAL_POWER_MANAGEMENT_REGS::@3716 Undoc
struct MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER::@3860 Bits
struct MSR_IA32_VMX_PROCBASED_CTLS_REGISTER::@3859 Bits
ULONG Ebx
Definition: ketypes.h:367
ULONG Eax
Definition: ketypes.h:366
UINT32 AsUINT32[4]
Definition: ketypes.h:363
ULONG Ecx
Definition: ketypes.h:368
ULONG Edx
Definition: ketypes.h:369
ULONG Unused
Definition: cpu.c:47
ULONG ExtendedFamily
Definition: cpu.c:49
ULONG Model
Definition: cpu.c:45
ULONG Unused2
Definition: cpu.c:50
ULONG Family
Definition: cpu.c:46
ULONG AsULONG
Definition: cpu.c:52
ULONG Step
Definition: cpu.c:44
ULONG ExtendedModel
Definition: cpu.c:48
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:778
unsigned char UCHAR
Definition: xmlstorage.h:181
char CHAR
Definition: xmlstorage.h:175
void _mm_setcsr(unsigned int a)
Definition: xmmintrin.h:542
unsigned int _mm_getcsr(void)
Definition: xmmintrin.h:535