ReactOS 0.4.16-dev-1535-gea189a3
cpu.c
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1/*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/amd64/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
7 * Timo Kreuzer (timo.kreuzer@reactos.org)
8 */
9
10/* INCLUDES *****************************************************************/
11
12#include <ntoskrnl.h>
13#include <x86x64/Cpuid.h>
14#include <x86x64/Msr.h>
15
16#define NDEBUG
17#include <debug.h>
18
19/* GLOBALS *******************************************************************/
20
21/* The Boot TSS */
23
24/* CPU Features and Flags */
32
33/* Flush data */
35
36/* CPU Signatures */
37static const CHAR CmpIntelID[] = "GenuineIntel";
38static const CHAR CmpAmdID[] = "AuthenticAMD";
39static const CHAR CmpCentaurID[] = "CentaurHauls";
40
41typedef union _CPU_SIGNATURE
42{
43 struct
44 {
52 };
55
56/* FUNCTIONS *****************************************************************/
57
61{
62 PKPRCB Prcb = KeGetCurrentPrcb();
63 CPU_INFO CpuInfo;
64
65 /* Get the Vendor ID and null-terminate it */
66 KiCpuId(&CpuInfo, 0);
67
68 /* Copy it to the PRCB and null-terminate it */
69 *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
70 *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
71 *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
72 Prcb->VendorString[12] = 0;
73
74 /* Now check the CPU Type */
76 {
77 Prcb->CpuVendor = CPU_INTEL;
78 }
79 else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
80 {
81 Prcb->CpuVendor = CPU_AMD;
82 }
83 else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
84 {
85 DPRINT1("VIA CPUs not fully supported\n");
86 Prcb->CpuVendor = CPU_VIA;
87 }
88 else
89 {
90 /* Invalid CPU */
91 DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
92 Prcb->CpuVendor = CPU_UNKNOWN;
93 }
94
95 return Prcb->CpuVendor;
96}
97
98VOID
101{
102 CPU_INFO CpuInfo;
103 CPU_SIGNATURE CpuSignature;
104 BOOLEAN ExtendModel;
105 ULONG Stepping, Type, Vendor;
106
107 /* This initializes Prcb->CpuVendor */
108 Vendor = KiGetCpuVendor();
109
110 /* Do CPUID 1 now */
111 KiCpuId(&CpuInfo, 1);
112
113 /*
114 * Get the Stepping and Type. The stepping contains both the
115 * Model and the Step, while the Type contains the returned Family.
116 *
117 * For the stepping, we convert this: zzzzzzxy into this: x0y
118 */
119 CpuSignature.AsULONG = CpuInfo.Eax;
120 Stepping = CpuSignature.Model;
121 ExtendModel = (CpuSignature.Family == 15);
122#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
123 if (CpuSignature.Family == 6)
124 {
125 ExtendModel |= (Vendor == CPU_INTEL);
126#if (NTDDI_VERSION >= NTDDI_WIN8)
127 ExtendModel |= (Vendor == CPU_CENTAUR);
128#endif
129 }
130#endif
131 if (ExtendModel)
132 {
133 /* Add ExtendedModel to distinguish from non-extended values. */
134 Stepping |= (CpuSignature.ExtendedModel << 4);
135 }
136 Stepping = (Stepping << 8) | CpuSignature.Step;
137 Type = CpuSignature.Family;
138 if (CpuSignature.Family == 15)
139 {
140 /* Add ExtendedFamily to distinguish from non-extended values.
141 * It must not be larger than 0xF0 to avoid overflow. */
142 Type += min(CpuSignature.ExtendedFamily, 0xF0);
143 }
144
145 /* Save them in the PRCB */
146 KeGetCurrentPrcb()->CpuID = TRUE;
147 KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
148 KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
149}
150
165NTAPI
167{
168 PKPRCB Prcb = KeGetCurrentPrcb();
169 ULONG Vendor;
170 ULONG64 FeatureBits = 0;
173 CPUID_EXTENDED_FUNCTION_REGS extendedFunction;
174
175 /* Get the Vendor ID */
176 Vendor = Prcb->CpuVendor;
177
178 /* Make sure we got a valid vendor ID at least. */
179 if (Vendor == CPU_UNKNOWN) return FeatureBits;
180
181 /* Get signature CPUID for the maximum function */
183
184 /* Get the CPUID Info. */
186
187 /* Set the initial APIC ID */
188 Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId;
189
190 /* Convert all CPUID Feature bits into our format */
191 if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4;
192 if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
193 if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC;
194 if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B;
195 if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL;
196 if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR;
197 if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
198 if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV;
199 if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT;
200 if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS;
201 if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX;
202 if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR;
203 if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI;
204 if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64;
205
206 if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3;
207 if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3;
208 if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B;
209 if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1;
210 if (VersionInfo.Ecx.Bits.SSE4_2) FeatureBits |= KF_SSE4_2;
211 if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE;
212 if (VersionInfo.Ecx.Bits.RDRAND) FeatureBits |= KF_RDRAND;
213 if (VersionInfo.Ecx.Bits.AVX) FeatureBits |= KF_AVX;
214
215 /* Check if the CPU has hyper-threading */
216 if (VersionInfo.Edx.Bits.HTT)
217 {
218 /* Set the number of logical CPUs */
220 VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors;
222 {
223 /* We're on dual-core */
225 }
226 }
227 else
228 {
229 /* We only have a single CPU */
231 }
232
233 /* Check if CPUID_THERMAL_POWER_MANAGEMENT (0x06) is supported */
235 {
236 /* Read CPUID_THERMAL_POWER_MANAGEMENT */
239
240 if (PowerInfo.Undoc.Ecx.ACNT2) FeatureBits |= KF_ACNT2;
241 }
242
243 /* Check if CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) is supported */
245 {
246 /* Read CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS */
248 __cpuidex(ExtFlags.AsInt32,
251
252 if (ExtFlags.Ebx.Bits.SMEP) FeatureBits |= KF_SMEP;
253 if (ExtFlags.Ebx.Bits.FSGSBASE) FeatureBits |= KF_RDWRFSGSBASE;
254 if (ExtFlags.Ebx.Bits.SMAP) FeatureBits |= KF_SMAP;
255 if (ExtFlags.Ebx.Bits.AVX2) FeatureBits |= KF_AVX2;
256 if (ExtFlags.Ebx.Bits.AVX512F) FeatureBits |= KF_AVX512F;
257 }
258
259 /* Check if CPUID_EXTENDED_STATE (0x0D) is supported */
260 if (signature.MaxLeaf >= CPUID_EXTENDED_STATE)
261 {
262 /* Read CPUID_EXTENDED_STATE */
264 __cpuidex(ExtStateSub.AsInt32,
267
268 if (ExtStateSub.Eax.Bits.XSAVEOPT) FeatureBits |= KF_XSAVEOPT;
269 if (ExtStateSub.Eax.Bits.XSAVES) FeatureBits |= KF_XSAVES;
270 }
271
272 /* Check extended cpuid features */
273 __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION);
274 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
275 {
276 /* Check if CPUID_EXTENDED_CPU_SIG (0x80000001) is supported */
277 if (extendedFunction.MaxLeaf >= CPUID_EXTENDED_CPU_SIG)
278 {
279 /* Read CPUID_EXTENDED_CPU_SIG */
282
283 /* Check if NX-bit is supported */
284 if (ExtSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT;
285 if (ExtSig.Intel.Edx.Bits.Page1GB) FeatureBits |= KF_HUGEPAGE;
286 if (ExtSig.Intel.Edx.Bits.RDTSCP) FeatureBits |= KF_RDTSCP;
287
288 /* AMD specific */
289 if (Vendor == CPU_AMD)
290 {
291 if (ExtSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW;
292 }
293 }
294 }
295
296 /* Vendor specific */
297 if (Vendor == CPU_INTEL)
298 {
299 FeatureBits |= KF_GENUINE_INTEL;
300
301 /* Check for models that support LBR */
302 if (VersionInfo.Eax.Bits.FamilyId == 6)
303 {
304 if ((VersionInfo.Eax.Bits.Model == 15) ||
305 (VersionInfo.Eax.Bits.Model == 22) ||
306 (VersionInfo.Eax.Bits.Model == 23) ||
307 (VersionInfo.Eax.Bits.Model == 26))
308 {
309 FeatureBits |= KF_BRANCH;
310 }
311 }
312
313 /* Check if VMX is available */
314 if (VersionInfo.Ecx.Bits.VMX)
315 {
316 /* Read PROCBASED ctls and check if secondary are allowed */
319 if (ProcBasedCtls.Bits.Allowed1.ActivateSecondaryControls)
320 {
321 /* Read secondary controls and check if EPT is allowed */
324 if (ProcBasedCtls2.Bits.Allowed1.EPT)
325 FeatureBits |= KF_SLAT;
326 }
327 }
328 }
329 else if (Vendor == CPU_AMD)
330 {
331 FeatureBits |= KF_AUTHENTICAMD;
332 FeatureBits |= KF_BRANCH;
333
334 /* Check extended cpuid features */
335 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
336 {
337 /* Check if CPUID_AMD_SVM_FEATURES (0x8000000A) is supported */
338 if (extendedFunction.MaxLeaf >= CPUID_AMD_SVM_FEATURES)
339 {
340 /* Read CPUID_AMD_SVM_FEATURES and check if Nested Paging is available */
341 CPUID_AMD_SVM_FEATURES_REGS SvmFeatures;
343 if (SvmFeatures.Edx.Bits.NP) FeatureBits |= KF_SLAT;
344 }
345 }
346 }
347
348 /* Return the Feature Bits */
349 return FeatureBits;
350}
351
352#if DBG
353VOID
354KiReportCpuFeatures(IN PKPRCB Prcb)
355{
356 ULONG64 FeatureBits = Prcb->FeatureBits | ((ULONG64)Prcb->FeatureBitsHigh << 32);
357 ULONG CpuFeatures = 0;
358 CPU_INFO CpuInfo;
359
360 if (Prcb->CpuVendor)
361 {
362 KiCpuId(&CpuInfo, 1);
363 CpuFeatures = CpuInfo.Edx;
364 }
365
366 DPRINT1("Supported CPU features:");
367
368#define print_kf_bit(kf_value) if (FeatureBits & kf_value) DbgPrint(" " #kf_value)
369 print_kf_bit(KF_SMEP);
370 print_kf_bit(KF_RDTSC);
371 print_kf_bit(KF_CR4);
372 print_kf_bit(KF_CMOV);
373 print_kf_bit(KF_GLOBAL_PAGE);
374 print_kf_bit(KF_LARGE_PAGE);
375 print_kf_bit(KF_MTRR);
376 print_kf_bit(KF_CMPXCHG8B);
377 print_kf_bit(KF_MMX);
378 print_kf_bit(KF_DTS);
379 print_kf_bit(KF_PAT);
380 print_kf_bit(KF_FXSR);
381 print_kf_bit(KF_FAST_SYSCALL);
382 print_kf_bit(KF_XMMI);
383 print_kf_bit(KF_3DNOW);
384 print_kf_bit(KF_XSAVEOPT);
385 print_kf_bit(KF_XMMI64);
386 print_kf_bit(KF_BRANCH);
387 print_kf_bit(KF_00040000);
388 print_kf_bit(KF_SSE3);
389 print_kf_bit(KF_CMPXCHG16B);
390 print_kf_bit(KF_AUTHENTICAMD);
391 print_kf_bit(KF_ACNT2);
392 print_kf_bit(KF_XSTATE);
393 print_kf_bit(KF_GENUINE_INTEL);
394 print_kf_bit(KF_SLAT);
395 print_kf_bit(KF_VIRT_FIRMWARE_ENABLED);
396 print_kf_bit(KF_RDWRFSGSBASE);
397 print_kf_bit(KF_NX_BIT);
398 print_kf_bit(KF_NX_DISABLED);
399 print_kf_bit(KF_NX_ENABLED);
400 print_kf_bit(KF_RDRAND);
401 print_kf_bit(KF_SMAP);
402 print_kf_bit(KF_RDTSCP);
403 print_kf_bit(KF_HUGEPAGE);
404 print_kf_bit(KF_XSAVES);
405 print_kf_bit(KF_FPU_LEAKAGE);
406 print_kf_bit(KF_CAT);
407 print_kf_bit(KF_CET_SS);
408 print_kf_bit(KF_SSSE3);
409 print_kf_bit(KF_SSE4_1);
410 print_kf_bit(KF_SSE4_2);
411 print_kf_bit(KF_AVX);
412 print_kf_bit(KF_AVX2);
413 print_kf_bit(KF_AVX512F);
414#undef print_kf_bit
415
416#define print_cf(cpu_flag) if (CpuFeatures & cpu_flag) DbgPrint(" " #cpu_flag)
417 print_cf(X86_FEATURE_PAE);
418 print_cf(X86_FEATURE_HT);
419#undef print_cf
420
421 DbgPrint("\n");
422}
423#endif // DBG
424
425VOID
426NTAPI
428{
429 PKIPCR Pcr = (PKIPCR)KeGetPcr();
430 ULONG Vendor;
431 ULONG CacheRequests = 0, i;
432 ULONG CurrentRegister;
433 UCHAR RegisterByte;
434 BOOLEAN FirstPass = TRUE;
435 CPU_INFO CpuInfo;
436
437 /* Set default L2 size */
438 Pcr->SecondLevelCacheSize = 0;
439
440 /* Get the Vendor ID and make sure we support CPUID */
441 Vendor = KiGetCpuVendor();
442 if (!Vendor) return;
443
444 /* Check the Vendor ID */
445 switch (Vendor)
446 {
447 /* Handle Intel case */
448 case CPU_INTEL:
449
450 /*Check if we support CPUID 2 */
451 KiCpuId(&CpuInfo, 0);
452 if (CpuInfo.Eax >= 2)
453 {
454 /* We need to loop for the number of times CPUID will tell us to */
455 do
456 {
457 /* Do the CPUID call */
458 KiCpuId(&CpuInfo, 2);
459
460 /* Check if it was the first call */
461 if (FirstPass)
462 {
463 /*
464 * The number of times to loop is the first byte. Read
465 * it and then destroy it so we don't get confused.
466 */
467 CacheRequests = CpuInfo.Eax & 0xFF;
468 CpuInfo.Eax &= 0xFFFFFF00;
469
470 /* Don't go over this again */
471 FirstPass = FALSE;
472 }
473
474 /* Loop all 4 registers */
475 for (i = 0; i < 4; i++)
476 {
477 /* Get the current register */
478 CurrentRegister = CpuInfo.AsUINT32[i];
479
480 /*
481 * If the upper bit is set, then this register should
482 * be skipped.
483 */
484 if (CurrentRegister & 0x80000000) continue;
485
486 /* Keep looping for every byte inside this register */
487 while (CurrentRegister)
488 {
489 /* Read a byte, skip a byte. */
490 RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
491 CurrentRegister >>= 8;
492 if (!RegisterByte) continue;
493
494 /*
495 * Valid values are from 0x40 (0 bytes) to 0x49
496 * (32MB), or from 0x80 to 0x89 (same size but
497 * 8-way associative.
498 */
499 if (((RegisterByte > 0x40) &&
500 (RegisterByte <= 0x49)) ||
501 ((RegisterByte > 0x80) &&
502 (RegisterByte <= 0x89)))
503 {
504 /* Mask out only the first nibble */
505 RegisterByte &= 0x0F;
506
507 /* Set the L2 Cache Size */
508 Pcr->SecondLevelCacheSize = 0x10000 <<
509 RegisterByte;
510 }
511 }
512 }
513 } while (--CacheRequests);
514 }
515 break;
516
517 case CPU_AMD:
518
519 /* Check if we support CPUID 0x80000006 */
520 KiCpuId(&CpuInfo, 0x80000000);
521 if (CpuInfo.Eax >= 6)
522 {
523 /* Get 2nd level cache and tlb size */
524 KiCpuId(&CpuInfo, 0x80000006);
525
526 /* Set the L2 Cache Size */
527 Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
528 }
529 break;
530 }
531}
532
533VOID
534NTAPI
536{
537 /* Flush the TLB by resetting CR3 */
539}
540
541VOID
542NTAPI
544{
545 /* Restore the CR registers */
546 __writecr0(ProcessorState->SpecialRegisters.Cr0);
547// __writecr2(ProcessorState->SpecialRegisters.Cr2);
548 __writecr3(ProcessorState->SpecialRegisters.Cr3);
549 __writecr4(ProcessorState->SpecialRegisters.Cr4);
550 __writecr8(ProcessorState->SpecialRegisters.Cr8);
551
552 /* Restore the DR registers */
553 __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
554 __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
555 __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
556 __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
557 __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
558 __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
559
560 /* Restore GDT, IDT, LDT and TSS */
561 __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
562// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
563// __ltr(&ProcessorState->SpecialRegisters.Tr);
564 __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
565
566 _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
567// ProcessorState->SpecialRegisters.DebugControl
568// ProcessorState->SpecialRegisters.LastBranchToRip
569// ProcessorState->SpecialRegisters.LastBranchFromRip
570// ProcessorState->SpecialRegisters.LastExceptionToRip
571// ProcessorState->SpecialRegisters.LastExceptionFromRip
572
573 /* Restore MSRs */
580
581}
582
583VOID
584NTAPI
586{
587 /* Save the CR registers */
588 ProcessorState->SpecialRegisters.Cr0 = __readcr0();
589 ProcessorState->SpecialRegisters.Cr2 = __readcr2();
590 ProcessorState->SpecialRegisters.Cr3 = __readcr3();
591 ProcessorState->SpecialRegisters.Cr4 = __readcr4();
592 ProcessorState->SpecialRegisters.Cr8 = __readcr8();
593
594 /* Save the DR registers */
595 ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
596 ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
597 ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
598 ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
599 ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
600 ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
601
602 /* Save GDT, IDT, LDT and TSS */
603 __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
604 __sldt(&ProcessorState->SpecialRegisters.Ldtr);
605 __str(&ProcessorState->SpecialRegisters.Tr);
606 __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
607
608 ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
609// ProcessorState->SpecialRegisters.DebugControl =
610// ProcessorState->SpecialRegisters.LastBranchToRip =
611// ProcessorState->SpecialRegisters.LastBranchFromRip =
612// ProcessorState->SpecialRegisters.LastExceptionToRip =
613// ProcessorState->SpecialRegisters.LastExceptionFromRip =
614
615 /* Save MSRs */
616 ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
617 ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
618 ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
619 ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
620 ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
621 ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
622}
623
624VOID
625NTAPI
627 _In_ PKTRAP_FRAME TrapFrame,
628 _In_ PKEXCEPTION_FRAME ExceptionFrame)
629{
630 PKPRCB Prcb = KeGetCurrentPrcb();
631
632 /* Save all context */
634 KeTrapFrameToContext(TrapFrame, ExceptionFrame, &Prcb->ProcessorState.ContextFrame);
635
636 /* Save control registers */
638}
639
640VOID
641NTAPI
643 _Out_ PKTRAP_FRAME TrapFrame,
644 _Out_ PKEXCEPTION_FRAME ExceptionFrame)
645{
646 PKPRCB Prcb = KeGetCurrentPrcb();
647
648 /* Restore all context */
650 ExceptionFrame,
651 TrapFrame,
653 TrapFrame->PreviousMode);
654
655 /* Restore control registers */
657}
658
659VOID
660NTAPI
662 IN BOOLEAN AllProcessors)
663{
665
666 // FIXME: halfplemented
667 /* Raise the IRQL for the TB Flush */
669
670 /* Flush the TB for the Current CPU, and update the flush stamp */
672
673 /* Update the flush stamp and return to original IRQL */
676
677}
678
680NTAPI
682{
683 UNREFERENCED_PARAMETER(FloatingState);
684 return STATUS_SUCCESS;
685}
686
688NTAPI
690{
691 UNREFERENCED_PARAMETER(FloatingState);
692 return STATUS_SUCCESS;
693}
694
696NTAPI
698{
699 /* Invalidate all caches */
700 __wbinvd();
701 return TRUE;
702}
703
704/*
705 * @implemented
706 */
707ULONG
708NTAPI
710{
711 /* Return the global variable */
712 return KeLargestCacheLine;
713}
714
715/*
716 * @implemented
717 */
718VOID
721{
722 /* Capture the context */
723 RtlCaptureContext(&State->ContextFrame);
724
725 /* Capture the control state */
727}
728
729/*
730 * @implemented
731 */
732VOID
733NTAPI
735{
736 /* Save the coherency globally */
737 KiDmaIoCoherency = Coherency;
738}
#define MSR_IA32_VMX_PROCBASED_CTLS
#define MSR_IA32_VMX_PROCBASED_CTLS2
#define CPUID_AMD_SVM_FEATURES
Definition: Cpuid.h:160
#define CPUID_EXTENDED_FUNCTION
Definition: Cpuid.h:3772
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
Definition: Cpuid.h:1301
#define CPUID_SIGNATURE
Definition: Cpuid.h:45
#define CPUID_VERSION_INFO
Definition: Cpuid.h:81
#define CPUID_EXTENDED_STATE
Definition: Cpuid.h:1918
#define CPUID_THERMAL_POWER_MANAGEMENT
Definition: Cpuid.h:1114
#define CPUID_EXTENDED_STATE_SUB_LEAF
Definition: Cpuid.h:2033
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
Definition: Cpuid.h:1306
#define CPUID_EXTENDED_CPU_SIG
Definition: Cpuid.h:3795
unsigned char BOOLEAN
Type
Definition: Type.h:7
int strcmp(const char *String1, const char *String2)
Definition: utclib.c:469
#define __cdecl
Definition: accygwin.h:79
@ Invalid
Definition: asmpp.cpp:30
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
OSVERSIONINFOW VersionInfo
Definition: wkssvc.c:40
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
UCHAR KIRQL
Definition: env_spec_w32.h:591
#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
Definition: pic.c:156
#define DbgPrint
Definition: hal.h:12
#define InterlockedExchangeAdd
Definition: interlocked.h:196
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
PPC_QUAL void __cpuid(int CPUInfo[], const int InfoType)
Definition: intrin_ppc.h:682
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1832
__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2041
__INTRIN_INLINE void __cpuidex(int CPUInfo[4], int InfoType, int ECXValue)
Definition: intrin_x86.h:1662
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
Definition: intrin_x86.h:1916
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1839
__INTRIN_INLINE unsigned long __readcr0(void)
Definition: intrin_x86.h:1818
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1808
__INTRIN_INLINE unsigned long __readcr2(void)
Definition: intrin_x86.h:1825
__INTRIN_INLINE void __writecr0(unsigned int Data)
Definition: intrin_x86.h:1803
__INTRIN_INLINE void __sidt(void *Destination)
Definition: intrin_x86.h:2046
__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1813
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
Definition: intrin_x86.h:1949
if(dx< 0)
Definition: linetemp.h:194
unsigned __int64 ULONG64
Definition: imports.h:198
#define min(a, b)
Definition: monoChain.cc:55
#define KF_SSE4_2
Definition: ketypes.h:74
#define KF_SMEP
Definition: ketypes.h:31
#define KF_FPU_LEAKAGE
Definition: ketypes.h:69
#define KF_SSSE3
Definition: ketypes.h:72
#define KF_MTRR
Definition: ketypes.h:37
#define KF_HUGEPAGE
Definition: ketypes.h:67
#define KF_XSTATE
Definition: ketypes.h:55
#define KF_DTS
Definition: ketypes.h:40
#define KF_VIRT_FIRMWARE_ENABLED
Definition: ketypes.h:59
#define KF_CMPXCHG16B
Definition: ketypes.h:52
#define KF_CET_SS
Definition: ketypes.h:71
#define KF_NX_DISABLED
Definition: ketypes.h:62
#define KF_CR4
Definition: ketypes.h:33
#define KF_AUTHENTICAMD
Definition: ketypes.h:53
#define KF_XMMI64
Definition: ketypes.h:48
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1187
#define KF_CMOV
Definition: ketypes.h:34
#define KF_ACNT2
Definition: ketypes.h:54
#define KF_SSE4_1
Definition: ketypes.h:73
#define KF_RDWRFSGSBASE
Definition: ketypes.h:60
#define KF_00040000
Definition: ketypes.h:50
#define KF_CMPXCHG8B
Definition: ketypes.h:38
#define KF_NX_ENABLED
Definition: ketypes.h:63
#define KF_RDTSC
Definition: ketypes.h:32
#define KF_FAST_SYSCALL
Definition: ketypes.h:43
#define KF_3DNOW
Definition: ketypes.h:45
struct _KIPCR * PKIPCR
#define KF_NX_BIT
Definition: ketypes.h:61
#define KF_FXSR
Definition: ketypes.h:42
#define KF_RDRAND
Definition: ketypes.h:64
#define KF_CAT
Definition: ketypes.h:70
@ CPU_VIA
Definition: ketypes.h:101
@ CPU_INTEL
Definition: ketypes.h:100
@ CPU_UNKNOWN
Definition: ketypes.h:98
@ CPU_AMD
Definition: ketypes.h:99
#define KF_XSAVES
Definition: ketypes.h:68
#define KF_LARGE_PAGE
Definition: ketypes.h:36
#define KF_BRANCH
Definition: ketypes.h:49
#define KF_AVX
Definition: ketypes.h:77
#define KF_GENUINE_INTEL
Definition: ketypes.h:56
#define KF_XMMI
Definition: ketypes.h:44
#define KF_MMX
Definition: ketypes.h:39
#define KF_XSAVEOPT
Definition: ketypes.h:47
#define KF_SSE3
Definition: ketypes.h:51
#define KF_SLAT
Definition: ketypes.h:58
#define KF_PAT
Definition: ketypes.h:41
#define KF_AVX2
Definition: ketypes.h:78
#define KF_RDTSCP
Definition: ketypes.h:66
#define KF_GLOBAL_PAGE
Definition: ketypes.h:35
#define KF_SMAP
Definition: ketypes.h:65
#define KF_AVX512F
Definition: ketypes.h:79
#define KeGetPcr()
Definition: ketypes.h:81
@ CPU_CENTAUR
Definition: ketypes.h:95
NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)
#define _Out_
Definition: no_sal2.h:160
#define _In_
Definition: no_sal2.h:158
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:329
#define X86_MSR_CSTAR
Definition: ke.h:75
#define X86_FEATURE_HT
Definition: ke.h:47
#define X86_MSR_GSBASE
Definition: ke.h:70
#define X86_MSR_LSTAR
Definition: ke.h:74
#define X86_FEATURE_PAE
Definition: ke.h:35
#define X86_MSR_SFMASK
Definition: ke.h:76
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:71
#define X86_MSR_STAR
Definition: ke.h:73
VOID NTAPI KeTrapFrameToContext(IN PKTRAP_FRAME TrapFrame, IN PKEXCEPTION_FRAME ExceptionFrame, IN OUT PCONTEXT Context)
Definition: context.c:169
VOID NTAPI KeContextToTrapFrame(PCONTEXT Context, PKEXCEPTION_FRAME ExeptionFrame, PKTRAP_FRAME TrapFrame, ULONG ContextFlags, KPROCESSOR_MODE PreviousMode)
ULONG NTAPI KeGetRecommendedSharedDataAlignment(VOID)
Definition: cpu.c:709
VOID NTAPI KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:543
ULONG KeI386NpxPresent
Definition: cpu.c:28
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:535
VOID NTAPI KiSetProcessorType(VOID)
Definition: cpu.c:100
ULONG KeI386MachineType
Definition: cpu.c:27
VOID NTAPI KeFlushEntireTb(IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
Definition: cpu.c:661
ULONG KeLargestCacheLine
Definition: cpu.c:29
VOID __cdecl KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
Definition: cpu.c:720
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:31
ULONG64 NTAPI KiGetFeatureBits(VOID)
Evaluates the KeFeatureFlag bits for the current CPU.
Definition: cpu.c:166
BOOLEAN NTAPI KeInvalidateAllCaches(VOID)
Definition: cpu.c:697
NTSTATUS NTAPI KxRestoreFloatingPointState(IN PKFLOATING_SAVE FloatingState)
Definition: cpu.c:689
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:60
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:34
VOID NTAPI KiSaveProcessorState(_In_ PKTRAP_FRAME TrapFrame, _In_ PKEXCEPTION_FRAME ExceptionFrame)
Definition: cpu.c:626
VOID NTAPI KeSetDmaIoCoherency(IN ULONG Coherency)
Definition: cpu.c:734
KTSS64 KiBootTss
Definition: cpu.c:22
ULONG KeI386CpuType
Definition: cpu.c:25
NTSTATUS NTAPI KxSaveFloatingPointState(OUT PKFLOATING_SAVE FloatingState)
Definition: cpu.c:681
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:585
static const CHAR CmpIntelID[]
Definition: cpu.c:37
static const CHAR CmpAmdID[]
Definition: cpu.c:38
VOID NTAPI KiRestoreProcessorState(_Out_ PKTRAP_FRAME TrapFrame, _Out_ PKEXCEPTION_FRAME ExceptionFrame)
Definition: cpu.c:642
static const CHAR CmpCentaurID[]
Definition: cpu.c:39
ULONG KiDmaIoCoherency
Definition: cpu.c:30
VOID NTAPI KiGetCacheInformation(VOID)
Definition: cpu.c:427
union _CPU_SIGNATURE CPU_SIGNATURE
ULONG KeI386CpuStep
Definition: cpu.c:26
long LONG
Definition: pedump.c:60
unsigned short USHORT
Definition: pedump.c:61
#define CONTEXT_ALL
#define STATUS_SUCCESS
Definition: shellext.h:65
ULONG ContextFlags
Definition: nt_native.h:1426
USHORT Limit
Definition: ketypes.h:449
ULONG SecondLevelCacheSize
Definition: ketypes.h:985
UCHAR CpuVendor
Definition: ketypes.h:698
UCHAR VendorString[13]
Definition: ketypes.h:895
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:759
ULONG InitialApicId
Definition: ketypes.h:715
KPROCESSOR_STATE ProcessorState
Definition: ketypes.h:677
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:629
CONTEXT ContextFrame
Definition: ketypes.h:630
ULONG64 KernelDr1
Definition: ketypes.h:600
ULONG64 MsrLStar
Definition: ketypes.h:619
ULONG64 KernelDr2
Definition: ketypes.h:601
ULONG64 KernelDr0
Definition: ketypes.h:599
KDESCRIPTOR Gdtr
Definition: ketypes.h:605
ULONG64 MsrGsBase
Definition: ketypes.h:616
KDESCRIPTOR Idtr
Definition: ketypes.h:606
ULONG64 MsrCStar
Definition: ketypes.h:620
ULONG64 KernelDr7
Definition: ketypes.h:604
ULONG64 KernelDr6
Definition: ketypes.h:603
ULONG64 MsrSyscallMask
Definition: ketypes.h:621
ULONG64 KernelDr3
Definition: ketypes.h:602
ULONG64 MsrGsSwap
Definition: ketypes.h:617
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
struct CPUID_AMD_SVM_FEATURES_EDX::@3950 Bits
CPUID_AMD_SVM_FEATURES_EDX Edx
Definition: Cpuid.h:220
struct CPUID_EXTENDED_CPU_SIG_REGS::@3948 Amd
struct CPUID_EXTENDED_CPU_SIG_REGS::@3947 Intel
struct CPUID_EXTENDED_STATE_SUB_LEAF_EAX::@4045 Bits
CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax
Definition: Cpuid.h:107
struct CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::@4035 Bits
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx
Definition: Cpuid.h:80
struct CPUID_THERMAL_POWER_MANAGEMENT_REGS::@3936 Undoc
struct MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER::@4082 Bits
struct MSR_IA32_VMX_PROCBASED_CTLS_REGISTER::@4081 Bits
ULONG Ebx
Definition: ketypes.h:396
ULONG Eax
Definition: ketypes.h:395
UINT32 AsUINT32[4]
Definition: ketypes.h:392
ULONG Ecx
Definition: ketypes.h:397
ULONG Edx
Definition: ketypes.h:398
ULONG Unused
Definition: cpu.c:48
ULONG ExtendedFamily
Definition: cpu.c:50
ULONG Model
Definition: cpu.c:46
ULONG Unused2
Definition: cpu.c:51
ULONG Family
Definition: cpu.c:47
ULONG AsULONG
Definition: cpu.c:53
ULONG Step
Definition: cpu.c:45
ULONG ExtendedModel
Definition: cpu.c:49
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:778
unsigned char UCHAR
Definition: xmlstorage.h:181
char CHAR
Definition: xmlstorage.h:175
void _mm_setcsr(unsigned int a)
Definition: xmmintrin.h:542
unsigned int _mm_getcsr(void)
Definition: xmmintrin.h:535