ReactOS 0.4.16-dev-981-g80eb313
cpu.c
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1/*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/amd64/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
7 * Timo Kreuzer (timo.kreuzer@reactos.org)
8 */
9
10/* INCLUDES *****************************************************************/
11
12#include <ntoskrnl.h>
13#include <x86x64/Cpuid.h>
14#include <x86x64/Msr.h>
15
16#define NDEBUG
17#include <debug.h>
18
19/* GLOBALS *******************************************************************/
20
21/* The Boot TSS */
23
24/* CPU Features and Flags */
32
33/* Flush data */
35
36/* CPU Signatures */
37static const CHAR CmpIntelID[] = "GenuineIntel";
38static const CHAR CmpAmdID[] = "AuthenticAMD";
39static const CHAR CmpCentaurID[] = "CentaurHauls";
40
41typedef union _CPU_SIGNATURE
42{
43 struct
44 {
52 };
55
56/* FUNCTIONS *****************************************************************/
57
61{
62 PKPRCB Prcb = KeGetCurrentPrcb();
63 CPU_INFO CpuInfo;
64
65 /* Get the Vendor ID and null-terminate it */
66 KiCpuId(&CpuInfo, 0);
67
68 /* Copy it to the PRCB and null-terminate it */
69 *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
70 *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
71 *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
72 Prcb->VendorString[12] = 0;
73
74 /* Now check the CPU Type */
76 {
77 Prcb->CpuVendor = CPU_INTEL;
78 }
79 else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
80 {
81 Prcb->CpuVendor = CPU_AMD;
82 }
83 else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
84 {
85 DPRINT1("VIA CPUs not fully supported\n");
86 Prcb->CpuVendor = CPU_VIA;
87 }
88 else
89 {
90 /* Invalid CPU */
91 DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
92 Prcb->CpuVendor = CPU_UNKNOWN;
93 }
94
95 return Prcb->CpuVendor;
96}
97
98VOID
101{
102 CPU_INFO CpuInfo;
103 CPU_SIGNATURE CpuSignature;
104 BOOLEAN ExtendModel;
105 ULONG Stepping, Type, Vendor;
106
107 /* This initializes Prcb->CpuVendor */
108 Vendor = KiGetCpuVendor();
109
110 /* Do CPUID 1 now */
111 KiCpuId(&CpuInfo, 1);
112
113 /*
114 * Get the Stepping and Type. The stepping contains both the
115 * Model and the Step, while the Type contains the returned Family.
116 *
117 * For the stepping, we convert this: zzzzzzxy into this: x0y
118 */
119 CpuSignature.AsULONG = CpuInfo.Eax;
120 Stepping = CpuSignature.Model;
121 ExtendModel = (CpuSignature.Family == 15);
122#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
123 if (CpuSignature.Family == 6)
124 {
125 ExtendModel |= (Vendor == CPU_INTEL);
126#if (NTDDI_VERSION >= NTDDI_WIN8)
127 ExtendModel |= (Vendor == CPU_CENTAUR);
128#endif
129 }
130#endif
131 if (ExtendModel)
132 {
133 /* Add ExtendedModel to distinguish from non-extended values. */
134 Stepping |= (CpuSignature.ExtendedModel << 4);
135 }
136 Stepping = (Stepping << 8) | CpuSignature.Step;
137 Type = CpuSignature.Family;
138 if (CpuSignature.Family == 15)
139 {
140 /* Add ExtendedFamily to distinguish from non-extended values.
141 * It must not be larger than 0xF0 to avoid overflow. */
142 Type += min(CpuSignature.ExtendedFamily, 0xF0);
143 }
144
145 /* Save them in the PRCB */
146 KeGetCurrentPrcb()->CpuID = TRUE;
147 KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
148 KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
149}
150
165NTAPI
167{
168 PKPRCB Prcb = KeGetCurrentPrcb();
169 ULONG Vendor;
170 ULONG64 FeatureBits = 0;
173 CPUID_EXTENDED_FUNCTION_REGS extendedFunction;
174
175 /* Get the Vendor ID */
176 Vendor = Prcb->CpuVendor;
177
178 /* Make sure we got a valid vendor ID at least. */
179 if (Vendor == CPU_UNKNOWN) return FeatureBits;
180
181 /* Get signature CPUID for the maximum function */
183
184 /* Get the CPUID Info. */
186
187 /* Set the initial APIC ID */
188 Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId;
189
190 /* Convert all CPUID Feature bits into our format */
191 if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4;
192 if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
193 if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC;
194 if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B;
195 if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL;
196 if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR;
197 if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
198 if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV;
199 if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT;
200 if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS;
201 if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX;
202 if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR;
203 if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI;
204 if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64;
205
206 if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3;
207 if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3;
208 if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B;
209 if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1;
210 if (VersionInfo.Ecx.Bits.SSE4_2) FeatureBits |= KF_SSE4_2;
211 if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE;
212 if (VersionInfo.Ecx.Bits.RDRAND) FeatureBits |= KF_RDRAND;
213
214 /* Check if the CPU has hyper-threading */
215 if (VersionInfo.Edx.Bits.HTT)
216 {
217 /* Set the number of logical CPUs */
219 VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors;
221 {
222 /* We're on dual-core */
224 }
225 }
226 else
227 {
228 /* We only have a single CPU */
230 }
231
232 /* Check if CPUID_THERMAL_POWER_MANAGEMENT (0x06) is supported */
234 {
235 /* Read CPUID_THERMAL_POWER_MANAGEMENT */
238
239 if (PowerInfo.Undoc.Ecx.ACNT2) FeatureBits |= KF_ACNT2;
240 }
241
242 /* Check if CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) is supported */
244 {
245 /* Read CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS */
247 __cpuidex(ExtFlags.AsInt32,
250
251 if (ExtFlags.Ebx.Bits.SMEP) FeatureBits |= KF_SMEP;
252 if (ExtFlags.Ebx.Bits.FSGSBASE) FeatureBits |= KF_RDWRFSGSBASE;
253 if (ExtFlags.Ebx.Bits.SMAP) FeatureBits |= KF_SMAP;
254 }
255
256 /* Check if CPUID_EXTENDED_STATE (0x0D) is supported */
257 if (signature.MaxLeaf >= CPUID_EXTENDED_STATE)
258 {
259 /* Read CPUID_EXTENDED_STATE */
261 __cpuidex(ExtStateSub.AsInt32,
264
265 if (ExtStateSub.Eax.Bits.XSAVEOPT) FeatureBits |= KF_XSAVEOPT;
266 if (ExtStateSub.Eax.Bits.XSAVES) FeatureBits |= KF_XSAVES;
267 }
268
269 /* Check extended cpuid features */
270 __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION);
271 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
272 {
273 /* Check if CPUID_EXTENDED_CPU_SIG (0x80000001) is supported */
274 if (extendedFunction.MaxLeaf >= CPUID_EXTENDED_CPU_SIG)
275 {
276 /* Read CPUID_EXTENDED_CPU_SIG */
279
280 /* Check if NX-bit is supported */
281 if (ExtSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT;
282 if (ExtSig.Intel.Edx.Bits.Page1GB) FeatureBits |= KF_HUGEPAGE;
283 if (ExtSig.Intel.Edx.Bits.RDTSCP) FeatureBits |= KF_RDTSCP;
284
285 /* AMD specific */
286 if (Vendor == CPU_AMD)
287 {
288 if (ExtSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW;
289 }
290 }
291 }
292
293 /* Vendor specific */
294 if (Vendor == CPU_INTEL)
295 {
296 FeatureBits |= KF_GENUINE_INTEL;
297
298 /* Check for models that support LBR */
299 if (VersionInfo.Eax.Bits.FamilyId == 6)
300 {
301 if ((VersionInfo.Eax.Bits.Model == 15) ||
302 (VersionInfo.Eax.Bits.Model == 22) ||
303 (VersionInfo.Eax.Bits.Model == 23) ||
304 (VersionInfo.Eax.Bits.Model == 26))
305 {
306 FeatureBits |= KF_BRANCH;
307 }
308 }
309
310 /* Check if VMX is available */
311 if (VersionInfo.Ecx.Bits.VMX)
312 {
313 /* Read PROCBASED ctls and check if secondary are allowed */
316 if (ProcBasedCtls.Bits.Allowed1.ActivateSecondaryControls)
317 {
318 /* Read secondary controls and check if EPT is allowed */
321 if (ProcBasedCtls2.Bits.Allowed1.EPT)
322 FeatureBits |= KF_SLAT;
323 }
324 }
325 }
326 else if (Vendor == CPU_AMD)
327 {
328 FeatureBits |= KF_AUTHENTICAMD;
329 FeatureBits |= KF_BRANCH;
330
331 /* Check extended cpuid features */
332 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
333 {
334 /* Check if CPUID_AMD_SVM_FEATURES (0x8000000A) is supported */
335 if (extendedFunction.MaxLeaf >= CPUID_AMD_SVM_FEATURES)
336 {
337 /* Read CPUID_AMD_SVM_FEATURES and check if Nested Paging is available */
338 CPUID_AMD_SVM_FEATURES_REGS SvmFeatures;
340 if (SvmFeatures.Edx.Bits.NP) FeatureBits |= KF_SLAT;
341 }
342 }
343 }
344
345 /* Return the Feature Bits */
346 return FeatureBits;
347}
348
349#if DBG
350VOID
351KiReportCpuFeatures(IN PKPRCB Prcb)
352{
353 ULONG CpuFeatures = 0;
354 CPU_INFO CpuInfo;
355
356 if (Prcb->CpuVendor)
357 {
358 KiCpuId(&CpuInfo, 1);
359 CpuFeatures = CpuInfo.Edx;
360 }
361
362 DPRINT1("Supported CPU features:");
363
364#define print_kf_bit(kf_value) if (Prcb->FeatureBits & kf_value) DbgPrint(" " #kf_value)
365 print_kf_bit(KF_SMEP);
366 print_kf_bit(KF_RDTSC);
367 print_kf_bit(KF_CR4);
368 print_kf_bit(KF_CMOV);
369 print_kf_bit(KF_GLOBAL_PAGE);
370 print_kf_bit(KF_LARGE_PAGE);
371 print_kf_bit(KF_MTRR);
372 print_kf_bit(KF_CMPXCHG8B);
373 print_kf_bit(KF_MMX);
374 print_kf_bit(KF_DTS);
375 print_kf_bit(KF_PAT);
376 print_kf_bit(KF_FXSR);
377 print_kf_bit(KF_FAST_SYSCALL);
378 print_kf_bit(KF_XMMI);
379 print_kf_bit(KF_3DNOW);
380 print_kf_bit(KF_XSAVEOPT);
381 print_kf_bit(KF_XMMI64);
382 print_kf_bit(KF_BRANCH);
383 print_kf_bit(KF_00040000);
384 print_kf_bit(KF_SSE3);
385 print_kf_bit(KF_CMPXCHG16B);
386 print_kf_bit(KF_AUTHENTICAMD);
387 print_kf_bit(KF_ACNT2);
388 print_kf_bit(KF_XSTATE);
389 print_kf_bit(KF_GENUINE_INTEL);
390 print_kf_bit(KF_SLAT);
391 print_kf_bit(KF_VIRT_FIRMWARE_ENABLED);
392 print_kf_bit(KF_RDWRFSGSBASE);
393 print_kf_bit(KF_NX_BIT);
394 print_kf_bit(KF_NX_DISABLED);
395 print_kf_bit(KF_NX_ENABLED);
396 print_kf_bit(KF_RDRAND);
397 print_kf_bit(KF_SMAP);
398 print_kf_bit(KF_RDTSCP);
399 print_kf_bit(KF_HUGEPAGE);
400 print_kf_bit(KF_XSAVES);
401 print_kf_bit(KF_FPU_LEAKAGE);
402 print_kf_bit(KF_CAT);
403 print_kf_bit(KF_CET_SS);
404 print_kf_bit(KF_SSSE3);
405 print_kf_bit(KF_SSE4_1);
406 print_kf_bit(KF_SSE4_2);
407#undef print_kf_bit
408
409#define print_cf(cpu_flag) if (CpuFeatures & cpu_flag) DbgPrint(" " #cpu_flag)
410 print_cf(X86_FEATURE_PAE);
411 print_cf(X86_FEATURE_HT);
412#undef print_cf
413
414 DbgPrint("\n");
415}
416#endif // DBG
417
418VOID
419NTAPI
421{
422 PKIPCR Pcr = (PKIPCR)KeGetPcr();
423 ULONG Vendor;
424 ULONG CacheRequests = 0, i;
425 ULONG CurrentRegister;
426 UCHAR RegisterByte;
427 BOOLEAN FirstPass = TRUE;
428 CPU_INFO CpuInfo;
429
430 /* Set default L2 size */
431 Pcr->SecondLevelCacheSize = 0;
432
433 /* Get the Vendor ID and make sure we support CPUID */
434 Vendor = KiGetCpuVendor();
435 if (!Vendor) return;
436
437 /* Check the Vendor ID */
438 switch (Vendor)
439 {
440 /* Handle Intel case */
441 case CPU_INTEL:
442
443 /*Check if we support CPUID 2 */
444 KiCpuId(&CpuInfo, 0);
445 if (CpuInfo.Eax >= 2)
446 {
447 /* We need to loop for the number of times CPUID will tell us to */
448 do
449 {
450 /* Do the CPUID call */
451 KiCpuId(&CpuInfo, 2);
452
453 /* Check if it was the first call */
454 if (FirstPass)
455 {
456 /*
457 * The number of times to loop is the first byte. Read
458 * it and then destroy it so we don't get confused.
459 */
460 CacheRequests = CpuInfo.Eax & 0xFF;
461 CpuInfo.Eax &= 0xFFFFFF00;
462
463 /* Don't go over this again */
464 FirstPass = FALSE;
465 }
466
467 /* Loop all 4 registers */
468 for (i = 0; i < 4; i++)
469 {
470 /* Get the current register */
471 CurrentRegister = CpuInfo.AsUINT32[i];
472
473 /*
474 * If the upper bit is set, then this register should
475 * be skipped.
476 */
477 if (CurrentRegister & 0x80000000) continue;
478
479 /* Keep looping for every byte inside this register */
480 while (CurrentRegister)
481 {
482 /* Read a byte, skip a byte. */
483 RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
484 CurrentRegister >>= 8;
485 if (!RegisterByte) continue;
486
487 /*
488 * Valid values are from 0x40 (0 bytes) to 0x49
489 * (32MB), or from 0x80 to 0x89 (same size but
490 * 8-way associative.
491 */
492 if (((RegisterByte > 0x40) &&
493 (RegisterByte <= 0x49)) ||
494 ((RegisterByte > 0x80) &&
495 (RegisterByte <= 0x89)))
496 {
497 /* Mask out only the first nibble */
498 RegisterByte &= 0x0F;
499
500 /* Set the L2 Cache Size */
501 Pcr->SecondLevelCacheSize = 0x10000 <<
502 RegisterByte;
503 }
504 }
505 }
506 } while (--CacheRequests);
507 }
508 break;
509
510 case CPU_AMD:
511
512 /* Check if we support CPUID 0x80000006 */
513 KiCpuId(&CpuInfo, 0x80000000);
514 if (CpuInfo.Eax >= 6)
515 {
516 /* Get 2nd level cache and tlb size */
517 KiCpuId(&CpuInfo, 0x80000006);
518
519 /* Set the L2 Cache Size */
520 Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
521 }
522 break;
523 }
524}
525
526VOID
527NTAPI
529{
530 /* Flush the TLB by resetting CR3 */
532}
533
534VOID
535NTAPI
537{
538 /* Restore the CR registers */
539 __writecr0(ProcessorState->SpecialRegisters.Cr0);
540// __writecr2(ProcessorState->SpecialRegisters.Cr2);
541 __writecr3(ProcessorState->SpecialRegisters.Cr3);
542 __writecr4(ProcessorState->SpecialRegisters.Cr4);
543 __writecr8(ProcessorState->SpecialRegisters.Cr8);
544
545 /* Restore the DR registers */
546 __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
547 __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
548 __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
549 __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
550 __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
551 __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
552
553 /* Restore GDT, IDT, LDT and TSS */
554 __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
555// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
556// __ltr(&ProcessorState->SpecialRegisters.Tr);
557 __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
558
559 _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
560// ProcessorState->SpecialRegisters.DebugControl
561// ProcessorState->SpecialRegisters.LastBranchToRip
562// ProcessorState->SpecialRegisters.LastBranchFromRip
563// ProcessorState->SpecialRegisters.LastExceptionToRip
564// ProcessorState->SpecialRegisters.LastExceptionFromRip
565
566 /* Restore MSRs */
573
574}
575
576VOID
577NTAPI
579{
580 /* Save the CR registers */
581 ProcessorState->SpecialRegisters.Cr0 = __readcr0();
582 ProcessorState->SpecialRegisters.Cr2 = __readcr2();
583 ProcessorState->SpecialRegisters.Cr3 = __readcr3();
584 ProcessorState->SpecialRegisters.Cr4 = __readcr4();
585 ProcessorState->SpecialRegisters.Cr8 = __readcr8();
586
587 /* Save the DR registers */
588 ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
589 ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
590 ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
591 ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
592 ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
593 ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
594
595 /* Save GDT, IDT, LDT and TSS */
596 __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
597 __sldt(&ProcessorState->SpecialRegisters.Ldtr);
598 __str(&ProcessorState->SpecialRegisters.Tr);
599 __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
600
601 ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
602// ProcessorState->SpecialRegisters.DebugControl =
603// ProcessorState->SpecialRegisters.LastBranchToRip =
604// ProcessorState->SpecialRegisters.LastBranchFromRip =
605// ProcessorState->SpecialRegisters.LastExceptionToRip =
606// ProcessorState->SpecialRegisters.LastExceptionFromRip =
607
608 /* Save MSRs */
609 ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
610 ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
611 ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
612 ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
613 ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
614 ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
615}
616
617VOID
618NTAPI
620 _In_ PKTRAP_FRAME TrapFrame,
621 _In_ PKEXCEPTION_FRAME ExceptionFrame)
622{
623 PKPRCB Prcb = KeGetCurrentPrcb();
624
625 /* Save all context */
627 KeTrapFrameToContext(TrapFrame, ExceptionFrame, &Prcb->ProcessorState.ContextFrame);
628
629 /* Save control registers */
631}
632
633VOID
634NTAPI
636 _Out_ PKTRAP_FRAME TrapFrame,
637 _Out_ PKEXCEPTION_FRAME ExceptionFrame)
638{
639 PKPRCB Prcb = KeGetCurrentPrcb();
640
641 /* Restore all context */
643 ExceptionFrame,
644 TrapFrame,
646 TrapFrame->PreviousMode);
647
648 /* Restore control registers */
650}
651
652VOID
653NTAPI
655 IN BOOLEAN AllProcessors)
656{
658
659 // FIXME: halfplemented
660 /* Raise the IRQL for the TB Flush */
662
663 /* Flush the TB for the Current CPU, and update the flush stamp */
665
666 /* Update the flush stamp and return to original IRQL */
669
670}
671
673NTAPI
675{
676 UNREFERENCED_PARAMETER(FloatingState);
677 return STATUS_SUCCESS;
678}
679
681NTAPI
683{
684 UNREFERENCED_PARAMETER(FloatingState);
685 return STATUS_SUCCESS;
686}
687
689NTAPI
691{
692 /* Invalidate all caches */
693 __wbinvd();
694 return TRUE;
695}
696
697/*
698 * @implemented
699 */
700ULONG
701NTAPI
703{
704 /* Return the global variable */
705 return KeLargestCacheLine;
706}
707
708/*
709 * @implemented
710 */
711VOID
714{
715 /* Capture the context */
716 RtlCaptureContext(&State->ContextFrame);
717
718 /* Capture the control state */
720}
721
722/*
723 * @implemented
724 */
725VOID
726NTAPI
728{
729 /* Save the coherency globally */
730 KiDmaIoCoherency = Coherency;
731}
#define MSR_IA32_VMX_PROCBASED_CTLS
#define MSR_IA32_VMX_PROCBASED_CTLS2
#define CPUID_AMD_SVM_FEATURES
Definition: Cpuid.h:146
#define CPUID_EXTENDED_FUNCTION
Definition: Cpuid.h:3745
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
Definition: Cpuid.h:1301
#define CPUID_SIGNATURE
Definition: Cpuid.h:45
#define CPUID_VERSION_INFO
Definition: Cpuid.h:81
#define CPUID_EXTENDED_STATE
Definition: Cpuid.h:1918
#define CPUID_THERMAL_POWER_MANAGEMENT
Definition: Cpuid.h:1114
#define CPUID_EXTENDED_STATE_SUB_LEAF
Definition: Cpuid.h:2033
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
Definition: Cpuid.h:1306
#define CPUID_EXTENDED_CPU_SIG
Definition: Cpuid.h:3768
unsigned char BOOLEAN
Type
Definition: Type.h:7
int strcmp(const char *String1, const char *String2)
Definition: utclib.c:469
#define __cdecl
Definition: accygwin.h:79
@ Invalid
Definition: asmpp.cpp:30
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
OSVERSIONINFOW VersionInfo
Definition: wkssvc.c:40
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
UCHAR KIRQL
Definition: env_spec_w32.h:591
#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
Definition: pic.c:156
#define DbgPrint
Definition: hal.h:12
#define InterlockedExchangeAdd
Definition: interlocked.h:181
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
PPC_QUAL void __cpuid(int CPUInfo[], const int InfoType)
Definition: intrin_ppc.h:682
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1832
__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2041
__INTRIN_INLINE void __cpuidex(int CPUInfo[4], int InfoType, int ECXValue)
Definition: intrin_x86.h:1662
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
Definition: intrin_x86.h:1916
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1839
__INTRIN_INLINE unsigned long __readcr0(void)
Definition: intrin_x86.h:1818
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1808
__INTRIN_INLINE unsigned long __readcr2(void)
Definition: intrin_x86.h:1825
__INTRIN_INLINE void __writecr0(unsigned int Data)
Definition: intrin_x86.h:1803
__INTRIN_INLINE void __sidt(void *Destination)
Definition: intrin_x86.h:2046
__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1813
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
Definition: intrin_x86.h:1949
if(dx< 0)
Definition: linetemp.h:194
unsigned __int64 ULONG64
Definition: imports.h:198
#define min(a, b)
Definition: monoChain.cc:55
#define KF_SSE4_2
Definition: ketypes.h:74
#define KF_SMEP
Definition: ketypes.h:31
#define KF_FPU_LEAKAGE
Definition: ketypes.h:69
#define KF_SSSE3
Definition: ketypes.h:72
#define KF_MTRR
Definition: ketypes.h:37
#define KF_HUGEPAGE
Definition: ketypes.h:67
#define KF_XSTATE
Definition: ketypes.h:55
#define KF_DTS
Definition: ketypes.h:40
#define KF_VIRT_FIRMWARE_ENABLED
Definition: ketypes.h:59
#define KF_CMPXCHG16B
Definition: ketypes.h:52
#define KF_CET_SS
Definition: ketypes.h:71
#define KF_NX_DISABLED
Definition: ketypes.h:62
#define KF_CR4
Definition: ketypes.h:33
#define KF_AUTHENTICAMD
Definition: ketypes.h:53
#define KF_XMMI64
Definition: ketypes.h:48
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1182
#define KF_CMOV
Definition: ketypes.h:34
#define KF_ACNT2
Definition: ketypes.h:54
#define KF_SSE4_1
Definition: ketypes.h:73
#define KF_RDWRFSGSBASE
Definition: ketypes.h:60
#define KF_00040000
Definition: ketypes.h:50
#define KF_CMPXCHG8B
Definition: ketypes.h:38
#define KF_NX_ENABLED
Definition: ketypes.h:63
#define KF_RDTSC
Definition: ketypes.h:32
#define KF_FAST_SYSCALL
Definition: ketypes.h:43
#define KF_3DNOW
Definition: ketypes.h:45
struct _KIPCR * PKIPCR
#define KF_NX_BIT
Definition: ketypes.h:61
#define KF_FXSR
Definition: ketypes.h:42
#define KF_RDRAND
Definition: ketypes.h:64
#define KF_CAT
Definition: ketypes.h:70
@ CPU_VIA
Definition: ketypes.h:96
@ CPU_INTEL
Definition: ketypes.h:95
@ CPU_UNKNOWN
Definition: ketypes.h:93
@ CPU_AMD
Definition: ketypes.h:94
#define KF_XSAVES
Definition: ketypes.h:68
#define KF_LARGE_PAGE
Definition: ketypes.h:36
#define KF_BRANCH
Definition: ketypes.h:49
#define KF_GENUINE_INTEL
Definition: ketypes.h:56
#define KF_XMMI
Definition: ketypes.h:44
#define KF_MMX
Definition: ketypes.h:39
#define KF_XSAVEOPT
Definition: ketypes.h:47
#define KF_SSE3
Definition: ketypes.h:51
#define KF_SLAT
Definition: ketypes.h:58
#define KF_PAT
Definition: ketypes.h:41
#define KF_RDTSCP
Definition: ketypes.h:66
#define KF_GLOBAL_PAGE
Definition: ketypes.h:35
#define KF_SMAP
Definition: ketypes.h:65
#define KeGetPcr()
Definition: ketypes.h:81
@ CPU_CENTAUR
Definition: ketypes.h:95
NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)
#define _Out_
Definition: no_sal2.h:160
#define _In_
Definition: no_sal2.h:158
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:325
#define X86_MSR_CSTAR
Definition: ke.h:75
#define X86_FEATURE_HT
Definition: ke.h:47
#define X86_MSR_GSBASE
Definition: ke.h:70
#define X86_MSR_LSTAR
Definition: ke.h:74
#define X86_FEATURE_PAE
Definition: ke.h:35
#define X86_MSR_SFMASK
Definition: ke.h:76
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:71
#define X86_MSR_STAR
Definition: ke.h:73
VOID NTAPI KeTrapFrameToContext(IN PKTRAP_FRAME TrapFrame, IN PKEXCEPTION_FRAME ExceptionFrame, IN OUT PCONTEXT Context)
Definition: context.c:169
VOID NTAPI KeContextToTrapFrame(PCONTEXT Context, PKEXCEPTION_FRAME ExeptionFrame, PKTRAP_FRAME TrapFrame, ULONG ContextFlags, KPROCESSOR_MODE PreviousMode)
ULONG NTAPI KeGetRecommendedSharedDataAlignment(VOID)
Definition: cpu.c:702
VOID NTAPI KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:536
ULONG KeI386NpxPresent
Definition: cpu.c:28
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:528
VOID NTAPI KiSetProcessorType(VOID)
Definition: cpu.c:100
ULONG KeI386MachineType
Definition: cpu.c:27
VOID NTAPI KeFlushEntireTb(IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
Definition: cpu.c:654
ULONG KeLargestCacheLine
Definition: cpu.c:29
VOID __cdecl KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
Definition: cpu.c:713
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:31
ULONG64 NTAPI KiGetFeatureBits(VOID)
Evaluates the KeFeatureFlag bits for the current CPU.
Definition: cpu.c:166
BOOLEAN NTAPI KeInvalidateAllCaches(VOID)
Definition: cpu.c:690
NTSTATUS NTAPI KxRestoreFloatingPointState(IN PKFLOATING_SAVE FloatingState)
Definition: cpu.c:682
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:60
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:34
VOID NTAPI KiSaveProcessorState(_In_ PKTRAP_FRAME TrapFrame, _In_ PKEXCEPTION_FRAME ExceptionFrame)
Definition: cpu.c:619
VOID NTAPI KeSetDmaIoCoherency(IN ULONG Coherency)
Definition: cpu.c:727
KTSS64 KiBootTss
Definition: cpu.c:22
ULONG KeI386CpuType
Definition: cpu.c:25
NTSTATUS NTAPI KxSaveFloatingPointState(OUT PKFLOATING_SAVE FloatingState)
Definition: cpu.c:674
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:578
static const CHAR CmpIntelID[]
Definition: cpu.c:37
static const CHAR CmpAmdID[]
Definition: cpu.c:38
VOID NTAPI KiRestoreProcessorState(_Out_ PKTRAP_FRAME TrapFrame, _Out_ PKEXCEPTION_FRAME ExceptionFrame)
Definition: cpu.c:635
static const CHAR CmpCentaurID[]
Definition: cpu.c:39
ULONG KiDmaIoCoherency
Definition: cpu.c:30
VOID NTAPI KiGetCacheInformation(VOID)
Definition: cpu.c:420
union _CPU_SIGNATURE CPU_SIGNATURE
ULONG KeI386CpuStep
Definition: cpu.c:26
long LONG
Definition: pedump.c:60
unsigned short USHORT
Definition: pedump.c:61
#define CONTEXT_ALL
#define STATUS_SUCCESS
Definition: shellext.h:65
ULONG ContextFlags
Definition: nt_native.h:1426
USHORT Limit
Definition: ketypes.h:449
ULONG SecondLevelCacheSize
Definition: ketypes.h:980
UCHAR CpuVendor
Definition: ketypes.h:693
UCHAR VendorString[13]
Definition: ketypes.h:890
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:759
ULONG InitialApicId
Definition: ketypes.h:710
KPROCESSOR_STATE ProcessorState
Definition: ketypes.h:672
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:624
CONTEXT ContextFrame
Definition: ketypes.h:625
ULONG64 KernelDr1
Definition: ketypes.h:595
ULONG64 MsrLStar
Definition: ketypes.h:614
ULONG64 KernelDr2
Definition: ketypes.h:596
ULONG64 KernelDr0
Definition: ketypes.h:594
KDESCRIPTOR Gdtr
Definition: ketypes.h:600
ULONG64 MsrGsBase
Definition: ketypes.h:611
KDESCRIPTOR Idtr
Definition: ketypes.h:601
ULONG64 MsrCStar
Definition: ketypes.h:615
ULONG64 KernelDr7
Definition: ketypes.h:599
ULONG64 KernelDr6
Definition: ketypes.h:598
ULONG64 MsrSyscallMask
Definition: ketypes.h:616
ULONG64 KernelDr3
Definition: ketypes.h:597
ULONG64 MsrGsSwap
Definition: ketypes.h:612
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
struct CPUID_AMD_SVM_FEATURES_EDX::@3820 Bits
CPUID_AMD_SVM_FEATURES_EDX Edx
Definition: Cpuid.h:206
struct CPUID_EXTENDED_CPU_SIG_REGS::@3817 Intel
struct CPUID_EXTENDED_CPU_SIG_REGS::@3818 Amd
struct CPUID_EXTENDED_STATE_SUB_LEAF_EAX::@3915 Bits
CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax
Definition: Cpuid.h:107
struct CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::@3905 Bits
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx
Definition: Cpuid.h:80
struct CPUID_THERMAL_POWER_MANAGEMENT_REGS::@3808 Undoc
struct MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER::@3952 Bits
struct MSR_IA32_VMX_PROCBASED_CTLS_REGISTER::@3951 Bits
ULONG Ebx
Definition: ketypes.h:391
ULONG Eax
Definition: ketypes.h:390
UINT32 AsUINT32[4]
Definition: ketypes.h:387
ULONG Ecx
Definition: ketypes.h:392
ULONG Edx
Definition: ketypes.h:393
ULONG Unused
Definition: cpu.c:48
ULONG ExtendedFamily
Definition: cpu.c:50
ULONG Model
Definition: cpu.c:46
ULONG Unused2
Definition: cpu.c:51
ULONG Family
Definition: cpu.c:47
ULONG AsULONG
Definition: cpu.c:53
ULONG Step
Definition: cpu.c:45
ULONG ExtendedModel
Definition: cpu.c:49
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:778
unsigned char UCHAR
Definition: xmlstorage.h:181
char CHAR
Definition: xmlstorage.h:175
void _mm_setcsr(unsigned int a)
Definition: xmmintrin.h:542
unsigned int _mm_getcsr(void)
Definition: xmmintrin.h:535