ReactOS 0.4.15-dev-6644-g539123c
cpu.c
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1/*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/amd64/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
7 * Timo Kreuzer (timo.kreuzer@reactos.org)
8 */
9
10/* INCLUDES *****************************************************************/
11
12#include <ntoskrnl.h>
13#define NDEBUG
14#include <debug.h>
15
16/* GLOBALS *******************************************************************/
17
18/* The Boot TSS */
20
21/* CPU Features and Flags */
29
30/* Flush data */
32
33/* CPU Signatures */
34static const CHAR CmpIntelID[] = "GenuineIntel";
35static const CHAR CmpAmdID[] = "AuthenticAMD";
36static const CHAR CmpCentaurID[] = "CentaurHauls";
37
38typedef union _CPU_SIGNATURE
39{
40 struct
41 {
49 };
52
53/* FUNCTIONS *****************************************************************/
54
58{
59 PKPRCB Prcb = KeGetCurrentPrcb();
60 CPU_INFO CpuInfo;
61
62 /* Get the Vendor ID and null-terminate it */
63 KiCpuId(&CpuInfo, 0);
64
65 /* Copy it to the PRCB and null-terminate it */
66 *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
67 *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
68 *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
69 Prcb->VendorString[12] = 0;
70
71 /* Now check the CPU Type */
73 {
74 Prcb->CpuVendor = CPU_INTEL;
75 }
76 else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
77 {
78 Prcb->CpuVendor = CPU_AMD;
79 }
80 else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
81 {
82 DPRINT1("VIA CPUs not fully supported\n");
83 Prcb->CpuVendor = CPU_VIA;
84 }
85 else
86 {
87 /* Invalid CPU */
88 DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
89 Prcb->CpuVendor = CPU_UNKNOWN;
90 }
91
92 return Prcb->CpuVendor;
93}
94
95VOID
98{
99 CPU_INFO CpuInfo;
100 CPU_SIGNATURE CpuSignature;
101 BOOLEAN ExtendModel;
102 ULONG Stepping, Type, Vendor;
103
104 /* This initializes Prcb->CpuVendor */
105 Vendor = KiGetCpuVendor();
106
107 /* Do CPUID 1 now */
108 KiCpuId(&CpuInfo, 1);
109
110 /*
111 * Get the Stepping and Type. The stepping contains both the
112 * Model and the Step, while the Type contains the returned Family.
113 *
114 * For the stepping, we convert this: zzzzzzxy into this: x0y
115 */
116 CpuSignature.AsULONG = CpuInfo.Eax;
117 Stepping = CpuSignature.Model;
118 ExtendModel = (CpuSignature.Family == 15);
119#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
120 if (CpuSignature.Family == 6)
121 {
122 ExtendModel |= (Vendor == CPU_INTEL);
123#if (NTDDI_VERSION >= NTDDI_WIN8)
124 ExtendModel |= (Vendor == CPU_CENTAUR);
125#endif
126 }
127#endif
128 if (ExtendModel)
129 {
130 /* Add ExtendedModel to distinguish from non-extended values. */
131 Stepping |= (CpuSignature.ExtendedModel << 4);
132 }
133 Stepping = (Stepping << 8) | CpuSignature.Step;
134 Type = CpuSignature.Family;
135 if (CpuSignature.Family == 15)
136 {
137 /* Add ExtendedFamily to distinguish from non-extended values.
138 * It must not be larger than 0xF0 to avoid overflow. */
139 Type += min(CpuSignature.ExtendedFamily, 0xF0);
140 }
141
142 /* Save them in the PRCB */
143 KeGetCurrentPrcb()->CpuID = TRUE;
144 KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
145 KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
146}
147
148ULONG
149NTAPI
151{
152 PKPRCB Prcb = KeGetCurrentPrcb();
153 ULONG Vendor;
154 ULONG FeatureBits = KF_WORKING_PTE;
155 CPU_INFO CpuInfo;
156
157 /* Get the Vendor ID */
158 Vendor = Prcb->CpuVendor;
159
160 /* Make sure we got a valid vendor ID at least. */
161 if (!Vendor) return FeatureBits;
162
163 /* Get the CPUID Info. */
164 KiCpuId(&CpuInfo, 1);
165
166 /* Set the initial APIC ID */
167 Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
168
169 /* Convert all CPUID Feature bits into our format */
170 if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4;
171 if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
172 if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC;
173 if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B;
174 if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL;
175 if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR;
176 if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
177 if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV;
178 if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT;
179 if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS;
180 if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX;
181 if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR;
182 if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI;
183 if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64;
184
185 if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3;
186 //if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR;
187 //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP;
188 if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B;
189 //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41;
190 //if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT;
191 if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE;
192
193 /* Check if the CPU has hyper-threading */
194 if (CpuInfo.Edx & X86_FEATURE_HT)
195 {
196 /* Set the number of logical CPUs */
197 Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
199 {
200 /* We're on dual-core */
202 }
203 }
204 else
205 {
206 /* We only have a single CPU */
208 }
209
210 /* Check extended cpuid features */
211 KiCpuId(&CpuInfo, 0x80000000);
212 if ((CpuInfo.Eax & 0xffffff00) == 0x80000000)
213 {
214 /* Check if CPUID 0x80000001 is supported */
215 if (CpuInfo.Eax >= 0x80000001)
216 {
217 /* Check which extended features are available. */
218 KiCpuId(&CpuInfo, 0x80000001);
219
220 /* Check if NX-bit is supported */
221 if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT;
222
223 /* Now handle each features for each CPU Vendor */
224 switch (Vendor)
225 {
226 case CPU_AMD:
227 if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW;
228 break;
229 }
230 }
231 }
232
233 /* Return the Feature Bits */
234 return FeatureBits;
235}
236
237#if DBG
238VOID
239KiReportCpuFeatures(IN PKPRCB Prcb)
240{
241 ULONG CpuFeatures = 0;
242 CPU_INFO CpuInfo;
243
244 if (Prcb->CpuVendor)
245 {
246 KiCpuId(&CpuInfo, 1);
247 CpuFeatures = CpuInfo.Edx;
248 }
249
250 DPRINT1("Supported CPU features: ");
251
252#define print_kf_bit(kf_value) if (Prcb->FeatureBits & kf_value) DbgPrint(#kf_value " ")
253 print_kf_bit(KF_V86_VIS);
254 print_kf_bit(KF_RDTSC);
255 print_kf_bit(KF_CR4);
256 print_kf_bit(KF_CMOV);
257 print_kf_bit(KF_GLOBAL_PAGE);
258 print_kf_bit(KF_LARGE_PAGE);
259 print_kf_bit(KF_MTRR);
260 print_kf_bit(KF_CMPXCHG8B);
261 print_kf_bit(KF_CMPXCHG16B);
262 print_kf_bit(KF_MMX);
263 print_kf_bit(KF_WORKING_PTE);
264 print_kf_bit(KF_PAT);
265 print_kf_bit(KF_FXSR);
266 print_kf_bit(KF_FAST_SYSCALL);
267 print_kf_bit(KF_XMMI);
268 print_kf_bit(KF_3DNOW);
269 print_kf_bit(KF_XMMI64);
270 print_kf_bit(KF_DTS);
271 print_kf_bit(KF_NX_BIT);
272 print_kf_bit(KF_NX_DISABLED);
273 print_kf_bit(KF_NX_ENABLED);
274 print_kf_bit(KF_SSE3);
275 //print_kf_bit(KF_SSE3SUP);
276 //print_kf_bit(KF_SSE41);
277 //print_kf_bit(KF_MONITOR);
278 //print_kf_bit(KF_POPCNT);
279 print_kf_bit(KF_XSTATE);
280#undef print_kf_bit
281
282#define print_cf(cpu_flag) if (CpuFeatures & cpu_flag) DbgPrint(#cpu_flag " ")
283 print_cf(X86_FEATURE_PAE);
284 print_cf(X86_FEATURE_HT);
285#undef print_cf
286
287 DbgPrint("\n");
288}
289#endif // DBG
290
291VOID
292NTAPI
294{
295 PKIPCR Pcr = (PKIPCR)KeGetPcr();
296 ULONG Vendor;
297 ULONG CacheRequests = 0, i;
298 ULONG CurrentRegister;
299 UCHAR RegisterByte;
300 BOOLEAN FirstPass = TRUE;
301 CPU_INFO CpuInfo;
302
303 /* Set default L2 size */
304 Pcr->SecondLevelCacheSize = 0;
305
306 /* Get the Vendor ID and make sure we support CPUID */
307 Vendor = KiGetCpuVendor();
308 if (!Vendor) return;
309
310 /* Check the Vendor ID */
311 switch (Vendor)
312 {
313 /* Handle Intel case */
314 case CPU_INTEL:
315
316 /*Check if we support CPUID 2 */
317 KiCpuId(&CpuInfo, 0);
318 if (CpuInfo.Eax >= 2)
319 {
320 /* We need to loop for the number of times CPUID will tell us to */
321 do
322 {
323 /* Do the CPUID call */
324 KiCpuId(&CpuInfo, 2);
325
326 /* Check if it was the first call */
327 if (FirstPass)
328 {
329 /*
330 * The number of times to loop is the first byte. Read
331 * it and then destroy it so we don't get confused.
332 */
333 CacheRequests = CpuInfo.Eax & 0xFF;
334 CpuInfo.Eax &= 0xFFFFFF00;
335
336 /* Don't go over this again */
337 FirstPass = FALSE;
338 }
339
340 /* Loop all 4 registers */
341 for (i = 0; i < 4; i++)
342 {
343 /* Get the current register */
344 CurrentRegister = CpuInfo.AsUINT32[i];
345
346 /*
347 * If the upper bit is set, then this register should
348 * be skipped.
349 */
350 if (CurrentRegister & 0x80000000) continue;
351
352 /* Keep looping for every byte inside this register */
353 while (CurrentRegister)
354 {
355 /* Read a byte, skip a byte. */
356 RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
357 CurrentRegister >>= 8;
358 if (!RegisterByte) continue;
359
360 /*
361 * Valid values are from 0x40 (0 bytes) to 0x49
362 * (32MB), or from 0x80 to 0x89 (same size but
363 * 8-way associative.
364 */
365 if (((RegisterByte > 0x40) &&
366 (RegisterByte <= 0x49)) ||
367 ((RegisterByte > 0x80) &&
368 (RegisterByte <= 0x89)))
369 {
370 /* Mask out only the first nibble */
371 RegisterByte &= 0x0F;
372
373 /* Set the L2 Cache Size */
374 Pcr->SecondLevelCacheSize = 0x10000 <<
375 RegisterByte;
376 }
377 }
378 }
379 } while (--CacheRequests);
380 }
381 break;
382
383 case CPU_AMD:
384
385 /* Check if we support CPUID 0x80000006 */
386 KiCpuId(&CpuInfo, 0x80000000);
387 if (CpuInfo.Eax >= 6)
388 {
389 /* Get 2nd level cache and tlb size */
390 KiCpuId(&CpuInfo, 0x80000006);
391
392 /* Set the L2 Cache Size */
393 Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
394 }
395 break;
396 }
397}
398
399VOID
400NTAPI
402{
403 /* Flush the TLB by resetting CR3 */
405}
406
407VOID
408NTAPI
410{
411 /* Restore the CR registers */
412 __writecr0(ProcessorState->SpecialRegisters.Cr0);
413// __writecr2(ProcessorState->SpecialRegisters.Cr2);
414 __writecr3(ProcessorState->SpecialRegisters.Cr3);
415 __writecr4(ProcessorState->SpecialRegisters.Cr4);
416 __writecr8(ProcessorState->SpecialRegisters.Cr8);
417
418 /* Restore the DR registers */
419 __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
420 __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
421 __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
422 __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
423 __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
424 __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
425
426 /* Restore GDT, IDT, LDT and TSS */
427 __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
428// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
429// __ltr(&ProcessorState->SpecialRegisters.Tr);
430 __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
431
432 _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
433// ProcessorState->SpecialRegisters.DebugControl
434// ProcessorState->SpecialRegisters.LastBranchToRip
435// ProcessorState->SpecialRegisters.LastBranchFromRip
436// ProcessorState->SpecialRegisters.LastExceptionToRip
437// ProcessorState->SpecialRegisters.LastExceptionFromRip
438
439 /* Restore MSRs */
446
447}
448
449VOID
450NTAPI
452{
453 /* Save the CR registers */
454 ProcessorState->SpecialRegisters.Cr0 = __readcr0();
455 ProcessorState->SpecialRegisters.Cr2 = __readcr2();
456 ProcessorState->SpecialRegisters.Cr3 = __readcr3();
457 ProcessorState->SpecialRegisters.Cr4 = __readcr4();
458 ProcessorState->SpecialRegisters.Cr8 = __readcr8();
459
460 /* Save the DR registers */
461 ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
462 ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
463 ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
464 ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
465 ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
466 ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
467
468 /* Save GDT, IDT, LDT and TSS */
469 __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
470 __sldt(&ProcessorState->SpecialRegisters.Ldtr);
471 __str(&ProcessorState->SpecialRegisters.Tr);
472 __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
473
474 ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
475// ProcessorState->SpecialRegisters.DebugControl =
476// ProcessorState->SpecialRegisters.LastBranchToRip =
477// ProcessorState->SpecialRegisters.LastBranchFromRip =
478// ProcessorState->SpecialRegisters.LastExceptionToRip =
479// ProcessorState->SpecialRegisters.LastExceptionFromRip =
480
481 /* Save MSRs */
482 ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
483 ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
484 ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
485 ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
486 ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
487 ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
488}
489
490VOID
491NTAPI
493 IN BOOLEAN AllProcessors)
494{
496
497 // FIXME: halfplemented
498 /* Raise the IRQL for the TB Flush */
500
501 /* Flush the TB for the Current CPU, and update the flush stamp */
503
504 /* Update the flush stamp and return to original IRQL */
507
508}
509
511NTAPI
513{
514 PAGED_CODE();
515
516 /* Simply return the number of active processors */
517 return KeActiveProcessors;
518}
519
521NTAPI
523{
524 UNREFERENCED_PARAMETER(FloatingState);
525 return STATUS_SUCCESS;
526}
527
529NTAPI
531{
532 UNREFERENCED_PARAMETER(FloatingState);
533 return STATUS_SUCCESS;
534}
535
537NTAPI
539{
540 /* Invalidate all caches */
541 __wbinvd();
542 return TRUE;
543}
544
545/*
546 * @implemented
547 */
548ULONG
549NTAPI
551{
552 /* Return the global variable */
553 return KeLargestCacheLine;
554}
555
556/*
557 * @implemented
558 */
559VOID
562{
563 /* Capture the context */
564 RtlCaptureContext(&State->ContextFrame);
565
566 /* Capture the control state */
568}
569
570/*
571 * @implemented
572 */
573VOID
574NTAPI
576{
577 /* Save the coherency globally */
578 KiDmaIoCoherency = Coherency;
579}
#define PAGED_CODE()
unsigned char BOOLEAN
Type
Definition: Type.h:7
int strcmp(const char *String1, const char *String2)
Definition: utclib.c:469
#define __cdecl
Definition: accygwin.h:79
@ Invalid
Definition: asmpp.cpp:30
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
ULONG_PTR KAFFINITY
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UCHAR KIRQL
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#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
Definition: pic.c:156
#define DbgPrint
Definition: hal.h:12
#define InterlockedExchangeAdd
Definition: interlocked.h:181
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1818
__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2018
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
Definition: intrin_x86.h:1902
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1825
__INTRIN_INLINE unsigned long __readcr0(void)
Definition: intrin_x86.h:1804
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1794
__INTRIN_INLINE unsigned long __readcr2(void)
Definition: intrin_x86.h:1811
__INTRIN_INLINE void __writecr0(unsigned int Data)
Definition: intrin_x86.h:1789
__INTRIN_INLINE void __sidt(void *Destination)
Definition: intrin_x86.h:2023
__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1799
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
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if(dx< 0)
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#define min(a, b)
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FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1084
struct _KIPCR * PKIPCR
@ CPU_VIA
Definition: ketypes.h:46
@ CPU_INTEL
Definition: ketypes.h:45
@ CPU_UNKNOWN
Definition: ketypes.h:43
@ CPU_AMD
Definition: ketypes.h:44
@ CPU_CENTAUR
Definition: ketypes.h:47
#define KF_WORKING_PTE
Definition: ketypes.h:152
#define KF_MTRR
Definition: ketypes.h:149
#define KF_XSTATE
Definition: ketypes.h:164
#define KF_DTS
Definition: ketypes.h:160
#define KF_CMPXCHG16B
Definition: ketypes.h:163
#define KF_NX_DISABLED
Definition: ketypes.h:166
#define KF_CR4
Definition: ketypes.h:145
#define KF_XMMI64
Definition: ketypes.h:159
#define KF_CMOV
Definition: ketypes.h:146
#define KF_CMPXCHG8B
Definition: ketypes.h:150
#define KF_NX_ENABLED
Definition: ketypes.h:167
#define KF_RDTSC
Definition: ketypes.h:144
#define KF_FAST_SYSCALL
Definition: ketypes.h:155
#define KF_3DNOW
Definition: ketypes.h:157
#define KF_NX_BIT
Definition: ketypes.h:165
#define KF_FXSR
Definition: ketypes.h:154
#define KF_V86_VIS
Definition: ketypes.h:143
#define KF_LARGE_PAGE
Definition: ketypes.h:148
#define KF_XMMI
Definition: ketypes.h:156
#define KF_MMX
Definition: ketypes.h:151
#define KF_SSE3
Definition: ketypes.h:162
#define KF_PAT
Definition: ketypes.h:153
#define KF_GLOBAL_PAGE
Definition: ketypes.h:147
NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317
#define X86_MSR_CSTAR
Definition: ke.h:75
#define X86_FEATURE_TSC
Definition: ke.h:34
#define X86_FEATURE_HT
Definition: ke.h:47
#define X86_FEATURE_SSE2
Definition: ke.h:46
#define X86_FEATURE_SSE
Definition: ke.h:45
#define X86_FEATURE_PGE
Definition: ke.h:39
#define X86_FEATURE_XSAVE
Definition: ke.h:60
#define X86_FEATURE_DS
Definition: ke.h:42
#define X86_FEATURE_VME
Definition: ke.h:31
#define X86_FEATURE_MMX
Definition: ke.h:43
#define X86_MSR_GSBASE
Definition: ke.h:70
#define X86_FEATURE_PSE
Definition: ke.h:33
#define X86_MSR_LSTAR
Definition: ke.h:74
#define X86_FEATURE_PAE
Definition: ke.h:35
#define X86_FEATURE_SSE3
Definition: ke.h:50
#define X86_FEATURE_PAT
Definition: ke.h:41
#define X86_FEATURE_MTTR
Definition: ke.h:38
#define X86_FEATURE_CMOV
Definition: ke.h:40
#define X86_FEATURE_CX8
Definition: ke.h:36
#define X86_FEATURE_SYSCALL
Definition: ke.h:37
#define X86_MSR_SFMASK
Definition: ke.h:76
#define X86_FEATURE_NX
Definition: ke.h:63
#define X86_FEATURE_FXSR
Definition: ke.h:44
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:71
#define X86_MSR_STAR
Definition: ke.h:73
#define X86_FEATURE_CX16
Definition: ke.h:55
KAFFINITY KeActiveProcessors
Definition: krnlinit.c:23
ULONG NTAPI KeGetRecommendedSharedDataAlignment(VOID)
Definition: cpu.c:550
VOID NTAPI KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:409
ULONG KeI386NpxPresent
Definition: cpu.c:25
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:401
VOID NTAPI KiSetProcessorType(VOID)
Definition: cpu.c:97
ULONG KeI386MachineType
Definition: cpu.c:24
VOID NTAPI KeFlushEntireTb(IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
Definition: cpu.c:492
ULONG KeLargestCacheLine
Definition: cpu.c:26
VOID __cdecl KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
Definition: cpu.c:561
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:28
BOOLEAN NTAPI KeInvalidateAllCaches(VOID)
Definition: cpu.c:538
NTSTATUS NTAPI KxRestoreFloatingPointState(IN PKFLOATING_SAVE FloatingState)
Definition: cpu.c:530
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:57
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:31
VOID NTAPI KeSetDmaIoCoherency(IN ULONG Coherency)
Definition: cpu.c:575
KTSS64 KiBootTss
Definition: cpu.c:19
ULONG KeI386CpuType
Definition: cpu.c:22
NTSTATUS NTAPI KxSaveFloatingPointState(OUT PKFLOATING_SAVE FloatingState)
Definition: cpu.c:522
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:451
static const CHAR CmpIntelID[]
Definition: cpu.c:34
static const CHAR CmpAmdID[]
Definition: cpu.c:35
ULONG NTAPI KiGetFeatureBits(VOID)
Definition: cpu.c:150
static const CHAR CmpCentaurID[]
Definition: cpu.c:36
ULONG KiDmaIoCoherency
Definition: cpu.c:27
VOID NTAPI KiGetCacheInformation(VOID)
Definition: cpu.c:293
union _CPU_SIGNATURE CPU_SIGNATURE
KAFFINITY NTAPI KeQueryActiveProcessors(VOID)
Definition: cpu.c:512
ULONG KeI386CpuStep
Definition: cpu.c:23
long LONG
Definition: pedump.c:60
unsigned short USHORT
Definition: pedump.c:61
#define KeGetPcr()
Definition: ke.h:26
#define STATUS_SUCCESS
Definition: shellext.h:65
USHORT Limit
Definition: ketypes.h:396
ULONG SecondLevelCacheSize
Definition: ketypes.h:890
UCHAR VendorString[13]
Definition: ketypes.h:806
UCHAR CpuVendor
Definition: ketypes.h:609
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:706
ULONG InitialApicId
Definition: ketypes.h:626
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:539
ULONG64 KernelDr0
Definition: ketypes.h:509
ULONG64 KernelDr7
Definition: ketypes.h:514
ULONG64 MsrLStar
Definition: ketypes.h:529
KDESCRIPTOR Gdtr
Definition: ketypes.h:515
ULONG64 KernelDr2
Definition: ketypes.h:511
ULONG64 MsrGsBase
Definition: ketypes.h:526
KDESCRIPTOR Idtr
Definition: ketypes.h:516
ULONG64 KernelDr1
Definition: ketypes.h:510
ULONG64 MsrCStar
Definition: ketypes.h:530
ULONG64 MsrSyscallMask
Definition: ketypes.h:531
ULONG64 MsrGsSwap
Definition: ketypes.h:527
ULONG64 KernelDr3
Definition: ketypes.h:512
ULONG64 KernelDr6
Definition: ketypes.h:513
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
ULONG Ebx
Definition: ketypes.h:306
ULONG Eax
Definition: ketypes.h:305
UINT32 AsUINT32[4]
Definition: ketypes.h:302
ULONG Ecx
Definition: ketypes.h:307
ULONG Edx
Definition: ketypes.h:308
ULONG Unused
Definition: cpu.c:45
ULONG ExtendedFamily
Definition: cpu.c:47
ULONG Model
Definition: cpu.c:43
ULONG Unused2
Definition: cpu.c:48
ULONG Family
Definition: cpu.c:44
ULONG AsULONG
Definition: cpu.c:50
ULONG Step
Definition: cpu.c:42
ULONG ExtendedModel
Definition: cpu.c:46
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:792
unsigned char UCHAR
Definition: xmlstorage.h:181
char CHAR
Definition: xmlstorage.h:175
void _mm_setcsr(unsigned int a)
Definition: xmmintrin.h:542
unsigned int _mm_getcsr(void)
Definition: xmmintrin.h:535