ReactOS 0.4.16-dev-822-gbcedb53
cpu.c
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1/*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/amd64/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
7 * Timo Kreuzer (timo.kreuzer@reactos.org)
8 */
9
10/* INCLUDES *****************************************************************/
11
12#include <ntoskrnl.h>
13#include <x86x64/Cpuid.h>
14#include <x86x64/Msr.h>
15#define NDEBUG
16#include <debug.h>
17
18/* GLOBALS *******************************************************************/
19
20/* The Boot TSS */
22
23/* CPU Features and Flags */
31
32/* Flush data */
34
35/* CPU Signatures */
36static const CHAR CmpIntelID[] = "GenuineIntel";
37static const CHAR CmpAmdID[] = "AuthenticAMD";
38static const CHAR CmpCentaurID[] = "CentaurHauls";
39
40typedef union _CPU_SIGNATURE
41{
42 struct
43 {
51 };
54
55/* FUNCTIONS *****************************************************************/
56
60{
61 PKPRCB Prcb = KeGetCurrentPrcb();
62 CPU_INFO CpuInfo;
63
64 /* Get the Vendor ID and null-terminate it */
65 KiCpuId(&CpuInfo, 0);
66
67 /* Copy it to the PRCB and null-terminate it */
68 *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
69 *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
70 *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
71 Prcb->VendorString[12] = 0;
72
73 /* Now check the CPU Type */
75 {
76 Prcb->CpuVendor = CPU_INTEL;
77 }
78 else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
79 {
80 Prcb->CpuVendor = CPU_AMD;
81 }
82 else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
83 {
84 DPRINT1("VIA CPUs not fully supported\n");
85 Prcb->CpuVendor = CPU_VIA;
86 }
87 else
88 {
89 /* Invalid CPU */
90 DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
91 Prcb->CpuVendor = CPU_UNKNOWN;
92 }
93
94 return Prcb->CpuVendor;
95}
96
97VOID
100{
101 CPU_INFO CpuInfo;
102 CPU_SIGNATURE CpuSignature;
103 BOOLEAN ExtendModel;
104 ULONG Stepping, Type, Vendor;
105
106 /* This initializes Prcb->CpuVendor */
107 Vendor = KiGetCpuVendor();
108
109 /* Do CPUID 1 now */
110 KiCpuId(&CpuInfo, 1);
111
112 /*
113 * Get the Stepping and Type. The stepping contains both the
114 * Model and the Step, while the Type contains the returned Family.
115 *
116 * For the stepping, we convert this: zzzzzzxy into this: x0y
117 */
118 CpuSignature.AsULONG = CpuInfo.Eax;
119 Stepping = CpuSignature.Model;
120 ExtendModel = (CpuSignature.Family == 15);
121#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
122 if (CpuSignature.Family == 6)
123 {
124 ExtendModel |= (Vendor == CPU_INTEL);
125#if (NTDDI_VERSION >= NTDDI_WIN8)
126 ExtendModel |= (Vendor == CPU_CENTAUR);
127#endif
128 }
129#endif
130 if (ExtendModel)
131 {
132 /* Add ExtendedModel to distinguish from non-extended values. */
133 Stepping |= (CpuSignature.ExtendedModel << 4);
134 }
135 Stepping = (Stepping << 8) | CpuSignature.Step;
136 Type = CpuSignature.Family;
137 if (CpuSignature.Family == 15)
138 {
139 /* Add ExtendedFamily to distinguish from non-extended values.
140 * It must not be larger than 0xF0 to avoid overflow. */
141 Type += min(CpuSignature.ExtendedFamily, 0xF0);
142 }
143
144 /* Save them in the PRCB */
145 KeGetCurrentPrcb()->CpuID = TRUE;
146 KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
147 KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
148}
149
164NTAPI
166{
167 PKPRCB Prcb = KeGetCurrentPrcb();
168 ULONG Vendor;
169 ULONG64 FeatureBits = 0;
172 CPUID_EXTENDED_FUNCTION_REGS extendedFunction;
173
174 /* Get the Vendor ID */
175 Vendor = Prcb->CpuVendor;
176
177 /* Make sure we got a valid vendor ID at least. */
178 if (Vendor == CPU_UNKNOWN) return FeatureBits;
179
180 /* Get signature CPUID for the maximum function */
182
183 /* Get the CPUID Info. */
185
186 /* Set the initial APIC ID */
187 Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId;
188
189 /* Convert all CPUID Feature bits into our format */
190 if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4;
191 if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
192 if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC;
193 if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B;
194 if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL;
195 if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR;
196 if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
197 if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV;
198 if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT;
199 if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS;
200 if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX;
201 if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR;
202 if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI;
203 if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64;
204
205 if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3;
206 if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3;
207 if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B;
208 if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1;
209 if (VersionInfo.Ecx.Bits.SSE4_2) FeatureBits |= KF_SSE4_2;
210 if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE;
211 if (VersionInfo.Ecx.Bits.RDRAND) FeatureBits |= KF_RDRAND;
212
213 /* Check if the CPU has hyper-threading */
214 if (VersionInfo.Edx.Bits.HTT)
215 {
216 /* Set the number of logical CPUs */
218 VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors;
220 {
221 /* We're on dual-core */
223 }
224 }
225 else
226 {
227 /* We only have a single CPU */
229 }
230
231 /* Check if CPUID_THERMAL_POWER_MANAGEMENT (0x06) is supported */
233 {
234 /* Read CPUID_THERMAL_POWER_MANAGEMENT */
237
238 if (PowerInfo.Undoc.Ecx.ACNT2) FeatureBits |= KF_ACNT2;
239 }
240
241 /* Check if CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) is supported */
243 {
244 /* Read CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS */
246 __cpuidex(ExtFlags.AsInt32,
249
250 if (ExtFlags.Ebx.Bits.SMEP) FeatureBits |= KF_SMEP;
251 if (ExtFlags.Ebx.Bits.FSGSBASE) FeatureBits |= KF_RDWRFSGSBASE;
252 if (ExtFlags.Ebx.Bits.SMAP) FeatureBits |= KF_SMAP;
253 }
254
255 /* Check if CPUID_EXTENDED_STATE (0x0D) is supported */
256 if (signature.MaxLeaf >= CPUID_EXTENDED_STATE)
257 {
258 /* Read CPUID_EXTENDED_STATE */
260 __cpuidex(ExtStateSub.AsInt32,
263
264 if (ExtStateSub.Eax.Bits.XSAVEOPT) FeatureBits |= KF_XSAVEOPT;
265 if (ExtStateSub.Eax.Bits.XSAVES) FeatureBits |= KF_XSAVES;
266 }
267
268 /* Check extended cpuid features */
269 __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION);
270 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
271 {
272 /* Check if CPUID_EXTENDED_CPU_SIG (0x80000001) is supported */
273 if (extendedFunction.MaxLeaf >= CPUID_EXTENDED_CPU_SIG)
274 {
275 /* Read CPUID_EXTENDED_CPU_SIG */
278
279 /* Check if NX-bit is supported */
280 if (ExtSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT;
281 if (ExtSig.Intel.Edx.Bits.Page1GB) FeatureBits |= KF_HUGEPAGE;
282 if (ExtSig.Intel.Edx.Bits.RDTSCP) FeatureBits |= KF_RDTSCP;
283
284 /* AMD specific */
285 if (Vendor == CPU_AMD)
286 {
287 if (ExtSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW;
288 }
289 }
290 }
291
292 /* Vendor specific */
293 if (Vendor == CPU_INTEL)
294 {
295 FeatureBits |= KF_GENUINE_INTEL;
296
297 /* Check for models that support LBR */
298 if (VersionInfo.Eax.Bits.FamilyId == 6)
299 {
300 if ((VersionInfo.Eax.Bits.Model == 15) ||
301 (VersionInfo.Eax.Bits.Model == 22) ||
302 (VersionInfo.Eax.Bits.Model == 23) ||
303 (VersionInfo.Eax.Bits.Model == 26))
304 {
305 FeatureBits |= KF_BRANCH;
306 }
307 }
308
309 /* Check if VMX is available */
310 if (VersionInfo.Ecx.Bits.VMX)
311 {
312 /* Read PROCBASED ctls and check if secondary are allowed */
315 if (ProcBasedCtls.Bits.Allowed1.ActivateSecondaryControls)
316 {
317 /* Read secondary controls and check if EPT is allowed */
320 if (ProcBasedCtls2.Bits.Allowed1.EPT)
321 FeatureBits |= KF_SLAT;
322 }
323 }
324 }
325 else if (Vendor == CPU_AMD)
326 {
327 FeatureBits |= KF_AUTHENTICAMD;
328 FeatureBits |= KF_BRANCH;
329
330 /* Check extended cpuid features */
331 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
332 {
333 /* Check if CPUID_AMD_SVM_FEATURES (0x8000000A) is supported */
334 if (extendedFunction.MaxLeaf >= CPUID_AMD_SVM_FEATURES)
335 {
336 /* Read CPUID_AMD_SVM_FEATURES and check if Nested Paging is available */
337 CPUID_AMD_SVM_FEATURES_REGS SvmFeatures;
339 if (SvmFeatures.Edx.Bits.NP) FeatureBits |= KF_SLAT;
340 }
341 }
342 }
343
344 /* Return the Feature Bits */
345 return FeatureBits;
346}
347
348#if DBG
349VOID
350KiReportCpuFeatures(IN PKPRCB Prcb)
351{
352 ULONG CpuFeatures = 0;
353 CPU_INFO CpuInfo;
354
355 if (Prcb->CpuVendor)
356 {
357 KiCpuId(&CpuInfo, 1);
358 CpuFeatures = CpuInfo.Edx;
359 }
360
361 DPRINT1("Supported CPU features: ");
362
363#define print_kf_bit(kf_value) if (Prcb->FeatureBits & kf_value) DbgPrint(#kf_value " ")
364 print_kf_bit(KF_SMEP);
365 print_kf_bit(KF_RDTSC);
366 print_kf_bit(KF_CR4);
367 print_kf_bit(KF_CMOV);
368 print_kf_bit(KF_GLOBAL_PAGE);
369 print_kf_bit(KF_LARGE_PAGE);
370 print_kf_bit(KF_MTRR);
371 print_kf_bit(KF_CMPXCHG8B);
372 print_kf_bit(KF_MMX);
373 print_kf_bit(KF_DTS);
374 print_kf_bit(KF_PAT);
375 print_kf_bit(KF_FXSR);
376 print_kf_bit(KF_FAST_SYSCALL);
377 print_kf_bit(KF_XMMI);
378 print_kf_bit(KF_3DNOW);
379 print_kf_bit(KF_XSAVEOPT);
380 print_kf_bit(KF_XMMI64);
381 print_kf_bit(KF_BRANCH);
382 print_kf_bit(KF_00040000);
383 print_kf_bit(KF_SSE3);
384 print_kf_bit(KF_CMPXCHG16B);
385 print_kf_bit(KF_AUTHENTICAMD);
386 print_kf_bit(KF_ACNT2);
387 print_kf_bit(KF_XSTATE);
388 print_kf_bit(KF_GENUINE_INTEL);
389 print_kf_bit(KF_SLAT);
390 print_kf_bit(KF_VIRT_FIRMWARE_ENABLED);
391 print_kf_bit(KF_RDWRFSGSBASE);
392 print_kf_bit(KF_NX_BIT);
393 print_kf_bit(KF_NX_DISABLED);
394 print_kf_bit(KF_NX_ENABLED);
395 print_kf_bit(KF_RDRAND);
396 print_kf_bit(KF_SMAP);
397 print_kf_bit(KF_RDTSCP);
398 print_kf_bit(KF_HUGEPAGE);
399 print_kf_bit(KF_XSAVES);
400 print_kf_bit(KF_FPU_LEAKAGE);
401 print_kf_bit(KF_CAT);
402 print_kf_bit(KF_CET_SS);
403 print_kf_bit(KF_SSSE3);
404 print_kf_bit(KF_SSE4_1);
405 print_kf_bit(KF_SSE4_2);
406#undef print_kf_bit
407
408#define print_cf(cpu_flag) if (CpuFeatures & cpu_flag) DbgPrint(#cpu_flag " ")
409 print_cf(X86_FEATURE_PAE);
410 print_cf(X86_FEATURE_HT);
411#undef print_cf
412
413 DbgPrint("\n");
414}
415#endif // DBG
416
417VOID
418NTAPI
420{
421 PKIPCR Pcr = (PKIPCR)KeGetPcr();
422 ULONG Vendor;
423 ULONG CacheRequests = 0, i;
424 ULONG CurrentRegister;
425 UCHAR RegisterByte;
426 BOOLEAN FirstPass = TRUE;
427 CPU_INFO CpuInfo;
428
429 /* Set default L2 size */
430 Pcr->SecondLevelCacheSize = 0;
431
432 /* Get the Vendor ID and make sure we support CPUID */
433 Vendor = KiGetCpuVendor();
434 if (!Vendor) return;
435
436 /* Check the Vendor ID */
437 switch (Vendor)
438 {
439 /* Handle Intel case */
440 case CPU_INTEL:
441
442 /*Check if we support CPUID 2 */
443 KiCpuId(&CpuInfo, 0);
444 if (CpuInfo.Eax >= 2)
445 {
446 /* We need to loop for the number of times CPUID will tell us to */
447 do
448 {
449 /* Do the CPUID call */
450 KiCpuId(&CpuInfo, 2);
451
452 /* Check if it was the first call */
453 if (FirstPass)
454 {
455 /*
456 * The number of times to loop is the first byte. Read
457 * it and then destroy it so we don't get confused.
458 */
459 CacheRequests = CpuInfo.Eax & 0xFF;
460 CpuInfo.Eax &= 0xFFFFFF00;
461
462 /* Don't go over this again */
463 FirstPass = FALSE;
464 }
465
466 /* Loop all 4 registers */
467 for (i = 0; i < 4; i++)
468 {
469 /* Get the current register */
470 CurrentRegister = CpuInfo.AsUINT32[i];
471
472 /*
473 * If the upper bit is set, then this register should
474 * be skipped.
475 */
476 if (CurrentRegister & 0x80000000) continue;
477
478 /* Keep looping for every byte inside this register */
479 while (CurrentRegister)
480 {
481 /* Read a byte, skip a byte. */
482 RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
483 CurrentRegister >>= 8;
484 if (!RegisterByte) continue;
485
486 /*
487 * Valid values are from 0x40 (0 bytes) to 0x49
488 * (32MB), or from 0x80 to 0x89 (same size but
489 * 8-way associative.
490 */
491 if (((RegisterByte > 0x40) &&
492 (RegisterByte <= 0x49)) ||
493 ((RegisterByte > 0x80) &&
494 (RegisterByte <= 0x89)))
495 {
496 /* Mask out only the first nibble */
497 RegisterByte &= 0x0F;
498
499 /* Set the L2 Cache Size */
500 Pcr->SecondLevelCacheSize = 0x10000 <<
501 RegisterByte;
502 }
503 }
504 }
505 } while (--CacheRequests);
506 }
507 break;
508
509 case CPU_AMD:
510
511 /* Check if we support CPUID 0x80000006 */
512 KiCpuId(&CpuInfo, 0x80000000);
513 if (CpuInfo.Eax >= 6)
514 {
515 /* Get 2nd level cache and tlb size */
516 KiCpuId(&CpuInfo, 0x80000006);
517
518 /* Set the L2 Cache Size */
519 Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
520 }
521 break;
522 }
523}
524
525VOID
526NTAPI
528{
529 /* Flush the TLB by resetting CR3 */
531}
532
533VOID
534NTAPI
536{
537 /* Restore the CR registers */
538 __writecr0(ProcessorState->SpecialRegisters.Cr0);
539// __writecr2(ProcessorState->SpecialRegisters.Cr2);
540 __writecr3(ProcessorState->SpecialRegisters.Cr3);
541 __writecr4(ProcessorState->SpecialRegisters.Cr4);
542 __writecr8(ProcessorState->SpecialRegisters.Cr8);
543
544 /* Restore the DR registers */
545 __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
546 __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
547 __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
548 __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
549 __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
550 __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
551
552 /* Restore GDT, IDT, LDT and TSS */
553 __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
554// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
555// __ltr(&ProcessorState->SpecialRegisters.Tr);
556 __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
557
558 _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
559// ProcessorState->SpecialRegisters.DebugControl
560// ProcessorState->SpecialRegisters.LastBranchToRip
561// ProcessorState->SpecialRegisters.LastBranchFromRip
562// ProcessorState->SpecialRegisters.LastExceptionToRip
563// ProcessorState->SpecialRegisters.LastExceptionFromRip
564
565 /* Restore MSRs */
572
573}
574
575VOID
576NTAPI
578{
579 /* Save the CR registers */
580 ProcessorState->SpecialRegisters.Cr0 = __readcr0();
581 ProcessorState->SpecialRegisters.Cr2 = __readcr2();
582 ProcessorState->SpecialRegisters.Cr3 = __readcr3();
583 ProcessorState->SpecialRegisters.Cr4 = __readcr4();
584 ProcessorState->SpecialRegisters.Cr8 = __readcr8();
585
586 /* Save the DR registers */
587 ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
588 ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
589 ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
590 ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
591 ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
592 ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
593
594 /* Save GDT, IDT, LDT and TSS */
595 __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
596 __sldt(&ProcessorState->SpecialRegisters.Ldtr);
597 __str(&ProcessorState->SpecialRegisters.Tr);
598 __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
599
600 ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
601// ProcessorState->SpecialRegisters.DebugControl =
602// ProcessorState->SpecialRegisters.LastBranchToRip =
603// ProcessorState->SpecialRegisters.LastBranchFromRip =
604// ProcessorState->SpecialRegisters.LastExceptionToRip =
605// ProcessorState->SpecialRegisters.LastExceptionFromRip =
606
607 /* Save MSRs */
608 ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
609 ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
610 ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
611 ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
612 ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
613 ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
614}
615
616VOID
617NTAPI
619 _In_ PKTRAP_FRAME TrapFrame,
620 _In_ PKEXCEPTION_FRAME ExceptionFrame)
621{
622 PKPRCB Prcb = KeGetCurrentPrcb();
623
624 /* Save all context */
626 KeTrapFrameToContext(TrapFrame, ExceptionFrame, &Prcb->ProcessorState.ContextFrame);
627
628 /* Save control registers */
630}
631
632VOID
633NTAPI
635 _Out_ PKTRAP_FRAME TrapFrame,
636 _Out_ PKEXCEPTION_FRAME ExceptionFrame)
637{
638 PKPRCB Prcb = KeGetCurrentPrcb();
639
640 /* Restore all context */
642 ExceptionFrame,
643 TrapFrame,
645 TrapFrame->PreviousMode);
646
647 /* Restore control registers */
649}
650
651VOID
652NTAPI
654 IN BOOLEAN AllProcessors)
655{
657
658 // FIXME: halfplemented
659 /* Raise the IRQL for the TB Flush */
661
662 /* Flush the TB for the Current CPU, and update the flush stamp */
664
665 /* Update the flush stamp and return to original IRQL */
668
669}
670
672NTAPI
674{
675 UNREFERENCED_PARAMETER(FloatingState);
676 return STATUS_SUCCESS;
677}
678
680NTAPI
682{
683 UNREFERENCED_PARAMETER(FloatingState);
684 return STATUS_SUCCESS;
685}
686
688NTAPI
690{
691 /* Invalidate all caches */
692 __wbinvd();
693 return TRUE;
694}
695
696/*
697 * @implemented
698 */
699ULONG
700NTAPI
702{
703 /* Return the global variable */
704 return KeLargestCacheLine;
705}
706
707/*
708 * @implemented
709 */
710VOID
713{
714 /* Capture the context */
715 RtlCaptureContext(&State->ContextFrame);
716
717 /* Capture the control state */
719}
720
721/*
722 * @implemented
723 */
724VOID
725NTAPI
727{
728 /* Save the coherency globally */
729 KiDmaIoCoherency = Coherency;
730}
#define MSR_IA32_VMX_PROCBASED_CTLS
#define MSR_IA32_VMX_PROCBASED_CTLS2
#define CPUID_AMD_SVM_FEATURES
Definition: Cpuid.h:146
#define CPUID_EXTENDED_FUNCTION
Definition: Cpuid.h:3745
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
Definition: Cpuid.h:1301
#define CPUID_SIGNATURE
Definition: Cpuid.h:45
#define CPUID_VERSION_INFO
Definition: Cpuid.h:81
#define CPUID_EXTENDED_STATE
Definition: Cpuid.h:1918
#define CPUID_THERMAL_POWER_MANAGEMENT
Definition: Cpuid.h:1114
#define CPUID_EXTENDED_STATE_SUB_LEAF
Definition: Cpuid.h:2033
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
Definition: Cpuid.h:1306
#define CPUID_EXTENDED_CPU_SIG
Definition: Cpuid.h:3768
unsigned char BOOLEAN
Type
Definition: Type.h:7
int strcmp(const char *String1, const char *String2)
Definition: utclib.c:469
#define __cdecl
Definition: accygwin.h:79
@ Invalid
Definition: asmpp.cpp:30
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
OSVERSIONINFOW VersionInfo
Definition: wkssvc.c:40
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
UCHAR KIRQL
Definition: env_spec_w32.h:591
#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
Definition: pic.c:156
#define DbgPrint
Definition: hal.h:12
#define InterlockedExchangeAdd
Definition: interlocked.h:181
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
PPC_QUAL void __cpuid(int CPUInfo[], const int InfoType)
Definition: intrin_ppc.h:682
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1832
__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2041
__INTRIN_INLINE void __cpuidex(int CPUInfo[4], int InfoType, int ECXValue)
Definition: intrin_x86.h:1662
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
Definition: intrin_x86.h:1916
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1839
__INTRIN_INLINE unsigned long __readcr0(void)
Definition: intrin_x86.h:1818
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1808
__INTRIN_INLINE unsigned long __readcr2(void)
Definition: intrin_x86.h:1825
__INTRIN_INLINE void __writecr0(unsigned int Data)
Definition: intrin_x86.h:1803
__INTRIN_INLINE void __sidt(void *Destination)
Definition: intrin_x86.h:2046
__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1813
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
Definition: intrin_x86.h:1949
if(dx< 0)
Definition: linetemp.h:194
unsigned __int64 ULONG64
Definition: imports.h:198
#define min(a, b)
Definition: monoChain.cc:55
#define KF_SSE4_2
Definition: ketypes.h:74
#define KF_SMEP
Definition: ketypes.h:31
#define KF_FPU_LEAKAGE
Definition: ketypes.h:69
#define KF_SSSE3
Definition: ketypes.h:72
#define KF_MTRR
Definition: ketypes.h:37
#define KF_HUGEPAGE
Definition: ketypes.h:67
#define KF_XSTATE
Definition: ketypes.h:55
#define KF_DTS
Definition: ketypes.h:40
#define KF_VIRT_FIRMWARE_ENABLED
Definition: ketypes.h:59
#define KF_CMPXCHG16B
Definition: ketypes.h:52
#define KF_CET_SS
Definition: ketypes.h:71
#define KF_NX_DISABLED
Definition: ketypes.h:62
#define KF_CR4
Definition: ketypes.h:33
#define KF_AUTHENTICAMD
Definition: ketypes.h:53
#define KF_XMMI64
Definition: ketypes.h:48
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1182
#define KF_CMOV
Definition: ketypes.h:34
#define KF_ACNT2
Definition: ketypes.h:54
#define KF_SSE4_1
Definition: ketypes.h:73
#define KF_RDWRFSGSBASE
Definition: ketypes.h:60
#define KF_00040000
Definition: ketypes.h:50
#define KF_CMPXCHG8B
Definition: ketypes.h:38
#define KF_NX_ENABLED
Definition: ketypes.h:63
#define KF_RDTSC
Definition: ketypes.h:32
#define KF_FAST_SYSCALL
Definition: ketypes.h:43
#define KF_3DNOW
Definition: ketypes.h:45
struct _KIPCR * PKIPCR
#define KF_NX_BIT
Definition: ketypes.h:61
#define KF_FXSR
Definition: ketypes.h:42
#define KF_RDRAND
Definition: ketypes.h:64
#define KF_CAT
Definition: ketypes.h:70
@ CPU_VIA
Definition: ketypes.h:96
@ CPU_INTEL
Definition: ketypes.h:95
@ CPU_UNKNOWN
Definition: ketypes.h:93
@ CPU_AMD
Definition: ketypes.h:94
#define KF_XSAVES
Definition: ketypes.h:68
#define KF_LARGE_PAGE
Definition: ketypes.h:36
#define KF_BRANCH
Definition: ketypes.h:49
#define KF_GENUINE_INTEL
Definition: ketypes.h:56
#define KF_XMMI
Definition: ketypes.h:44
#define KF_MMX
Definition: ketypes.h:39
#define KF_XSAVEOPT
Definition: ketypes.h:47
#define KF_SSE3
Definition: ketypes.h:51
#define KF_SLAT
Definition: ketypes.h:58
#define KF_PAT
Definition: ketypes.h:41
#define KF_RDTSCP
Definition: ketypes.h:66
#define KF_GLOBAL_PAGE
Definition: ketypes.h:35
#define KF_SMAP
Definition: ketypes.h:65
#define KeGetPcr()
Definition: ketypes.h:81
@ CPU_CENTAUR
Definition: ketypes.h:95
NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)
#define _Out_
Definition: no_sal2.h:160
#define _In_
Definition: no_sal2.h:158
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:325
#define X86_MSR_CSTAR
Definition: ke.h:75
#define X86_FEATURE_HT
Definition: ke.h:47
#define X86_MSR_GSBASE
Definition: ke.h:70
#define X86_MSR_LSTAR
Definition: ke.h:74
#define X86_FEATURE_PAE
Definition: ke.h:35
#define X86_MSR_SFMASK
Definition: ke.h:76
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:71
#define X86_MSR_STAR
Definition: ke.h:73
VOID NTAPI KeTrapFrameToContext(IN PKTRAP_FRAME TrapFrame, IN PKEXCEPTION_FRAME ExceptionFrame, IN OUT PCONTEXT Context)
Definition: context.c:169
VOID NTAPI KeContextToTrapFrame(PCONTEXT Context, PKEXCEPTION_FRAME ExeptionFrame, PKTRAP_FRAME TrapFrame, ULONG ContextFlags, KPROCESSOR_MODE PreviousMode)
ULONG NTAPI KeGetRecommendedSharedDataAlignment(VOID)
Definition: cpu.c:701
VOID NTAPI KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:535
ULONG KeI386NpxPresent
Definition: cpu.c:27
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:527
VOID NTAPI KiSetProcessorType(VOID)
Definition: cpu.c:99
ULONG KeI386MachineType
Definition: cpu.c:26
VOID NTAPI KeFlushEntireTb(IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
Definition: cpu.c:653
ULONG KeLargestCacheLine
Definition: cpu.c:28
VOID __cdecl KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
Definition: cpu.c:712
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:30
ULONG64 NTAPI KiGetFeatureBits(VOID)
Evaluates the KeFeatureFlag bits for the current CPU.
Definition: cpu.c:165
BOOLEAN NTAPI KeInvalidateAllCaches(VOID)
Definition: cpu.c:689
NTSTATUS NTAPI KxRestoreFloatingPointState(IN PKFLOATING_SAVE FloatingState)
Definition: cpu.c:681
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:59
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:33
VOID NTAPI KiSaveProcessorState(_In_ PKTRAP_FRAME TrapFrame, _In_ PKEXCEPTION_FRAME ExceptionFrame)
Definition: cpu.c:618
VOID NTAPI KeSetDmaIoCoherency(IN ULONG Coherency)
Definition: cpu.c:726
KTSS64 KiBootTss
Definition: cpu.c:21
ULONG KeI386CpuType
Definition: cpu.c:24
NTSTATUS NTAPI KxSaveFloatingPointState(OUT PKFLOATING_SAVE FloatingState)
Definition: cpu.c:673
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:577
static const CHAR CmpIntelID[]
Definition: cpu.c:36
static const CHAR CmpAmdID[]
Definition: cpu.c:37
VOID NTAPI KiRestoreProcessorState(_Out_ PKTRAP_FRAME TrapFrame, _Out_ PKEXCEPTION_FRAME ExceptionFrame)
Definition: cpu.c:634
static const CHAR CmpCentaurID[]
Definition: cpu.c:38
ULONG KiDmaIoCoherency
Definition: cpu.c:29
VOID NTAPI KiGetCacheInformation(VOID)
Definition: cpu.c:419
union _CPU_SIGNATURE CPU_SIGNATURE
ULONG KeI386CpuStep
Definition: cpu.c:25
long LONG
Definition: pedump.c:60
unsigned short USHORT
Definition: pedump.c:61
#define CONTEXT_ALL
#define STATUS_SUCCESS
Definition: shellext.h:65
ULONG ContextFlags
Definition: nt_native.h:1426
USHORT Limit
Definition: ketypes.h:449
ULONG SecondLevelCacheSize
Definition: ketypes.h:980
UCHAR CpuVendor
Definition: ketypes.h:693
UCHAR VendorString[13]
Definition: ketypes.h:890
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:759
ULONG InitialApicId
Definition: ketypes.h:710
KPROCESSOR_STATE ProcessorState
Definition: ketypes.h:672
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:624
CONTEXT ContextFrame
Definition: ketypes.h:625
ULONG64 KernelDr1
Definition: ketypes.h:595
ULONG64 MsrLStar
Definition: ketypes.h:614
ULONG64 KernelDr2
Definition: ketypes.h:596
ULONG64 KernelDr0
Definition: ketypes.h:594
KDESCRIPTOR Gdtr
Definition: ketypes.h:600
ULONG64 MsrGsBase
Definition: ketypes.h:611
KDESCRIPTOR Idtr
Definition: ketypes.h:601
ULONG64 MsrCStar
Definition: ketypes.h:615
ULONG64 KernelDr7
Definition: ketypes.h:599
ULONG64 KernelDr6
Definition: ketypes.h:598
ULONG64 MsrSyscallMask
Definition: ketypes.h:616
ULONG64 KernelDr3
Definition: ketypes.h:597
ULONG64 MsrGsSwap
Definition: ketypes.h:612
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
#define OUT
Definition: typedefs.h:40
char * PCHAR
Definition: typedefs.h:51
struct CPUID_AMD_SVM_FEATURES_EDX::@3745 Bits
CPUID_AMD_SVM_FEATURES_EDX Edx
Definition: Cpuid.h:206
struct CPUID_EXTENDED_CPU_SIG_REGS::@3743 Amd
struct CPUID_EXTENDED_CPU_SIG_REGS::@3742 Intel
struct CPUID_EXTENDED_STATE_SUB_LEAF_EAX::@3840 Bits
CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax
Definition: Cpuid.h:107
struct CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::@3830 Bits
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx
Definition: Cpuid.h:80
struct CPUID_THERMAL_POWER_MANAGEMENT_REGS::@3733 Undoc
struct MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER::@3877 Bits
struct MSR_IA32_VMX_PROCBASED_CTLS_REGISTER::@3876 Bits
ULONG Ebx
Definition: ketypes.h:391
ULONG Eax
Definition: ketypes.h:390
UINT32 AsUINT32[4]
Definition: ketypes.h:387
ULONG Ecx
Definition: ketypes.h:392
ULONG Edx
Definition: ketypes.h:393
ULONG Unused
Definition: cpu.c:47
ULONG ExtendedFamily
Definition: cpu.c:49
ULONG Model
Definition: cpu.c:45
ULONG Unused2
Definition: cpu.c:50
ULONG Family
Definition: cpu.c:46
ULONG AsULONG
Definition: cpu.c:52
ULONG Step
Definition: cpu.c:44
ULONG ExtendedModel
Definition: cpu.c:48
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:778
unsigned char UCHAR
Definition: xmlstorage.h:181
char CHAR
Definition: xmlstorage.h:175
void _mm_setcsr(unsigned int a)
Definition: xmmintrin.h:542
unsigned int _mm_getcsr(void)
Definition: xmmintrin.h:535