ReactOS 0.4.15-dev-8219-ge8b88cf
Cpuid.h
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1/*
2 * PROJECT: ReactOS SDK
3 * LICENSE: MIT (https://spdx.org/licenses/MIT)
4 * PURPOSE: Provides CPUID structure definitions
5 * COPYRIGHT: Copyright 2023 Timo Kreuzer <timo.kreuzer@reactos.org>
6 */
7
8#define CHAR8 char
9
10#include "Intel/Cpuid.h"
11#include "Amd/Cpuid.h"
12
13// CPUID_SIGNATURE (0)
14typedef union
15{
16 INT32 AsInt32[4];
17 struct
18 {
20 CHAR SignatureScrambled[12];
21 };
23
24// CPUID_VERSION_INFO (1)
25typedef union
26{
27 INT32 AsInt32[4];
28 struct
29 {
34 };
36
37// CPUID_EXTENDED_FUNCTION (0x80000000)
38typedef union
39{
40 INT32 AsInt32[4];
41 struct
42 {
47 };
49
50// CPUID_THERMAL_POWER_MANAGEMENT (6)
51typedef union
52{
53 INT32 AsInt32[4];
54 struct
55 {
60 };
61 struct
62 {
65 struct
66 {
68 UINT32 ACNT2 : 1; // See https://en.wikipedia.org/wiki/CPUID
69 } Ecx;
70 } Undoc;
72
73// CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
74typedef union
75{
76 INT32 AsInt32[4];
77 struct
78 {
83 };
85
86// CPUID_EXTENDED_STATE (0x0D)
87// CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
88typedef union
89{
90 INT32 AsInt32[4];
91 struct
92 {
97 };
99
100// CPUID_EXTENDED_STATE (0x0D)
101// CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
102typedef union
103{
104 INT32 AsInt32[4];
105 struct
106 {
108 struct
109 {
110 UINT32 XSaveAreaSize; // The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
111 } Ebx;
113 UINT32 Edx; // Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32] can be set to 1 only if EDX[n] is 1.
114 };
116
117// CPUID_EXTENDED_CPU_SIG (0x80000001)
118typedef union
119{
120 INT32 AsInt32[4];
121 struct
122 {
127 } Intel;
128 struct
129 {
134 } Amd;
136
137
138// Additional AMD specific CPUID:
139// See
140// - AMD64 Architecture Programmer’s Manual Volume 2: System Programming (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf)
141// - http://www.flounder.com/cpuid_explorer2.htm#CPUID(0x8000000A)
142// - https://www.spinics.net/lists/kvm/msg279165.html
143// - https://qemu-devel.nongnu.narkive.com/zgmvxGLq/patch-0-3-svm-feature-support-for-qemu
144// - https://github.com/torvalds/linux/blob/28f20a19294da7df158dfca259d0e2b5866baaf9/arch/x86/include/asm/cpufeatures.h#L361
145
146#define CPUID_AMD_SVM_FEATURES 0x8000000A
147
148typedef union
149{
150 struct
151 {
152 UINT SVMRev : 8; // EAX[7..0]
153 UINT Reserved : 24; // EAX[31..8]
154 } Bits;
155
158
159typedef union
160{
161 struct
162 {
163 UINT32 NP : 1; // EDX[0] Nested paging support
164 UINT32 LbrVirt : 1; // EDX[1] LBR virtualization
165 UINT32 SVML : 1; // EDX[2] SVM Lock
166 UINT32 NRIPS : 1; // EDX[3] Next RIP save on VMEXIT
167 UINT32 TscRateMsr : 1; // EDX[4] MSR based TSC ratio control
168 UINT32 VmcbClean : 1; // EDX[5] VMCB Clean bits support
169 UINT32 FlushByAsid : 1; // EDX[6] Flush by ASID support
170 UINT32 DecodeAssists : 1; // EDX[7] Decode assists support
171 UINT32 Reserved1 : 2; // EDX[9:8] Reserved
172 UINT32 PauseFilter : 1; // EDX[10] Pause filter support
173 UINT32 Reserved2 : 1; // EDX[11] Reserved
174 UINT32 PauseFilterThreshold : 1; // EDX[12] Pause filter threshold support
175 UINT32 AVIC : 1; // EDX[13:13] Advanced Virtual Interrupt Controller
176 UINT32 Unknown14 : 1; // EDX[14] Unknown. Described in AMD doc as X2AVIC, but that was probably a typo, since x2AVIC is bit 18.
177 UINT32 VMSAVEVirt : 1; // EDX[15] MSAVE and VMLOAD Virtualization
178 UINT32 VGIF : 1; // EDX[16] Virtual Global-Interrupt Flag
179 UINT32 GMET : 1; // EDX[17] Guest Mode Execute Trap Extension
180 UINT32 x2AVIC : 1; // EDX[18] Virtual x2APIC
181 UINT32 SSSCheck : 1; // EDX[19] AKA SupervisorShadowStack
182 UINT32 V_SPEC_CTRL : 1; // EDX[20] Virtual SPEC_CTRL
183 UINT32 ROGPT : 1; // EDX[21]
184 UINT32 Unknown22 : 1; // EDX[22]
185 UINT32 HOST_MCE_OVERRIDE : 1; // EDX[23]
186 UINT32 TLBSYNC : 1; // EDX[24] TLBSYNC instruction can be intercepted
187 UINT32 VNMI : 1; // EDX[25] NMI Virtualization support
188 UINT32 IbsVirt : 1; // EDX[26] Instruction Based Sampling Virtualization
189 UINT32 LVTReadAllowed : 1; // EDX[27]
190 UINT32 Unknown28 : 1; // EDX[28]
191 UINT32 BusLockThreshold : 1; // EDX[29]
192 } Bits;
193
196
197// CPUID_AMD_SVM_FEATURES (0x8000000A)
198typedef union
199{
200 INT32 AsInt32[4];
201 struct
202 {
207 };
signed int INT32
unsigned int UINT32
unsigned int UINT
Definition: ndis.h:50
CPUID_AMD_SVM_FEATURES_EDX Edx
Definition: Cpuid.h:206
CPUID_AMD_SVM_FEATURES_EAX Eax
Definition: Cpuid.h:203
CPUID_AMD_EXTENDED_CPU_SIG_ECX Ecx
Definition: Cpuid.h:132
CPUID_AMD_EXTENDED_CPU_SIG_EDX Edx
Definition: Cpuid.h:133
CPUID_AMD_EXTENDED_CPU_SIG_EAX Eax
Definition: Cpuid.h:130
CPUID_EXTENDED_CPU_SIG_EDX Edx
Definition: Cpuid.h:126
CPUID_AMD_EXTENDED_CPU_SIG_EBX Ebx
Definition: Cpuid.h:131
CPUID_EXTENDED_CPU_SIG_ECX Ecx
Definition: Cpuid.h:125
CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax
Definition: Cpuid.h:93
CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx
Definition: Cpuid.h:112
CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax
Definition: Cpuid.h:107
UINT32 MaxLeaf
Definition: Cpuid.h:19
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx
Definition: Cpuid.h:80
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx
Definition: Cpuid.h:82
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx
Definition: Cpuid.h:81
CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx
Definition: Cpuid.h:57
CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx
Definition: Cpuid.h:58
CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax
Definition: Cpuid.h:56
CPUID_VERSION_INFO_EAX Eax
Definition: Cpuid.h:30
CPUID_VERSION_INFO_EDX Edx
Definition: Cpuid.h:33
CPUID_VERSION_INFO_ECX Ecx
Definition: Cpuid.h:32
CPUID_VERSION_INFO_EBX Ebx
Definition: Cpuid.h:31
char CHAR
Definition: xmlstorage.h:175