ReactOS 0.4.15-dev-8219-ge8b88cf
cpu.c File Reference
#include <ntoskrnl.h>
#include <x86x64/Cpuid.h>
#include <x86x64/Msr.h>
#include <debug.h>
Include dependency graph for cpu.c:

Go to the source code of this file.

Classes

union  _CPU_SIGNATURE
 

Macros

#define NDEBUG
 

Typedefs

typedef union _CPU_SIGNATURE CPU_SIGNATURE
 

Functions

ULONG NTAPI KiGetCpuVendor (VOID)
 
VOID NTAPI KiSetProcessorType (VOID)
 
ULONG64 NTAPI KiGetFeatureBits (VOID)
 Evaluates the KeFeatureFlag bits for the current CPU.
 
VOID NTAPI KiGetCacheInformation (VOID)
 
VOID NTAPI KeFlushCurrentTb (VOID)
 
VOID NTAPI KiRestoreProcessorControlState (PKPROCESSOR_STATE ProcessorState)
 
VOID NTAPI KiSaveProcessorControlState (OUT PKPROCESSOR_STATE ProcessorState)
 
VOID NTAPI KiSaveProcessorState (_In_ PKTRAP_FRAME TrapFrame, _In_ PKEXCEPTION_FRAME ExceptionFrame)
 
VOID NTAPI KiRestoreProcessorState (_Out_ PKTRAP_FRAME TrapFrame, _Out_ PKEXCEPTION_FRAME ExceptionFrame)
 
VOID NTAPI KeFlushEntireTb (IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
 
KAFFINITY NTAPI KeQueryActiveProcessors (VOID)
 
NTSTATUS NTAPI KxSaveFloatingPointState (OUT PKFLOATING_SAVE FloatingState)
 
NTSTATUS NTAPI KxRestoreFloatingPointState (IN PKFLOATING_SAVE FloatingState)
 
BOOLEAN NTAPI KeInvalidateAllCaches (VOID)
 
ULONG NTAPI KeGetRecommendedSharedDataAlignment (VOID)
 
VOID __cdecl KeSaveStateForHibernate (IN PKPROCESSOR_STATE State)
 
VOID NTAPI KeSetDmaIoCoherency (IN ULONG Coherency)
 

Variables

KTSS64 KiBootTss
 
ULONG KeI386CpuType
 
ULONG KeI386CpuStep
 
ULONG KeI386MachineType
 
ULONG KeI386NpxPresent = 1
 
ULONG KeLargestCacheLine = 0x40
 
ULONG KiDmaIoCoherency = 0
 
BOOLEAN KiSMTProcessorsPresent
 
volatile LONG KiTbFlushTimeStamp
 
static const CHAR CmpIntelID [] = "GenuineIntel"
 
static const CHAR CmpAmdID [] = "AuthenticAMD"
 
static const CHAR CmpCentaurID [] = "CentaurHauls"
 

Macro Definition Documentation

◆ NDEBUG

#define NDEBUG

Definition at line 15 of file cpu.c.

Typedef Documentation

◆ CPU_SIGNATURE

Function Documentation

◆ KeFlushCurrentTb()

VOID NTAPI KeFlushCurrentTb ( VOID  )

Definition at line 526 of file cpu.c.

527{
528 /* Flush the TLB by resetting CR3 */
530}
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1818
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1794

Referenced by KeFlushEntireTb(), and KiFlushTargetEntireTb().

◆ KeFlushEntireTb()

VOID NTAPI KeFlushEntireTb ( IN BOOLEAN  Invalid,
IN BOOLEAN  AllProcessors 
)

Definition at line 652 of file cpu.c.

654{
656
657 // FIXME: halfplemented
658 /* Raise the IRQL for the TB Flush */
660
661 /* Flush the TB for the Current CPU, and update the flush stamp */
663
664 /* Update the flush stamp and return to original IRQL */
667
668}
UCHAR KIRQL
Definition: env_spec_w32.h:591
#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
Definition: pic.c:156
#define InterlockedExchangeAdd
Definition: interlocked.h:181
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:526
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:33
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:778

Referenced by MiAllocatePoolPages(), MiDeleteSystemPageableVm(), MiDereferenceSession(), MiMapLockedPagesInUserSpace(), MiProtectFreeNonPagedPool(), MiSetSystemCodeProtection(), MmFreeSpecialPool(), MmMapIoSpace(), and MmUnmapIoSpace().

◆ KeGetRecommendedSharedDataAlignment()

◆ KeInvalidateAllCaches()

BOOLEAN NTAPI KeInvalidateAllCaches ( VOID  )

Definition at line 698 of file cpu.c.

699{
700 /* Invalidate all caches */
701 __wbinvd();
702 return TRUE;
703}
#define TRUE
Definition: types.h:120
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759

◆ KeQueryActiveProcessors()

KAFFINITY NTAPI KeQueryActiveProcessors ( VOID  )

Definition at line 672 of file cpu.c.

673{
674 PAGED_CODE();
675
676 /* Simply return the number of active processors */
677 return KeActiveProcessors;
678}
#define PAGED_CODE()
KAFFINITY KeActiveProcessors
Definition: krnlinit.c:23

Referenced by get_num_of_processors(), and KeQueryActiveProcessorCount().

◆ KeSaveStateForHibernate()

VOID __cdecl KeSaveStateForHibernate ( IN PKPROCESSOR_STATE  State)

Definition at line 721 of file cpu.c.

722{
723 /* Capture the context */
724 RtlCaptureContext(&State->ContextFrame);
725
726 /* Capture the control state */
728}
NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:576

◆ KeSetDmaIoCoherency()

VOID NTAPI KeSetDmaIoCoherency ( IN ULONG  Coherency)

Definition at line 735 of file cpu.c.

736{
737 /* Save the coherency globally */
738 KiDmaIoCoherency = Coherency;
739}
ULONG KiDmaIoCoherency
Definition: cpu.c:29

◆ KiGetCacheInformation()

VOID NTAPI KiGetCacheInformation ( VOID  )

Definition at line 418 of file cpu.c.

419{
420 PKIPCR Pcr = (PKIPCR)KeGetPcr();
421 ULONG Vendor;
422 ULONG CacheRequests = 0, i;
423 ULONG CurrentRegister;
424 UCHAR RegisterByte;
425 BOOLEAN FirstPass = TRUE;
426 CPU_INFO CpuInfo;
427
428 /* Set default L2 size */
429 Pcr->SecondLevelCacheSize = 0;
430
431 /* Get the Vendor ID and make sure we support CPUID */
432 Vendor = KiGetCpuVendor();
433 if (!Vendor) return;
434
435 /* Check the Vendor ID */
436 switch (Vendor)
437 {
438 /* Handle Intel case */
439 case CPU_INTEL:
440
441 /*Check if we support CPUID 2 */
442 KiCpuId(&CpuInfo, 0);
443 if (CpuInfo.Eax >= 2)
444 {
445 /* We need to loop for the number of times CPUID will tell us to */
446 do
447 {
448 /* Do the CPUID call */
449 KiCpuId(&CpuInfo, 2);
450
451 /* Check if it was the first call */
452 if (FirstPass)
453 {
454 /*
455 * The number of times to loop is the first byte. Read
456 * it and then destroy it so we don't get confused.
457 */
458 CacheRequests = CpuInfo.Eax & 0xFF;
459 CpuInfo.Eax &= 0xFFFFFF00;
460
461 /* Don't go over this again */
462 FirstPass = FALSE;
463 }
464
465 /* Loop all 4 registers */
466 for (i = 0; i < 4; i++)
467 {
468 /* Get the current register */
469 CurrentRegister = CpuInfo.AsUINT32[i];
470
471 /*
472 * If the upper bit is set, then this register should
473 * be skipped.
474 */
475 if (CurrentRegister & 0x80000000) continue;
476
477 /* Keep looping for every byte inside this register */
478 while (CurrentRegister)
479 {
480 /* Read a byte, skip a byte. */
481 RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
482 CurrentRegister >>= 8;
483 if (!RegisterByte) continue;
484
485 /*
486 * Valid values are from 0x40 (0 bytes) to 0x49
487 * (32MB), or from 0x80 to 0x89 (same size but
488 * 8-way associative.
489 */
490 if (((RegisterByte > 0x40) &&
491 (RegisterByte <= 0x49)) ||
492 ((RegisterByte > 0x80) &&
493 (RegisterByte <= 0x89)))
494 {
495 /* Mask out only the first nibble */
496 RegisterByte &= 0x0F;
497
498 /* Set the L2 Cache Size */
499 Pcr->SecondLevelCacheSize = 0x10000 <<
500 RegisterByte;
501 }
502 }
503 }
504 } while (--CacheRequests);
505 }
506 break;
507
508 case CPU_AMD:
509
510 /* Check if we support CPUID 0x80000006 */
511 KiCpuId(&CpuInfo, 0x80000000);
512 if (CpuInfo.Eax >= 6)
513 {
514 /* Get 2nd level cache and tlb size */
515 KiCpuId(&CpuInfo, 0x80000006);
516
517 /* Set the L2 Cache Size */
518 Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
519 }
520 break;
521 }
522}
unsigned char BOOLEAN
#define FALSE
Definition: types.h:117
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
struct _KIPCR * PKIPCR
@ CPU_INTEL
Definition: ketypes.h:106
@ CPU_AMD
Definition: ketypes.h:105
#define KeGetPcr()
Definition: ketypes.h:81
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:59
ULONG SecondLevelCacheSize
Definition: ketypes.h:968
uint32_t ULONG
Definition: typedefs.h:59
ULONG Eax
Definition: ketypes.h:381
UINT32 AsUINT32[4]
Definition: ketypes.h:378
ULONG Ecx
Definition: ketypes.h:383
unsigned char UCHAR
Definition: xmlstorage.h:181

◆ KiGetCpuVendor()

ULONG NTAPI KiGetCpuVendor ( VOID  )

Definition at line 59 of file cpu.c.

60{
61 PKPRCB Prcb = KeGetCurrentPrcb();
62 CPU_INFO CpuInfo;
63
64 /* Get the Vendor ID and null-terminate it */
65 KiCpuId(&CpuInfo, 0);
66
67 /* Copy it to the PRCB and null-terminate it */
68 *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
69 *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
70 *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
71 Prcb->VendorString[12] = 0;
72
73 /* Now check the CPU Type */
75 {
76 Prcb->CpuVendor = CPU_INTEL;
77 }
78 else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
79 {
80 Prcb->CpuVendor = CPU_AMD;
81 }
82 else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
83 {
84 DPRINT1("VIA CPUs not fully supported\n");
85 Prcb->CpuVendor = CPU_VIA;
86 }
87 else
88 {
89 /* Invalid CPU */
90 DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
91 Prcb->CpuVendor = CPU_UNKNOWN;
92 }
93
94 return Prcb->CpuVendor;
95}
int strcmp(const char *String1, const char *String2)
Definition: utclib.c:469
#define DPRINT1
Definition: precomp.h:8
if(dx< 0)
Definition: linetemp.h:194
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1161
@ CPU_VIA
Definition: ketypes.h:107
@ CPU_UNKNOWN
Definition: ketypes.h:104
static const CHAR CmpIntelID[]
Definition: cpu.c:36
static const CHAR CmpAmdID[]
Definition: cpu.c:37
static const CHAR CmpCentaurID[]
Definition: cpu.c:38
UCHAR VendorString[13]
Definition: ketypes.h:881
UCHAR CpuVendor
Definition: ketypes.h:684
char * PCHAR
Definition: typedefs.h:51
ULONG Ebx
Definition: ketypes.h:382
ULONG Edx
Definition: ketypes.h:384

Referenced by KiGetCacheInformation(), KiGetFeatureBits(), and KiSetProcessorType().

◆ KiGetFeatureBits()

ULONG64 NTAPI KiGetFeatureBits ( VOID  )

Evaluates the KeFeatureFlag bits for the current CPU.

Returns
The feature flags for this CPU.
See also
https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/featurebits.htm
Todo:
  • KF_VIRT_FIRMWARE_ENABLED 0x08000000 (see notes from Geoff Chappell)
  • KF_FPU_LEAKAGE 0x0000020000000000ULL
  • KF_CAT 0x0000100000000000ULL
  • KF_CET_SS 0x0000400000000000ULL

Definition at line 165 of file cpu.c.

166{
167 PKPRCB Prcb = KeGetCurrentPrcb();
168 ULONG Vendor;
169 ULONG64 FeatureBits = 0;
170 CPUID_SIGNATURE_REGS signature;
172 CPUID_EXTENDED_FUNCTION_REGS extendedFunction;
173
174 /* Get the Vendor ID */
175 Vendor = Prcb->CpuVendor;
176
177 /* Make sure we got a valid vendor ID at least. */
178 if (Vendor == CPU_UNKNOWN) return FeatureBits;
179
180 /* Get signature CPUID for the maximum function */
181 __cpuid(signature.AsInt32, CPUID_SIGNATURE);
182
183 /* Get the CPUID Info. */
185
186 /* Set the initial APIC ID */
187 Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId;
188
189 /* Convert all CPUID Feature bits into our format */
190 if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4;
191 if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
192 if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC;
193 if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B;
194 if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL;
195 if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR;
196 if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
197 if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV;
198 if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT;
199 if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS;
200 if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX;
201 if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR;
202 if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI;
203 if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64;
204
205 if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3;
206 if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3;
207 if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B;
208 if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1;
209 if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE;
210 if (VersionInfo.Ecx.Bits.RDRAND) FeatureBits |= KF_RDRAND;
211
212 /* Check if the CPU has hyper-threading */
213 if (VersionInfo.Edx.Bits.HTT)
214 {
215 /* Set the number of logical CPUs */
217 VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors;
219 {
220 /* We're on dual-core */
222 }
223 }
224 else
225 {
226 /* We only have a single CPU */
228 }
229
230 /* Check if CPUID_THERMAL_POWER_MANAGEMENT (0x06) is supported */
232 {
233 /* Read CPUID_THERMAL_POWER_MANAGEMENT */
236
237 if (PowerInfo.Undoc.Ecx.ACNT2) FeatureBits |= KF_ACNT2;
238 }
239
240 /* Check if CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) is supported */
242 {
243 /* Read CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS */
245 __cpuidex(ExtFlags.AsInt32,
248
249 if (ExtFlags.Ebx.Bits.SMEP) FeatureBits |= KF_SMEP;
250 if (ExtFlags.Ebx.Bits.FSGSBASE) FeatureBits |= KF_RDWRFSGSBASE;
251 if (ExtFlags.Ebx.Bits.SMAP) FeatureBits |= KF_SMAP;
252 }
253
254 /* Check if CPUID_EXTENDED_STATE (0x0D) is supported */
255 if (signature.MaxLeaf >= CPUID_EXTENDED_STATE)
256 {
257 /* Read CPUID_EXTENDED_STATE */
259 __cpuidex(ExtStateSub.AsInt32,
262
263 if (ExtStateSub.Eax.Bits.XSAVEOPT) FeatureBits |= KF_XSAVEOPT;
264 if (ExtStateSub.Eax.Bits.XSAVES) FeatureBits |= KF_XSAVES;
265 }
266
267 /* Check extended cpuid features */
268 __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION);
269 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
270 {
271 /* Check if CPUID_EXTENDED_CPU_SIG (0x80000001) is supported */
272 if (extendedFunction.MaxLeaf >= CPUID_EXTENDED_CPU_SIG)
273 {
274 /* Read CPUID_EXTENDED_CPU_SIG */
277
278 /* Check if NX-bit is supported */
279 if (ExtSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT;
280 if (ExtSig.Intel.Edx.Bits.Page1GB) FeatureBits |= KF_HUGEPAGE;
281 if (ExtSig.Intel.Edx.Bits.RDTSCP) FeatureBits |= KF_RDTSCP;
282
283 /* AMD specific */
284 if (Vendor == CPU_AMD)
285 {
286 if (ExtSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW;
287 }
288 }
289 }
290
291 /* Vendor specific */
292 if (Vendor == CPU_INTEL)
293 {
294 FeatureBits |= KF_GENUINE_INTEL;
295
296 /* Check for models that support LBR */
297 if (VersionInfo.Eax.Bits.FamilyId == 6)
298 {
299 if ((VersionInfo.Eax.Bits.Model == 15) ||
300 (VersionInfo.Eax.Bits.Model == 22) ||
301 (VersionInfo.Eax.Bits.Model == 23) ||
302 (VersionInfo.Eax.Bits.Model == 26))
303 {
304 FeatureBits |= KF_BRANCH;
305 }
306 }
307
308 /* Check if VMX is available */
309 if (VersionInfo.Ecx.Bits.VMX)
310 {
311 /* Read PROCBASED ctls and check if secondary are allowed */
314 if (ProcBasedCtls.Bits.Allowed1.ActivateSecondaryControls)
315 {
316 /* Read secondary controls and check if EPT is allowed */
319 if (ProcBasedCtls2.Bits.Allowed1.EPT)
320 FeatureBits |= KF_SLAT;
321 }
322 }
323 }
324 else if (Vendor == CPU_AMD)
325 {
326 FeatureBits |= KF_AUTHENTICAMD;
327 FeatureBits |= KF_BRANCH;
328
329 /* Check extended cpuid features */
330 if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
331 {
332 /* Check if CPUID_AMD_SVM_FEATURES (0x8000000A) is supported */
333 if (extendedFunction.MaxLeaf >= CPUID_AMD_SVM_FEATURES)
334 {
335 /* Read CPUID_AMD_SVM_FEATURES and check if Nested Paging is available */
336 CPUID_AMD_SVM_FEATURES_REGS SvmFeatures;
338 if (SvmFeatures.Edx.Bits.NP) FeatureBits |= KF_SLAT;
339 }
340 }
341 }
342
343 /* Return the Feature Bits */
344 return FeatureBits;
345}
#define MSR_IA32_VMX_PROCBASED_CTLS
#define MSR_IA32_VMX_PROCBASED_CTLS2
#define CPUID_AMD_SVM_FEATURES
Definition: Cpuid.h:146
#define CPUID_EXTENDED_FUNCTION
Definition: Cpuid.h:3745
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
Definition: Cpuid.h:1301
#define CPUID_SIGNATURE
Definition: Cpuid.h:45
#define CPUID_VERSION_INFO
Definition: Cpuid.h:81
#define CPUID_EXTENDED_STATE
Definition: Cpuid.h:1918
#define CPUID_THERMAL_POWER_MANAGEMENT
Definition: Cpuid.h:1114
#define CPUID_EXTENDED_STATE_SUB_LEAF
Definition: Cpuid.h:2033
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
Definition: Cpuid.h:1306
#define CPUID_EXTENDED_CPU_SIG
Definition: Cpuid.h:3768
OSVERSIONINFOW VersionInfo
Definition: wkssvc.c:40
PPC_QUAL void __cpuid(int CPUInfo[], const int InfoType)
Definition: intrin_ppc.h:682
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
__INTRIN_INLINE void __cpuidex(int CPUInfo[4], int InfoType, int ECXValue)
Definition: intrin_x86.h:1649
unsigned __int64 ULONG64
Definition: imports.h:198
#define KF_SMEP
Definition: ketypes.h:31
#define KF_SSSE3
Definition: ketypes.h:72
#define KF_MTRR
Definition: ketypes.h:37
#define KF_HUGEPAGE
Definition: ketypes.h:67
#define KF_XSTATE
Definition: ketypes.h:55
#define KF_DTS
Definition: ketypes.h:40
#define KF_CMPXCHG16B
Definition: ketypes.h:52
#define KF_CR4
Definition: ketypes.h:33
#define KF_AUTHENTICAMD
Definition: ketypes.h:53
#define KF_XMMI64
Definition: ketypes.h:48
#define KF_CMOV
Definition: ketypes.h:34
#define KF_ACNT2
Definition: ketypes.h:54
#define KF_SSE4_1
Definition: ketypes.h:73
#define KF_RDWRFSGSBASE
Definition: ketypes.h:60
#define KF_CMPXCHG8B
Definition: ketypes.h:38
#define KF_RDTSC
Definition: ketypes.h:32
#define KF_FAST_SYSCALL
Definition: ketypes.h:43
#define KF_3DNOW
Definition: ketypes.h:45
#define KF_NX_BIT
Definition: ketypes.h:61
#define KF_FXSR
Definition: ketypes.h:42
#define KF_RDRAND
Definition: ketypes.h:64
#define KF_XSAVES
Definition: ketypes.h:68
#define KF_LARGE_PAGE
Definition: ketypes.h:36
#define KF_BRANCH
Definition: ketypes.h:49
#define KF_GENUINE_INTEL
Definition: ketypes.h:56
#define KF_XMMI
Definition: ketypes.h:44
#define KF_MMX
Definition: ketypes.h:39
#define KF_XSAVEOPT
Definition: ketypes.h:47
#define KF_SSE3
Definition: ketypes.h:51
#define KF_SLAT
Definition: ketypes.h:58
#define KF_PAT
Definition: ketypes.h:41
#define KF_RDTSCP
Definition: ketypes.h:66
#define KF_GLOBAL_PAGE
Definition: ketypes.h:35
#define KF_SMAP
Definition: ketypes.h:65
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:30
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:759
ULONG InitialApicId
Definition: ketypes.h:701
struct CPUID_AMD_SVM_FEATURES_EDX::@3741 Bits
CPUID_AMD_SVM_FEATURES_EDX Edx
Definition: Cpuid.h:206
struct CPUID_EXTENDED_CPU_SIG_REGS::@3738 Intel
struct CPUID_EXTENDED_CPU_SIG_REGS::@3739 Amd
CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax
Definition: Cpuid.h:107
struct CPUID_EXTENDED_STATE_SUB_LEAF_EAX::@3836 Bits
UINT32 MaxLeaf
Definition: Cpuid.h:19
INT32 AsInt32[4]
Definition: Cpuid.h:16
struct CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::@3826 Bits
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx
Definition: Cpuid.h:80
struct CPUID_THERMAL_POWER_MANAGEMENT_REGS::@3729 Undoc
struct MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER::@3873 Bits
struct MSR_IA32_VMX_PROCBASED_CTLS_REGISTER::@3872 Bits

◆ KiRestoreProcessorControlState()

VOID NTAPI KiRestoreProcessorControlState ( PKPROCESSOR_STATE  ProcessorState)

Definition at line 534 of file cpu.c.

535{
536 /* Restore the CR registers */
537 __writecr0(ProcessorState->SpecialRegisters.Cr0);
538// __writecr2(ProcessorState->SpecialRegisters.Cr2);
539 __writecr3(ProcessorState->SpecialRegisters.Cr3);
540 __writecr4(ProcessorState->SpecialRegisters.Cr4);
541 __writecr8(ProcessorState->SpecialRegisters.Cr8);
542
543 /* Restore the DR registers */
544 __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
545 __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
546 __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
547 __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
548 __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
549 __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
550
551 /* Restore GDT, IDT, LDT and TSS */
552 __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
553// __lldt(&ProcessorState->SpecialRegisters.Ldtr);
554// __ltr(&ProcessorState->SpecialRegisters.Tr);
555 __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
556
557 _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
558// ProcessorState->SpecialRegisters.DebugControl
559// ProcessorState->SpecialRegisters.LastBranchToRip
560// ProcessorState->SpecialRegisters.LastBranchFromRip
561// ProcessorState->SpecialRegisters.LastExceptionToRip
562// ProcessorState->SpecialRegisters.LastExceptionFromRip
563
564 /* Restore MSRs */
571
572}
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2018
__INTRIN_INLINE void __writecr0(unsigned int Data)
Definition: intrin_x86.h:1789
__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1799
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
Definition: intrin_x86.h:1935
#define X86_MSR_CSTAR
Definition: ke.h:75
#define X86_MSR_GSBASE
Definition: ke.h:70
#define X86_MSR_LSTAR
Definition: ke.h:74
#define X86_MSR_SFMASK
Definition: ke.h:76
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:71
#define X86_MSR_STAR
Definition: ke.h:73
USHORT Limit
Definition: ketypes.h:449
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:615
ULONG64 KernelDr0
Definition: ketypes.h:585
ULONG64 KernelDr7
Definition: ketypes.h:590
ULONG64 MsrLStar
Definition: ketypes.h:605
KDESCRIPTOR Gdtr
Definition: ketypes.h:591
ULONG64 KernelDr2
Definition: ketypes.h:587
ULONG64 MsrGsBase
Definition: ketypes.h:602
KDESCRIPTOR Idtr
Definition: ketypes.h:592
ULONG64 KernelDr1
Definition: ketypes.h:586
ULONG64 MsrCStar
Definition: ketypes.h:606
ULONG64 MsrSyscallMask
Definition: ketypes.h:607
ULONG64 MsrGsSwap
Definition: ketypes.h:603
ULONG64 KernelDr3
Definition: ketypes.h:588
ULONG64 KernelDr6
Definition: ketypes.h:589
void _mm_setcsr(unsigned int a)
Definition: xmmintrin.h:542

Referenced by KiRestoreProcessorState().

◆ KiRestoreProcessorState()

VOID NTAPI KiRestoreProcessorState ( _Out_ PKTRAP_FRAME  TrapFrame,
_Out_ PKEXCEPTION_FRAME  ExceptionFrame 
)

Definition at line 633 of file cpu.c.

636{
637 PKPRCB Prcb = KeGetCurrentPrcb();
638
639 /* Restore all context */
641 ExceptionFrame,
642 TrapFrame,
644 TrapFrame->PreviousMode);
645
646 /* Restore control registers */
648}
VOID NTAPI KeContextToTrapFrame(PCONTEXT Context, PKEXCEPTION_FRAME ExeptionFrame, PKTRAP_FRAME TrapFrame, ULONG ContextFlags, KPROCESSOR_MODE PreviousMode)
VOID NTAPI KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:534
#define CONTEXT_ALL
KPROCESSOR_STATE ProcessorState
Definition: ketypes.h:663
CONTEXT ContextFrame
Definition: ketypes.h:616

Referenced by KiProcessorFreezeHandler().

◆ KiSaveProcessorControlState()

VOID NTAPI KiSaveProcessorControlState ( OUT PKPROCESSOR_STATE  ProcessorState)

Definition at line 576 of file cpu.c.

577{
578 /* Save the CR registers */
579 ProcessorState->SpecialRegisters.Cr0 = __readcr0();
580 ProcessorState->SpecialRegisters.Cr2 = __readcr2();
581 ProcessorState->SpecialRegisters.Cr3 = __readcr3();
582 ProcessorState->SpecialRegisters.Cr4 = __readcr4();
583 ProcessorState->SpecialRegisters.Cr8 = __readcr8();
584
585 /* Save the DR registers */
586 ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
587 ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
588 ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
589 ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
590 ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
591 ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
592
593 /* Save GDT, IDT, LDT and TSS */
594 __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
595 __sldt(&ProcessorState->SpecialRegisters.Ldtr);
596 __str(&ProcessorState->SpecialRegisters.Tr);
597 __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
598
599 ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
600// ProcessorState->SpecialRegisters.DebugControl =
601// ProcessorState->SpecialRegisters.LastBranchToRip =
602// ProcessorState->SpecialRegisters.LastBranchFromRip =
603// ProcessorState->SpecialRegisters.LastExceptionToRip =
604// ProcessorState->SpecialRegisters.LastExceptionFromRip =
605
606 /* Save MSRs */
607 ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
608 ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
609 ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
610 ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
611 ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
612 ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
613}
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
Definition: intrin_x86.h:1902
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1825
__INTRIN_INLINE unsigned long __readcr0(void)
Definition: intrin_x86.h:1804
__INTRIN_INLINE unsigned long __readcr2(void)
Definition: intrin_x86.h:1811
__INTRIN_INLINE void __sidt(void *Destination)
Definition: intrin_x86.h:2023
unsigned int _mm_getcsr(void)
Definition: xmmintrin.h:535

Referenced by KeSaveStateForHibernate(), and KiSaveProcessorState().

◆ KiSaveProcessorState()

VOID NTAPI KiSaveProcessorState ( _In_ PKTRAP_FRAME  TrapFrame,
_In_ PKEXCEPTION_FRAME  ExceptionFrame 
)

Definition at line 617 of file cpu.c.

620{
621 PKPRCB Prcb = KeGetCurrentPrcb();
622
623 /* Save all context */
625 KeTrapFrameToContext(TrapFrame, ExceptionFrame, &Prcb->ProcessorState.ContextFrame);
626
627 /* Save control registers */
629}
VOID NTAPI KeTrapFrameToContext(IN PKTRAP_FRAME TrapFrame, IN PKEXCEPTION_FRAME ExceptionFrame, IN OUT PCONTEXT Context)
Definition: context.c:169
ULONG ContextFlags
Definition: nt_native.h:1426

Referenced by KiProcessorFreezeHandler(), and KiTrap02Handler().

◆ KiSetProcessorType()

VOID NTAPI KiSetProcessorType ( VOID  )

Definition at line 99 of file cpu.c.

100{
101 CPU_INFO CpuInfo;
102 CPU_SIGNATURE CpuSignature;
103 BOOLEAN ExtendModel;
104 ULONG Stepping, Type, Vendor;
105
106 /* This initializes Prcb->CpuVendor */
107 Vendor = KiGetCpuVendor();
108
109 /* Do CPUID 1 now */
110 KiCpuId(&CpuInfo, 1);
111
112 /*
113 * Get the Stepping and Type. The stepping contains both the
114 * Model and the Step, while the Type contains the returned Family.
115 *
116 * For the stepping, we convert this: zzzzzzxy into this: x0y
117 */
118 CpuSignature.AsULONG = CpuInfo.Eax;
119 Stepping = CpuSignature.Model;
120 ExtendModel = (CpuSignature.Family == 15);
121#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
122 if (CpuSignature.Family == 6)
123 {
124 ExtendModel |= (Vendor == CPU_INTEL);
125#if (NTDDI_VERSION >= NTDDI_WIN8)
126 ExtendModel |= (Vendor == CPU_CENTAUR);
127#endif
128 }
129#endif
130 if (ExtendModel)
131 {
132 /* Add ExtendedModel to distinguish from non-extended values. */
133 Stepping |= (CpuSignature.ExtendedModel << 4);
134 }
135 Stepping = (Stepping << 8) | CpuSignature.Step;
136 Type = CpuSignature.Family;
137 if (CpuSignature.Family == 15)
138 {
139 /* Add ExtendedFamily to distinguish from non-extended values.
140 * It must not be larger than 0xF0 to avoid overflow. */
141 Type += min(CpuSignature.ExtendedFamily, 0xF0);
142 }
143
144 /* Save them in the PRCB */
145 KeGetCurrentPrcb()->CpuID = TRUE;
146 KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
147 KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
148}
Type
Definition: Type.h:7
#define min(a, b)
Definition: monoChain.cc:55
@ CPU_CENTAUR
Definition: ketypes.h:95
unsigned short USHORT
Definition: pedump.c:61
ULONG ExtendedFamily
Definition: cpu.c:49
ULONG Model
Definition: cpu.c:45
ULONG Family
Definition: cpu.c:46
ULONG AsULONG
Definition: cpu.c:52
ULONG Step
Definition: cpu.c:44
ULONG ExtendedModel
Definition: cpu.c:48

◆ KxRestoreFloatingPointState()

NTSTATUS NTAPI KxRestoreFloatingPointState ( IN PKFLOATING_SAVE  FloatingState)

Definition at line 690 of file cpu.c.

691{
692 UNREFERENCED_PARAMETER(FloatingState);
693 return STATUS_SUCCESS;
694}
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317
#define STATUS_SUCCESS
Definition: shellext.h:65

◆ KxSaveFloatingPointState()

NTSTATUS NTAPI KxSaveFloatingPointState ( OUT PKFLOATING_SAVE  FloatingState)

Definition at line 682 of file cpu.c.

683{
684 UNREFERENCED_PARAMETER(FloatingState);
685 return STATUS_SUCCESS;
686}

Variable Documentation

◆ CmpAmdID

const CHAR CmpAmdID[] = "AuthenticAMD"
static

Definition at line 37 of file cpu.c.

Referenced by KiGetCpuVendor().

◆ CmpCentaurID

const CHAR CmpCentaurID[] = "CentaurHauls"
static

Definition at line 38 of file cpu.c.

Referenced by KiGetCpuVendor().

◆ CmpIntelID

const CHAR CmpIntelID[] = "GenuineIntel"
static

Definition at line 36 of file cpu.c.

Referenced by KiGetCpuVendor().

◆ KeI386CpuStep

ULONG KeI386CpuStep

Definition at line 25 of file cpu.c.

◆ KeI386CpuType

ULONG KeI386CpuType

Definition at line 24 of file cpu.c.

Referenced by KeInvalidateAllCaches().

◆ KeI386MachineType

ULONG KeI386MachineType

Definition at line 26 of file cpu.c.

Referenced by KiInitializeMachineType().

◆ KeI386NpxPresent

ULONG KeI386NpxPresent = 1

Definition at line 27 of file cpu.c.

Referenced by KeRestoreFloatingPointState(), and KeSaveFloatingPointState().

◆ KeLargestCacheLine

ULONG KeLargestCacheLine = 0x40

Definition at line 28 of file cpu.c.

Referenced by KeGetRecommendedSharedDataAlignment(), and KiGetCacheInformation().

◆ KiBootTss

KTSS64 KiBootTss

Definition at line 21 of file cpu.c.

◆ KiDmaIoCoherency

ULONG KiDmaIoCoherency = 0

Definition at line 29 of file cpu.c.

Referenced by KeSetDmaIoCoherency(), and KiInitializeKernel().

◆ KiSMTProcessorsPresent

BOOLEAN KiSMTProcessorsPresent

Definition at line 30 of file cpu.c.

Referenced by KiGetFeatureBits().

◆ KiTbFlushTimeStamp

volatile LONG KiTbFlushTimeStamp

Definition at line 33 of file cpu.c.

Referenced by KeFlushEntireTb().