cpu.c File Reference

#include <ntoskrnl.h>
#include <debug.h>

Include dependency graph for cpu.c:

Go to the source code of this file.

Classes
union	_CPU_SIGNATURE

Macros
#define	NDEBUG

Typedefs
typedef union _CPU_SIGNATURE	CPU_SIGNATURE

Functions
ULONG NTAPI	KiGetCpuVendor (VOID)
VOID NTAPI	KiSetProcessorType (VOID)
ULONG NTAPI	KiGetFeatureBits (VOID)
VOID NTAPI	KiGetCacheInformation (VOID)
VOID NTAPI	KeFlushCurrentTb (VOID)
VOID NTAPI	KiRestoreProcessorControlState (PKPROCESSOR_STATE ProcessorState)
VOID NTAPI	KiSaveProcessorControlState (OUT PKPROCESSOR_STATE ProcessorState)
VOID NTAPI	KeFlushEntireTb (IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
KAFFINITY NTAPI	KeQueryActiveProcessors (VOID)
NTSTATUS NTAPI	KxSaveFloatingPointState (OUT PKFLOATING_SAVE FloatingState)
NTSTATUS NTAPI	KxRestoreFloatingPointState (IN PKFLOATING_SAVE FloatingState)
BOOLEAN NTAPI	KeInvalidateAllCaches (VOID)
ULONG NTAPI	KeGetRecommendedSharedDataAlignment (VOID)
VOID __cdecl	KeSaveStateForHibernate (IN PKPROCESSOR_STATE State)
VOID NTAPI	KeSetDmaIoCoherency (IN ULONG Coherency)

Variables
KTSS64	KiBootTss
ULONG	KeI386CpuType
ULONG	KeI386CpuStep
ULONG	KeI386MachineType
ULONG	KeI386NpxPresent = 1
ULONG	KeLargestCacheLine = 0x40
ULONG	KiDmaIoCoherency = 0
BOOLEAN	KiSMTProcessorsPresent
volatile LONG	KiTbFlushTimeStamp
static const CHAR	CmpIntelID [] = "GenuineIntel"
static const CHAR	CmpAmdID [] = "AuthenticAMD"
static const CHAR	CmpCentaurID [] = "CentaurHauls"

Macro Definition Documentation

NDEBUG

#define NDEBUG

Definition at line 13 of file cpu.c.

Typedef Documentation

CPU_SIGNATURE

typedef union _CPU_SIGNATURE CPU_SIGNATURE

Function Documentation

KeFlushCurrentTb()

VOID NTAPI KeFlushCurrentTb

(

VOID

)

Definition at line 347 of file cpu.c.

{
    /* Flush the TLB by resetting CR3 */
    __writecr3(__readcr3());
}

Referenced by KeFlushEntireTb(), and KiFlushTargetEntireTb().

KeFlushEntireTb()

VOID NTAPI KeFlushEntireTb	(	IN BOOLEAN	Invalid,
		IN BOOLEAN	AllProcessors
	)

Definition at line 438 of file cpu.c.

{
    KIRQL OldIrql;
 
    // FIXME: halfplemented
    /* Raise the IRQL for the TB Flush */
    OldIrql = KeRaiseIrqlToSynchLevel();
 
    /* Flush the TB for the Current CPU, and update the flush stamp */
    KeFlushCurrentTb();
 
    /* Update the flush stamp and return to original IRQL */
    InterlockedExchangeAdd(&KiTbFlushTimeStamp, 1);
    KeLowerIrql(OldIrql);
 
}

Referenced by MiAllocatePoolPages(), MiDeleteSystemPageableVm(), MiDereferenceSession(), MiMapLockedPagesInUserSpace(), MiProtectFreeNonPagedPool(), MiSetSystemCodeProtection(), MmFreeSpecialPool(), MmMapIoSpace(), and MmUnmapIoSpace().

KeGetRecommendedSharedDataAlignment()

ULONG NTAPI KeGetRecommendedSharedDataAlignment

(

VOID

)

Definition at line 496 of file cpu.c.

{
    /* Return the global variable */
    return KeLargestCacheLine;
}

Referenced by ClassGetLBProvisioningResources(), ClasspDeviceGetBlockDeviceCharacteristicsVPDPage(), ClasspDeviceGetBlockLimitsVPDPage(), ClasspDeviceGetLBAStatusWorker(), ClasspDeviceGetLBProvisioningVPDPage(), ClasspGetBlockDeviceTokenLimitsInfo(), ClasspGetInquiryVpdSupportInfo(), ClassReadCapacity16(), ClassSendSrbSynchronous(), DeviceProcessDsmTrimRequest(), ExAllocateCacheAwareRundownProtection(), ExInitializeRundownProtectionCacheAware(), ExSizeOfRundownProtectionCacheAware(), and NdisGetSharedDataAlignment().

KeInvalidateAllCaches()

BOOLEAN NTAPI KeInvalidateAllCaches

(

VOID

)

Definition at line 484 of file cpu.c.

{
    /* Invalidate all caches */
    __wbinvd();
    return TRUE;
}

KeQueryActiveProcessors()

KAFFINITY NTAPI KeQueryActiveProcessors

(

VOID

)

Definition at line 458 of file cpu.c.

{
    PAGED_CODE();
 
    /* Simply return the number of active processors */
    return KeActiveProcessors;
}

Referenced by get_num_of_processors(), and KeQueryActiveProcessorCount().

KeSaveStateForHibernate()

VOID __cdecl KeSaveStateForHibernate

(

IN PKPROCESSOR_STATE

State

)

Definition at line 507 of file cpu.c.

{
    /* Capture the context */
    RtlCaptureContext(&State->ContextFrame);
 
    /* Capture the control state */
    KiSaveProcessorControlState(State);
}

KeSetDmaIoCoherency()

VOID NTAPI KeSetDmaIoCoherency

(

IN ULONG

Coherency

)

Definition at line 521 of file cpu.c.

{
    /* Save the coherency globally */
    KiDmaIoCoherency = Coherency;
}

KiGetCacheInformation()

VOID NTAPI KiGetCacheInformation

(

VOID

)

Definition at line 239 of file cpu.c.

{
    PKIPCR Pcr = (PKIPCR)KeGetPcr();
    ULONG Vendor;
    ULONG CacheRequests = 0, i;
    ULONG CurrentRegister;
    UCHAR RegisterByte;
    BOOLEAN FirstPass = TRUE;
    CPU_INFO CpuInfo;
 
    /* Set default L2 size */
    Pcr->SecondLevelCacheSize = 0;
 
    /* Get the Vendor ID and make sure we support CPUID */
    Vendor = KiGetCpuVendor();
    if (!Vendor) return;
 
    /* Check the Vendor ID */
    switch (Vendor)
    {
        /* Handle Intel case */
        case CPU_INTEL:
 
            /*Check if we support CPUID 2 */
            KiCpuId(&CpuInfo, 0);
            if (CpuInfo.Eax >= 2)
            {
                /* We need to loop for the number of times CPUID will tell us to */
                do
                {
                    /* Do the CPUID call */
                    KiCpuId(&CpuInfo, 2);
 
                    /* Check if it was the first call */
                    if (FirstPass)
                    {
                        /*
                         * The number of times to loop is the first byte. Read
                         * it and then destroy it so we don't get confused.
                         */
                        CacheRequests = CpuInfo.Eax & 0xFF;
                        CpuInfo.Eax &= 0xFFFFFF00;
 
                        /* Don't go over this again */
                        FirstPass = FALSE;
                    }
 
                    /* Loop all 4 registers */
                    for (i = 0; i < 4; i++)
                    {
                        /* Get the current register */
                        CurrentRegister = CpuInfo.AsUINT32[i];
 
                        /*
                         * If the upper bit is set, then this register should
                         * be skipped.
                         */
                        if (CurrentRegister & 0x80000000) continue;
 
                        /* Keep looping for every byte inside this register */
                        while (CurrentRegister)
                        {
                            /* Read a byte, skip a byte. */
                            RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
                            CurrentRegister >>= 8;
                            if (!RegisterByte) continue;
 
                            /*
                             * Valid values are from 0x40 (0 bytes) to 0x49
                             * (32MB), or from 0x80 to 0x89 (same size but
                             * 8-way associative.
                             */
                            if (((RegisterByte > 0x40) &&
                                 (RegisterByte <= 0x49)) ||
                                ((RegisterByte > 0x80) &&
                                (RegisterByte <= 0x89)))
                            {
                                /* Mask out only the first nibble */
                                RegisterByte &= 0x0F;
 
                                /* Set the L2 Cache Size */
                                Pcr->SecondLevelCacheSize = 0x10000 <<
                                                            RegisterByte;
                            }
                        }
                    }
                } while (--CacheRequests);
            }
            break;
 
        case CPU_AMD:
 
            /* Check if we support CPUID 0x80000006 */
            KiCpuId(&CpuInfo, 0x80000000);
            if (CpuInfo.Eax >= 6)
            {
                /* Get 2nd level cache and tlb size */
                KiCpuId(&CpuInfo, 0x80000006);
 
                /* Set the L2 Cache Size */
                Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
            }
            break;
    }
}

KiGetCpuVendor()

ULONG NTAPI KiGetCpuVendor

(

VOID

)

Definition at line 57 of file cpu.c.

{
    PKPRCB Prcb = KeGetCurrentPrcb();
    CPU_INFO CpuInfo;
 
    /* Get the Vendor ID and null-terminate it */
    KiCpuId(&CpuInfo, 0);
 
    /* Copy it to the PRCB and null-terminate it */
    *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
    *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
    *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
    Prcb->VendorString[12] = 0;
 
    /* Now check the CPU Type */
    if (!strcmp((PCHAR)Prcb->VendorString, CmpIntelID))
    {
        Prcb->CpuVendor = CPU_INTEL;
    }
    else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
    {
        Prcb->CpuVendor = CPU_AMD;
    }
    else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
    {
        DPRINT1("VIA CPUs not fully supported\n");
        Prcb->CpuVendor = CPU_VIA;
    }
    else
    {
        /* Invalid CPU */
        DPRINT1("%s CPU support not fully tested!\n", Prcb->VendorString);
        Prcb->CpuVendor = CPU_UNKNOWN;
    }
 
    return Prcb->CpuVendor;
}

Referenced by KiGetCacheInformation(), KiGetFeatureBits(), and KiSetProcessorType().

KiGetFeatureBits()

ULONG NTAPI KiGetFeatureBits

(

VOID

)

Definition at line 150 of file cpu.c.

{
    PKPRCB Prcb = KeGetCurrentPrcb();
    ULONG Vendor;
    ULONG FeatureBits = KF_WORKING_PTE;
    CPU_INFO CpuInfo;
 
    /* Get the Vendor ID */
    Vendor = Prcb->CpuVendor;
 
    /* Make sure we got a valid vendor ID at least. */
    if (!Vendor) return FeatureBits;
 
    /* Get the CPUID Info. */
    KiCpuId(&CpuInfo, 1);
 
    /* Set the initial APIC ID */
    Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
 
    /* Convert all CPUID Feature bits into our format */
    if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4;
    if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
    if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC;
    if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B;
    if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL;
    if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR;
    if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
    if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV;
    if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT;
    if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS;
    if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX;
    if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR;
    if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI;
    if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64;
 
    if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3;
    //if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR;
    //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP;
    if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B;
    //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41;
    //if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT;
    if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE;
 
    /* Check if the CPU has hyper-threading */
    if (CpuInfo.Edx & X86_FEATURE_HT)
    {
        /* Set the number of logical CPUs */
        Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
        if (Prcb->LogicalProcessorsPerPhysicalProcessor > 1)
        {
            /* We're on dual-core */
            KiSMTProcessorsPresent = TRUE;
        }
    }
    else
    {
        /* We only have a single CPU */
        Prcb->LogicalProcessorsPerPhysicalProcessor = 1;
    }
 
    /* Check extended cpuid features */
    KiCpuId(&CpuInfo, 0x80000000);
    if ((CpuInfo.Eax & 0xffffff00) == 0x80000000)
    {
        /* Check if CPUID 0x80000001 is supported */
        if (CpuInfo.Eax >= 0x80000001)
        {
            /* Check which extended features are available. */
            KiCpuId(&CpuInfo, 0x80000001);
 
            /* Check if NX-bit is supported */
            if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT;
 
            /* Now handle each features for each CPU Vendor */
            switch (Vendor)
            {
                case CPU_AMD:
                    if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW;
                    break;
            }
        }
    }
 
    /* Return the Feature Bits */
    return FeatureBits;
}

KiRestoreProcessorControlState()

VOID NTAPI KiRestoreProcessorControlState

(

PKPROCESSOR_STATE

ProcessorState

)

Definition at line 355 of file cpu.c.

{
    /* Restore the CR registers */
    __writecr0(ProcessorState->SpecialRegisters.Cr0);
//    __writecr2(ProcessorState->SpecialRegisters.Cr2);
    __writecr3(ProcessorState->SpecialRegisters.Cr3);
    __writecr4(ProcessorState->SpecialRegisters.Cr4);
    __writecr8(ProcessorState->SpecialRegisters.Cr8);
 
    /* Restore the DR registers */
    __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
    __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
    __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
    __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
    __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
    __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
 
    /* Restore GDT, IDT, LDT and TSS */
    __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
//    __lldt(&ProcessorState->SpecialRegisters.Ldtr);
//    __ltr(&ProcessorState->SpecialRegisters.Tr);
    __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
 
    _mm_setcsr(ProcessorState->SpecialRegisters.MxCsr);
//    ProcessorState->SpecialRegisters.DebugControl
//    ProcessorState->SpecialRegisters.LastBranchToRip
//    ProcessorState->SpecialRegisters.LastBranchFromRip
//    ProcessorState->SpecialRegisters.LastExceptionToRip
//    ProcessorState->SpecialRegisters.LastExceptionFromRip
 
    /* Restore MSRs */
    __writemsr(X86_MSR_GSBASE, ProcessorState->SpecialRegisters.MsrGsBase);
    __writemsr(X86_MSR_KERNEL_GSBASE, ProcessorState->SpecialRegisters.MsrGsSwap);
    __writemsr(X86_MSR_STAR, ProcessorState->SpecialRegisters.MsrStar);
    __writemsr(X86_MSR_LSTAR, ProcessorState->SpecialRegisters.MsrLStar);
    __writemsr(X86_MSR_CSTAR, ProcessorState->SpecialRegisters.MsrCStar);
    __writemsr(X86_MSR_SFMASK, ProcessorState->SpecialRegisters.MsrSyscallMask);
 
}

KiSaveProcessorControlState()

VOID NTAPI KiSaveProcessorControlState

(

OUT PKPROCESSOR_STATE

ProcessorState

)

Definition at line 397 of file cpu.c.

{
    /* Save the CR registers */
    ProcessorState->SpecialRegisters.Cr0 = __readcr0();
    ProcessorState->SpecialRegisters.Cr2 = __readcr2();
    ProcessorState->SpecialRegisters.Cr3 = __readcr3();
    ProcessorState->SpecialRegisters.Cr4 = __readcr4();
    ProcessorState->SpecialRegisters.Cr8 = __readcr8();
 
    /* Save the DR registers */
    ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
    ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
    ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
    ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
    ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
    ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
 
    /* Save GDT, IDT, LDT and TSS */
    __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
    __sldt(&ProcessorState->SpecialRegisters.Ldtr);
    __str(&ProcessorState->SpecialRegisters.Tr);
    __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
 
    ProcessorState->SpecialRegisters.MxCsr = _mm_getcsr();
//    ProcessorState->SpecialRegisters.DebugControl =
//    ProcessorState->SpecialRegisters.LastBranchToRip =
//    ProcessorState->SpecialRegisters.LastBranchFromRip =
//    ProcessorState->SpecialRegisters.LastExceptionToRip =
//    ProcessorState->SpecialRegisters.LastExceptionFromRip =
 
    /* Save MSRs */
    ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
    ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
    ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
    ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
    ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
    ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
}

Referenced by KeSaveStateForHibernate(), and KiSaveProcessorState().

KiSetProcessorType()

VOID NTAPI KiSetProcessorType

(

VOID

)

Definition at line 97 of file cpu.c.

{
    CPU_INFO CpuInfo;
    CPU_SIGNATURE CpuSignature;
    BOOLEAN ExtendModel;
    ULONG Stepping, Type, Vendor;
 
    /* This initializes Prcb->CpuVendor */
    Vendor = KiGetCpuVendor();
 
    /* Do CPUID 1 now */
    KiCpuId(&CpuInfo, 1);
 
    /*
     * Get the Stepping and Type. The stepping contains both the
     * Model and the Step, while the Type contains the returned Family.
     *
     * For the stepping, we convert this: zzzzzzxy into this: x0y
     */
    CpuSignature.AsULONG = CpuInfo.Eax;
    Stepping = CpuSignature.Model;
    ExtendModel = (CpuSignature.Family == 15);
#if ( (NTDDI_VERSION >= NTDDI_WINXPSP2) && (NTDDI_VERSION < NTDDI_WS03) ) || (NTDDI_VERSION >= NTDDI_WS03SP1)
    if (CpuSignature.Family == 6)
    {
        ExtendModel |= (Vendor == CPU_INTEL);
#if (NTDDI_VERSION >= NTDDI_WIN8)
        ExtendModel |= (Vendor == CPU_CENTAUR);
#endif
    }
#endif
    if (ExtendModel)
    {
        /* Add ExtendedModel to distinguish from non-extended values. */
        Stepping |= (CpuSignature.ExtendedModel << 4);
    }
    Stepping = (Stepping << 8) | CpuSignature.Step;
    Type = CpuSignature.Family;
    if (CpuSignature.Family == 15)
    {
        /* Add ExtendedFamily to distinguish from non-extended values.
         * It must not be larger than 0xF0 to avoid overflow. */
        Type += min(CpuSignature.ExtendedFamily, 0xF0);
    }
 
    /* Save them in the PRCB */
    KeGetCurrentPrcb()->CpuID = TRUE;
    KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
    KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
}

KxRestoreFloatingPointState()

NTSTATUS NTAPI KxRestoreFloatingPointState

(

IN PKFLOATING_SAVE

FloatingState

)

Definition at line 476 of file cpu.c.

{
    UNREFERENCED_PARAMETER(FloatingState);
    return STATUS_SUCCESS;
}

KxSaveFloatingPointState()

NTSTATUS NTAPI KxSaveFloatingPointState

(

OUT PKFLOATING_SAVE

FloatingState

)

Definition at line 468 of file cpu.c.

{
    UNREFERENCED_PARAMETER(FloatingState);
    return STATUS_SUCCESS;
}

Variable Documentation

CmpAmdID

const CHAR CmpAmdID[] = "AuthenticAMD"

static

Definition at line 35 of file cpu.c.

Referenced by KiGetCpuVendor().

CmpCentaurID

const CHAR CmpCentaurID[] = "CentaurHauls"

static

Definition at line 36 of file cpu.c.

Referenced by KiGetCpuVendor().

CmpIntelID

const CHAR CmpIntelID[] = "GenuineIntel"

static

Definition at line 34 of file cpu.c.

Referenced by KiGetCpuVendor().

KeI386CpuStep

ULONG KeI386CpuStep

Definition at line 23 of file cpu.c.

KeI386CpuType

ULONG KeI386CpuType

Definition at line 22 of file cpu.c.

Referenced by KeInvalidateAllCaches().

KeI386MachineType

ULONG KeI386MachineType

Definition at line 24 of file cpu.c.

Referenced by KiInitializeMachineType().

KeI386NpxPresent

ULONG KeI386NpxPresent = 1

Definition at line 25 of file cpu.c.

Referenced by KeRestoreFloatingPointState(), and KeSaveFloatingPointState().

KeLargestCacheLine

ULONG KeLargestCacheLine = 0x40

Definition at line 26 of file cpu.c.

Referenced by KeGetRecommendedSharedDataAlignment(), and KiGetCacheInformation().

KiBootTss

KTSS64 KiBootTss

Definition at line 19 of file cpu.c.

KiDmaIoCoherency

ULONG KiDmaIoCoherency = 0

Definition at line 27 of file cpu.c.

Referenced by KeSetDmaIoCoherency(), and KiInitializeKernel().

KiSMTProcessorsPresent

BOOLEAN KiSMTProcessorsPresent

Definition at line 28 of file cpu.c.

Referenced by KiGetFeatureBits().

KiTbFlushTimeStamp

volatile LONG KiTbFlushTimeStamp

Definition at line 31 of file cpu.c.

Referenced by KeFlushEntireTb().