ReactOS  0.4.15-dev-2947-g59e1b78
cpu.c File Reference
#include <ntoskrnl.h>
#include <debug.h>
Include dependency graph for cpu.c:

Go to the source code of this file.

Macros

#define NDEBUG
 

Functions

VOID NTAPI KiSetProcessorType (VOID)
 
ULONG NTAPI KiGetCpuVendor (VOID)
 
ULONG NTAPI KiGetFeatureBits (VOID)
 
VOID NTAPI KiGetCacheInformation (VOID)
 
VOID NTAPI KeFlushCurrentTb (VOID)
 
VOID NTAPI KiRestoreProcessorControlState (PKPROCESSOR_STATE ProcessorState)
 
VOID NTAPI KiSaveProcessorControlState (OUT PKPROCESSOR_STATE ProcessorState)
 
VOID NTAPI KeFlushEntireTb (IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
 
KAFFINITY NTAPI KeQueryActiveProcessors (VOID)
 
NTSTATUS NTAPI KxSaveFloatingPointState (OUT PKFLOATING_SAVE FloatingState)
 
NTSTATUS NTAPI KxRestoreFloatingPointState (IN PKFLOATING_SAVE FloatingState)
 
BOOLEAN NTAPI KeInvalidateAllCaches (VOID)
 
ULONG NTAPI KeGetRecommendedSharedDataAlignment (VOID)
 
VOID __cdecl KeSaveStateForHibernate (IN PKPROCESSOR_STATE State)
 
VOID NTAPI KeSetDmaIoCoherency (IN ULONG Coherency)
 

Variables

KTSS64 KiBootTss
 
ULONG KeI386CpuType
 
ULONG KeI386CpuStep
 
ULONG KeI386MachineType
 
ULONG KeI386NpxPresent = 1
 
ULONG KeLargestCacheLine = 0x40
 
ULONG KiDmaIoCoherency = 0
 
BOOLEAN KiSMTProcessorsPresent
 
volatile LONG KiTbFlushTimeStamp
 
static const CHAR CmpIntelID [] = "GenuineIntel"
 
static const CHAR CmpAmdID [] = "AuthenticAMD"
 
static const CHAR CmpCyrixID [] = "CyrixInstead"
 
static const CHAR CmpTransmetaID [] = "GenuineTMx86"
 
static const CHAR CmpCentaurID [] = "CentaurHauls"
 
static const CHAR CmpRiseID [] = "RiseRiseRise"
 

Macro Definition Documentation

◆ NDEBUG

#define NDEBUG

Definition at line 13 of file cpu.c.

Function Documentation

◆ KeFlushCurrentTb()

VOID NTAPI KeFlushCurrentTb ( VOID  )

Definition at line 312 of file cpu.c.

313 {
314  /* Flush the TLB by resetting CR3 */
316 }
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1819
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1795

Referenced by KeFlushEntireTb(), and KiFlushTargetEntireTb().

◆ KeFlushEntireTb()

VOID NTAPI KeFlushEntireTb ( IN BOOLEAN  Invalid,
IN BOOLEAN  AllProcessors 
)

Definition at line 403 of file cpu.c.

405 {
406  KIRQL OldIrql;
407 
408  // FIXME: halfplemented
409  /* Raise the IRQL for the TB Flush */
411 
412  /* Flush the TB for the Current CPU, and update the flush stamp */
414 
415  /* Update the flush stamp and return to original IRQL */
418 
419 }
#define KeLowerIrql(oldIrql)
Definition: env_spec_w32.h:602
UCHAR KIRQL
Definition: env_spec_w32.h:591
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:312
volatile LONG KiTbFlushTimeStamp
Definition: cpu.c:31
#define InterlockedExchangeAdd
Definition: interlocked.h:181
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:790
KIRQL NTAPI KeRaiseIrqlToSynchLevel(VOID)
Definition: pic.c:156

Referenced by MiAllocatePoolPages(), MiDeleteSystemPageableVm(), MiDereferenceSession(), MiMapLockedPagesInUserSpace(), MiProtectFreeNonPagedPool(), MiSetSystemCodeProtection(), MmFreeSpecialPool(), MmMapIoSpace(), and MmUnmapIoSpace().

◆ KeGetRecommendedSharedDataAlignment()

◆ KeInvalidateAllCaches()

BOOLEAN NTAPI KeInvalidateAllCaches ( VOID  )

Definition at line 449 of file cpu.c.

450 {
451  /* Invalidate all caches */
452  __wbinvd();
453  return TRUE;
454 }
#define TRUE
Definition: types.h:120
PPC_QUAL void __wbinvd(void)
Definition: intrin_ppc.h:759

◆ KeQueryActiveProcessors()

KAFFINITY NTAPI KeQueryActiveProcessors ( VOID  )

Definition at line 423 of file cpu.c.

424 {
425  PAGED_CODE();
426 
427  /* Simply return the number of active processors */
428  return KeActiveProcessors;
429 }
KAFFINITY KeActiveProcessors
Definition: krnlinit.c:23
#define PAGED_CODE()

Referenced by get_num_of_processors(), and KeQueryActiveProcessorCount().

◆ KeSaveStateForHibernate()

VOID __cdecl KeSaveStateForHibernate ( IN PKPROCESSOR_STATE  State)

Definition at line 472 of file cpu.c.

473 {
474  /* Capture the context */
475  RtlCaptureContext(&State->ContextFrame);
476 
477  /* Capture the control state */
479 }
VOID NTAPI KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
Definition: cpu.c:362
NTSYSAPI VOID NTAPI RtlCaptureContext(_Out_ PCONTEXT ContextRecord)

◆ KeSetDmaIoCoherency()

VOID NTAPI KeSetDmaIoCoherency ( IN ULONG  Coherency)

Definition at line 486 of file cpu.c.

487 {
488  /* Save the coherency globally */
489  KiDmaIoCoherency = Coherency;
490 }
ULONG KiDmaIoCoherency
Definition: cpu.c:27

◆ KiGetCacheInformation()

VOID NTAPI KiGetCacheInformation ( VOID  )

Definition at line 204 of file cpu.c.

205 {
206  PKIPCR Pcr = (PKIPCR)KeGetPcr();
207  ULONG Vendor;
208  ULONG CacheRequests = 0, i;
209  ULONG CurrentRegister;
210  UCHAR RegisterByte;
211  BOOLEAN FirstPass = TRUE;
212  CPU_INFO CpuInfo;
213 
214  /* Set default L2 size */
215  Pcr->SecondLevelCacheSize = 0;
216 
217  /* Get the Vendor ID and make sure we support CPUID */
218  Vendor = KiGetCpuVendor();
219  if (!Vendor) return;
220 
221  /* Check the Vendor ID */
222  switch (Vendor)
223  {
224  /* Handle Intel case */
225  case CPU_INTEL:
226 
227  /*Check if we support CPUID 2 */
228  KiCpuId(&CpuInfo, 0);
229  if (CpuInfo.Eax >= 2)
230  {
231  /* We need to loop for the number of times CPUID will tell us to */
232  do
233  {
234  /* Do the CPUID call */
235  KiCpuId(&CpuInfo, 2);
236 
237  /* Check if it was the first call */
238  if (FirstPass)
239  {
240  /*
241  * The number of times to loop is the first byte. Read
242  * it and then destroy it so we don't get confused.
243  */
244  CacheRequests = CpuInfo.Eax & 0xFF;
245  CpuInfo.Eax &= 0xFFFFFF00;
246 
247  /* Don't go over this again */
248  FirstPass = FALSE;
249  }
250 
251  /* Loop all 4 registers */
252  for (i = 0; i < 4; i++)
253  {
254  /* Get the current register */
255  CurrentRegister = CpuInfo.AsUINT32[i];
256 
257  /*
258  * If the upper bit is set, then this register should
259  * be skipped.
260  */
261  if (CurrentRegister & 0x80000000) continue;
262 
263  /* Keep looping for every byte inside this register */
264  while (CurrentRegister)
265  {
266  /* Read a byte, skip a byte. */
267  RegisterByte = (UCHAR)(CurrentRegister & 0xFF);
268  CurrentRegister >>= 8;
269  if (!RegisterByte) continue;
270 
271  /*
272  * Valid values are from 0x40 (0 bytes) to 0x49
273  * (32MB), or from 0x80 to 0x89 (same size but
274  * 8-way associative.
275  */
276  if (((RegisterByte > 0x40) &&
277  (RegisterByte <= 0x49)) ||
278  ((RegisterByte > 0x80) &&
279  (RegisterByte <= 0x89)))
280  {
281  /* Mask out only the first nibble */
282  RegisterByte &= 0x0F;
283 
284  /* Set the L2 Cache Size */
285  Pcr->SecondLevelCacheSize = 0x10000 <<
286  RegisterByte;
287  }
288  }
289  }
290  } while (--CacheRequests);
291  }
292  break;
293 
294  case CPU_AMD:
295 
296  /* Check if we support CPUID 0x80000006 */
297  KiCpuId(&CpuInfo, 0x80000000);
298  if (CpuInfo.Eax >= 6)
299  {
300  /* Get 2nd level cache and tlb size */
301  KiCpuId(&CpuInfo, 0x80000006);
302 
303  /* Set the L2 Cache Size */
304  Pcr->SecondLevelCacheSize = (CpuInfo.Ecx & 0xFFFF0000) >> 6;
305  }
306  break;
307  }
308 }
#define TRUE
Definition: types.h:120
struct _KIPCR * PKIPCR
#define KeGetPcr()
Definition: ke.h:26
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:75
#define FALSE
Definition: types.h:117
unsigned char BOOLEAN
ULONG SecondLevelCacheSize
Definition: ketypes.h:885
ULONG Eax
Definition: ketypes.h:300
ULONG Ecx
Definition: ketypes.h:302
unsigned char UCHAR
Definition: xmlstorage.h:181
UINT32 AsUINT32[4]
Definition: ketypes.h:297
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
unsigned int ULONG
Definition: retypes.h:1

◆ KiGetCpuVendor()

ULONG NTAPI KiGetCpuVendor ( VOID  )

Definition at line 75 of file cpu.c.

76 {
77  PKPRCB Prcb = KeGetCurrentPrcb();
78  CPU_INFO CpuInfo;
79 
80  /* Get the Vendor ID and null-terminate it */
81  KiCpuId(&CpuInfo, 0);
82 
83  /* Copy it to the PRCB and null-terminate it */
84  *(ULONG*)&Prcb->VendorString[0] = CpuInfo.Ebx;
85  *(ULONG*)&Prcb->VendorString[4] = CpuInfo.Edx;
86  *(ULONG*)&Prcb->VendorString[8] = CpuInfo.Ecx;
87  Prcb->VendorString[12] = 0;
88 
89  /* Now check the CPU Type */
91  {
92  return CPU_INTEL;
93  }
94  else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
95  {
96  return CPU_AMD;
97  }
98  else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
99  {
100  DPRINT1("VIA CPUs not fully supported\n");
101  return CPU_VIA;
102  }
103  else if (!strcmp((PCHAR)Prcb->VendorString, CmpRiseID))
104  {
105  DPRINT1("Rise CPUs not fully supported\n");
106  return 0;
107  }
108 
109  /* Invalid CPU */
110  return CPU_UNKNOWN;
111 }
static const CHAR CmpRiseID[]
Definition: cpu.c:39
signed char * PCHAR
Definition: retypes.h:7
static const CHAR CmpAmdID[]
Definition: cpu.c:35
static const CHAR CmpCentaurID[]
Definition: cpu.c:38
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1079
UCHAR VendorString[13]
Definition: ketypes.h:801
if(dx==0 &&dy==0)
Definition: linetemp.h:174
ULONG Ebx
Definition: ketypes.h:301
ULONG Ecx
Definition: ketypes.h:302
static const CHAR CmpIntelID[]
Definition: cpu.c:34
#define DPRINT1
Definition: precomp.h:8
unsigned int ULONG
Definition: retypes.h:1
int strcmp(const char *String1, const char *String2)
Definition: utclib.c:469
ULONG Edx
Definition: ketypes.h:303

Referenced by KiGetCacheInformation(), and KiGetFeatureBits().

◆ KiGetFeatureBits()

ULONG NTAPI KiGetFeatureBits ( VOID  )

Definition at line 115 of file cpu.c.

116 {
117  PKPRCB Prcb = KeGetCurrentPrcb();
118  ULONG Vendor;
119  ULONG FeatureBits = KF_WORKING_PTE;
120  CPU_INFO CpuInfo;
121 
122  /* Get the Vendor ID */
123  Vendor = KiGetCpuVendor();
124 
125  /* Make sure we got a valid vendor ID at least. */
126  if (!Vendor) return FeatureBits;
127 
128  /* Get the CPUID Info. */
129  KiCpuId(&CpuInfo, 1);
130 
131  /* Set the initial APIC ID */
132  Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
133 
134  /* Convert all CPUID Feature bits into our format */
135  if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4;
136  if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
137  if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC;
138  if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B;
139  if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL;
140  if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR;
141  if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
142  if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV;
143  if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT;
144  if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS;
145  if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX;
146  if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR;
147  if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI;
148  if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64;
149 
150  if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3;
151  //if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR;
152  //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP;
153  if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B;
154  //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41;
155  //if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT;
156  if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE;
157 
158  /* Check if the CPU has hyper-threading */
159  if (CpuInfo.Edx & X86_FEATURE_HT)
160  {
161  /* Set the number of logical CPUs */
162  Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
164  {
165  /* We're on dual-core */
167  }
168  }
169  else
170  {
171  /* We only have a single CPU */
173  }
174 
175  /* Check extended cpuid features */
176  KiCpuId(&CpuInfo, 0x80000000);
177  if ((CpuInfo.Eax & 0xffffff00) == 0x80000000)
178  {
179  /* Check if CPUID 0x80000001 is supported */
180  if (CpuInfo.Eax >= 0x80000001)
181  {
182  /* Check which extended features are available. */
183  KiCpuId(&CpuInfo, 0x80000001);
184 
185  /* Check if NX-bit is supported */
186  if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT;
187 
188  /* Now handle each features for each CPU Vendor */
189  switch (Vendor)
190  {
191  case CPU_AMD:
192  if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW;
193  break;
194  }
195  }
196  }
197 
198  /* Return the Feature Bits */
199  return FeatureBits;
200 }
#define X86_FEATURE_PGE
Definition: ke.h:35
#define X86_FEATURE_SYSCALL
Definition: ke.h:33
#define X86_FEATURE_VME
Definition: ke.h:27
UCHAR LogicalProcessorsPerPhysicalProcessor
Definition: ketypes.h:705
#define KF_CMPXCHG8B
Definition: ketypes.h:150
#define TRUE
Definition: types.h:120
#define X86_FEATURE_MMX
Definition: ke.h:39
#define X86_FEATURE_SSE2
Definition: ke.h:42
#define X86_FEATURE_HT
Definition: ke.h:43
#define KF_RDTSC
Definition: ketypes.h:144
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1079
#define KF_MMX
Definition: ketypes.h:151
#define X86_FEATURE_FXSR
Definition: ke.h:40
#define KF_NX_BIT
Definition: ketypes.h:165
#define X86_FEATURE_XSAVE
Definition: ke.h:56
ULONG NTAPI KiGetCpuVendor(VOID)
Definition: cpu.c:75
#define KF_LARGE_PAGE
Definition: ketypes.h:148
#define KF_PAT
Definition: ketypes.h:153
#define KF_XMMI
Definition: ketypes.h:156
#define X86_FEATURE_CX16
Definition: ke.h:51
#define X86_FEATURE_PSE
Definition: ke.h:29
ULONG Eax
Definition: ketypes.h:300
#define X86_FEATURE_PAT
Definition: ke.h:37
#define KF_CR4
Definition: ketypes.h:145
ULONG Ebx
Definition: ketypes.h:301
#define KF_MTRR
Definition: ketypes.h:149
ULONG Ecx
Definition: ketypes.h:302
#define X86_FEATURE_NX
Definition: ke.h:59
#define KF_WORKING_PTE
Definition: ketypes.h:152
#define KF_FAST_SYSCALL
Definition: ketypes.h:155
#define KF_V86_VIS
Definition: ketypes.h:143
#define KF_FXSR
Definition: ketypes.h:154
#define KF_3DNOW
Definition: ketypes.h:157
#define X86_FEATURE_MTTR
Definition: ke.h:34
unsigned char UCHAR
Definition: xmlstorage.h:181
#define KF_XMMI64
Definition: ketypes.h:159
#define KF_CMPXCHG16B
Definition: ketypes.h:163
#define X86_FEATURE_SSE
Definition: ke.h:41
#define X86_FEATURE_CX8
Definition: ke.h:32
#define KF_SSE3
Definition: ketypes.h:162
#define X86_FEATURE_CMOV
Definition: ke.h:36
unsigned int ULONG
Definition: retypes.h:1
#define KF_DTS
Definition: ketypes.h:160
#define X86_FEATURE_TSC
Definition: ke.h:30
#define KF_XSTATE
Definition: ketypes.h:164
#define X86_FEATURE_DS
Definition: ke.h:38
#define KF_GLOBAL_PAGE
Definition: ketypes.h:147
ULONG Edx
Definition: ketypes.h:303
BOOLEAN KiSMTProcessorsPresent
Definition: cpu.c:28
#define KF_CMOV
Definition: ketypes.h:146
#define X86_FEATURE_SSE3
Definition: ke.h:46
ULONG InitialApicId
Definition: ketypes.h:621

◆ KiRestoreProcessorControlState()

VOID NTAPI KiRestoreProcessorControlState ( PKPROCESSOR_STATE  ProcessorState)

Definition at line 320 of file cpu.c.

321 {
322  /* Restore the CR registers */
323  __writecr0(ProcessorState->SpecialRegisters.Cr0);
324 // __writecr2(ProcessorState->SpecialRegisters.Cr2);
325  __writecr3(ProcessorState->SpecialRegisters.Cr3);
326  __writecr4(ProcessorState->SpecialRegisters.Cr4);
327  __writecr8(ProcessorState->SpecialRegisters.Cr8);
328 
329  /* Restore the DR registers */
330  __writedr(0, ProcessorState->SpecialRegisters.KernelDr0);
331  __writedr(1, ProcessorState->SpecialRegisters.KernelDr1);
332  __writedr(2, ProcessorState->SpecialRegisters.KernelDr2);
333  __writedr(3, ProcessorState->SpecialRegisters.KernelDr3);
334  __writedr(6, ProcessorState->SpecialRegisters.KernelDr6);
335  __writedr(7, ProcessorState->SpecialRegisters.KernelDr7);
336 
337  /* Restore GDT, IDT, LDT and TSS */
338  __lgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
339 // __lldt(&ProcessorState->SpecialRegisters.Ldtr);
340 // __ltr(&ProcessorState->SpecialRegisters.Tr);
341  __lidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
342 
343 // __ldmxcsr(&ProcessorState->SpecialRegisters.MxCsr); // FIXME
344 // ProcessorState->SpecialRegisters.DebugControl
345 // ProcessorState->SpecialRegisters.LastBranchToRip
346 // ProcessorState->SpecialRegisters.LastBranchFromRip
347 // ProcessorState->SpecialRegisters.LastExceptionToRip
348 // ProcessorState->SpecialRegisters.LastExceptionFromRip
349 
350  /* Restore MSRs */
357 
358 }
__INTRIN_INLINE void __writecr4(unsigned int Data)
Definition: intrin_x86.h:1800
__INTRIN_INLINE void __writedr(unsigned reg, unsigned int value)
Definition: intrin_x86.h:1936
#define X86_MSR_STAR
Definition: ke.h:69
ULONG64 KernelDr7
Definition: ketypes.h:509
#define X86_MSR_CSTAR
Definition: ke.h:71
ULONG64 KernelDr2
Definition: ketypes.h:506
__INTRIN_INLINE void __lidt(void *Source)
Definition: intrin_x86.h:2019
ULONG64 MsrLStar
Definition: ketypes.h:524
KSPECIAL_REGISTERS SpecialRegisters
Definition: ketypes.h:534
#define X86_MSR_LSTAR
Definition: ke.h:70
ULONG64 KernelDr1
Definition: ketypes.h:505
USHORT Limit
Definition: ketypes.h:489
__INTRIN_INLINE void __writecr3(unsigned int Data)
Definition: intrin_x86.h:1795
ULONG64 MsrGsSwap
Definition: ketypes.h:522
ULONG64 MsrCStar
Definition: ketypes.h:525
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:67
__INTRIN_INLINE void __writecr0(unsigned int Data)
Definition: intrin_x86.h:1790
KDESCRIPTOR Gdtr
Definition: ketypes.h:510
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
#define X86_MSR_GSBASE
Definition: ke.h:66
ULONG64 KernelDr3
Definition: ketypes.h:507
#define X86_MSR_SFMASK
Definition: ke.h:72
ULONG64 MsrSyscallMask
Definition: ketypes.h:526
ULONG64 KernelDr6
Definition: ketypes.h:508
ULONG64 KernelDr0
Definition: ketypes.h:504
ULONG64 MsrGsBase
Definition: ketypes.h:521
KDESCRIPTOR Idtr
Definition: ketypes.h:511

◆ KiSaveProcessorControlState()

VOID NTAPI KiSaveProcessorControlState ( OUT PKPROCESSOR_STATE  ProcessorState)

Definition at line 362 of file cpu.c.

363 {
364  /* Save the CR registers */
365  ProcessorState->SpecialRegisters.Cr0 = __readcr0();
366  ProcessorState->SpecialRegisters.Cr2 = __readcr2();
367  ProcessorState->SpecialRegisters.Cr3 = __readcr3();
368  ProcessorState->SpecialRegisters.Cr4 = __readcr4();
369  ProcessorState->SpecialRegisters.Cr8 = __readcr8();
370 
371  /* Save the DR registers */
372  ProcessorState->SpecialRegisters.KernelDr0 = __readdr(0);
373  ProcessorState->SpecialRegisters.KernelDr1 = __readdr(1);
374  ProcessorState->SpecialRegisters.KernelDr2 = __readdr(2);
375  ProcessorState->SpecialRegisters.KernelDr3 = __readdr(3);
376  ProcessorState->SpecialRegisters.KernelDr6 = __readdr(6);
377  ProcessorState->SpecialRegisters.KernelDr7 = __readdr(7);
378 
379  /* Save GDT, IDT, LDT and TSS */
380  __sgdt(&ProcessorState->SpecialRegisters.Gdtr.Limit);
381  __sldt(&ProcessorState->SpecialRegisters.Ldtr);
382  __str(&ProcessorState->SpecialRegisters.Tr);
383  __sidt(&ProcessorState->SpecialRegisters.Idtr.Limit);
384 
385 // __stmxcsr(&ProcessorState->SpecialRegisters.MxCsr);
386 // ProcessorState->SpecialRegisters.DebugControl =
387 // ProcessorState->SpecialRegisters.LastBranchToRip =
388 // ProcessorState->SpecialRegisters.LastBranchFromRip =
389 // ProcessorState->SpecialRegisters.LastExceptionToRip =
390 // ProcessorState->SpecialRegisters.LastExceptionFromRip =
391 
392  /* Save MSRs */
393  ProcessorState->SpecialRegisters.MsrGsBase = __readmsr(X86_MSR_GSBASE);
394  ProcessorState->SpecialRegisters.MsrGsSwap = __readmsr(X86_MSR_KERNEL_GSBASE);
395  ProcessorState->SpecialRegisters.MsrStar = __readmsr(X86_MSR_STAR);
396  ProcessorState->SpecialRegisters.MsrLStar = __readmsr(X86_MSR_LSTAR);
397  ProcessorState->SpecialRegisters.MsrCStar = __readmsr(X86_MSR_CSTAR);
398  ProcessorState->SpecialRegisters.MsrSyscallMask = __readmsr(X86_MSR_SFMASK);
399 }
__INTRIN_INLINE unsigned long __readcr2(void)
Definition: intrin_x86.h:1812
#define X86_MSR_STAR
Definition: ke.h:69
#define X86_MSR_CSTAR
Definition: ke.h:71
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1819
#define X86_MSR_LSTAR
Definition: ke.h:70
#define X86_MSR_KERNEL_GSBASE
Definition: ke.h:67
__INTRIN_INLINE void __sidt(void *Destination)
Definition: intrin_x86.h:2024
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
__INTRIN_INLINE unsigned int __readdr(unsigned int reg)
Definition: intrin_x86.h:1903
__INTRIN_INLINE unsigned long __readcr0(void)
Definition: intrin_x86.h:1805
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1826
#define X86_MSR_GSBASE
Definition: ke.h:66
#define X86_MSR_SFMASK
Definition: ke.h:72

Referenced by KeSaveStateForHibernate(), and KiSaveProcessorState().

◆ KiSetProcessorType()

VOID NTAPI KiSetProcessorType ( VOID  )

Definition at line 45 of file cpu.c.

46 {
47  CPU_INFO CpuInfo;
48  ULONG Stepping, Type;
49 
50  /* Do CPUID 1 now */
51  KiCpuId(&CpuInfo, 1);
52 
53  /*
54  * Get the Stepping and Type. The stepping contains both the
55  * Model and the Step, while the Type contains the returned Type.
56  * We ignore the family.
57  *
58  * For the stepping, we convert this: zzzzzzxy into this: x0y
59  */
60  Stepping = CpuInfo.Eax & 0xF0;
61  Stepping <<= 4;
62  Stepping += (CpuInfo.Eax & 0xFF);
63  Stepping &= 0xF0F;
64  Type = CpuInfo.Eax & 0xF00;
65  Type >>= 8;
66 
67  /* Save them in the PRCB */
68  KeGetCurrentPrcb()->CpuID = TRUE;
69  KeGetCurrentPrcb()->CpuType = (UCHAR)Type;
70  KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
71 }
#define TRUE
Definition: types.h:120
FORCEINLINE struct _KPRCB * KeGetCurrentPrcb(VOID)
Definition: ketypes.h:1079
ULONG Eax
Definition: ketypes.h:300
Type
Definition: Type.h:6
unsigned char UCHAR
Definition: xmlstorage.h:181
unsigned short USHORT
Definition: pedump.c:61
unsigned int ULONG
Definition: retypes.h:1

◆ KxRestoreFloatingPointState()

NTSTATUS NTAPI KxRestoreFloatingPointState ( IN PKFLOATING_SAVE  FloatingState)

Definition at line 441 of file cpu.c.

442 {
443  UNREFERENCED_PARAMETER(FloatingState);
444  return STATUS_SUCCESS;
445 }
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317
#define STATUS_SUCCESS
Definition: shellext.h:65

◆ KxSaveFloatingPointState()

NTSTATUS NTAPI KxSaveFloatingPointState ( OUT PKFLOATING_SAVE  FloatingState)

Definition at line 433 of file cpu.c.

434 {
435  UNREFERENCED_PARAMETER(FloatingState);
436  return STATUS_SUCCESS;
437 }
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317
#define STATUS_SUCCESS
Definition: shellext.h:65

Variable Documentation

◆ CmpAmdID

const CHAR CmpAmdID[] = "AuthenticAMD"
static

Definition at line 35 of file cpu.c.

Referenced by KiGetCpuVendor().

◆ CmpCentaurID

const CHAR CmpCentaurID[] = "CentaurHauls"
static

Definition at line 38 of file cpu.c.

Referenced by KiGetCpuVendor().

◆ CmpCyrixID

const CHAR CmpCyrixID[] = "CyrixInstead"
static

Definition at line 36 of file cpu.c.

◆ CmpIntelID

const CHAR CmpIntelID[] = "GenuineIntel"
static

Definition at line 34 of file cpu.c.

Referenced by KiGetCpuVendor().

◆ CmpRiseID

const CHAR CmpRiseID[] = "RiseRiseRise"
static

Definition at line 39 of file cpu.c.

Referenced by KiGetCpuVendor().

◆ CmpTransmetaID

const CHAR CmpTransmetaID[] = "GenuineTMx86"
static

Definition at line 37 of file cpu.c.

◆ KeI386CpuStep

ULONG KeI386CpuStep

Definition at line 23 of file cpu.c.

◆ KeI386CpuType

ULONG KeI386CpuType

Definition at line 22 of file cpu.c.

Referenced by KeInvalidateAllCaches().

◆ KeI386MachineType

ULONG KeI386MachineType

Definition at line 24 of file cpu.c.

Referenced by KiInitializeMachineType().

◆ KeI386NpxPresent

ULONG KeI386NpxPresent = 1

Definition at line 25 of file cpu.c.

Referenced by KeSaveFloatingPointState().

◆ KeLargestCacheLine

ULONG KeLargestCacheLine = 0x40

Definition at line 26 of file cpu.c.

Referenced by KeGetRecommendedSharedDataAlignment(), and KiGetCacheInformation().

◆ KiBootTss

KTSS64 KiBootTss

Definition at line 19 of file cpu.c.

◆ KiDmaIoCoherency

ULONG KiDmaIoCoherency = 0

Definition at line 27 of file cpu.c.

Referenced by KeSetDmaIoCoherency(), and KiInitializeKernel().

◆ KiSMTProcessorsPresent

BOOLEAN KiSMTProcessorsPresent

Definition at line 28 of file cpu.c.

Referenced by KiGetFeatureBits().

◆ KiTbFlushTimeStamp

volatile LONG KiTbFlushTimeStamp

Definition at line 31 of file cpu.c.

Referenced by KeFlushEntireTb().