15 #define MODULE_INVOLVED_IN_ARM3 72 #if !defined(_M_AMD64) 101 if (!PointerPte)
return NULL;
126 switch (CacheAttribute)
180 }
while (--PageCount);
#define MI_PAGE_WRITE_COMBINED(x)
PMMPTE NTAPI MiReserveSystemPtes(IN ULONG NumberOfPtes, IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType)
PVOID NTAPI MmMapIoSpace(IN PHYSICAL_ADDRESS PhysicalAddress, IN SIZE_T NumberOfBytes, IN MEMORY_CACHING_TYPE CacheType)
enum _MI_PFN_CACHE_ATTRIBUTE MI_PFN_CACHE_ATTRIBUTE
#define MiAddressToPte(x)
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
FORCEINLINE VOID MI_WRITE_VALID_PTE(IN PMMPTE PointerPte, IN MMPTE TempPte)
MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType]
PVOID NTAPI MmMapVideoDisplay(IN PHYSICAL_ADDRESS PhysicalAddress, IN SIZE_T NumberOfBytes, IN MEMORY_CACHING_TYPE CacheType)
_Must_inspect_result_ _In_ PHYSICAL_ADDRESS _In_ PHYSICAL_ADDRESS _In_opt_ PHYSICAL_ADDRESS _In_ MEMORY_CACHING_TYPE CacheType
VOID NTAPI MiReleaseSystemPtes(IN PMMPTE StartingPte, IN ULONG NumberOfPtes, IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType)
VOID NTAPI KeFlushEntireTb(IN BOOLEAN Invalid, IN BOOLEAN AllProcessors)
#define ADDRESS_AND_SIZE_TO_SPAN_PAGES(_Va, _Size)
BOOLEAN NTAPI KeInvalidateAllCaches(VOID)
_In_ HANDLE _Outptr_result_bytebuffer_ ViewSize PVOID * BaseAddress
HARDWARE_PTE_ARMV6 TempPte
#define MI_PAGE_WRITE_THROUGH(x)
LOGICAL NTAPI MmIsIoSpaceActive(IN PHYSICAL_ADDRESS StartAddress, IN SIZE_T NumberOfBytes)
_Must_inspect_result_ typedef _In_ PHYSICAL_ADDRESS PhysicalAddress
FORCEINLINE PMMPFN MiGetPfnEntry(IN PFN_NUMBER Pfn)
VOID NTAPI MmUnmapIoSpace(IN PVOID BaseAddress, IN SIZE_T NumberOfBytes)
_Must_inspect_result_ typedef _In_ PHYSICAL_ADDRESS _Inout_ PLARGE_INTEGER NumberOfBytes
#define MI_PAGE_DISABLE_CACHE(x)
VOID NTAPI MmUnmapVideoDisplay(IN PVOID BaseAddress, IN SIZE_T NumberOfBytes)
#define RtlZeroMemory(Destination, Length)
FORCEINLINE PVOID MiPteToAddress(PMMPTE PointerPte)
enum _MEMORY_CACHING_TYPE MEMORY_CACHING_TYPE