ReactOS 0.4.15-dev-7942-gd23573b
mm.h
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1/*
2 * kernel internal memory management definitions for amd64
3 */
4#pragma once
5
6#define _MI_PAGING_LEVELS 4
7#define _MI_HAS_NO_EXECUTE 1
8
9/* Memory layout base addresses (This is based on Vista!) */
10#define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL
11#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL
12#define MI_REAL_SYSTEM_RANGE_START 0xFFFF800000000000ULL
13//#define MI_PAGE_TABLE_BASE 0xFFFFF68000000000ULL // 512 GB page tables
14#define HYPER_SPACE 0xFFFFF70000000000ULL // 512 GB hyper space [MiVaProcessSpace]
15#define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
16//#define MI_SHARED_SYSTEM_PAGE 0xFFFFF78000000000ULL
17#define MI_SYSTEM_CACHE_WS_START 0xFFFFF78000001000ULL // 512 GB - 4 KB system cache working set
18//#define MI_LOADER_MAPPINGS 0xFFFFF80000000000ULL // 512 GB loader mappings aka KSEG0_BASE (NDK) [MiVaBootLoaded]
19#define MM_SYSTEM_SPACE_START 0xFFFFF88000000000ULL // 128 GB system PTEs [MiVaSystemPtes]
20#define MI_DEBUG_MAPPING (PVOID)0xFFFFF89FFFFFF000ULL // FIXME should be allocated from System PTEs
21#define MI_PAGED_POOL_START (PVOID)0xFFFFF8A000000000ULL // 128 GB paged pool [MiVaPagedPool]
22//#define MI_PAGED_POOL_END 0xFFFFF8BFFFFFFFFFULL
23//#define MI_SESSION_SPACE_START 0xFFFFF90000000000ULL // 512 GB session space [MiVaSessionSpace]
24//#define MI_SESSION_VIEW_END 0xFFFFF97FFF000000ULL
25#define MI_SESSION_SPACE_END 0xFFFFF98000000000ULL
26#define MI_SYSTEM_CACHE_START 0xFFFFF98000000000ULL // 1 TB system cache (on Vista+ this is dynamic VA space) [MiVaSystemCache,MiVaSpecialPoolPaged,MiVaSpecialPoolNonPaged]
27#define MI_SYSTEM_CACHE_END 0xFFFFFA7FFFFFFFFFULL
28#define MI_PFN_DATABASE 0xFFFFFA8000000000ULL // up to 5.5 TB PFN database followed by non paged pool [MiVaPfnDatabase/MiVaNonPagedPool]
29#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFFFFFFBFFFFFULL
30//#define MM_HAL_VA_START 0xFFFFFFFFFFC00000ULL // 4 MB HAL mappings, defined in NDK [MiVaHal]
31#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
32#define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
33
34/* WOW64 address definitions */
35#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
36#define MM_SYSTEM_RANGE_START_WOW64 0x80000000
37
38/* The size of the virtual memory area that is mapped using a single PDE */
39#define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
40
41/* Misc address definitions */
42//#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME
43//#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START
44//#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
45#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE)
46#define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
47#define MI_MAPPING_RANGE_START HYPER_SPACE
48#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
49#define MI_DUMMY_PTE (MI_MAPPING_RANGE_END + PAGE_SIZE)
50#define MI_VAD_BITMAP (MI_DUMMY_PTE + PAGE_SIZE)
51#define MI_WORKING_SET_LIST (MI_VAD_BITMAP + PAGE_SIZE)
52
53/* Memory sizes */
54#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
55#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
56#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
57#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
58#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
59#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
60#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
61#define MI_SYSTEM_VIEW_SIZE (104 * _1MB)
62#define MI_SESSION_VIEW_SIZE (104 * _1MB)
63#define MI_SESSION_POOL_SIZE (64 * _1MB)
64#define MI_SESSION_IMAGE_SIZE (16 * _1MB)
65#define MI_SESSION_WORKING_SET_SIZE (16 * _1MB)
66#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
67 MI_SESSION_POOL_SIZE + \
68 MI_SESSION_IMAGE_SIZE + \
69 MI_SESSION_WORKING_SET_SIZE)
70#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
71#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
72#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
73
74/* Misc constants */
75#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
76#define MI_MIN_SECONDARY_COLORS 8
77#define MI_SECONDARY_COLORS 64
78#define MI_MAX_SECONDARY_COLORS 1024
79#define MI_NUMBER_SYSTEM_PTES 22000
80#define MI_MAX_FREE_PAGE_LISTS 4
81#define MI_HYPERSPACE_PTES (256 - 1)
82#define MI_ZERO_PTES (32)
83#define MI_MAX_ZERO_BITS 53
84#define SESSION_POOL_LOOKASIDES 21
85
86/* MMPTE related defines */
87#define MM_EMPTY_PTE_LIST ((ULONG64)0xFFFFFFFF)
88#define MM_EMPTY_LIST ((ULONG_PTR)-1)
89
90
91/* Easy accessing PFN in PTE */
92#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
93#define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
94#define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
95#define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
96
97/* Macros for portable PTE modification */
98#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
99#define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0)
100#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
101#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
102#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
103#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
104#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
105#if !defined(CONFIG_SMP)
106#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
107#else
108#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
109#endif
110#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
111#define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0)
112#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
113#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
114#if !defined(CONFIG_SMP)
115#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
116#else
117#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
118#endif
119
120/* Macros to identify the page fault reason from the error code */
121#define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x00000001)
122#define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x00000002)
123// 0x00000004: user-mode access.
124// 0x00000008: reserved bit violation.
125#define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x00000010)
126// 0x00000020: protection-key violation.
127// 0x00000040: shadow-stack access.
128// Bits 7-14: reserved.
129// 0x00008000: violation of SGX-specific access-control requirements.
130// Bits 16-31: reserved.
131
132/* On x64, these are the same */
133#define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
134#define ValidKernelPpe ValidKernelPde
135
136/* Convert an address to a corresponding PTE */
138PMMPTE
140{
142 Offset &= 0xFFFFFFFFFULL << 3;
143 return (PMMPTE)(PTE_BASE + Offset);
144}
145#define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
146
147/* Convert an address to a corresponding PDE */
149PMMPTE
151{
153 Offset &= 0x7FFFFFF << 3;
154 return (PMMPTE)(PDE_BASE + Offset);
155}
156#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
157
158/* Convert an address to a corresponding PPE */
160PMMPTE
162{
164 Offset &= 0x3FFFF << 3;
165 return (PMMPTE)(PPE_BASE + Offset);
166}
167
168/* Convert an address to a corresponding PXE */
170PMMPTE
172{
174 Offset &= PXI_MASK << 3;
175 return (PMMPTE)(PXE_BASE + Offset);
176}
177
178/* Convert an address to a corresponding PTE offset/index */
180ULONG
182{
183 return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
184}
185#define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
186
187/* Convert an address to a corresponding PDE offset/index */
189ULONG
191{
192 return ((((ULONG64)Address) >> PDI_SHIFT) & 0x1FF);
193}
194#define MiAddressToPdeOffset(x) MiAddressToPdi(x)
195#define MiGetPdeOffset(x) MiAddressToPdi(x)
196
197/* Convert an address to a corresponding PXE offset/index */
199ULONG
201{
202 return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
203}
204
205/* Convert a PTE into a corresponding address */
207PVOID
209{
210 /* Use signed math */
211 return (PVOID)(((LONG64)PointerPte << 25) >> 16);
212}
213
214/* Convert a PDE into a corresponding address */
216PVOID
218{
219 /* Use signed math */
220 return (PVOID)(((LONG64)PointerPde << 34) >> 16);
221}
222
223/* Convert a PPE into a corresponding address */
225PVOID
227{
228 /* Use signed math */
229 return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
230}
231
232/* Convert a PXE into a corresponding address */
234PVOID
236{
237 /* Use signed math */
238 return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
239}
240
241/* Convert a PDE into its lowest PTE */
243PMMPTE
245{
246 return (PMMPTE)MiPteToAddress(PointerPde);
247}
248
249/* Convert a PPE into its lowest PTE */
251PMMPTE
253{
254 return (PMMPTE)MiPdeToAddress(PointerPpe);
255}
256
257/* Convert a PXE into its lowest PTE */
259PMMPTE
261{
262 return (PMMPTE)MiPpeToAddress(PointerPxe);
263}
264
265/* Convert a PTE to a corresponding PDE */
267PMMPDE
269{
270 return (PMMPDE)MiAddressToPte(PointerPte);
271}
272
273/* Convert a PTE to a corresponding PPE */
275PMMPPE
277{
278 return (PMMPPE)MiAddressToPde(PointerPte);
279}
280
281/* Convert a PTE to a corresponding PXE */
283PMMPXE
285{
286 return (PMMPXE)MiAddressToPpe(PointerPte);
287}
288
289/* Convert a PDE to a corresponding PPE */
291PMMPDE
293{
294 return (PMMPPE)MiAddressToPte(PointerPde);
295}
296
297/* Convert a PDE to a corresponding PXE */
299PMMPXE
301{
302 return (PMMPXE)MiAddressToPde(PointerPde);
303}
304
305/* Check P*E boundaries */
306#define MiIsPteOnPdeBoundary(PointerPte) \
307 ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
308#define MiIsPteOnPpeBoundary(PointerPte) \
309 ((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
310#define MiIsPteOnPxeBoundary(PointerPte) \
311 ((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
312
313//
314// Decodes a Prototype PTE into the underlying PTE
315//
316#define MiProtoPteToPte(x) \
317 (PMMPTE)(((LONG64)(x)->u.Long) >> 16) /* Sign extend 48 bits */
318
319//
320// Decodes a Prototype PTE into the underlying PTE
321// The 48 bit signed value gets sign-extended to 64 bits.
322//
323#define MiSubsectionPteToSubsection(x) \
324 (PMMPTE)((LONG64)(x)->u.Subsect.SubsectionAddress)
325
327VOID
329 _Out_ PMMPTE NewPte,
331{
332 /* Mark this as a prototype */
333 NewPte->u.Long = 0;
334 NewPte->u.Subsect.Prototype = 1;
335
336 /* Store the lower 48 bits of the Segment address */
337 NewPte->u.Subsect.SubsectionAddress = ((ULONG_PTR)Segment & 0x0000FFFFFFFFFFFF);
338}
339
341VOID
343 IN PMMPTE PointerPte)
344{
345 /* Store the Address */
346 NewPte->u.Long = (ULONG64)PointerPte << 16;
347
348 /* Mark this as a prototype PTE */
349 NewPte->u.Proto.Prototype = 1;
350
351 ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
352}
353
357{
358 return ((PointerPte->u.Hard.Valid != 0) ||
359 (PointerPte->u.Proto.Prototype != 0) ||
360 (PointerPte->u.Trans.Transition != 0) ||
361 (PointerPte->u.Hard.PageFrameNumber != 0));
362}
363
367{
368 return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
369 (MiAddressToPpe(Address)->u.Hard.Valid) &&
370 (MiAddressToPde(Address)->u.Hard.Valid));
371}
372
unsigned char BOOLEAN
#define PDE_BASE
Definition: winldr.c:21
#define ULONG_PTR
Definition: config.h:101
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble * u
Definition: glfuncs.h:240
#define PTE_BASE
Definition: mmx86.c:14
#define ASSERT(a)
Definition: mode.c:44
unsigned __int64 ULONG64
Definition: imports.h:198
#define _Out_
Definition: ms_sal.h:345
#define _In_
Definition: ms_sal.h:308
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
FORCEINLINE ULONG MiAddressToPxi(PVOID Address)
Definition: mm.h:200
FORCEINLINE PMMPXE MiPdeToPxe(PMMPDE PointerPde)
Definition: mm.h:300
#define MiAddressToPte(x)
Definition: mm.h:145
FORCEINLINE PVOID MiPpeToAddress(PMMPTE PointerPpe)
Definition: mm.h:226
FORCEINLINE PMMPDE MiPdeToPpe(PMMPDE PointerPde)
Definition: mm.h:292
FORCEINLINE PMMPPE MiPteToPpe(PMMPTE PointerPte)
Definition: mm.h:276
FORCEINLINE PMMPTE MiPxeToPte(PMMPXE PointerPxe)
Definition: mm.h:260
FORCEINLINE ULONG MiAddressToPdi(PVOID Address)
Definition: mm.h:190
FORCEINLINE VOID MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte, IN PMMPTE PointerPte)
Definition: mm.h:342
FORCEINLINE BOOLEAN MiIsPdeForAddressValid(PVOID Address)
Definition: mm.h:366
FORCEINLINE PMMPTE MiPpeToPte(PMMPPE PointerPpe)
Definition: mm.h:252
FORCEINLINE PMMPTE _MiAddressToPte(PVOID Address)
Definition: mm.h:139
FORCEINLINE PMMPTE MiAddressToPpe(PVOID Address)
Definition: mm.h:161
#define MiProtoPteToPte(x)
Definition: mm.h:316
FORCEINLINE PMMPTE MiAddressToPxe(PVOID Address)
Definition: mm.h:171
FORCEINLINE ULONG MiAddressToPti(PVOID Address)
Definition: mm.h:181
FORCEINLINE BOOLEAN MI_IS_MAPPED_PTE(PMMPTE PointerPte)
Definition: mm.h:356
#define MiAddressToPde(x)
Definition: mm.h:156
FORCEINLINE PMMPTE _MiAddressToPde(PVOID Address)
Definition: mm.h:150
FORCEINLINE VOID MI_MAKE_SUBSECTION_PTE(_Out_ PMMPTE NewPte, _In_ PVOID Segment)
Definition: mm.h:328
FORCEINLINE PMMPXE MiPteToPxe(PMMPTE PointerPte)
Definition: mm.h:284
FORCEINLINE PVOID MiPxeToAddress(PMMPTE PointerPxe)
Definition: mm.h:235
#define MiPdeToAddress(_Pde)
Definition: mm.h:117
#define MiPteToPde(_Pte)
Definition: mm.h:121
#define MiPteToAddress(_Pte)
Definition: mm.h:116
#define MiPdeToPte(_Pde)
Definition: mm.h:120
static WCHAR Address[46]
Definition: ping.c:68
#define PXE_BASE
#define PDI_SHIFT
#define PPE_BASE
#define PXI_SHIFT
#define PXI_MASK
#define PPI_SHIFT
#define PTI_SHIFT
ULONG64 Valid
Definition: mmtypes.h:150
ULONG64 PageFrameNumber
Definition: mmtypes.h:171
ULONG64 Prototype
Definition: mmtypes.h:121
ULONG64 Transition
Definition: mmtypes.h:105
union _MMPTE::@2330 u
MMPTE_TRANSITION Trans
Definition: mmtypes.h:220
MMPTE_PROTOTYPE Proto
Definition: mmtypes.h:218
MMPTE_HARDWARE Hard
Definition: mmtypes.h:217
int64_t LONG64
Definition: typedefs.h:68
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
#define FORCEINLINE
Definition: wdftypes.h:67
_Inout_ PVOID Segment
Definition: exfuncs.h:1101