ReactOS  0.4.10-dev-486-g11b7619
init.c
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1 /*
2  * COPYRIGHT: GPL, See COPYING in the top level directory
3  * PROJECT: ReactOS kernel
4  * FILE: ntoskrnl/mm/amd64/init.c
5  * PURPOSE: Memory Manager Initialization for amd64
6  *
7  * PROGRAMMERS: Timo kreuzer (timo.kreuzer@reactos.org)
8  * ReactOS Portable Systems Group
9  */
10 
11 /* INCLUDES ***************************************************************/
12 
13 #include <ntoskrnl.h>
14 //#define NDEBUG
15 #include <debug.h>
16 
17 #include <mm/ARM3/miarm.h>
18 
19 #ifdef _WINKD_
20 extern PMMPTE MmDebugPte;
21 #endif
22 
23 /* Helper macros */
24 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
25 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
26 
27 /* GLOBALS *****************************************************************/
28 
29 /* Template PTE and PDE for a kernel page */
30 MMPTE ValidKernelPde = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
31 MMPTE ValidKernelPte = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
32 
33 /* The same, but for local pages */
34 MMPTE ValidKernelPdeLocal = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
35 MMPTE ValidKernelPteLocal = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
36 
37 /* Template PDE for a demand-zero page */
40 
41 /* Template PTE for prototype page */
43  PTE_PROTOTYPE | (MI_PTE_LOOKUP_NEEDED << 32)}};
44 
45 /* Template PTE for decommited page */
47 
48 /* Address ranges */
52 
57 
59 
60 /* FUNCTIONS *****************************************************************/
61 
62 VOID
63 NTAPI
66 {
72 
73  /* Set up session space */
75 
76  /* This is where we will load Win32k.sys and the video driver */
79 
80  /* The view starts right below the session working set (itself below
81  * the image area) */
85 
86  /* Session pool follows */
90 
91  /* And it all begins here */
93 
94  /* System view space ends at session space, so now that we know where
95  * this is, we can compute the base address of system view space itself. */
98 
99  /* Sanity checks */
102 }
103 
104 VOID
105 NTAPI
107  PVOID StartAddress,
108  PVOID EndAddress)
109 {
110  PMMPDE PointerPpe;
111  MMPDE TmplPde = ValidKernelPde;
112 
113  /* Loop the PPEs */
114  for (PointerPpe = MiAddressToPpe(StartAddress);
115  PointerPpe <= MiAddressToPpe(EndAddress);
116  PointerPpe++)
117  {
118  /* Check if its already mapped */
119  if (!PointerPpe->u.Hard.Valid)
120  {
121  /* No, map it! */
122  TmplPde.u.Hard.PageFrameNumber = MxGetNextPage(1);
123  MI_WRITE_VALID_PTE(PointerPpe, TmplPde);
124 
125  /* Zero out the page table */
126  RtlZeroMemory(MiPteToAddress(PointerPpe), PAGE_SIZE);
127  }
128  }
129 }
130 
131 VOID
132 NTAPI
134  PVOID StartAddress,
135  PVOID EndAddress)
136 {
137  PMMPDE PointerPde;
138  MMPDE TmplPde = ValidKernelPde;
139 
140  /* Loop the PDEs */
141  for (PointerPde = MiAddressToPde(StartAddress);
142  PointerPde <= MiAddressToPde(EndAddress);
143  PointerPde++)
144  {
145  /* Check if its already mapped */
146  if (!PointerPde->u.Hard.Valid)
147  {
148  /* No, map it! */
149  TmplPde.u.Hard.PageFrameNumber = MxGetNextPage(1);
150  MI_WRITE_VALID_PTE(PointerPde, TmplPde);
151 
152  /* Zero out the page table */
153  RtlZeroMemory(MiPteToAddress(PointerPde), PAGE_SIZE);
154  }
155  }
156 }
157 
158 VOID
159 NTAPI
161  PVOID StartAddress,
162  PVOID EndAddress)
163 {
164  PMMPTE PointerPte;
165  MMPTE TmplPte = ValidKernelPte;
166 
167  /* Loop the PTEs */
168  for (PointerPte = MiAddressToPte(StartAddress);
169  PointerPte <= MiAddressToPte(EndAddress);
170  PointerPte++)
171  {
172  /* Check if its already mapped */
173  if (!PointerPte->u.Hard.Valid)
174  {
175  /* No, map it! */
176  TmplPte.u.Hard.PageFrameNumber = MxGetNextPage(1);
177  MI_WRITE_VALID_PTE(PointerPte, TmplPte);
178 
179  /* Zero out the page (FIXME: not always neccessary) */
180  RtlZeroMemory(MiPteToAddress(PointerPte), PAGE_SIZE);
181  }
182  }
183 }
184 
185 VOID
186 NTAPI
189 {
190  ULONG64 PxePhysicalAddress;
191  MMPTE TmplPte, *PointerPxe;
192  PFN_NUMBER PxePfn;
193 
194  /* Get current directory base */
195  PxePfn = ((PMMPTE)PXE_SELFMAP)->u.Hard.PageFrameNumber;
196  PxePhysicalAddress = PxePfn << PAGE_SHIFT;
197  ASSERT(PxePhysicalAddress == __readcr3());
198 
199  /* Set directory base for the system process */
200  PsGetCurrentProcess()->Pcb.DirectoryTableBase[0] = PxePhysicalAddress;
201 
202  /* Enable global pages */
204  ASSERT(__readcr4() & CR4_PGE);
205 
206  /* Loop the user mode PXEs */
207  for (PointerPxe = MiAddressToPxe(0);
208  PointerPxe <= MiAddressToPxe(MmHighestUserAddress);
209  PointerPxe++)
210  {
211  /* Zero the PXE, clear all mappings */
212  PointerPxe->u.Long = 0;
213  }
214 
215  /* Flush the TLB */
217 
218  /* Set up a template PTE */
219  TmplPte.u.Long = 0;
220  TmplPte.u.Flush.Valid = 1;
221  TmplPte.u.Flush.Write = 1;
222  HyperTemplatePte = TmplPte;
223 
224  /* Create PDPTs (72 KB) for shared system address space,
225  * skip page tables TODO: use global pages. */
226 
227  /* Loop the PXEs */
228  for (PointerPxe = MiAddressToPxe((PVOID)HYPER_SPACE);
230  PointerPxe++)
231  {
232  /* Is the PXE already valid? */
233  if (!PointerPxe->u.Hard.Valid)
234  {
235  /* It's not Initialize it */
236  TmplPte.u.Flush.PageFrameNumber = MxGetNextPage(1);
237  *PointerPxe = TmplPte;
238 
239  /* Zero the page. The PXE is the PTE for the PDPT. */
240  RtlZeroMemory(MiPteToAddress(PointerPxe), PAGE_SIZE);
241  }
242  }
243 
244  /* Map PPEs for paged pool */
246 
247  /* Setup 1 PPE for hyper space */
248  MiMapPPEs((PVOID)HYPER_SPACE, (PVOID)HYPER_SPACE_END);
249 
250  /* Setup PPEs for system space view */
252 
253  /* Setup the mapping PDEs */
255 
256  /* Setup the mapping PTEs */
257  MmFirstReservedMappingPte = MiAddressToPte((PVOID)MI_MAPPING_RANGE_START);
258  MmLastReservedMappingPte = MiAddressToPte((PVOID)MI_MAPPING_RANGE_END);
260 
261 #ifdef _WINKD_
262  /* Setup debug mapping PTE */
263  MiMapPPEs((PVOID)MI_DEBUG_MAPPING, (PVOID)MI_DEBUG_MAPPING);
264  MiMapPDEs((PVOID)MI_DEBUG_MAPPING, (PVOID)MI_DEBUG_MAPPING);
265  MmDebugPte = MiAddressToPte((PVOID)MI_DEBUG_MAPPING);
266 #endif
267 
268  /* Setup PDE and PTEs for VAD bitmap and working set list */
270  MiMapPTEs((PVOID)MI_VAD_BITMAP, (PVOID)(MI_WORKING_SET_LIST + PAGE_SIZE - 1));
271 }
272 
273 VOID
274 NTAPI
277 {
278  /* Check if this is a machine with less than 256MB of RAM, and no overide */
281  {
282  /* Force the non paged pool to be 2MB so we can reduce RAM usage */
283  MmSizeOfNonPagedPoolInBytes = 2 * 1024 * 1024;
284  }
285 
286  /* Check if the user gave a ridicuously large nonpaged pool RAM size */
288  (MmNumberOfPhysicalPages * 7 / 8))
289  {
290  /* More than 7/8ths of RAM was dedicated to nonpaged pool, ignore! */
292  }
293 
294  /* Check if no registry setting was set, or if the setting was too low */
296  {
297  /* Start with the minimum (256 KB) and add 32 KB for each MB above 4 */
301  }
302 
303  /* Check if the registy setting or our dynamic calculation was too high */
305  {
306  /* Set it to the maximum */
308  }
309 
310  /* Check if a percentage cap was set through the registry */
312  {
313  /* Don't feel like supporting this right now */
315  }
316 
317  /* Page-align the nonpaged pool size */
319 
320  /* Now, check if there was a registry size for the maximum size */
322  {
323  /* Start with the default (1MB) and add 400 KB for each MB above 4 */
327  }
328 
329  /* Don't let the maximum go too high */
331  {
332  /* Set it to the upper limit */
334  }
335 
336  /* Convert nonpaged pool size from bytes to pages */
338 
339  /* Non paged pool starts after the PFN database */
341 
342  /* Calculate the nonpaged pool expansion start region */
346 
347  /* And this is where the none paged pool ends */
350 
351  /* Map PPEs and PDEs for non paged pool (including expansion) */
354 
355  /* Map the nonpaged pool PTEs (without expansion) */
357 
358  /* Initialize the ARM3 nonpaged pool */
361 
362 }
363 
364 VOID
365 NTAPI
368 {
369  PMMPTE PointerPte;
370  SIZE_T NonPagedSystemSize;
371 
372  /* Use the default number of system PTEs */
374  NonPagedSystemSize = (MmNumberOfSystemPtes + 1) * PAGE_SIZE;
375 
376  /* Put system PTEs at the start of the system VA space */
378  MiSystemPteSpaceEnd = (PUCHAR)MiSystemPteSpaceStart + NonPagedSystemSize;
379 
380  /* Map the PPEs and PDEs for the system PTEs */
383 
384  /* Initialize the system PTE space */
387 
388  /* Reserve system PTEs for zeroing PTEs and clear them */
391 
392  /* Set the counter to maximum */
394 }
395 
396 static
397 VOID
399  PFN_NUMBER PageFrameIndex,
400  PMMPTE PointerPte)
401 {
402  PMMPFN Pfn;
403  PMMPDE PointerPde;
404 
405  /* Get the pfn entry for this page */
406  Pfn = MiGetPfnEntry(PageFrameIndex);
407 
408  /* Check if it's valid memory */
409  if ((PageFrameIndex <= MmHighestPhysicalPage) &&
410  (MmIsAddressValid(Pfn)) &&
411  (Pfn->u3.e1.PageLocation == ActiveAndValid))
412  {
413  /* Setup the PFN entry */
414  Pfn->u1.WsIndex = 0;
415  Pfn->u2.ShareCount++;
416  Pfn->PteAddress = PointerPte;
417  Pfn->OriginalPte = *PointerPte;
420  Pfn->u3.e2.ReferenceCount = 1;
421  Pfn->u4.PteFrame = PFN_FROM_PTE(MiAddressToPte(PointerPte));
422  }
423 
424  /* Increase the shared count of the PFN entry for the PDE */
425  PointerPde = MiAddressToPde(MiPteToAddress(PointerPte));
426  Pfn = MiGetPfnEntry(PFN_FROM_PTE(PointerPde));
427  Pfn->u2.ShareCount++;
428 }
429 
430 VOID
431 NTAPI
433 {
434  PVOID Address = NULL;
435  PFN_NUMBER PageFrameIndex;
436  PMMPDE PointerPde;
437  PMMPTE PointerPte;
438  ULONG k, l;
439  PMMPFN Pfn;
440 #if (_MI_PAGING_LEVELS >= 3)
441  PMMPDE PointerPpe;
442  ULONG j;
443 #endif
444 #if (_MI_PAGING_LEVELS == 4)
445  PMMPDE PointerPxe;
446  ULONG i;
447 #endif
448 
449  /* Manual setup of the top level page directory */
450 #if (_MI_PAGING_LEVELS == 4)
451  PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PXE_BASE));
452 #elif (_MI_PAGING_LEVELS == 3)
453  PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PPE_BASE));
454 #else
455  PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PDE_BASE));
456 #endif
457  Pfn = MiGetPfnEntry(PageFrameIndex);
459  Pfn->u1.WsIndex = 0;
460  Pfn->u2.ShareCount = 1;
461  Pfn->PteAddress = NULL;
463  Pfn->u3.e2.ReferenceCount = 1;
464  Pfn->u4.PteFrame = 0;
465 
466 #if (_MI_PAGING_LEVELS == 4)
467  /* Loop all PXEs in the PML4 */
468  PointerPxe = MiAddressToPxe(Address);
469  for (i = 0; i < PXE_PER_PAGE; i++, PointerPxe++)
470  {
471  /* Skip invalid PXEs */
472  if (!PointerPxe->u.Hard.Valid) continue;
473 
474  /* Handle the PFN */
475  PageFrameIndex = PFN_FROM_PXE(PointerPxe);
476  MiSetupPfnForPageTable(PageFrameIndex, PointerPxe);
477 
478  /* Get starting VA for this PXE */
479  Address = MiPxeToAddress(PointerPxe);
480 #endif
481 #if (_MI_PAGING_LEVELS >= 3)
482  /* Loop all PPEs in this PDP */
483  PointerPpe = MiAddressToPpe(Address);
484  for (j = 0; j < PPE_PER_PAGE; j++, PointerPpe++)
485  {
486  /* Skip invalid PPEs */
487  if (!PointerPpe->u.Hard.Valid) continue;
488 
489  /* Handle the PFN */
490  PageFrameIndex = PFN_FROM_PPE(PointerPpe);
491  MiSetupPfnForPageTable(PageFrameIndex, PointerPpe);
492 
493  /* Get starting VA for this PPE */
494  Address = MiPpeToAddress(PointerPpe);
495 #endif
496  /* Loop all PDEs in this PD */
497  PointerPde = MiAddressToPde(Address);
498  for (k = 0; k < PDE_PER_PAGE; k++, PointerPde++)
499  {
500  /* Skip invalid PDEs */
501  if (!PointerPde->u.Hard.Valid) continue;
502 
503  /* Handle the PFN */
504  PageFrameIndex = PFN_FROM_PDE(PointerPde);
505  MiSetupPfnForPageTable(PageFrameIndex, PointerPde);
506 
507  /* Get starting VA for this PDE */
508  Address = MiPdeToAddress(PointerPde);
509 
510  /* Loop all PTEs in this PT */
511  PointerPte = MiAddressToPte(Address);
512  for (l = 0; l < PTE_PER_PAGE; l++, PointerPte++)
513  {
514  /* Skip invalid PTEs */
515  if (!PointerPte->u.Hard.Valid) continue;
516 
517  /* Handle the PFN */
518  PageFrameIndex = PFN_FROM_PTE(PointerPte);
519  MiSetupPfnForPageTable(PageFrameIndex, PointerPte);
520  }
521  }
522 #if (_MI_PAGING_LEVELS >= 3)
523  }
524 #endif
525 #if (_MI_PAGING_LEVELS == 4)
526  }
527 #endif
528 }
529 
530 VOID
531 NTAPI
534  PFN_NUMBER BasePage,
535  PFN_NUMBER PageCount,
537 {
538  PMMPFN Pfn;
539 
540  ASSERT(!MiIsMemoryTypeInvisible(MemoryType));
541 
542  /* Check if the memory is free */
543  if (MiIsMemoryTypeFree(MemoryType))
544  {
545  /* Get the last pfn of this descriptor. Note we loop backwards */
546  Pfn = &MmPfnDatabase[BasePage + PageCount - 1];
547 
548  /* Loop all pages */
549  while (PageCount--)
550  {
551  /* Add it to the free list */
553  MiInsertPageInFreeList(BasePage + PageCount);
554 
555  /* Go to the previous page */
556  Pfn--;
557  }
558  }
559  else if (MemoryType == LoaderXIPRom)
560  {
561  Pfn = &MmPfnDatabase[BasePage];
562  while (PageCount--)
563  {
564  /* Make it a pseudo-I/O ROM mapping */
565  Pfn->PteAddress = 0;
566  Pfn->u1.Flink = 0;
567  Pfn->u2.ShareCount = 0;
568  Pfn->u3.e1.PageLocation = 0;
570  Pfn->u3.e1.Rom = 1;
571  Pfn->u3.e1.PrototypePte = 1;
572  Pfn->u3.e2.ReferenceCount = 0;
573  Pfn->u4.InPageError = 0;
574  Pfn->u4.PteFrame = 0;
575 
576  /* Advance one */
577  Pfn++;
578  }
579  }
580  else if (MemoryType == LoaderBad)
581  {
582  // FIXME: later
583  ASSERT(FALSE);
584  }
585  else
586  {
587  /* For now skip it */
588  DbgPrint("Skipping BasePage=0x%lx, PageCount=0x%lx, MemoryType=%lx\n",
589  BasePage, PageCount, MemoryType);
590  Pfn = &MmPfnDatabase[BasePage];
591  while (PageCount--)
592  {
593  /* Make an active PFN */
595 
596  /* Advance one */
597  Pfn++;
598  }
599  }
600 }
601 
602 VOID
603 NTAPI
606 {
607  PLIST_ENTRY ListEntry;
609  PFN_NUMBER BasePage, PageCount;
610 
611  /* Map the PDEs and PPEs for the pfn database (ignore holes) */
612 #if (_MI_PAGING_LEVELS >= 3)
614 #endif
616 
617  /* First initialize the color tables */
619 
620  /* Loop the memory descriptors */
621  for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
622  ListEntry != &LoaderBlock->MemoryDescriptorListHead;
623  ListEntry = ListEntry->Flink)
624  {
625  /* Get the descriptor */
626  Descriptor = CONTAINING_RECORD(ListEntry,
628  ListEntry);
629 
630  /* Skip invisible memory */
631  if (MiIsMemoryTypeInvisible(Descriptor->MemoryType)) continue;
632 
633  /* If this is the free descriptor, use the copy instead */
634  if (Descriptor == MxFreeDescriptor) Descriptor = &MxOldFreeDescriptor;
635 
636  /* Get the range for this descriptor */
637  BasePage = Descriptor->BasePage;
638  PageCount = Descriptor->PageCount;
639 
640  /* Map the pages for the database */
641  MiMapPTEs(&MmPfnDatabase[BasePage],
642  (PUCHAR)(&MmPfnDatabase[BasePage + PageCount]) - 1);
643 
644  /* If this was the free descriptor, skip the next step */
645  if (Descriptor == &MxOldFreeDescriptor) continue;
646 
647  /* Add this descriptor to the database */
648  MiAddDescriptorToDatabase(BasePage, PageCount, Descriptor->MemoryType);
649  }
650 
651  /* At this point the whole pfn database is mapped. We are about to add the
652  pages from the free descriptor to the database, so from now on we cannot
653  use it anymore. */
654 
655  /* Now add the free descriptor */
656  BasePage = MxFreeDescriptor->BasePage;
657  PageCount = MxFreeDescriptor->PageCount;
658  MiAddDescriptorToDatabase(BasePage, PageCount, LoaderFree);
659 
660  /* And finally the memory we used */
661  BasePage = MxOldFreeDescriptor.BasePage;
662  PageCount = MxFreeDescriptor->BasePage - BasePage;
663  MiAddDescriptorToDatabase(BasePage, PageCount, LoaderMemoryData);
664 
665  /* Reset the descriptor back so we can create the correct memory blocks */
667 }
668 
669 NTSTATUS
670 NTAPI
673 {
674  KIRQL OldIrql;
675 
676  ASSERT(MxPfnAllocation != 0);
677 
678  /* Set some hardcoded addresses */
683 
684 
685 // PrototypePte.u.Proto.Valid = 1
686 // PrototypePte.u.ReadOnly
687 // PrototypePte.u.Prototype
688 // PrototypePte.u.Protection = MM_READWRITE;
689 // PrototypePte.u.ProtoAddress
690  PrototypePte.u.Soft.PageFileHigh = MI_PTE_LOOKUP_NEEDED;
691 
692 
694 
696 
698 
699  /* Need to be at DISPATCH_LEVEL for MiInsertPageInFreeList */
700  KeRaiseIrql(DISPATCH_LEVEL, &OldIrql);
701 
702  /* Map the PFN database pages */
703  MiBuildPfnDatabase(LoaderBlock);
704 
705  /* Now process the page tables */
707 
708  /* PFNs are initialized now! */
710 
711  //KeLowerIrql(OldIrql);
712 
713  /* Need to be at DISPATCH_LEVEL for InitializePool */
714  //KeRaiseIrql(DISPATCH_LEVEL, &OldIrql);
715 
716  /* Initialize the nonpaged pool */
718 
719  KeLowerIrql(OldIrql);
720 
721  /* Initialize the balancer */
723 
724  /* Make sure we have everything we need */
735 
736  return STATUS_SUCCESS;
737 }
ULONG64 Valid
Definition: mmtypes.h:66
DWORD *typedef PVOID
Definition: winlogon.h:60
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Definition: mm.h:18
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GLenum GLclampf GLint GLenum GLuint GLenum GLenum GLsizei GLenum const GLvoid GLfloat GLfloat GLfloat GLfloat GLclampd GLint GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean GLboolean GLboolean GLboolean GLint GLenum GLsizei const GLvoid GLenum GLint GLenum GLint GLint GLsizei GLint GLenum GLint GLint GLint GLint GLsizei GLenum GLsizei const GLuint GLboolean GLenum GLenum GLint GLsizei GLenum GLsizei GLenum const GLvoid GLboolean const GLboolean GLenum const GLdouble const GLfloat const GLdouble const GLfloat GLenum GLint GLint GLint GLint GLint GLint j
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#define KeRaiseIrql(irql, oldIrql)
Definition: env_spec_w32.h:597
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#define TRUE
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#define PXE_PER_PAGE
PVOID ULONG Address
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VOID NTAPI MiMapPDEs(PVOID StartAddress, PVOID EndAddress)
Definition: init.c:133
#define PFN_FROM_PDE(v)
Definition: mm.h:89
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Definition: env_spec_w32.h:602
NTSTATUS NTAPI INIT_FUNCTION MiInitMachineDependent(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
Definition: init.c:672
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Definition: mm.h:62
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Definition: pfnlist.c:604
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Definition: init.c:32
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Definition: init.c:34
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Definition: mminit.c:39
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Definition: loader.c:25
PFN_NUMBER MxFreePageBase
Definition: init.c:55
ASSERT((InvokeOnSuccess||InvokeOnError||InvokeOnCancel)?(CompletionRoutine!=NULL):TRUE)
PMMPTE NTAPI MiReserveSystemPtes(IN ULONG NumberOfPtes, IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType)
Definition: syspte.c:246
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Definition: init.c:50
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Definition: init.c:20
#define MI_VAD_BITMAP
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Definition: init.c:29
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Definition: mminit.c:42
union _MMPFN::@1663 u2
PFN_NUMBER Flink
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Definition: init.c:25
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Definition: miarm.h:51
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Definition: mm.h:224
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HARDWARE_PTE Flush
Definition: mmtypes.h:216
PVOID MmPagedPoolEnd
Definition: init.c:26
union _MMPFN::@1662 u1
union _MMPFN::@1664 u3
PMMPTE MmLastReservedMappingPte
Definition: hypermap.c:20
#define MM_PTE_SOFTWARE_PROTECTION_BITS
Definition: mm.h:71
VOID NTAPI MiMapPTEs(PVOID StartAddress, PVOID EndAddress)
Definition: init.c:160
PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor
Definition: init.c:46
GLenum GLclampf GLint GLenum GLuint GLenum GLenum GLsizei GLenum const GLvoid GLfloat GLfloat GLfloat GLfloat GLclampd GLint GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean GLboolean GLboolean GLboolean GLint GLenum GLsizei const GLvoid GLenum GLint GLenum GLint GLint GLsizei GLint GLenum GLint GLint GLint GLint GLsizei GLenum GLsizei const GLuint GLboolean GLenum GLenum GLint GLsizei GLenum GLsizei GLenum const GLvoid GLboolean const GLboolean GLenum const GLdouble * u
Definition: glfuncs.h:88
PMMPTE FORCEINLINE MiAddressToPpe(PVOID Address)
Definition: mm.h:150
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1711
VOID NTAPI INIT_FUNCTION MiInitializePageTable(VOID)
Definition: init.c:188
ULONG MmSessionImageSize
Definition: init.c:37
PFN_NUMBER MmAvailablePages
Definition: freelist.c:26
#define PPE_PER_PAGE
Definition: mm.h:21
struct _MMPFN::@1664::@1670 e2
USHORT PageLocation
Definition: mm.h:297
PMMPFN MmPfnDatabase
Definition: freelist.c:24
PVOID MmNonPagedPoolEnd
Definition: mminit.c:99
enum _TYPE_OF_MEMORY TYPE_OF_MEMORY
#define CR4_PGE
Definition: ketypes.h:91
USHORT PrototypePte
Definition: mm.h:295
UCHAR KIRQL
Definition: env_spec_w32.h:591
FORCEINLINE BOOLEAN MiIsMemoryTypeInvisible(TYPE_OF_MEMORY MemoryType)
Definition: miarm.h:653
MMPFNENTRY e1
Definition: mm.h:329
TYPE_OF_MEMORY MemoryType
Definition: arc.h:193
PVOID MmSessionBase
Definition: init.c:33
GLenum GLclampf GLint i
Definition: glfuncs.h:14
USHORT CacheAttribute
Definition: mm.h:299
#define MiAddressToPte(x)
Definition: mmx86.c:19
ULONG PFN_NUMBER
Definition: ke.h:8
PVOID MmNonPagedSystemStart
Definition: init.c:23
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
#define FALSE
Definition: types.h:117
FORCEINLINE VOID MI_WRITE_VALID_PTE(IN PMMPTE PointerPte, IN MMPTE TempPte)
Definition: miarm.h:916
ULONG MmSystemViewSize
Definition: init.c:39
ULONG_PTR ShareCount
Definition: mm.h:322
#define MI_NUMBER_SYSTEM_PTES
Definition: mm.h:75
#define PDE_BASE
Definition: winldr.c:20
VOID NTAPI MiInitializeSystemPtes(IN PMMPTE StartingPte, IN ULONG NumberOfPtes, IN MMSYSTEM_PTE_POOL_TYPE PoolType)
Definition: syspte.c:399
Definition: arc.h:130
PMMPTE MmFirstReservedMappingPte
Definition: hypermap.c:20
ULONG MmSessionViewSize
Definition: init.c:35
PVOID MiSystemViewStart
Definition: init.c:38
VOID NTAPI INIT_FUNCTION MiInitializeSessionSpaceLayout(VOID)
Definition: init.c:65
#define PsGetCurrentProcess
Definition: psfuncs.h:17
#define MI_HYPERSPACE_PTES
Definition: mm.h:77
smooth NULL
Definition: ftsmooth.c:416
PVOID FORCEINLINE MiPteToAddress(PMMPTE PointerPte)
Definition: mm.h:197
VOID NTAPI MiBuildPfnDatabaseFromPageTables(VOID)
Definition: init.c:432
PFLT_MESSAGE_WAITER_QUEUE CONTAINING_RECORD(Csq, DEVICE_EXTENSION, IrpQueue)) -> WaiterQ.mLock) _IRQL_raises_(DISPATCH_LEVEL) VOID NTAPI FltpAcquireMessageWaiterLock(_In_ PIO_CSQ Csq, _Out_ PKIRQL Irql)
Definition: Messaging.c:560
#define PCHAR
Definition: match.c:90
#define PXE_SELFMAP
r l[0]
Definition: byte_order.h:167
PMMPTE MmDebugPte
Definition: mmdbg.c:33
MMPTE HyperTemplatePte
Definition: hypermap.c:22
#define MI_DEBUG_MAPPING
Definition: mm.h:19
PVOID FORCEINLINE MiPdeToAddress(PMMPTE PointerPde)
Definition: mm.h:206
struct _LIST_ENTRY * Flink
Definition: typedefs.h:119
unsigned char BOOLEAN
LONG NTSTATUS
Definition: precomp.h:26
PVOID MiSessionViewEnd
Definition: init.c:49
#define MI_WORKING_SET_LIST
Definition: mm.h:47
VOID NTAPI INIT_SECTION InitializePool(IN POOL_TYPE PoolType, IN ULONG Threshold)
Definition: expool.c:1015
BOOLEAN MiIncludeType[LoaderMaximum]
Definition: init.c:54
#define MI_MAPPING_RANGE_END
Definition: mm.h:44
MMPTE ValidKernelPteLocal
Definition: init.c:35
VOID NTAPI INIT_FUNCTION MiAddDescriptorToDatabase(PFN_NUMBER BasePage, PFN_NUMBER PageCount, TYPE_OF_MEMORY MemoryType)
Definition: init.c:533
ULONG64 Valid
Definition: mmtypes.h:150
struct _MMPTE * PMMPTE
PVOID MiSessionSpaceEnd
Definition: init.c:27
#define MI_SESSION_IMAGE_SIZE
Definition: mm.h:60
#define PTE_PER_PAGE
Definition: mm.h:19
VOID NTAPI INIT_FUNCTION MiBuildNonPagedPool(VOID)
Definition: init.c:276
PVOID MiSessionImageEnd
Definition: init.c:28
#define PPE_BASE
MMPTE ValidKernelPte
Definition: init.c:31
ULONG MmHighestPhysicalPage
Definition: init.c:48
BOOLEAN NTAPI MmIsAddressValid(IN PVOID VirtualAddress)
Definition: mmsup.c:174
#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING
Definition: mm.h:50
#define HYPER_SPACE_END
Definition: mm.h:14
unsigned __int64 ULONG64
Definition: imports.h:198
ULONG64 PageFrameNumber
Definition: mmtypes.h:78
PVOID MmHighestUserAddress
Definition: init.c:51
#define MI_MAPPING_RANGE_START
Definition: mm.h:43
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:803
ULONG64 PageFileHigh
Definition: mmtypes.h:93
PFN_NUMBER MmMaximumNonPagedPoolInPages
Definition: mminit.c:30
PVOID MiSystemPteSpaceEnd
Definition: init.c:51
ULONG64 MxFreePageCount
Definition: init.c:56
Definition: mm.h:305
ULONG MmMinAdditionNonPagedPoolPerMb
Definition: mminit.c:40
PMMPTE FORCEINLINE MiAddressToPxe(PVOID Address)
Definition: mm.h:160
#define PAGE_SIZE
Definition: env_spec_w32.h:49
Definition: typedefs.h:117
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1718
FORCEINLINE PMMPFN MiGetPfnEntry(IN PFN_NUMBER Pfn)
Definition: mm.h:933
PMMWSL MmWorkingSetList
Definition: procsup.c:21
MMPTE ValidKernelPdeLocal
Definition: init.c:34
MMPTE ValidKernelPde
Definition: init.c:30
ULONG_PTR Long
Definition: mmtypes.h:215
PVOID MmPagedPoolStart
Definition: miarm.h:554
PVOID MmNonPagedPoolStart
Definition: init.c:24
ULONG MmSessionPoolSize
Definition: init.c:36
union _MMPTE::@2170 u
#define DISPATCH_LEVEL
Definition: env_spec_w32.h:696
ULONG_PTR SIZE_T
Definition: typedefs.h:78
static VOID MiSetupPfnForPageTable(PFN_NUMBER PageFrameIndex, PMMPTE PointerPte)
Definition: init.c:398
MMPTE_HARDWARE Hard
Definition: mmtypes.h:217
#define PXE_BASE
SIZE_T MmDefaultMaximumNonPagedPool
Definition: mminit.c:41
PVOID MiSessionViewStart
Definition: init.c:30
#define IS_PAGE_ALIGNED(addr)
Definition: init.c:25
VOID NTAPI MmInitializeBalancer(ULONG NrAvailablePages, ULONG NrSystemPages)
Definition: balance.c:53
ULONG_PTR PteFrame
Definition: mm.h:350
PFN_NUMBER NTAPI MxGetNextPage(IN PFN_NUMBER PageCount)
Definition: mminit.c:483
ULONG MmMaximumNonPagedPoolInBytes
Definition: init.c:22
VOID NTAPI MiInitializeNonPagedPoolThresholds(VOID)
Definition: pool.c:184
USHORT Rom
Definition: mm.h:300
PMMPTE PteAddress
Definition: mm.h:318
MMPTE_SOFTWARE Soft
Definition: mmtypes.h:219
union _MMPFN::@1667 u4
MMPTE OriginalPte
Definition: mm.h:339
ULONG MmNumberOfPhysicalPages
Definition: init.c:48
MMPDE DemandZeroPde
Definition: init.c:38
#define MI_MAX_INIT_NONPAGED_POOL_SIZE
Definition: mm.h:55
#define MI_SESSION_VIEW_END
Definition: mm.h:23
ULONG MxPfnAllocation
Definition: init.c:43
ULONG64 Write
Definition: mmtypes.h:67
ULONG WsIndex
Definition: mm.h:310
FORCEINLINE BOOLEAN MiIsMemoryTypeFree(TYPE_OF_MEMORY MemoryType)
Definition: miarm.h:643
#define MI_SYSTEM_VIEW_SIZE
Definition: mm.h:57
#define MI_SESSION_SPACE_END
Definition: mm.h:24
#define HYPER_SPACE
Definition: mm.h:13
PVOID MiSessionPoolEnd
Definition: init.c:31
PVOID MmHyperSpaceEnd
Definition: init.c:56
unsigned int ULONG
Definition: retypes.h:1
VOID NTAPI MiInitializeColorTables(VOID)
Definition: mminit.c:562
#define PFN_FROM_PXE(v)
Definition: mm.h:91
#define UNIMPLEMENTED
Definition: debug.h:114
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:261
ULONG64 PageFrameNumber
Definition: mmtypes.h:171
PMMPTE MiFirstReservedZeroingPte
Definition: hypermap.c:21
MMPTE DemandZeroPte
Definition: init.c:39
VOID NTAPI MiMapPPEs(PVOID StartAddress, PVOID EndAddress)
Definition: init.c:106
#define MI_SESSION_VIEW_SIZE
Definition: mm.h:58
VOID NTAPI MiInitializeNonPagedPool(VOID)
Definition: pool.c:276
#define MI_SESSION_POOL_SIZE
Definition: mm.h:59
MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor
Definition: init.c:47
ULONG_PTR InPageError
Definition: mm.h:351
ULONG MmSizeOfNonPagedPoolInBytes
Definition: init.c:21
MMPTE MmDecommittedPte
Definition: init.c:46
#define MI_ZERO_PTES
Definition: mm.h:78
#define PFN_FROM_PTE(v)
Definition: mm.h:88
VOID NTAPI INIT_FUNCTION MiBuildPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
Definition: init.c:605
int k
Definition: mpi.c:3369
#define MI_HIGHEST_SYSTEM_ADDRESS
Definition: mm.h:30
#define PFN_FROM_PPE(v)
Definition: mm.h:90
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:322
#define INIT_FUNCTION
Definition: ntoskrnl.h:11
VOID NTAPI INIT_FUNCTION MiBuildSystemPteSpace(VOID)
Definition: init.c:367
_In_ PSTORAGE_PROPERTY_ID _Outptr_ PSTORAGE_DESCRIPTOR_HEADER * Descriptor
Definition: classpnp.h:966