ReactOS  r73918
init.c
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1 /*
2  * COPYRIGHT: GPL, See COPYING in the top level directory
3  * PROJECT: ReactOS kernel
4  * FILE: ntoskrnl/mm/amd64/init.c
5  * PURPOSE: Memory Manager Initialization for amd64
6  *
7  * PROGRAMMERS: Timo kreuzer (timo.kreuzer@reactos.org)
8  * ReactOS Portable Systems Group
9  */
10 
11 /* INCLUDES ***************************************************************/
12 
13 #include <ntoskrnl.h>
14 //#define NDEBUG
15 #include <debug.h>
16 
17 #include <mm/ARM3/miarm.h>
18 
19 #ifdef _WINKD_
20 extern PMMPTE MmDebugPte;
21 #endif
22 
23 /* Helper macros */
24 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
25 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
26 
27 /* GLOBALS *****************************************************************/
28 
29 /* Template PTE and PDE for a kernel page */
30 MMPTE ValidKernelPde = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
31 MMPTE ValidKernelPte = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
32 
33 /* The same, but for local pages */
34 MMPTE ValidKernelPdeLocal = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
35 MMPTE ValidKernelPteLocal = {{PTE_VALID|PTE_READWRITE|PTE_DIRTY|PTE_ACCESSED}};
36 
37 /* Template PDE for a demand-zero page */
40 
41 /* Template PTE for prototype page */
43  PTE_PROTOTYPE | (MI_PTE_LOOKUP_NEEDED << 32)}};
44 
45 /* Template PTE for decommited page */
47 
48 /* Address ranges */
52 
57 
59 
60 /* FUNCTIONS *****************************************************************/
61 
62 VOID
63 NTAPI
66 {
72 
73  /* Set up session space */
75 
76  /* This is where we will load Win32k.sys and the video driver */
79 
80  /* The view starts right below the session working set (itself below
81  * the image area) */
85 
86  /* Session pool follows */
90 
91  /* And it all begins here */
93 
94  /* System view space ends at session space, so now that we know where
95  * this is, we can compute the base address of system view space itself. */
98 
99  /* Sanity checks */
102 }
103 
104 VOID
105 NTAPI
107  PVOID StartAddress,
108  PVOID EndAddress)
109 {
110  PMMPDE PointerPpe;
111  MMPDE TmplPde = ValidKernelPde;
112 
113  /* Loop the PPEs */
114  for (PointerPpe = MiAddressToPpe(StartAddress);
115  PointerPpe <= MiAddressToPpe(EndAddress);
116  PointerPpe++)
117  {
118  /* Check if its already mapped */
119  if (!PointerPpe->u.Hard.Valid)
120  {
121  /* No, map it! */
122  TmplPde.u.Hard.PageFrameNumber = MxGetNextPage(1);
123  MI_WRITE_VALID_PTE(PointerPpe, TmplPde);
124 
125  /* Zero out the page table */
126  RtlZeroMemory(MiPteToAddress(PointerPpe), PAGE_SIZE);
127  }
128  }
129 }
130 
131 VOID
132 NTAPI
134  PVOID StartAddress,
135  PVOID EndAddress)
136 {
137  PMMPDE PointerPde;
138  MMPDE TmplPde = ValidKernelPde;
139 
140  /* Loop the PDEs */
141  for (PointerPde = MiAddressToPde(StartAddress);
142  PointerPde <= MiAddressToPde(EndAddress);
143  PointerPde++)
144  {
145  /* Check if its already mapped */
146  if (!PointerPde->u.Hard.Valid)
147  {
148  /* No, map it! */
149  TmplPde.u.Hard.PageFrameNumber = MxGetNextPage(1);
150  MI_WRITE_VALID_PTE(PointerPde, TmplPde);
151 
152  /* Zero out the page table */
153  RtlZeroMemory(MiPteToAddress(PointerPde), PAGE_SIZE);
154  }
155  }
156 }
157 
158 VOID
159 NTAPI
161  PVOID StartAddress,
162  PVOID EndAddress)
163 {
164  PMMPTE PointerPte;
165  MMPTE TmplPte = ValidKernelPte;
166 
167  /* Loop the PTEs */
168  for (PointerPte = MiAddressToPte(StartAddress);
169  PointerPte <= MiAddressToPte(EndAddress);
170  PointerPte++)
171  {
172  /* Check if its already mapped */
173  if (!PointerPte->u.Hard.Valid)
174  {
175  /* No, map it! */
176  TmplPte.u.Hard.PageFrameNumber = MxGetNextPage(1);
177  MI_WRITE_VALID_PTE(PointerPte, TmplPte);
178 
179  /* Zero out the page (FIXME: not always neccessary) */
180  RtlZeroMemory(MiPteToAddress(PointerPte), PAGE_SIZE);
181  }
182  }
183 }
184 
185 VOID
186 NTAPI
189 {
190  ULONG64 PxePhysicalAddress;
191  MMPTE TmplPte, *PointerPxe;
192  PFN_NUMBER PxePfn;
193 
194  /* Get current directory base */
195  PxePfn = ((PMMPTE)PXE_SELFMAP)->u.Hard.PageFrameNumber;
196  PxePhysicalAddress = PxePfn << PAGE_SHIFT;
197  ASSERT(PxePhysicalAddress == __readcr3());
198 
199  /* Set directory base for the system process */
200  PsGetCurrentProcess()->Pcb.DirectoryTableBase[0] = PxePhysicalAddress;
201 
202  /* Enable global pages */
204  ASSERT(__readcr4() & CR4_PGE);
205 
206  /* Enable no execute */
208 
209  /* Loop the user mode PXEs */
210  for (PointerPxe = MiAddressToPxe(0);
211  PointerPxe <= MiAddressToPxe(MmHighestUserAddress);
212  PointerPxe++)
213  {
214  /* Zero the PXE, clear all mappings */
215  PointerPxe->u.Long = 0;
216  }
217 
218  /* Flush the TLB */
220 
221  /* Set up a template PTE */
222  TmplPte.u.Long = 0;
223  TmplPte.u.Flush.Valid = 1;
224  TmplPte.u.Flush.Write = 1;
225  HyperTemplatePte = TmplPte;
226 
227  /* Create PDPTs (72 KB) for shared system address space,
228  * skip page tables TODO: use global pages. */
229 
230  /* Loop the PXEs */
231  for (PointerPxe = MiAddressToPxe((PVOID)HYPER_SPACE);
233  PointerPxe++)
234  {
235  /* Is the PXE already valid? */
236  if (!PointerPxe->u.Hard.Valid)
237  {
238  /* It's not Initialize it */
239  TmplPte.u.Flush.PageFrameNumber = MxGetNextPage(1);
240  *PointerPxe = TmplPte;
241 
242  /* Zero the page. The PXE is the PTE for the PDPT. */
243  RtlZeroMemory(MiPteToAddress(PointerPxe), PAGE_SIZE);
244  }
245  }
246 
247  /* Map PPEs for paged pool */
249 
250  /* Setup 1 PPE for hyper space */
251  MiMapPPEs((PVOID)HYPER_SPACE, (PVOID)HYPER_SPACE_END);
252 
253  /* Setup PPEs for system space view */
255 
256  /* Setup the mapping PDEs */
258 
259  /* Setup the mapping PTEs */
260  MmFirstReservedMappingPte = MiAddressToPte((PVOID)MI_MAPPING_RANGE_START);
261  MmLastReservedMappingPte = MiAddressToPte((PVOID)MI_MAPPING_RANGE_END);
263 
264 #ifdef _WINKD_
265  /* Setup debug mapping PTE */
266  MiMapPPEs((PVOID)MI_DEBUG_MAPPING, (PVOID)MI_DEBUG_MAPPING);
267  MiMapPDEs((PVOID)MI_DEBUG_MAPPING, (PVOID)MI_DEBUG_MAPPING);
268  MmDebugPte = MiAddressToPte((PVOID)MI_DEBUG_MAPPING);
269 #endif
270 
271  /* Setup PDE and PTEs for VAD bitmap and working set list */
273  MiMapPTEs((PVOID)MI_VAD_BITMAP, (PVOID)(MI_WORKING_SET_LIST + PAGE_SIZE - 1));
274 }
275 
276 VOID
277 NTAPI
280 {
281  /* Check if this is a machine with less than 256MB of RAM, and no overide */
284  {
285  /* Force the non paged pool to be 2MB so we can reduce RAM usage */
286  MmSizeOfNonPagedPoolInBytes = 2 * 1024 * 1024;
287  }
288 
289  /* Check if the user gave a ridicuously large nonpaged pool RAM size */
291  (MmNumberOfPhysicalPages * 7 / 8))
292  {
293  /* More than 7/8ths of RAM was dedicated to nonpaged pool, ignore! */
295  }
296 
297  /* Check if no registry setting was set, or if the setting was too low */
299  {
300  /* Start with the minimum (256 KB) and add 32 KB for each MB above 4 */
304  }
305 
306  /* Check if the registy setting or our dynamic calculation was too high */
308  {
309  /* Set it to the maximum */
311  }
312 
313  /* Check if a percentage cap was set through the registry */
315  {
316  /* Don't feel like supporting this right now */
318  }
319 
320  /* Page-align the nonpaged pool size */
322 
323  /* Now, check if there was a registry size for the maximum size */
325  {
326  /* Start with the default (1MB) and add 400 KB for each MB above 4 */
330  }
331 
332  /* Don't let the maximum go too high */
334  {
335  /* Set it to the upper limit */
337  }
338 
339  /* Convert nonpaged pool size from bytes to pages */
341 
342  /* Non paged pool starts after the PFN database */
344 
345  /* Calculate the nonpaged pool expansion start region */
349 
350  /* And this is where the none paged pool ends */
353 
354  /* Map PPEs and PDEs for non paged pool (including expansion) */
357 
358  /* Map the nonpaged pool PTEs (without expansion) */
360 
361  /* Initialize the ARM3 nonpaged pool */
364 
365 }
366 
367 VOID
368 NTAPI
371 {
372  PMMPTE PointerPte;
373  SIZE_T NonPagedSystemSize;
374 
375  /* Use the default number of system PTEs */
377  NonPagedSystemSize = (MmNumberOfSystemPtes + 1) * PAGE_SIZE;
378 
379  /* Put system PTEs at the start of the system VA space */
381  MiSystemPteSpaceEnd = (PUCHAR)MiSystemPteSpaceStart + NonPagedSystemSize;
382 
383  /* Map the PPEs and PDEs for the system PTEs */
386 
387  /* Initialize the system PTE space */
390 
391  /* Reserve system PTEs for zeroing PTEs and clear them */
394 
395  /* Set the counter to maximum */
397 }
398 
399 static
400 VOID
402  PFN_NUMBER PageFrameIndex,
403  PMMPTE PointerPte)
404 {
405  PMMPFN Pfn;
406  PMMPDE PointerPde;
407 
408  /* Get the pfn entry for this page */
409  Pfn = MiGetPfnEntry(PageFrameIndex);
410 
411  /* Check if it's valid memory */
412  if ((PageFrameIndex <= MmHighestPhysicalPage) &&
413  (MmIsAddressValid(Pfn)) &&
414  (Pfn->u3.e1.PageLocation == ActiveAndValid))
415  {
416  /* Setup the PFN entry */
417  Pfn->u1.WsIndex = 0;
418  Pfn->u2.ShareCount++;
419  Pfn->PteAddress = PointerPte;
420  Pfn->OriginalPte = *PointerPte;
423  Pfn->u3.e2.ReferenceCount = 1;
424  Pfn->u4.PteFrame = PFN_FROM_PTE(MiAddressToPte(PointerPte));
425  }
426 
427  /* Increase the shared count of the PFN entry for the PDE */
428  PointerPde = MiAddressToPde(MiPteToAddress(PointerPte));
429  Pfn = MiGetPfnEntry(PFN_FROM_PTE(PointerPde));
430  Pfn->u2.ShareCount++;
431 }
432 
433 VOID
434 NTAPI
436 {
437  PVOID Address = NULL;
438  PFN_NUMBER PageFrameIndex;
439  PMMPDE PointerPde;
440  PMMPTE PointerPte;
441  ULONG k, l;
442  PMMPFN Pfn;
443 #if (_MI_PAGING_LEVELS >= 3)
444  PMMPDE PointerPpe;
445  ULONG j;
446 #endif
447 #if (_MI_PAGING_LEVELS == 4)
448  PMMPDE PointerPxe;
449  ULONG i;
450 #endif
451 
452  /* Manual setup of the top level page directory */
453 #if (_MI_PAGING_LEVELS == 4)
454  PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PXE_BASE));
455 #elif (_MI_PAGING_LEVELS == 3)
456  PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PPE_BASE));
457 #else
458  PageFrameIndex = PFN_FROM_PTE(MiAddressToPte(PDE_BASE));
459 #endif
460  Pfn = MiGetPfnEntry(PageFrameIndex);
462  Pfn->u1.WsIndex = 0;
463  Pfn->u2.ShareCount = 1;
464  Pfn->PteAddress = NULL;
466  Pfn->u3.e2.ReferenceCount = 1;
467  Pfn->u4.PteFrame = 0;
468 
469 #if (_MI_PAGING_LEVELS == 4)
470  /* Loop all PXEs in the PML4 */
471  PointerPxe = MiAddressToPxe(Address);
472  for (i = 0; i < PXE_PER_PAGE; i++, PointerPxe++)
473  {
474  /* Skip invalid PXEs */
475  if (!PointerPxe->u.Hard.Valid) continue;
476 
477  /* Handle the PFN */
478  PageFrameIndex = PFN_FROM_PXE(PointerPxe);
479  MiSetupPfnForPageTable(PageFrameIndex, PointerPxe);
480 
481  /* Get starting VA for this PXE */
482  Address = MiPxeToAddress(PointerPxe);
483 #endif
484 #if (_MI_PAGING_LEVELS >= 3)
485  /* Loop all PPEs in this PDP */
486  PointerPpe = MiAddressToPpe(Address);
487  for (j = 0; j < PPE_PER_PAGE; j++, PointerPpe++)
488  {
489  /* Skip invalid PPEs */
490  if (!PointerPpe->u.Hard.Valid) continue;
491 
492  /* Handle the PFN */
493  PageFrameIndex = PFN_FROM_PPE(PointerPpe);
494  MiSetupPfnForPageTable(PageFrameIndex, PointerPpe);
495 
496  /* Get starting VA for this PPE */
497  Address = MiPpeToAddress(PointerPpe);
498 #endif
499  /* Loop all PDEs in this PD */
500  PointerPde = MiAddressToPde(Address);
501  for (k = 0; k < PDE_PER_PAGE; k++, PointerPde++)
502  {
503  /* Skip invalid PDEs */
504  if (!PointerPde->u.Hard.Valid) continue;
505 
506  /* Handle the PFN */
507  PageFrameIndex = PFN_FROM_PDE(PointerPde);
508  MiSetupPfnForPageTable(PageFrameIndex, PointerPde);
509 
510  /* Get starting VA for this PDE */
511  Address = MiPdeToAddress(PointerPde);
512 
513  /* Loop all PTEs in this PT */
514  PointerPte = MiAddressToPte(Address);
515  for (l = 0; l < PTE_PER_PAGE; l++, PointerPte++)
516  {
517  /* Skip invalid PTEs */
518  if (!PointerPte->u.Hard.Valid) continue;
519 
520  /* Handle the PFN */
521  PageFrameIndex = PFN_FROM_PTE(PointerPte);
522  MiSetupPfnForPageTable(PageFrameIndex, PointerPte);
523  }
524  }
525 #if (_MI_PAGING_LEVELS >= 3)
526  }
527 #endif
528 #if (_MI_PAGING_LEVELS == 4)
529  }
530 #endif
531 }
532 
533 VOID
534 NTAPI
537  PFN_NUMBER BasePage,
538  PFN_NUMBER PageCount,
540 {
541  PMMPFN Pfn;
542 
543  ASSERT(!MiIsMemoryTypeInvisible(MemoryType));
544 
545  /* Check if the memory is free */
546  if (MiIsMemoryTypeFree(MemoryType))
547  {
548  /* Get the last pfn of this descriptor. Note we loop backwards */
549  Pfn = &MmPfnDatabase[BasePage + PageCount - 1];
550 
551  /* Loop all pages */
552  while (PageCount--)
553  {
554  /* Add it to the free list */
556  MiInsertPageInFreeList(BasePage + PageCount);
557 
558  /* Go to the previous page */
559  Pfn--;
560  }
561  }
562  else if (MemoryType == LoaderXIPRom)
563  {
564  Pfn = &MmPfnDatabase[BasePage];
565  while (PageCount--)
566  {
567  /* Make it a pseudo-I/O ROM mapping */
568  Pfn->PteAddress = 0;
569  Pfn->u1.Flink = 0;
570  Pfn->u2.ShareCount = 0;
571  Pfn->u3.e1.PageLocation = 0;
573  Pfn->u3.e1.Rom = 1;
574  Pfn->u3.e1.PrototypePte = 1;
575  Pfn->u3.e2.ReferenceCount = 0;
576  Pfn->u4.InPageError = 0;
577  Pfn->u4.PteFrame = 0;
578 
579  /* Advance one */
580  Pfn++;
581  }
582  }
583  else if (MemoryType == LoaderBad)
584  {
585  // FIXME: later
586  ASSERT(FALSE);
587  }
588  else
589  {
590  /* For now skip it */
591  DbgPrint("Skipping BasePage=0x%lx, PageCount=0x%lx, MemoryType=%lx\n",
592  BasePage, PageCount, MemoryType);
593  Pfn = &MmPfnDatabase[BasePage];
594  while (PageCount--)
595  {
596  /* Make an active PFN */
598 
599  /* Advance one */
600  Pfn++;
601  }
602  }
603 }
604 
605 VOID
606 NTAPI
609 {
610  PLIST_ENTRY ListEntry;
612  PFN_NUMBER BasePage, PageCount;
613 
614  /* Map the PDEs and PPEs for the pfn database (ignore holes) */
615 #if (_MI_PAGING_LEVELS >= 3)
617 #endif
619 
620  /* First initialize the color tables */
622 
623  /* Loop the memory descriptors */
624  for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
625  ListEntry != &LoaderBlock->MemoryDescriptorListHead;
626  ListEntry = ListEntry->Flink)
627  {
628  /* Get the descriptor */
629  Descriptor = CONTAINING_RECORD(ListEntry,
631  ListEntry);
632 
633  /* Skip invisible memory */
634  if (MiIsMemoryTypeInvisible(Descriptor->MemoryType)) continue;
635 
636  /* If this is the free descriptor, use the copy instead */
637  if (Descriptor == MxFreeDescriptor) Descriptor = &MxOldFreeDescriptor;
638 
639  /* Get the range for this descriptor */
640  BasePage = Descriptor->BasePage;
641  PageCount = Descriptor->PageCount;
642 
643  /* Map the pages for the database */
644  MiMapPTEs(&MmPfnDatabase[BasePage],
645  (PUCHAR)(&MmPfnDatabase[BasePage + PageCount]) - 1);
646 
647  /* If this was the free descriptor, skip the next step */
648  if (Descriptor == &MxOldFreeDescriptor) continue;
649 
650  /* Add this descriptor to the database */
651  MiAddDescriptorToDatabase(BasePage, PageCount, Descriptor->MemoryType);
652  }
653 
654  /* At this point the whole pfn database is mapped. We are about to add the
655  pages from the free descriptor to the database, so from now on we cannot
656  use it anymore. */
657 
658  /* Now add the free descriptor */
659  BasePage = MxFreeDescriptor->BasePage;
660  PageCount = MxFreeDescriptor->PageCount;
661  MiAddDescriptorToDatabase(BasePage, PageCount, LoaderFree);
662 
663  /* And finally the memory we used */
664  BasePage = MxOldFreeDescriptor.BasePage;
665  PageCount = MxFreeDescriptor->BasePage - BasePage;
666  MiAddDescriptorToDatabase(BasePage, PageCount, LoaderMemoryData);
667 
668  /* Reset the descriptor back so we can create the correct memory blocks */
670 }
671 
672 NTSTATUS
673 NTAPI
676 {
677  KIRQL OldIrql;
678 
679  ASSERT(MxPfnAllocation != 0);
680 
681  /* Set some hardcoded addresses */
686 
687 
688 // PrototypePte.u.Proto.Valid = 1
689 // PrototypePte.u.ReadOnly
690 // PrototypePte.u.Prototype
691 // PrototypePte.u.Protection = MM_READWRITE;
692 // PrototypePte.u.ProtoAddress
693  PrototypePte.u.Soft.PageFileHigh = MI_PTE_LOOKUP_NEEDED;
694 
695 
697 
699 
701 
702  /* Need to be at DISPATCH_LEVEL for MiInsertPageInFreeList */
703  KeRaiseIrql(DISPATCH_LEVEL, &OldIrql);
704 
705  /* Map the PFN database pages */
706  MiBuildPfnDatabase(LoaderBlock);
707 
708  /* Now process the page tables */
710 
711  /* PFNs are initialized now! */
713 
714  //KeLowerIrql(OldIrql);
715 
716  /* Need to be at DISPATCH_LEVEL for InitializePool */
717  //KeRaiseIrql(DISPATCH_LEVEL, &OldIrql);
718 
719  /* Initialize the nonpaged pool */
721 
722  KeLowerIrql(OldIrql);
723 
724  /* Initialize the balancer */
726 
727  /* Make sure we have everything we need */
738 
739  return STATUS_SUCCESS;
740 }
ULONG64 Valid
Definition: mmtypes.h:66
DWORD *typedef PVOID
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Definition: mm.h:20
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struct _MMPFN::@1488::@1494 e2
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GLenum GLclampf GLint GLenum GLuint GLenum GLenum GLsizei GLenum const GLvoid GLfloat GLfloat GLfloat GLfloat GLclampd GLint GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean GLboolean GLboolean GLboolean GLint GLenum GLsizei const GLvoid GLenum GLint GLenum GLint GLint GLsizei GLint GLenum GLint GLint GLint GLint GLsizei GLenum GLsizei const GLuint GLboolean GLenum GLenum GLint GLsizei GLenum GLsizei GLenum const GLvoid GLboolean const GLboolean GLenum const GLdouble const GLfloat const GLdouble const GLfloat GLenum GLint GLint GLint GLint GLint GLint j
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#define KeRaiseIrql(irql, oldIrql)
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VOID NTAPI MiMapPDEs(PVOID StartAddress, PVOID EndAddress)
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#define PFN_FROM_PDE(v)
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Definition: pfnlist.c:604
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Definition: init.c:32
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Definition: mminit.c:39
union _MMPFN::@1491 u4
#define DbgPrint
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Definition: init.c:50
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Definition: init.c:20
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BOOLEAN MiPfnsInitialized
Definition: init.c:58
HARDWARE_PTE Flush
Definition: mmtypes.h:216
PVOID MmPagedPoolEnd
Definition: init.c:26
PMMPTE MmLastReservedMappingPte
Definition: hypermap.c:20
#define MM_PTE_SOFTWARE_PROTECTION_BITS
Definition: mm.h:65
#define EFER_NXE
Definition: ke.h:53
VOID NTAPI MiMapPTEs(PVOID StartAddress, PVOID EndAddress)
Definition: init.c:160
PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor
Definition: init.c:46
GLenum GLclampf GLint GLenum GLuint GLenum GLenum GLsizei GLenum const GLvoid GLfloat GLfloat GLfloat GLfloat GLclampd GLint GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean GLboolean GLboolean GLboolean GLint GLenum GLsizei const GLvoid GLenum GLint GLenum GLint GLint GLsizei GLint GLenum GLint GLint GLint GLint GLsizei GLenum GLsizei const GLuint GLboolean GLenum GLenum GLint GLsizei GLenum GLsizei GLenum const GLvoid GLboolean const GLboolean GLenum const GLdouble * u
Definition: glfuncs.h:88
PMMPTE FORCEINLINE MiAddressToPpe(PVOID Address)
Definition: mm.h:138
__INTRIN_INLINE unsigned long __readcr3(void)
Definition: intrin_x86.h:1601
VOID NTAPI INIT_FUNCTION MiInitializePageTable(VOID)
Definition: init.c:188
union _MMPFN::@1487 u2
ULONG MmSessionImageSize
Definition: init.c:37
PFN_NUMBER MmAvailablePages
Definition: freelist.c:26
#define PPE_PER_PAGE
Definition: mm.h:20
USHORT PageLocation
Definition: mm.h:297
PMMPFN MmPfnDatabase
Definition: freelist.c:24
PVOID MmNonPagedPoolEnd
Definition: mminit.c:99
enum _TYPE_OF_MEMORY TYPE_OF_MEMORY
#define CR4_PGE
Definition: ketypes.h:91
USHORT PrototypePte
Definition: mm.h:295
UCHAR KIRQL
Definition: env_spec_w32.h:591
FORCEINLINE BOOLEAN MiIsMemoryTypeInvisible(TYPE_OF_MEMORY MemoryType)
Definition: miarm.h:651
MMPFNENTRY e1
Definition: mm.h:329
TYPE_OF_MEMORY MemoryType
Definition: arc.h:193
PVOID MmSessionBase
Definition: init.c:33
GLenum GLclampf GLint i
Definition: glfuncs.h:14
USHORT CacheAttribute
Definition: mm.h:299
#define MiAddressToPte(x)
Definition: mmx86.c:19
ULONG PFN_NUMBER
Definition: ke.h:8
PVOID MmNonPagedSystemStart
Definition: init.c:23
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
FORCEINLINE VOID MI_WRITE_VALID_PTE(IN PMMPTE PointerPte, IN MMPTE TempPte)
Definition: miarm.h:914
ULONG MmSystemViewSize
Definition: init.c:39
ULONG_PTR ShareCount
Definition: mm.h:322
#define MI_NUMBER_SYSTEM_PTES
Definition: mm.h:69
#define PDE_BASE
Definition: winldr.c:20
VOID NTAPI MiInitializeSystemPtes(IN PMMPTE StartingPte, IN ULONG NumberOfPtes, IN MMSYSTEM_PTE_POOL_TYPE PoolType)
Definition: syspte.c:399
Definition: arc.h:130
PMMPTE MmFirstReservedMappingPte
Definition: hypermap.c:20
ULONG MmSessionViewSize
Definition: init.c:35
#define NULL
Definition: mystdio.h:57
uint64_t ULONG64
Definition: typedefs.h:66
PVOID MiSystemViewStart
Definition: init.c:38
VOID NTAPI INIT_FUNCTION MiInitializeSessionSpaceLayout(VOID)
Definition: init.c:65
#define PsGetCurrentProcess
Definition: psfuncs.h:17
#define MI_HYPERSPACE_PTES
Definition: mm.h:71
PVOID FORCEINLINE MiPteToAddress(PMMPTE PointerPte)
Definition: mm.h:185
PPC_QUAL unsigned long long __readmsr()
Definition: intrin_ppc.h:741
VOID NTAPI MiBuildPfnDatabaseFromPageTables(VOID)
Definition: init.c:435
union _MMPFN::@1488 u3
#define PXE_SELFMAP
r l[0]
Definition: byte_order.h:167
PMMPTE MmDebugPte
Definition: mmdbg.c:33
MMPTE HyperTemplatePte
Definition: hypermap.c:22
#define MI_DEBUG_MAPPING
Definition: mm.h:22
PVOID FORCEINLINE MiPdeToAddress(PMMPTE PointerPde)
Definition: mm.h:194
struct _LIST_ENTRY * Flink
Definition: typedefs.h:120
unsigned char BOOLEAN
PVOID MiSessionViewEnd
Definition: init.c:49
#define MI_WORKING_SET_LIST
Definition: mm.h:41
VOID NTAPI INIT_SECTION InitializePool(IN POOL_TYPE PoolType, IN ULONG Threshold)
Definition: expool.c:849
BOOLEAN MiIncludeType[LoaderMaximum]
Definition: init.c:54
#define MI_MAPPING_RANGE_END
Definition: mm.h:38
MMPTE ValidKernelPteLocal
Definition: init.c:35
VOID NTAPI INIT_FUNCTION MiAddDescriptorToDatabase(PFN_NUMBER BasePage, PFN_NUMBER PageCount, TYPE_OF_MEMORY MemoryType)
Definition: init.c:536
ULONG64 Valid
Definition: mmtypes.h:150
struct _MMPTE * PMMPTE
PVOID MiSessionSpaceEnd
Definition: init.c:27
#define MI_SESSION_IMAGE_SIZE
Definition: mm.h:54
#define PTE_PER_PAGE
Definition: mm.h:18
VOID NTAPI INIT_FUNCTION MiBuildNonPagedPool(VOID)
Definition: init.c:279
PVOID MiSessionImageEnd
Definition: init.c:28
#define PPE_BASE
MMPTE ValidKernelPte
Definition: init.c:31
ULONG MmHighestPhysicalPage
Definition: init.c:48
BOOLEAN NTAPI MmIsAddressValid(IN PVOID VirtualAddress)
Definition: mmsup.c:174
#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING
Definition: mm.h:44
#define HYPER_SPACE_END
Definition: mm.h:13
ULONG64 PageFrameNumber
Definition: mmtypes.h:78
PVOID MmHighestUserAddress
Definition: init.c:51
#define MI_MAPPING_RANGE_START
Definition: mm.h:37
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:803
ULONG64 PageFileHigh
Definition: mmtypes.h:93
PFN_NUMBER MmMaximumNonPagedPoolInPages
Definition: mminit.c:30
PVOID MiSystemPteSpaceEnd
Definition: init.c:51
ULONG64 MxFreePageCount
Definition: init.c:56
Definition: mm.h:305
union _MMPFN::@1486 u1
ULONG MmMinAdditionNonPagedPoolPerMb
Definition: mminit.c:40
PMMPTE FORCEINLINE MiAddressToPxe(PVOID Address)
Definition: mm.h:148
#define PAGE_SIZE
Definition: env_spec_w32.h:49
Definition: typedefs.h:118
__INTRIN_INLINE unsigned long __readcr4(void)
Definition: intrin_x86.h:1608
FORCEINLINE PMMPFN MiGetPfnEntry(IN PFN_NUMBER Pfn)
Definition: mm.h:877
PMMWSL MmWorkingSetList
Definition: procsup.c:21
MMPTE ValidKernelPdeLocal
Definition: init.c:34
MMPTE ValidKernelPde
Definition: init.c:30
PPC_QUAL void __writemsr(const unsigned long Value)
Definition: intrin_ppc.h:748
ULONG_PTR Long
Definition: mmtypes.h:215
PVOID MmPagedPoolStart
Definition: miarm.h:552
PVOID MmNonPagedPoolStart
Definition: init.c:24
ULONG MmSessionPoolSize
Definition: init.c:36
#define DISPATCH_LEVEL
Definition: env_spec_w32.h:696
ULONG_PTR SIZE_T
Definition: typedefs.h:79
static VOID MiSetupPfnForPageTable(PFN_NUMBER PageFrameIndex, PMMPTE PointerPte)
Definition: init.c:401
MMPTE_HARDWARE Hard
Definition: mmtypes.h:217
union _MMPTE::@1885 u
#define PXE_BASE
LONG NTSTATUS
Definition: DriverTester.h:11
SIZE_T MmDefaultMaximumNonPagedPool
Definition: mminit.c:41
PVOID MiSessionViewStart
Definition: init.c:30
#define IS_PAGE_ALIGNED(addr)
Definition: init.c:25
VOID NTAPI MmInitializeBalancer(ULONG NrAvailablePages, ULONG NrSystemPages)
Definition: balance.c:53
ULONG_PTR PteFrame
Definition: mm.h:350
PFN_NUMBER NTAPI MxGetNextPage(IN PFN_NUMBER PageCount)
Definition: mminit.c:473
ULONG MmMaximumNonPagedPoolInBytes
Definition: init.c:22
VOID NTAPI MiInitializeNonPagedPoolThresholds(VOID)
Definition: pool.c:184
USHORT Rom
Definition: mm.h:300
PMMPTE PteAddress
Definition: mm.h:318
MMPTE_SOFTWARE Soft
Definition: mmtypes.h:219
MMPTE OriginalPte
Definition: mm.h:339
ULONG MmNumberOfPhysicalPages
Definition: init.c:48
MMPDE DemandZeroPde
Definition: init.c:38
#define MI_MAX_INIT_NONPAGED_POOL_SIZE
Definition: mm.h:49
#define MI_SESSION_VIEW_END
Definition: mm.h:18
ULONG MxPfnAllocation
Definition: init.c:43
ULONG64 Write
Definition: mmtypes.h:67
ULONG WsIndex
Definition: mm.h:310
FORCEINLINE BOOLEAN MiIsMemoryTypeFree(TYPE_OF_MEMORY MemoryType)
Definition: miarm.h:641
signed char * PCHAR
Definition: retypes.h:7
#define MI_SYSTEM_VIEW_SIZE
Definition: mm.h:51
#define FALSE
Definition: numbers.c:16
#define MI_SESSION_SPACE_END
Definition: mm.h:19
#define HYPER_SPACE
Definition: mm.h:12
PVOID MiSessionPoolEnd
Definition: init.c:31
PVOID MmHyperSpaceEnd
Definition: init.c:56
unsigned int ULONG
Definition: retypes.h:1
#define CONTAINING_RECORD(address, type, field)
Definition: typedefs.h:260
VOID NTAPI MiInitializeColorTables(VOID)
Definition: mminit.c:552
#define PFN_FROM_PXE(v)
Definition: mm.h:85
#define UNIMPLEMENTED
Definition: debug.h:114
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
ULONG64 PageFrameNumber
Definition: mmtypes.h:171
PMMPTE MiFirstReservedZeroingPte
Definition: hypermap.c:21
MMPTE DemandZeroPte
Definition: init.c:39
VOID NTAPI MiMapPPEs(PVOID StartAddress, PVOID EndAddress)
Definition: init.c:106
#define MI_SESSION_VIEW_SIZE
Definition: mm.h:52
VOID NTAPI MiInitializeNonPagedPool(VOID)
Definition: pool.c:276
#define MI_SESSION_POOL_SIZE
Definition: mm.h:53
MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor
Definition: init.c:47
ULONG_PTR InPageError
Definition: mm.h:351
ULONG MmSizeOfNonPagedPoolInBytes
Definition: init.c:21
MMPTE MmDecommittedPte
Definition: init.c:46
#define MI_ZERO_PTES
Definition: mm.h:72
#define PFN_FROM_PTE(v)
Definition: mm.h:82
VOID NTAPI INIT_FUNCTION MiBuildPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
Definition: init.c:608
int k
Definition: mpi.c:3369
#define MI_HIGHEST_SYSTEM_ADDRESS
Definition: mm.h:24
#define PFN_FROM_PPE(v)
Definition: mm.h:84
VOID NTAPI KeFlushCurrentTb(VOID)
Definition: cpu.c:332
#define INIT_FUNCTION
Definition: ntoskrnl.h:11
VOID NTAPI INIT_FUNCTION MiBuildSystemPteSpace(VOID)
Definition: init.c:370
_In_ PSTORAGE_PROPERTY_ID _Outptr_ PSTORAGE_DESCRIPTOR_HEADER * Descriptor
Definition: classpnp.h:966