ReactOS 0.4.15-dev-7928-g68a8619
apicp.h
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1/*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4 * PURPOSE: Header file for APIC hal
5 * COPYRIGHT: Copyright 2011 Timo Kreuzer <timo.kreuzer@reactos.org>
6 * Copyright 2021 Justin Miller <justinmiller100@gmail.com>
7 */
8
9#pragma once
10
11#ifdef _M_AMD64
12 #define LOCAL_APIC_BASE 0xFFFFFFFFFFFE0000ULL
13 #define IOAPIC_BASE 0xFFFFFFFFFFFE1000ULL
14
15 /* Vectors */
16 #define APC_VECTOR 0x1F // IRQL 01 (APC_LEVEL) - KiApcInterrupt
17 #define DISPATCH_VECTOR 0x2F // IRQL 02 (DISPATCH_LEVEL) - KiDpcInterrupt
18 #define CMCI_VECTOR 0x35 // IRQL 05 (CMCI_LEVEL) - HalpInterruptCmciService
19 #define APIC_CLOCK_VECTOR 0xD1 // IRQL 13 (CLOCK_LEVEL), IRQ 8 - HalpTimerClockInterrupt
20 #define CLOCK_IPI_VECTOR 0xD2 // IRQL 13 (CLOCK_LEVEL) - HalpTimerClockIpiRoutine
21 #define REBOOT_VECTOR 0xD7 // IRQL 15 (PROFILE_LEVEL) - HalpInterruptRebootService
22 #define STUB_VECTOR 0xD8 // IRQL 15 (PROFILE_LEVEL) - HalpInterruptStubService
23 #define APIC_SPURIOUS_VECTOR 0xDF // IRQL 13 (CLOCK_LEVEL) - HalpInterruptSpuriousService
24 #define APIC_IPI_VECTOR 0xE1 // IRQL 14 (IPI_LEVEL) - KiIpiInterrupt
25 #define APIC_ERROR_VECTOR 0xE2 // IRQL 14 (IPI_LEVEL) - HalpInterruptLocalErrorService
26 #define POWERFAIL_VECTOR 0xE3 // IRQL 14 (POWER_LEVEL) : HalpInterruptDeferredRecoveryService
27 #define APIC_PROFILE_VECTOR 0xFD // IRQL 15 (PROFILE_LEVEL) - HalpTimerProfileInterrupt
28 #define APIC_PERF_VECTOR 0xFE // IRQL 15 (PROFILE_LEVEL) - HalpPerfInterrupt
29 #define APIC_NMI_VECTOR 0xFF
30
31 #define IrqlToTpr(Irql) (Irql << 4)
32 #define IrqlToSoftVector(Irql) ((Irql << 4)|0xf)
33 #define TprToIrql(Tpr) ((KIRQL)(Tpr >> 4))
34 #define CLOCK2_LEVEL CLOCK_LEVEL
35#else
36 #define LOCAL_APIC_BASE 0xFFFE0000
37 #define IOAPIC_BASE 0xFFFE1000
38
39 /* Vectors */
40 #define APIC_SPURIOUS_VECTOR 0x1f
41 #define APC_VECTOR 0x3D // IRQL 01
42 #define DISPATCH_VECTOR 0x41 // IRQL 02
43 #define APIC_GENERIC_VECTOR 0xC1 // IRQL 27
44 #define APIC_CLOCK_VECTOR 0xD1 // IRQL 28
45 #define APIC_SYNCH_VECTOR 0xD1 // IRQL 28
46 #define CLOCK_IPI_VECTOR 0xD2 // IRQL 28
47 #define APIC_IPI_VECTOR 0xE1 // IRQL 29
48 #define APIC_ERROR_VECTOR 0xE3
49 #define POWERFAIL_VECTOR 0xEF // IRQL 30
50 #define APIC_PROFILE_VECTOR 0xFD // IRQL 31
51 #define APIC_PERF_VECTOR 0xFE
52 #define APIC_NMI_VECTOR 0xFF
53
54 #define IrqlToTpr(Irql) (HalpIRQLtoTPR[Irql])
55 #define IrqlToSoftVector(Irql) IrqlToTpr(Irql)
56 #define TprToIrql(Tpr) (HalVectorToIRQL[Tpr >> 4])
57#endif
58
59#define APIC_MAX_IRQ 24
60#define APIC_FREE_VECTOR 0xFF
61#define APIC_RESERVED_VECTOR 0xFE
62
63/* The IMCR is supported by two read/writable or write-only I/O ports,
64 22h and 23h, which receive address and data respectively.
65 To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR.
66 Then write the data to I/O port 23h. The power-on default value is zero,
67 which connects the NMI and 8259 INTR lines directly to the BSP.
68 Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC.
69*/
70#define IMCR_ADDRESS_PORT (PUCHAR)0x0022
71#define IMCR_DATA_PORT (PUCHAR)0x0023
72#define IMCR_SELECT 0x70
73#define IMCR_PIC_DIRECT 0x00
74#define IMCR_PIC_VIA_APIC 0x01
75
76
77/* APIC Register Address Map */
78typedef enum _APIC_REGISTER
79{
80 APIC_ID = 0x0020, /* Local APIC ID Register (R/W) */
81 APIC_VER = 0x0030, /* Local APIC Version Register (R) */
82 APIC_TPR = 0x0080, /* Task Priority Register (R/W) */
83 APIC_APR = 0x0090, /* Arbitration Priority Register (R) */
84 APIC_PPR = 0x00A0, /* Processor Priority Register (R) */
85 APIC_EOI = 0x00B0, /* EOI Register (W) */
86 APIC_RRR = 0x00C0, /* Remote Read Register () */
87 APIC_LDR = 0x00D0, /* Logical Destination Register (R/W) */
88 APIC_DFR = 0x00E0, /* Destination Format Register (0-27 R, 28-31 R/W) */
89 APIC_SIVR = 0x00F0, /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
90 APIC_ISR = 0x0100, /* Interrupt Service Register 0-255 (R) */
91 APIC_TMR = 0x0180, /* Trigger Mode Register 0-255 (R) */
92 APIC_IRR = 0x0200, /* Interrupt Request Register 0-255 (r) */
93 APIC_ESR = 0x0280, /* Error Status Register (R) */
94 APIC_ICR0 = 0x0300, /* Interrupt Command Register 0-31 (R/W) */
95 APIC_ICR1 = 0x0310, /* Interrupt Command Register 32-63 (R/W) */
96 APIC_TMRLVTR = 0x0320, /* Timer Local Vector Table (R/W) */
97 APIC_THRMLVTR = 0x0330, /* Thermal Local Vector Table */
98 APIC_PCLVTR = 0x0340, /* Performance Counter Local Vector Table (R/W) */
99 APIC_LINT0 = 0x0350, /* LINT0 Local Vector Table (R/W) */
100 APIC_LINT1 = 0x0360, /* LINT1 Local Vector Table (R/W) */
101 APIC_ERRLVTR = 0x0370, /* Error Local Vector Table (R/W) */
102 APIC_TICR = 0x0380, /* Initial Count Register for Timer (R/W) */
103 APIC_TCCR = 0x0390, /* Current Count Register for Timer (R) */
104 APIC_TDCR = 0x03E0, /* Timer Divide Configuration Register (R/W) */
105 APIC_EAFR = 0x0400, /* extended APIC Feature register (R/W) */
106 APIC_EACR = 0x0410, /* Extended APIC Control Register (R/W) */
107 APIC_SEOI = 0x0420, /* Specific End Of Interrupt Register (W) */
108 APIC_EXT0LVTR = 0x0500, /* Extended Interrupt 0 Local Vector Table */
109 APIC_EXT1LVTR = 0x0510, /* Extended Interrupt 1 Local Vector Table */
110 APIC_EXT2LVTR = 0x0520, /* Extended Interrupt 2 Local Vector Table */
111 APIC_EXT3LVTR = 0x0530 /* Extended Interrupt 3 Local Vector Table */
113
114#define MSR_APIC_BASE 0x0000001B
115#define IOAPIC_PHYS_BASE 0xFEC00000
116#define APIC_CLOCK_INDEX 8
117#define ApicLogicalId(Cpu) ((UCHAR)(1<< Cpu))
118
119/* The following definitions are based on AMD documentation.
120 They differ slightly in Intel documentation. */
121
122/* Message Type (Intel: "Delivery Mode") */
123typedef enum _APIC_MT
124{
134
135/* Trigger Mode */
136typedef enum _APIC_TGM
137{
141
142/* Destination Mode */
143typedef enum _APIC_DM
144{
148
149/* Destination Short Hand */
150typedef enum _APIC_DSH
151{
157
158/* Write Constants */
159typedef enum _APIC_DF
160{
161 APIC_DF_Flat = 0xFFFFFFFF,
162 APIC_DF_Cluster = 0x0FFFFFFF
164
165/* Remote Read Status */
166typedef enum _APIC_RRS
167{
170 APIC_RRS_Done = 2
172
173/* Timer Constants */
174typedef enum _TIMER_DV
175{
185
186#include <pshpack1.h>
188{
190 struct
191 {
198 };
200
202{
204 struct
205 {
210 };
212
214{
216 struct
217 {
223 };
225
227{
229 struct
230 {
235 };
237
239{
241 struct
242 {
245 };
246 struct
247 {
255 UINT64 RemoteReadStatus:2; /* Intel: Reserved */
259 };
261
262typedef union _LVT_REGISTER
263{
265 struct
266 {
277 };
279
280/* IOAPIC offsets */
281#define IOAPIC_IOREGSEL 0x00
282#define IOAPIC_IOWIN 0x10
283
284/* IOAPIC Constants */
285#define IOAPIC_ID 0x00
286#define IOAPIC_VER 0x01
287#define IOAPIC_ARB 0x02
288#define IOAPIC_REDTBL 0x10
289
291{
293 struct
294 {
297 };
298 struct
299 {
310 };
312#include <poppack.h>
313
315ULONG
317{
319}
320
322VOID
324{
326}
327
328VOID
329NTAPI
331
332VOID
333NTAPI
335
336VOID
337NTAPI
339
unsigned long long UINT64
unsigned int UINT32
#define __cdecl
Definition: accygwin.h:79
VOID NTAPI HalInitializeProfiling(VOID)
Definition: apictimer.c:76
_APIC_DF
Definition: apicp.h:160
@ APIC_DF_Flat
Definition: apicp.h:161
@ APIC_DF_Cluster
Definition: apicp.h:162
_APIC_DM
Definition: apicp.h:144
@ APIC_DM_Logical
Definition: apicp.h:146
@ APIC_DM_Physical
Definition: apicp.h:145
_APIC_DSH
Definition: apicp.h:151
@ APIC_DSH_AllIncludingSelf
Definition: apicp.h:154
@ APIC_DSH_Destination
Definition: apicp.h:152
@ APIC_DSH_Self
Definition: apicp.h:153
@ APIC_DSH_AllExcludingSelf
Definition: apicp.h:155
_APIC_RRS
Definition: apicp.h:167
@ APIC_RRS_Done
Definition: apicp.h:170
@ APIC_RRS_Invalid
Definition: apicp.h:168
@ APIC_RRS_Pending
Definition: apicp.h:169
enum _APIC_DF APIC_DF
_APIC_MT
Definition: apicp.h:124
@ APIC_MT_INIT
Definition: apicp.h:130
@ APIC_MT_LowestPriority
Definition: apicp.h:126
@ APIC_MT_Fixed
Definition: apicp.h:125
@ APIC_MT_NMI
Definition: apicp.h:129
@ APIC_MT_ExtInt
Definition: apicp.h:132
@ APIC_MT_SMI
Definition: apicp.h:127
@ APIC_MT_Startup
Definition: apicp.h:131
@ APIC_MT_RemoteRead
Definition: apicp.h:128
union _LVT_REGISTER LVT_REGISTER
union _APIC_EXTENDED_CONTROL_REGISTER APIC_EXTENDED_CONTROL_REGISTER
enum _APIC_MT APIC_MT
enum _APIC_REGISTER APIC_REGISTER
enum _APIC_RRS APIC_RRS
VOID NTAPI ApicInitializeTimer(ULONG Cpu)
Definition: apictimer.c:50
VOID __cdecl ApicSpuriousService(VOID)
union _APIC_INTERRUPT_COMMAND_REGISTER APIC_INTERRUPT_COMMAND_REGISTER
FORCEINLINE ULONG ApicRead(APIC_REGISTER Register)
Definition: apicp.h:316
enum _APIC_DM APIC_DM
union _APIC_BASE_ADDRESS_REGISTER APIC_BASE_ADDRESS_REGISTER
FORCEINLINE VOID ApicWrite(APIC_REGISTER Register, ULONG Value)
Definition: apicp.h:323
union _APIC_VERSION_REGISTER APIC_VERSION_REGISTER
_TIMER_DV
Definition: apicp.h:175
@ TIMER_DV_DivideBy128
Definition: apicp.h:182
@ TIMER_DV_DivideBy4
Definition: apicp.h:177
@ TIMER_DV_DivideBy8
Definition: apicp.h:178
@ TIMER_DV_DivideBy1
Definition: apicp.h:183
@ TIMER_DV_DivideBy2
Definition: apicp.h:176
@ TIMER_DV_DivideBy64
Definition: apicp.h:181
@ TIMER_DV_DivideBy16
Definition: apicp.h:179
@ TIMER_DV_DivideBy32
Definition: apicp.h:180
enum _APIC_TGM APIC_TGM
_APIC_REGISTER
Definition: apicp.h:79
@ APIC_LINT1
Definition: apicp.h:100
@ APIC_RRR
Definition: apicp.h:86
@ APIC_PPR
Definition: apicp.h:84
@ APIC_ICR0
Definition: apicp.h:94
@ APIC_EXT3LVTR
Definition: apicp.h:111
@ APIC_TICR
Definition: apicp.h:102
@ APIC_SEOI
Definition: apicp.h:107
@ APIC_TPR
Definition: apicp.h:82
@ APIC_EXT1LVTR
Definition: apicp.h:109
@ APIC_TCCR
Definition: apicp.h:103
@ APIC_VER
Definition: apicp.h:81
@ APIC_EACR
Definition: apicp.h:106
@ APIC_LDR
Definition: apicp.h:87
@ APIC_ESR
Definition: apicp.h:93
@ APIC_ERRLVTR
Definition: apicp.h:101
@ APIC_IRR
Definition: apicp.h:92
@ APIC_PCLVTR
Definition: apicp.h:98
@ APIC_ICR1
Definition: apicp.h:95
@ APIC_ISR
Definition: apicp.h:90
@ APIC_TDCR
Definition: apicp.h:104
@ APIC_EXT2LVTR
Definition: apicp.h:110
@ APIC_EAFR
Definition: apicp.h:105
@ APIC_THRMLVTR
Definition: apicp.h:97
@ APIC_TMRLVTR
Definition: apicp.h:96
@ APIC_EOI
Definition: apicp.h:85
@ APIC_ID
Definition: apicp.h:80
@ APIC_DFR
Definition: apicp.h:88
@ APIC_LINT0
Definition: apicp.h:99
@ APIC_TMR
Definition: apicp.h:91
@ APIC_SIVR
Definition: apicp.h:89
@ APIC_EXT0LVTR
Definition: apicp.h:108
@ APIC_APR
Definition: apicp.h:83
enum _TIMER_DV TIMER_DV
union _APIC_SPURIOUS_INERRUPT_REGISTER APIC_SPURIOUS_INERRUPT_REGISTER
VOID NTAPI HalpInitApicInfo(IN PLOADER_PARAMETER_BLOCK KeLoaderBlock)
enum _APIC_DSH APIC_DSH
_APIC_TGM
Definition: apicp.h:137
@ APIC_TGM_Level
Definition: apicp.h:139
@ APIC_TGM_Edge
Definition: apicp.h:138
union _IOAPIC_REDIRECTION_REGISTER IOAPIC_REDIRECTION_REGISTER
#define WRITE_REGISTER_ULONG(r, v)
Definition: arm.h:27
#define READ_REGISTER_ULONG(r)
Definition: arm.h:26
PLOADER_PARAMETER_BLOCK KeLoaderBlock
Definition: krnlinit.c:29
#define APIC_BASE
Definition: ketypes.h:324
uint32_t * PULONG
Definition: typedefs.h:59
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
uint32_t ULONG
Definition: typedefs.h:59
UINT32 ExtRegSpacePresent
Definition: apicp.h:222
UINT32 RemoteIRR
Definition: apicp.h:272
UINT32 MessageType
Definition: apicp.h:268
UINT32 ReservedMBZ
Definition: apicp.h:269
UINT32 TimerMode
Definition: apicp.h:275
UINT32 Long
Definition: apicp.h:264
UINT32 Reserved1MBZ
Definition: apicp.h:271
UINT32 Vector
Definition: apicp.h:267
UINT32 Mask
Definition: apicp.h:274
UINT32 TriggerMode
Definition: apicp.h:273
UINT32 DeliveryStatus
Definition: apicp.h:270
UINT32 Reserved2MBZ
Definition: apicp.h:276
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING _Out_opt_ PUSHORT _Inout_opt_ PUNICODE_STRING Value
Definition: wdfregistry.h:413
#define FORCEINLINE
Definition: wdftypes.h:67