ReactOS  0.4.15-dev-3175-g222acf5
apicp.h
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1 /*
2  * PROJECT: ReactOS Kernel
3  * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4  * PURPOSE: Header file for APIC hal
5  * COPYRIGHT: Copyright 2011 Timo Kreuzer <timo.kreuzer@reactos.org>
6  * Copyright 2021 Justin Miller <justinmiller100@gmail.com>
7  */
8 
9 #pragma once
10 
11 #ifdef _M_AMD64
12  #define LOCAL_APIC_BASE 0xFFFFFFFFFFFE0000ULL
13  #define IOAPIC_BASE 0xFFFFFFFFFFFE1000ULL
14 
15  /* Vectors */
16  #define APC_VECTOR 0x1F // IRQL 01 (APC_LEVEL) - KiApcInterrupt
17  #define DISPATCH_VECTOR 0x2F // IRQL 02 (DISPATCH_LEVEL) - KiDpcInterrupt
18  #define CMCI_VECTOR 0x35 // IRQL 05 (CMCI_LEVEL) - HalpInterruptCmciService
19  #define APIC_CLOCK_VECTOR 0xD1 // IRQL 13 (CLOCK_LEVEL), IRQ 8 - HalpTimerClockInterrupt
20  #define CLOCK_IPI_VECTOR 0xD2 // IRQL 13 (CLOCK_LEVEL) - HalpTimerClockIpiRoutine
21  #define REBOOT_VECTOR 0xD7 // IRQL 15 (PROFILE_LEVEL) - HalpInterruptRebootService
22  #define STUB_VECTOR 0xD8 // IRQL 15 (PROFILE_LEVEL) - HalpInterruptStubService
23  #define APIC_SPURIOUS_VECTOR 0xDF // IRQL 13 (CLOCK_LEVEL) - HalpInterruptSpuriousService
24  #define APIC_IPI_VECTOR 0xE1 // IRQL 14 (IPI_LEVEL) - KiIpiInterrupt
25  #define APIC_ERROR_VECTOR 0xE2 // IRQL 14 (IPI_LEVEL) - HalpInterruptLocalErrorService
26  #define POWERFAIL_VECTOR 0xE3 // IRQL 14 (POWER_LEVEL) : HalpInterruptDeferredRecoveryService
27  #define APIC_PROFILE_VECTOR 0xFD // IRQL 15 (PROFILE_LEVEL) - HalpTimerProfileInterrupt
28  #define APIC_PERF_VECTOR 0xFE // IRQL 15 (PROFILE_LEVEL) - HalpPerfInterrupt
29  #define APIC_NMI_VECTOR 0xFF
30 
31  #define IrqlToTpr(Irql) (Irql << 4)
32  #define IrqlToSoftVector(Irql) ((Irql << 4)|0xf)
33  #define TprToIrql(Tpr) ((KIRQL)(Tpr >> 4))
34  #define CLOCK2_LEVEL CLOCK_LEVEL
35 #else
36  #define LOCAL_APIC_BASE 0xFFFE0000
37  #define IOAPIC_BASE 0xFFFE1000
38 
39  /* Vectors */
40  #define APIC_SPURIOUS_VECTOR 0x1f
41  #define APC_VECTOR 0x3D // IRQL 01
42  #define DISPATCH_VECTOR 0x41 // IRQL 02
43  #define APIC_GENERIC_VECTOR 0xC1 // IRQL 27
44  #define APIC_CLOCK_VECTOR 0xD1 // IRQL 28
45  #define APIC_SYNCH_VECTOR 0xD1 // IRQL 28
46  #define APIC_IPI_VECTOR 0xE1 // IRQL 29
47  #define APIC_ERROR_VECTOR 0xE3
48  #define POWERFAIL_VECTOR 0xEF // IRQL 30
49  #define APIC_PROFILE_VECTOR 0xFD // IRQL 31
50  #define APIC_PERF_VECTOR 0xFE
51  #define APIC_NMI_VECTOR 0xFF
52 
53  #define IrqlToTpr(Irql) (HalpIRQLtoTPR[Irql])
54  #define IrqlToSoftVector(Irql) IrqlToTpr(Irql)
55  #define TprToIrql(Tpr) (HalVectorToIRQL[Tpr >> 4])
56 #endif
57 
58 #define APIC_MAX_IRQ 24
59 #define APIC_FREE_VECTOR 0xFF
60 #define APIC_RESERVED_VECTOR 0xFE
61 
62 /* The IMCR is supported by two read/writable or write-only I/O ports,
63  22h and 23h, which receive address and data respectively.
64  To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR.
65  Then write the data to I/O port 23h. The power-on default value is zero,
66  which connects the NMI and 8259 INTR lines directly to the BSP.
67  Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC.
68 */
69 #define IMCR_ADDRESS_PORT (PUCHAR)0x0022
70 #define IMCR_DATA_PORT (PUCHAR)0x0023
71 #define IMCR_SELECT 0x70
72 #define IMCR_PIC_DIRECT 0x00
73 #define IMCR_PIC_VIA_APIC 0x01
74 
75 
76 /* APIC Register Address Map */
77 typedef enum _APIC_REGISTER
78 {
79  APIC_ID = 0x0020, /* Local APIC ID Register (R/W) */
80  APIC_VER = 0x0030, /* Local APIC Version Register (R) */
81  APIC_TPR = 0x0080, /* Task Priority Register (R/W) */
82  APIC_APR = 0x0090, /* Arbitration Priority Register (R) */
83  APIC_PPR = 0x00A0, /* Processor Priority Register (R) */
84  APIC_EOI = 0x00B0, /* EOI Register (W) */
85  APIC_RRR = 0x00C0, /* Remote Read Register () */
86  APIC_LDR = 0x00D0, /* Logical Destination Register (R/W) */
87  APIC_DFR = 0x00E0, /* Destination Format Register (0-27 R, 28-31 R/W) */
88  APIC_SIVR = 0x00F0, /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
89  APIC_ISR = 0x0100, /* Interrupt Service Register 0-255 (R) */
90  APIC_TMR = 0x0180, /* Trigger Mode Register 0-255 (R) */
91  APIC_IRR = 0x0200, /* Interrupt Request Register 0-255 (r) */
92  APIC_ESR = 0x0280, /* Error Status Register (R) */
93  APIC_ICR0 = 0x0300, /* Interrupt Command Register 0-31 (R/W) */
94  APIC_ICR1 = 0x0310, /* Interrupt Command Register 32-63 (R/W) */
95  APIC_TMRLVTR = 0x0320, /* Timer Local Vector Table (R/W) */
96  APIC_THRMLVTR = 0x0330, /* Thermal Local Vector Table */
97  APIC_PCLVTR = 0x0340, /* Performance Counter Local Vector Table (R/W) */
98  APIC_LINT0 = 0x0350, /* LINT0 Local Vector Table (R/W) */
99  APIC_LINT1 = 0x0360, /* LINT1 Local Vector Table (R/W) */
100  APIC_ERRLVTR = 0x0370, /* Error Local Vector Table (R/W) */
101  APIC_TICR = 0x0380, /* Initial Count Register for Timer (R/W) */
102  APIC_TCCR = 0x0390, /* Current Count Register for Timer (R) */
103  APIC_TDCR = 0x03E0, /* Timer Divide Configuration Register (R/W) */
104  APIC_EAFR = 0x0400, /* extended APIC Feature register (R/W) */
105  APIC_EACR = 0x0410, /* Extended APIC Control Register (R/W) */
106  APIC_SEOI = 0x0420, /* Specific End Of Interrupt Register (W) */
107  APIC_EXT0LVTR = 0x0500, /* Extended Interrupt 0 Local Vector Table */
108  APIC_EXT1LVTR = 0x0510, /* Extended Interrupt 1 Local Vector Table */
109  APIC_EXT2LVTR = 0x0520, /* Extended Interrupt 2 Local Vector Table */
110  APIC_EXT3LVTR = 0x0530 /* Extended Interrupt 3 Local Vector Table */
111 } APIC_REGISTER;
112 
113 #define MSR_APIC_BASE 0x0000001B
114 #define IOAPIC_PHYS_BASE 0xFEC00000
115 #define APIC_CLOCK_INDEX 8
116 #define ApicLogicalId(Cpu) ((UCHAR)(1<< Cpu))
117 
118 /* The following definitions are based on AMD documentation.
119  They differ slightly in Intel documentation. */
120 
121 /* Message Type (Intel: "Delivery Mode") */
122 typedef enum _APIC_MT
123 {
132 } APIC_MT;
133 
134 /* Trigger Mode */
135 typedef enum _APIC_TGM
136 {
139 } APIC_TGM;
140 
141 /* Destination Mode */
142 typedef enum _APIC_DM
143 {
146 } APIC_DM;
147 
148 /* Destination Short Hand */
149 typedef enum _APIC_DSH
150 {
155 } APIC_DSH;
156 
157 /* Write Constants */
158 typedef enum _APIC_DF
159 {
160  APIC_DF_Flat = 0xFFFFFFFF,
161  APIC_DF_Cluster = 0x0FFFFFFF
162 } APIC_DF;
163 
164 /* Remote Read Status */
165 typedef enum _APIC_RRS
166 {
170 } APIC_RRS;
171 
172 /* Timer Constants */
174 {
183 } TIMER_DV;
184 
185 #include <pshpack1.h>
187 {
189  struct
190  {
197  };
199 
201 {
203  struct
204  {
209  };
211 
213 {
215  struct
216  {
222  };
224 
226 {
228  struct
229  {
234  };
236 
238 {
240  struct
241  {
244  };
245  struct
246  {
254  UINT64 RemoteReadStatus:2; /* Intel: Reserved */
258  };
260 
261 typedef union _LVT_REGISTER
262 {
264  struct
265  {
276  };
277 } LVT_REGISTER;
278 
279 /* IOAPIC offsets */
280 enum
281 {
284 };
285 
286 /* IOAPIC Constants */
287 enum
288 {
289  IOAPIC_ID = 0x00,
290  IOAPIC_VER = 0x01,
291  IOAPIC_ARB = 0x02,
293 };
294 
296 {
298  struct
299  {
302  };
303  struct
304  {
315  };
317 #include <poppack.h>
318 
320 ULONG
322 {
323  return READ_REGISTER_ULONG((PULONG)(APIC_BASE + Register));
324 }
325 
327 VOID
329 {
330  WRITE_REGISTER_ULONG((PULONG)(APIC_BASE + Register), Value);
331 }
332 
333 VOID
334 NTAPI
336 
337 VOID
338 NTAPI
340 
341 VOID
342 NTAPI
344 
_APIC_DF
Definition: apicp.h:158
#define IN
Definition: typedefs.h:39
VOID NTAPI ApicInitializeTimer(ULONG Cpu)
Definition: apictimer.c:50
NTKERNELAPI VOID NTAPI WRITE_REGISTER_ULONG(IN PULONG Register, IN ULONG Value)
Definition: apicp.h:80
#define __cdecl
Definition: accygwin.h:79
enum _APIC_DM APIC_DM
Definition: apicp.h:87
_APIC_RRS
Definition: apicp.h:165
FORCEINLINE ULONG ApicRead(APIC_REGISTER Register)
Definition: apicp.h:321
union _APIC_INTERRUPT_COMMAND_REGISTER APIC_INTERRUPT_COMMAND_REGISTER
UINT32 Vector
Definition: apicp.h:266
UINT32 DeliveryStatus
Definition: apicp.h:269
enum _APIC_DSH APIC_DSH
Definition: apicp.h:82
NTKERNELAPI ULONG NTAPI READ_REGISTER_ULONG(IN PULONG Register)
Definition: apicp.h:85
VOID NTAPI HalInitializeProfiling(VOID)
Definition: apictimer.c:76
_APIC_TGM
Definition: apicp.h:135
UINT32 Reserved2MBZ
Definition: apicp.h:275
Definition: apicp.h:90
enum _TIMER_DV TIMER_DV
UINT32 Long
Definition: apicp.h:263
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
FORCEINLINE VOID ApicWrite(APIC_REGISTER Register, ULONG Value)
Definition: apicp.h:328
unsigned int UINT32
Definition: apicp.h:83
union _IOAPIC_REDIRECTION_REGISTER IOAPIC_REDIRECTION_REGISTER
_APIC_DM
Definition: apicp.h:142
Definition: apicp.h:92
Definition: apicp.h:79
_APIC_MT
Definition: apicp.h:122
Definition: apicp.h:89
PLOADER_PARAMETER_BLOCK KeLoaderBlock
Definition: krnlinit.c:29
UINT32 Reserved1MBZ
Definition: apicp.h:270
UINT32 TimerMode
Definition: apicp.h:274
UINT32 Mask
Definition: apicp.h:273
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING _Out_opt_ PUSHORT _Inout_opt_ PUNICODE_STRING Value
Definition: wdfregistry.h:406
enum _APIC_TGM APIC_TGM
UINT32 ReservedMBZ
Definition: apicp.h:268
_TIMER_DV
Definition: apicp.h:173
UINT32 RemoteIRR
Definition: apicp.h:271
UINT32 MessageType
Definition: apicp.h:267
enum _APIC_DF APIC_DF
union _APIC_EXTENDED_CONTROL_REGISTER APIC_EXTENDED_CONTROL_REGISTER
enum _APIC_MT APIC_MT
_APIC_REGISTER
Definition: apicp.h:77
_APIC_DSH
Definition: apicp.h:149
UINT32 ExtRegSpacePresent
Definition: apicp.h:221
Definition: apicp.h:86
#define FORCEINLINE
Definition: wdftypes.h:67
union _APIC_SPURIOUS_INERRUPT_REGISTER APIC_SPURIOUS_INERRUPT_REGISTER
unsigned int * PULONG
Definition: retypes.h:1
enum _APIC_REGISTER APIC_REGISTER
enum _APIC_RRS APIC_RRS
Definition: apicp.h:91
union _APIC_BASE_ADRESS_REGISTER APIC_BASE_ADRESS_REGISTER
union _LVT_REGISTER LVT_REGISTER
unsigned int ULONG
Definition: retypes.h:1
Definition: apicp.h:84
unsigned long long UINT64
union _APIC_VERSION_REGISTER APIC_VERSION_REGISTER
VOID __cdecl ApicSpuriousService(VOID)
UINT32 TriggerMode
Definition: apicp.h:272
#define APIC_BASE
Definition: ketypes.h:262
Definition: apicp.h:81
VOID NTAPI HalpInitApicInfo(IN PLOADER_PARAMETER_BLOCK KeLoaderBlock)