#include <ntifs.h>
#include <wdmguid.h>
#include <wchar.h>
#include <acpiioct.h>
#include <drivers/pci/pci.h>
#include <drivers/acpi/acpi.h>
#include <ndk/halfuncs.h>
#include <ndk/rtlfuncs.h>
#include <ndk/vffuncs.h>
#include <arbiter.h>
#include <cmreslist.h>

Include dependency graph for pci.h:

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Go to the source code of this file.

Classes
struct	_PCI_HACK_ENTRY

struct	_PCI_RESIZABLE_BAR_STATE

struct	_PCI_POWER_STATE

struct	_PCI_LOCK

struct	_PCI_FDO_EXTENSION

struct	_PCI_FUNCTION_RESOURCES

struct	_PCI_DEBUGGING_DEVICE

union	_PCI_HEADER_TYPE_DEPENDENT

struct	_PCI_PDO_EXTENSION

struct	_PCI_MN_DISPATCH_TABLE

struct	_PCI_MJ_DISPATCH_TABLE

struct	_PCI_INTERFACE

struct	PCI_SECONDARY_EXTENSION

struct	PCI_ARBITER_INSTANCE

struct	_PCI_VERIFIER_DATA

struct	_PCI_ID_BUFFER

struct	_PCI_CONFIGURATOR

struct	_PCI_CONFIGURATOR_CONTEXT

struct	_PCI_IPI_CONTEXT

struct	_PCI_LEGACY_DEVICE

Macros
#define	PCI_POOL_TAG 'BicP'

#define	TAG_PCI_ROUTING 'RicP'

#define	TAG_PCI_PRESERVED 'PicP'

#define	PCI_IS_ROOT_FDO(x) ((x)->BusRootFdoExtension == x)

#define	ASSERT_FDO(x) ASSERT((x)->ExtensionType == PciFdoExtensionType);

#define	ASSERT_PDO(x) ASSERT((x)->ExtensionType == PciPdoExtensionType);

#define	PCI_HACK_ENTRY_SIZE sizeof(L"VVVVdddd") - sizeof(UNICODE_NULL)

#define	PCI_HACK_ENTRY_REV_SIZE sizeof(L"VVVVddddRR") - sizeof(UNICODE_NULL)

#define	PCI_HACK_ENTRY_SUBSYS_SIZE sizeof(L"VVVVddddssssIIII") - sizeof(UNICODE_NULL)

#define	PCI_HACK_ENTRY_FULL_SIZE sizeof(L"VVVVddddssssIIIIRR") - sizeof(UNICODE_NULL)

#define	PCI_HACK_HAS_REVISION_INFO 0x01

#define	PCI_HACK_HAS_SUBSYSTEM_INFO 0x02

#define	PCI_INTERFACE_PDO 0x01

#define	PCI_INTERFACE_FDO 0x02

#define	PCI_INTERFACE_ROOT 0x04

#define	PCI_SKIP_DEVICE_ENUMERATION 0x01

#define	PCI_SKIP_RESOURCE_ENUMERATION 0x02

#define	PCI_HACK_FIXUP_BEFORE_CONFIGURATION 0x00

#define	PCI_HACK_FIXUP_AFTER_CONFIGURATION 0x01

#define	PCI_HACK_FIXUP_BEFORE_UPDATE 0x03

#define	PCI_LEGACY_CONFIG_LENGTH 0x100

#define	PCI_INTERRUPT_LINE_UNKNOWN 0xFF

#define	PCI_RBAR_EXTENDED_CAP_ID 0x0015

#define	PCI_RBAR_MAX_ENTRIES 6

#define	PCI_RBAR_ENTRY_CAPABILITY(n) (0x04 + ((n) * 8))

#define	PCI_RBAR_ENTRY_CONTROL(n) (0x08 + ((n) * 8))

#define	PCI_RBAR_CAPABILITY_SIZES_SHIFT 4

#define	PCI_RBAR_CONTROL_BAR_INDEX_MASK 0x00000007

#define	PCI_RBAR_CONTROL_COUNT_MASK 0x000000E0

#define	PCI_RBAR_CONTROL_COUNT_SHIFT 5

#define	PCI_RBAR_CONTROL_SIZE_MASK (0x3F << 8)

#define	PCI_RBAR_CONTROL_SIZE_SHIFT 8

#define	ARBITER_INTERFACE_VERSION 0

#define	MAX_DEBUGGING_DEVICES_SUPPORTED 0x04

#define	PCI_VERIFIER_CODES 0x04

#define	MAX_ANSI_STRINGS 0x08

Typedefs
typedef enum _PCI_SIGNATURE	PCI_SIGNATURE

typedef enum _PCI_SIGNATURE *	PPCI_SIGNATURE

typedef enum _PCI_DEVICE_TYPES	PCI_DEVICE_TYPES

typedef enum _PCI_STATE	PCI_STATE

typedef enum _PCI_DISPATCH_STYLE	PCI_DISPATCH_STYLE

typedef struct _PCI_HACK_ENTRY	PCI_HACK_ENTRY

typedef struct _PCI_HACK_ENTRY *	PPCI_HACK_ENTRY

typedef struct _PCI_RESIZABLE_BAR_STATE	PCI_RESIZABLE_BAR_STATE

typedef struct _PCI_RESIZABLE_BAR_STATE *	PPCI_RESIZABLE_BAR_STATE

typedef struct _PCI_POWER_STATE	PCI_POWER_STATE

typedef struct _PCI_POWER_STATE *	PPCI_POWER_STATE

typedef struct _PCI_LOCK	PCI_LOCK

typedef struct _PCI_LOCK *	PPCI_LOCK

typedef struct _PCI_FDO_EXTENSION	PCI_FDO_EXTENSION

typedef struct _PCI_FDO_EXTENSION *	PPCI_FDO_EXTENSION

typedef struct _PCI_FUNCTION_RESOURCES	PCI_FUNCTION_RESOURCES

typedef struct _PCI_FUNCTION_RESOURCES *	PPCI_FUNCTION_RESOURCES

typedef struct _PCI_DEBUGGING_DEVICE	PCI_DEBUGGING_DEVICE

typedef struct _PCI_DEBUGGING_DEVICE *	PPCI_DEBUGGING_DEVICE

typedef union _PCI_HEADER_TYPE_DEPENDENT	PCI_HEADER_TYPE_DEPENDENT

typedef union _PCI_HEADER_TYPE_DEPENDENT *	PPCI_HEADER_TYPE_DEPENDENT

typedef struct _PCI_PDO_EXTENSION	PCI_PDO_EXTENSION

typedef struct _PCI_PDO_EXTENSION *	PPCI_PDO_EXTENSION

typedef NTSTATUS(NTAPI *	PCI_DISPATCH_FUNCTION) (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PVOID DeviceExtension)

typedef struct _PCI_MN_DISPATCH_TABLE	PCI_MN_DISPATCH_TABLE

typedef struct _PCI_MN_DISPATCH_TABLE *	PPCI_MN_DISPATCH_TABLE

typedef struct _PCI_MJ_DISPATCH_TABLE	PCI_MJ_DISPATCH_TABLE

typedef struct _PCI_MJ_DISPATCH_TABLE *	PPCI_MJ_DISPATCH_TABLE

typedef NTSTATUS(NTAPI *	PCI_INTERFACE_CONSTRUCTOR) (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

typedef NTSTATUS(NTAPI *	PCI_INTERFACE_INITIALIZER) (IN PVOID Instance)

typedef struct _PCI_INTERFACE	PCI_INTERFACE

typedef struct _PCI_INTERFACE *	PPCI_INTERFACE

typedef struct PCI_SECONDARY_EXTENSION	PCI_SECONDARY_EXTENSION

typedef struct PCI_SECONDARY_EXTENSION *	PPCI_SECONDARY_EXTENSION

typedef struct PCI_ARBITER_INSTANCE	PCI_ARBITER_INSTANCE

typedef struct PCI_ARBITER_INSTANCE *	PPCI_ARBITER_INSTANCE

typedef struct _PCI_VERIFIER_DATA	PCI_VERIFIER_DATA

typedef struct _PCI_VERIFIER_DATA *	PPCI_VERIFIER_DATA

typedef struct _PCI_ID_BUFFER	PCI_ID_BUFFER

typedef struct _PCI_ID_BUFFER *	PPCI_ID_BUFFER

typedef VOID(NTAPI *	PCI_CONFIGURATOR_INITIALIZE) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

typedef VOID(NTAPI *	PCI_CONFIGURATOR_RESTORE_CURRENT) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

typedef VOID(NTAPI *	PCI_CONFIGURATOR_SAVE_LIMITS) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

typedef VOID(NTAPI *	PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

typedef NTSTATUS(NTAPI *	PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS) (_In_ PPCI_PDO_EXTENSION PdoExtension, _Inout_ PPCI_COMMON_HEADER PciData)

typedef VOID(NTAPI *	PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)

typedef VOID(NTAPI *	PCI_CONFIGURATOR_RESET_DEVICE) (IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)

typedef struct _PCI_CONFIGURATOR	PCI_CONFIGURATOR

typedef struct _PCI_CONFIGURATOR *	PPCI_CONFIGURATOR

typedef struct _PCI_CONFIGURATOR_CONTEXT	PCI_CONFIGURATOR_CONTEXT

typedef struct _PCI_CONFIGURATOR_CONTEXT *	PPCI_CONFIGURATOR_CONTEXT

typedef VOID(NTAPI *	PCI_IPI_FUNCTION) (IN PVOID Reserved, IN PVOID Context)

typedef struct _PCI_IPI_CONTEXT	PCI_IPI_CONTEXT

typedef struct _PCI_IPI_CONTEXT *	PPCI_IPI_CONTEXT

typedef struct _PCI_LEGACY_DEVICE	PCI_LEGACY_DEVICE

typedef struct _PCI_LEGACY_DEVICE *	PPCI_LEGACY_DEVICE

Enumerations
enum	_PCI_SIGNATURE { PciPdoExtensionType = 'icP0' , PciFdoExtensionType = 'icP1' , PciArb_Io = 'icP2' , PciArb_Memory = 'icP3' , PciArb_Interrupt = 'icP4' , PciArb_BusNumber = 'icP5' , PciTrans_Interrupt = 'icP6' , PciInterface_BusHandler = 'icP7' , PciInterface_IntRouteHandler = 'icP8' , PciInterface_PciCb = 'icP9' , PciInterface_LegacyDeviceDetection = 'icP:' , PciInterface_PmeHandler = 'icP;' , PciInterface_DevicePresent = 'icP<' , PciInterface_NativeIde = 'icP=' , PciInterface_AgpTarget = 'icP>' , PciInterface_Location = 'icP?' }

enum	_PCI_DEVICE_TYPES { PciTypeInvalid , PciTypeHostBridge , PciTypePciBridge , PciTypeCardbusBridge , PciTypeDevice }

enum	_PCI_STATE { PciNotStarted , PciStarted , PciDeleted , PciStopped , PciSurpriseRemoved , PciSynchronizedOperation , PciMaxObjectState }

enum	_PCI_DISPATCH_STYLE { IRP_COMPLETE , IRP_DOWNWARD , IRP_UPWARD , IRP_DISPATCH }

Functions
NTSTATUS NTAPI	PciDispatchIrp (IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp)

NTSTATUS NTAPI	PciIrpNotSupported (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPassIrpFromFdoToPdo (IN PPCI_FDO_EXTENSION DeviceExtension, IN PIRP Irp)

NTSTATUS NTAPI	PciCallDownIrpStack (IN PPCI_FDO_EXTENSION DeviceExtension, IN PIRP Irp)

NTSTATUS NTAPI	PciIrpInvalidDeviceRequest (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoWaitWake (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoSetPowerState (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpQueryPower (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciSetPowerManagedDevicePowerState (IN PPCI_PDO_EXTENSION DeviceExtension, IN DEVICE_POWER_STATE DeviceState, IN BOOLEAN IrpSet)

NTSTATUS NTAPI	PciAddDevice (IN PDRIVER_OBJECT DriverObject, IN PDEVICE_OBJECT PhysicalDeviceObject)

NTSTATUS NTAPI	PciFdoIrpStartDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpQueryRemoveDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpRemoveDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpCancelRemoveDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpStopDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpQueryStopDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpCancelStopDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpQueryDeviceRelations (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpQueryInterface (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpQueryCapabilities (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpDeviceUsageNotification (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpSurpriseRemoval (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciFdoIrpQueryLegacyBusInformation (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoCreate (IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_SLOT_NUMBER Slot, OUT PDEVICE_OBJECT *PdoDeviceObject)

NTSTATUS NTAPI	PciPdoWaitWake (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoSetPowerState (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryPower (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpStartDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryRemoveDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpRemoveDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpCancelRemoveDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpStopDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryStopDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpCancelStopDevice (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryDeviceRelations (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryInterface (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryCapabilities (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryResources (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryResourceRequirements (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryDeviceText (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpReadConfig (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpWriteConfig (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryId (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryDeviceState (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryBusInformation (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpDeviceUsageNotification (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpSurpriseRemoval (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciPdoIrpQueryLegacyBusInformation (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_PDO_EXTENSION DeviceExtension)

VOID NTAPI	PciHookHal (VOID)

VOID NTAPI	PciRestoreHalHooks (VOID)
	Gives the HAL back the routines PciHookHal replaced.

VOID NTAPI	PciVerifierInit (IN PDRIVER_OBJECT DriverObject)

VOID NTAPI	PciVerifierRelease (VOID)
	Drops the hardware profile notification taken by PciVerifierInit.

PPCI_VERIFIER_DATA NTAPI	PciVerifierRetrieveFailureData (IN ULONG FailureCode)

BOOLEAN NTAPI	PciStringToUSHORT (IN PWCHAR String, OUT PUSHORT Value)

BOOLEAN NTAPI	PciIsDatacenter (VOID)

NTSTATUS NTAPI	PciBuildDefaultExclusionLists (VOID)

BOOLEAN NTAPI	PciUnicodeStringStrStr (IN PUNICODE_STRING InputString, IN PCUNICODE_STRING EqualString, IN BOOLEAN CaseInSensitive)

BOOLEAN NTAPI	PciOpenKey (IN PWCHAR KeyName, IN HANDLE RootKey, IN ACCESS_MASK DesiredAccess, OUT PHANDLE KeyHandle, OUT PNTSTATUS KeyStatus)

NTSTATUS NTAPI	PciGetRegistryValue (IN PWCHAR ValueName, IN PWCHAR KeyName, IN HANDLE RootHandle, IN ULONG Type, OUT PVOID *OutputBuffer, OUT PULONG OutputLength)

PPCI_FDO_EXTENSION NTAPI	PciFindParentPciFdoExtension (IN PDEVICE_OBJECT DeviceObject, IN PKEVENT Lock)

VOID NTAPI	PciInsertEntryAtTail (IN PSINGLE_LIST_ENTRY ListHead, IN PPCI_FDO_EXTENSION DeviceExtension, IN PKEVENT Lock)

NTSTATUS NTAPI	PciGetDeviceProperty (IN PDEVICE_OBJECT DeviceObject, IN DEVICE_REGISTRY_PROPERTY DeviceProperty, OUT PVOID *OutputBuffer)

NTSTATUS NTAPI	PciSendIoctl (IN PDEVICE_OBJECT DeviceObject, IN ULONG IoControlCode, IN PVOID InputBuffer, IN ULONG InputBufferLength, IN PVOID OutputBuffer, IN ULONG OutputBufferLength)

VOID NTAPI	PcipLinkSecondaryExtension (IN PSINGLE_LIST_ENTRY List, IN PVOID Lock, IN PPCI_SECONDARY_EXTENSION SecondaryExtension, IN PCI_SIGNATURE ExtensionType, IN PVOID Destructor)

PPCI_SECONDARY_EXTENSION NTAPI	PciFindNextSecondaryExtension (IN PSINGLE_LIST_ENTRY ListHead, IN PCI_SIGNATURE ExtensionType)

ULONGLONG NTAPI	PciGetHackFlags (IN USHORT VendorId, IN USHORT DeviceId, IN USHORT SubVendorId, IN USHORT SubSystemId, IN UCHAR RevisionId)

PPCI_PDO_EXTENSION NTAPI	PciFindPdoByFunction (IN PPCI_FDO_EXTENSION DeviceExtension, IN ULONG FunctionNumber, IN PPCI_COMMON_HEADER PciData)

BOOLEAN NTAPI	PciIsCriticalDeviceClass (IN UCHAR BaseClass, IN UCHAR SubClass)

BOOLEAN NTAPI	PciIsDeviceOnDebugPath (IN PPCI_PDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciGetBiosConfig (IN PPCI_PDO_EXTENSION DeviceExtension, OUT PPCI_COMMON_HEADER PciData)

NTSTATUS NTAPI	PciSaveBiosConfig (IN PPCI_PDO_EXTENSION DeviceExtension, OUT PPCI_COMMON_HEADER PciData)

UCHAR NTAPI	PciReadDeviceCapability (IN PPCI_PDO_EXTENSION DeviceExtension, IN UCHAR Offset, IN ULONG CapabilityId, OUT PPCI_CAPABILITIES_HEADER Buffer, IN ULONG Length)

BOOLEAN NTAPI	PciCanDisableDecodes (IN PPCI_PDO_EXTENSION DeviceExtension, IN PPCI_COMMON_HEADER Config, IN ULONGLONG HackFlags, IN BOOLEAN ForPowerDown)

PCI_DEVICE_TYPES NTAPI	PciClassifyDeviceType (IN PPCI_PDO_EXTENSION PdoExtension)

ULONG_PTR NTAPI	PciExecuteCriticalSystemRoutine (IN ULONG_PTR IpiContext)

BOOLEAN NTAPI	PciCreateIoDescriptorFromBarLimit (_Out_ PIO_RESOURCE_DESCRIPTOR ResourceDescriptor, _In_ ULONG Bar, _In_ ULONG NextBar, _In_ BOOLEAN Rom)
	Builds the requirement of a BAR from the value it reads back after all ones were written to it.

BOOLEAN NTAPI	PciIsSlotPresentInParentMethod (IN PPCI_PDO_EXTENSION PdoExtension, IN ULONG Method)

VOID NTAPI	PciDecodeEnable (IN PPCI_PDO_EXTENSION PdoExtension, IN BOOLEAN Enable, OUT PUSHORT Command)

NTSTATUS NTAPI	PciQueryBusInformation (IN PPCI_PDO_EXTENSION PdoExtension, OUT PPNP_BUS_INFORMATION *Buffer)

NTSTATUS NTAPI	PciQueryCapabilities (IN PPCI_PDO_EXTENSION PdoExtension, IN OUT PDEVICE_CAPABILITIES DeviceCapability)

NTSTATUS NTAPI	PciGetConfigHandlers (IN PPCI_FDO_EXTENSION FdoExtension)

VOID NTAPI	PciInitializeEcam (_In_ PPCI_FDO_EXTENSION FdoExtension)
	Maps the bus an FDO decodes into the ECAM window and verifies the window the first time a bus with devices on it is seen.

VOID NTAPI	PciReleaseEcam (VOID)
	Unmaps every bus mapped through the ECAM window.

ULONG NTAPI	PciReadDeviceExtendedCapability (_In_ PPCI_PDO_EXTENSION DeviceExtension, _In_ ULONG CapabilityId, _Out_writes_bytes_(Length) PPCI_EXPRESS_ENHANCED_CAPABILITY_HEADER Buffer, _In_ ULONG Length)
	Finds an extended capability and reads it into the caller's buffer.

VOID NTAPI	PciGetExpressCapabilities (_Inout_ PPCI_PDO_EXTENSION PdoExtension)
	Records the Express capability of a new function and whether its extended configuration space can be reached.

VOID NTAPI	PciGetResizableBarCapability (_Inout_ PPCI_PDO_EXTENSION PdoExtension)
	Records which BARs of a new function can be resized and the sizes each of them supports.

ULONG NTAPI	PciAddResizableBarRequirements (_In_ PPCI_PDO_EXTENSION PdoExtension, _In_ ULONG BarIndex, _In_ PIO_RESOURCE_DESCRIPTOR Limit, _Out_writes_opt_(2) PIO_RESOURCE_DESCRIPTOR Descriptors)
	Writes the requirements for the sizes a resizable BAR can grow to. They go ahead of the default requirement, which the caller then lists as the alternative. The largest size is preferred, and the smallest supported size follows it when that is also bigger than the default.

VOID NTAPI	PciApplyResizableBarSizes (_In_ PPCI_PDO_EXTENSION PdoExtension)
	Sets every resizable BAR to the length it was assigned. The memory decode has to be off, since the size field changes what the BAR decodes. Critical devices call this from the IPI that updates their hardware.

BOOLEAN NTAPI	PciEcamReadWriteConfig (_In_ ULONG Bus, _In_ PCI_SLOT_NUMBER Slot, _Inout_updates_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length, _In_ BOOLEAN Read)
	Performs a configuration space access through the ECAM window.

VOID NTAPI	PciReadSlotConfig (IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)

VOID NTAPI	PciWriteDeviceConfig (IN PPCI_PDO_EXTENSION DeviceExtension, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)

VOID NTAPI	PciReadDeviceConfig (IN PPCI_PDO_EXTENSION DeviceExtension, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)

UCHAR NTAPI	PciGetAdjustedInterruptLine (IN PPCI_PDO_EXTENSION PdoExtension)

NTSTATUS NTAPI	PciUpdateDeviceUsage (_Inout_ PPCI_POWER_STATE PowerState, _In_ PIO_STACK_LOCATION IoStackLocation)
	Counts a paging, hibernation or dump file arriving on or leaving a device.

NTSTATUS NTAPI	PciSendDeviceUsageToParent (_In_ PPCI_FDO_EXTENSION ParentFdoExtension, _In_ PIO_STACK_LOCATION IoStackLocation)
	Sends a device usage notification to the top of the stack of a parent bus.

VOID NTAPI	PciInitializeState (IN PPCI_FDO_EXTENSION DeviceExtension)

NTSTATUS NTAPI	PciBeginStateTransition (IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_STATE NewState)

NTSTATUS NTAPI	PciCancelStateTransition (IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_STATE NewState)

VOID NTAPI	PciCommitStateTransition (IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_STATE NewState)

NTSTATUS NTAPI	PciInitializeArbiters (IN PPCI_FDO_EXTENSION FdoExtension)

NTSTATUS NTAPI	PciInitializeArbiterRanges (IN PPCI_FDO_EXTENSION DeviceExtension, IN PCM_RESOURCE_LIST Resources)

BOOLEAN NTAPI	PciDebugIrpDispatchDisplay (IN PIO_STACK_LOCATION IoStackLocation, IN PPCI_FDO_EXTENSION DeviceExtension, IN USHORT MaxMinor)

VOID NTAPI	PciDebugDumpCommonConfig (IN PPCI_COMMON_HEADER PciData)

VOID NTAPI	PciDebugDumpQueryCapabilities (IN PDEVICE_CAPABILITIES DeviceCaps)

VOID NTAPI	PciDebugPrintIoResReqList (IN PIO_RESOURCE_REQUIREMENTS_LIST Requirements)

VOID NTAPI	PciDebugPrintCmResList (IN PCM_RESOURCE_LIST ResourceList)

VOID NTAPI	PciDebugPrintPartialResource (IN PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialResource)

NTSTATUS NTAPI	PciQueryInterface (IN PPCI_FDO_EXTENSION DeviceExtension, IN CONST GUID *InterfaceType, IN ULONG Size, IN ULONG Version, IN PVOID InterfaceData, IN PINTERFACE Interface, IN BOOLEAN LastChance)

NTSTATUS NTAPI	PciPmeInterfaceInitializer (IN PVOID Instance)

NTSTATUS NTAPI	routeintrf_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	arbusno_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	arbusno_UnpackRequirement (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor, _Out_ PULONGLONG Minimum, _Out_ PULONGLONG Maximum, _Out_ PULONGLONG Length, _Out_ PULONGLONG Alignment)

NTSTATUS NTAPI	arbusno_PackResource (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor, _In_ ULONGLONG Start, _Out_ PCM_PARTIAL_RESOURCE_DESCRIPTOR Resource)

NTSTATUS NTAPI	arbusno_UnpackResource (_In_ PCM_PARTIAL_RESOURCE_DESCRIPTOR Resource, _Out_ PULONGLONG Start, _Out_ PULONGLONG Length)

INT32 NTAPI	arbusno_ScoreRequirement (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor)

NTSTATUS NTAPI	agpintrf_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	tranirq_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	busintrf_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	armem_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	ario_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	locintrf_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	pcicbintrf_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	lddintrf_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	devpresent_Initializer (IN PVOID Instance)

NTSTATUS NTAPI	agpintrf_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	arbusno_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	tranirq_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	armem_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	busintrf_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

ULONG NTAPI	PciBusInterface_GetBusData (_In_ PVOID Context, _In_ ULONG WhichSpace, _Out_writes_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)

ULONG NTAPI	PciBusInterface_SetBusData (_In_ PVOID Context, _In_ ULONG WhichSpace, _In_reads_bytes_(Length) PVOID Buffer, _In_ ULONG Offset, _In_ ULONG Length)

NTSTATUS NTAPI	ario_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

VOID NTAPI	ario_ApplyBrokenVideoHack (IN PPCI_FDO_EXTENSION FdoExtension)

NTSTATUS NTAPI	ario_UnpackRequirement (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor, _Out_ PULONGLONG Minimum, _Out_ PULONGLONG Maximum, _Out_ PULONGLONG Length, _Out_ PULONGLONG Alignment)

NTSTATUS NTAPI	ario_PackResource (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor, _In_ ULONGLONG Start, _Out_ PCM_PARTIAL_RESOURCE_DESCRIPTOR Resource)

NTSTATUS NTAPI	ario_UnpackResource (_In_ PCM_PARTIAL_RESOURCE_DESCRIPTOR Resource, _Out_ PULONGLONG Start, _Out_ PULONGLONG Length)

INT32 NTAPI	ario_ScoreRequirement (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor)

NTSTATUS NTAPI	armem_UnpackRequirement (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor, _Out_ PULONGLONG Minimum, _Out_ PULONGLONG Maximum, _Out_ PULONGLONG Length, _Out_ PULONGLONG Alignment)

NTSTATUS NTAPI	armem_PackResource (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor, _In_ ULONGLONG Start, _Out_ PCM_PARTIAL_RESOURCE_DESCRIPTOR Resource)

NTSTATUS NTAPI	armem_UnpackResource (_In_ PCM_PARTIAL_RESOURCE_DESCRIPTOR Resource, _Out_ PULONGLONG Start, _Out_ PULONGLONG Length)

INT32 NTAPI	armem_ScoreRequirement (_In_ PIO_RESOURCE_DESCRIPTOR Descriptor)

VOID NTAPI	PciArbiter_Reference (_In_ PVOID Context)

VOID NTAPI	PciArbiter_Dereference (_In_ PVOID Context)

NTSTATUS NTAPI	PciArbiterConstructor (_In_ PPCI_FDO_EXTENSION FdoExtension, _In_ PCI_SIGNATURE ArbiterType, _Out_ PARBITER_INTERFACE Interface)

NTSTATUS NTAPI	PciArbiter_PreprocessEntry (_In_ PARBITER_INSTANCE Arbiter, _Inout_ PARBITER_ALLOCATION_STATE State)
	Sets the range attributes of one arbitration entry before the engine looks for a placement for it.

BOOLEAN NTAPI	PciArbiter_FindSuitableRange (_In_ PARBITER_INSTANCE Arbiter, _Inout_ PARBITER_ALLOCATION_STATE State)
	Searches for a placement, remembering on the range whether it came from a fixed alternative.

BOOLEAN NTAPI	PciArbiter_OverrideConflict (_In_ PARBITER_INSTANCE Arbiter, _Inout_ PARBITER_ALLOCATION_STATE State)
	Lets a fixed requirement overlap ranges its own device was given by other fixed requirements.

NTSTATUS NTAPI	pcicbintrf_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	lddintrf_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	locintrf_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	PciPmeInterfaceConstructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	routeintrf_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	devpresent_Constructor (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

NTSTATUS NTAPI	PciQueryDeviceRelations (IN PPCI_FDO_EXTENSION DeviceExtension, IN OUT PDEVICE_RELATIONS *pDeviceRelations)

NTSTATUS NTAPI	PciQueryResources (IN PPCI_PDO_EXTENSION PdoExtension, OUT PCM_RESOURCE_LIST *Buffer)

NTSTATUS NTAPI	PciQueryTargetDeviceRelations (IN PPCI_PDO_EXTENSION PdoExtension, IN OUT PDEVICE_RELATIONS *pDeviceRelations)

NTSTATUS NTAPI	PciQueryEjectionRelations (IN PPCI_PDO_EXTENSION PdoExtension, IN OUT PDEVICE_RELATIONS *pDeviceRelations)

NTSTATUS NTAPI	PciQueryRequirements (IN PPCI_PDO_EXTENSION PdoExtension, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *RequirementsList)

BOOLEAN NTAPI	PciComputeNewCurrentSettings (IN PPCI_PDO_EXTENSION PdoExtension, IN PCM_RESOURCE_LIST ResourceList)

NTSTATUS NTAPI	PciSetResources (IN PPCI_PDO_EXTENSION PdoExtension, IN BOOLEAN DoReset, IN BOOLEAN SomethingSomethingDarkSide)

BOOLEAN NTAPI	PciIsRequirementDescriptor (_In_ PIO_RESOURCE_DESCRIPTOR Limit)
	Tells whether a discovered limit asks the arbiter for a range.

BOOLEAN NTAPI	PcipIsSameDevice (_In_ PPCI_PDO_EXTENSION DeviceExtension, _In_ PPCI_COMMON_HEADER PciData)

NTSTATUS NTAPI	PciBuildRequirementsList (IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData, OUT PIO_RESOURCE_REQUIREMENTS_LIST *Buffer)

PWCHAR NTAPI	PciGetDeviceDescriptionMessage (IN UCHAR BaseClass, IN UCHAR SubClass)

NTSTATUS NTAPI	PciQueryDeviceText (IN PPCI_PDO_EXTENSION PdoExtension, IN DEVICE_TEXT_TYPE QueryType, IN ULONG Locale, OUT PWCHAR *Buffer)

NTSTATUS NTAPI	PciQueryId (IN PPCI_PDO_EXTENSION DeviceExtension, IN BUS_QUERY_ID_TYPE QueryType, OUT PWCHAR *Buffer)

VOID NTAPI	Cardbus_MassageHeaderForLimitsDetermination (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Cardbus_SaveCurrentSettings (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Cardbus_SaveLimits (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Cardbus_RestoreCurrent (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Cardbus_GetAdditionalResourceDescriptors (IN PPCI_CONFIGURATOR_CONTEXT Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)

VOID NTAPI	Cardbus_ResetDevice (IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)

NTSTATUS NTAPI	Cardbus_ChangeResourceSettings (_In_ PPCI_PDO_EXTENSION PdoExtension, _Inout_ PPCI_COMMON_HEADER PciData)

VOID NTAPI	Device_MassageHeaderForLimitsDetermination (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Device_SaveCurrentSettings (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Device_SaveLimits (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Device_RestoreCurrent (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	Device_GetAdditionalResourceDescriptors (IN PPCI_CONFIGURATOR_CONTEXT Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)

VOID NTAPI	Device_ResetDevice (IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)

NTSTATUS NTAPI	Device_ChangeResourceSettings (_In_ PPCI_PDO_EXTENSION PdoExtension, _Inout_ PPCI_COMMON_HEADER PciData)
	Puts the ranges assigned to a function into its BARs and ROM BAR.

VOID NTAPI	PPBridge_MassageHeaderForLimitsDetermination (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	PPBridge_SaveCurrentSettings (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	PPBridge_SaveLimits (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	PPBridge_RestoreCurrent (IN PPCI_CONFIGURATOR_CONTEXT Context)

VOID NTAPI	PPBridge_GetAdditionalResourceDescriptors (IN PPCI_CONFIGURATOR_CONTEXT Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)

VOID NTAPI	PPBridge_ResetDevice (IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)

NTSTATUS NTAPI	PPBridge_ChangeResourceSettings (_In_ PPCI_PDO_EXTENSION PdoExtension, _Inout_ PPCI_COMMON_HEADER PciData)

BOOLEAN NTAPI	PciAreBusNumbersConfigured (IN PPCI_PDO_EXTENSION PdoExtension)

NTSTATUS NTAPI	PciCacheLegacyDeviceRouting (IN PDEVICE_OBJECT DeviceObject, IN ULONG BusNumber, IN ULONG SlotNumber, IN UCHAR InterruptLine, IN UCHAR InterruptPin, IN UCHAR BaseClass, IN UCHAR SubClass, IN PDEVICE_OBJECT PhysicalDeviceObject, IN PPCI_PDO_EXTENSION PdoExtension, OUT PDEVICE_OBJECT *pFoundDeviceObject)

VOID NTAPI	PciFreeLegacyDeviceCache (VOID)
	Frees the routing cached for slots claimed by legacy drivers.

Variables
DRIVER_DISPATCH	PciDispatchIrp

DRIVER_ADD_DEVICE	PciAddDevice

KIPI_BROADCAST_WORKER	PciExecuteCriticalSystemRoutine

SINGLE_LIST_ENTRY	PciFdoExtensionListHead

KEVENT	PciGlobalLock

PPCI_INTERFACE	PciInterfaces []

BOOLEAN	PciEcamVerified

PCI_INTERFACE	ArbiterInterfaceBusNumber

PCI_INTERFACE	ArbiterInterfaceMemory

PCI_INTERFACE	ArbiterInterfaceIo

PCI_INTERFACE	BusHandlerInterface

PCI_INTERFACE	PciRoutingInterface

PCI_INTERFACE	PciCardbusPrivateInterface

PCI_INTERFACE	PciLegacyDeviceDetectionInterface

PCI_INTERFACE	PciPmeInterface

PCI_INTERFACE	PciDevicePresentInterface

PCI_INTERFACE	PciLocationInterface

PCI_INTERFACE	AgpTargetInterface

PCI_INTERFACE	TranslatorInterfaceInterrupt

PDRIVER_OBJECT	PciDriverObject

PWATCHDOG_TABLE	WdTable

PPCI_HACK_ENTRY	PciHackTable

BOOLEAN	PciAssignBusNumbers

BOOLEAN	PciEnableNativeModeATA

PPCI_IRQ_ROUTING_TABLE	PciIrqRoutingTable

BOOLEAN	PciRunningDatacenter

PIO_RESOURCE_REQUIREMENTS_LIST	PciZeroIoResourceRequirements

RTL_RANGE_LIST	PciIsaBitExclusionList

RTL_RANGE_LIST	PciVgaAndIsaBitExclusionList

PCI_DEBUGGING_DEVICE	PciDebuggingDevices [MAX_DEBUGGING_DEVICES_SUPPORTED]

ULONG	PciDebugPortsCount

Macro Definition Documentation

◆ ARBITER_INTERFACE_VERSION

#define ARBITER_INTERFACE_VERSION 0

Definition at line 111 of file pci.h.

◆ ASSERT_FDO

#define ASSERT_FDO ( x ) ASSERT((x)->ExtensionType == PciFdoExtensionType);

Definition at line 47 of file pci.h.

◆ ASSERT_PDO

#define ASSERT_PDO ( x ) ASSERT((x)->ExtensionType == PciPdoExtensionType);

Definition at line 48 of file pci.h.

◆ MAX_ANSI_STRINGS

#define MAX_ANSI_STRINGS 0x08

Definition at line 126 of file pci.h.

◆ MAX_DEBUGGING_DEVICES_SUPPORTED

#define MAX_DEBUGGING_DEVICES_SUPPORTED 0x04

Definition at line 116 of file pci.h.

◆ PCI_HACK_ENTRY_FULL_SIZE

#define PCI_HACK_ENTRY_FULL_SIZE sizeof(L"VVVVddddssssIIIIRR") - sizeof(UNICODE_NULL)

Definition at line 56 of file pci.h.

◆ PCI_HACK_ENTRY_REV_SIZE

#define PCI_HACK_ENTRY_REV_SIZE sizeof(L"VVVVddddRR") - sizeof(UNICODE_NULL)

Definition at line 54 of file pci.h.

◆ PCI_HACK_ENTRY_SIZE

#define PCI_HACK_ENTRY_SIZE sizeof(L"VVVVdddd") - sizeof(UNICODE_NULL)

Definition at line 53 of file pci.h.

◆ PCI_HACK_ENTRY_SUBSYS_SIZE

#define PCI_HACK_ENTRY_SUBSYS_SIZE sizeof(L"VVVVddddssssIIII") - sizeof(UNICODE_NULL)

Definition at line 55 of file pci.h.

◆ PCI_HACK_FIXUP_AFTER_CONFIGURATION

#define PCI_HACK_FIXUP_AFTER_CONFIGURATION 0x01

Definition at line 81 of file pci.h.

◆ PCI_HACK_FIXUP_BEFORE_CONFIGURATION

#define PCI_HACK_FIXUP_BEFORE_CONFIGURATION 0x00

Definition at line 80 of file pci.h.

◆ PCI_HACK_FIXUP_BEFORE_UPDATE

#define PCI_HACK_FIXUP_BEFORE_UPDATE 0x03

Definition at line 82 of file pci.h.

◆ PCI_HACK_HAS_REVISION_INFO

#define PCI_HACK_HAS_REVISION_INFO 0x01

Definition at line 61 of file pci.h.

◆ PCI_HACK_HAS_SUBSYSTEM_INFO

#define PCI_HACK_HAS_SUBSYSTEM_INFO 0x02

Definition at line 62 of file pci.h.

◆ PCI_INTERFACE_FDO

#define PCI_INTERFACE_FDO 0x02

Definition at line 68 of file pci.h.

◆ PCI_INTERFACE_PDO

#define PCI_INTERFACE_PDO 0x01

Definition at line 67 of file pci.h.

◆ PCI_INTERFACE_ROOT

#define PCI_INTERFACE_ROOT 0x04

Definition at line 69 of file pci.h.

◆ PCI_INTERRUPT_LINE_UNKNOWN

#define PCI_INTERRUPT_LINE_UNKNOWN 0xFF

Definition at line 92 of file pci.h.

◆ PCI_IS_ROOT_FDO

#define PCI_IS_ROOT_FDO ( x ) ((x)->BusRootFdoExtension == x)

Definition at line 42 of file pci.h.

◆ PCI_LEGACY_CONFIG_LENGTH

#define PCI_LEGACY_CONFIG_LENGTH 0x100

Definition at line 87 of file pci.h.

◆ PCI_POOL_TAG

#define PCI_POOL_TAG 'BicP'

Definition at line 27 of file pci.h.

◆ PCI_RBAR_CAPABILITY_SIZES_SHIFT

#define PCI_RBAR_CAPABILITY_SIZES_SHIFT 4

Definition at line 101 of file pci.h.

◆ PCI_RBAR_CONTROL_BAR_INDEX_MASK

#define PCI_RBAR_CONTROL_BAR_INDEX_MASK 0x00000007

Definition at line 102 of file pci.h.

◆ PCI_RBAR_CONTROL_COUNT_MASK

#define PCI_RBAR_CONTROL_COUNT_MASK 0x000000E0

Definition at line 103 of file pci.h.

◆ PCI_RBAR_CONTROL_COUNT_SHIFT

#define PCI_RBAR_CONTROL_COUNT_SHIFT 5

Definition at line 104 of file pci.h.

◆ PCI_RBAR_CONTROL_SIZE_MASK

#define PCI_RBAR_CONTROL_SIZE_MASK (0x3F << 8)

Definition at line 105 of file pci.h.

◆ PCI_RBAR_CONTROL_SIZE_SHIFT

#define PCI_RBAR_CONTROL_SIZE_SHIFT 8

Definition at line 106 of file pci.h.

◆ PCI_RBAR_ENTRY_CAPABILITY

#define PCI_RBAR_ENTRY_CAPABILITY ( n ) (0x04 + ((n) * 8))

Definition at line 99 of file pci.h.

◆ PCI_RBAR_ENTRY_CONTROL

#define PCI_RBAR_ENTRY_CONTROL ( n ) (0x08 + ((n) * 8))

Definition at line 100 of file pci.h.

◆ PCI_RBAR_EXTENDED_CAP_ID

#define PCI_RBAR_EXTENDED_CAP_ID 0x0015

Definition at line 97 of file pci.h.

◆ PCI_RBAR_MAX_ENTRIES

#define PCI_RBAR_MAX_ENTRIES 6

Definition at line 98 of file pci.h.

◆ PCI_SKIP_DEVICE_ENUMERATION

#define PCI_SKIP_DEVICE_ENUMERATION 0x01

Definition at line 74 of file pci.h.

◆ PCI_SKIP_RESOURCE_ENUMERATION

#define PCI_SKIP_RESOURCE_ENUMERATION 0x02

Definition at line 75 of file pci.h.

◆ PCI_VERIFIER_CODES

#define PCI_VERIFIER_CODES 0x04

Definition at line 121 of file pci.h.

◆ TAG_PCI_PRESERVED

#define TAG_PCI_PRESERVED 'PicP'

Definition at line 37 of file pci.h.

◆ TAG_PCI_ROUTING

#define TAG_PCI_ROUTING 'RicP'

Definition at line 32 of file pci.h.

Typedef Documentation

◆ PCI_ARBITER_INSTANCE

typedef struct PCI_ARBITER_INSTANCE PCI_ARBITER_INSTANCE

◆ PCI_CONFIGURATOR

typedef struct _PCI_CONFIGURATOR PCI_CONFIGURATOR

◆ PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS

typedef NTSTATUS(NTAPI * PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS) (_In_ PPCI_PDO_EXTENSION PdoExtension, _Inout_ PPCI_COMMON_HEADER PciData)

Definition at line 520 of file pci.h.

◆ PCI_CONFIGURATOR_CONTEXT

typedef struct _PCI_CONFIGURATOR_CONTEXT PCI_CONFIGURATOR_CONTEXT

◆ PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS

typedef VOID(NTAPI * PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)

Definition at line 524 of file pci.h.

◆ PCI_CONFIGURATOR_INITIALIZE

typedef VOID(NTAPI * PCI_CONFIGURATOR_INITIALIZE) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

Definition at line 504 of file pci.h.

◆ PCI_CONFIGURATOR_RESET_DEVICE

typedef VOID(NTAPI * PCI_CONFIGURATOR_RESET_DEVICE) (IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)

Definition at line 530 of file pci.h.

◆ PCI_CONFIGURATOR_RESTORE_CURRENT

typedef VOID(NTAPI * PCI_CONFIGURATOR_RESTORE_CURRENT) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

Definition at line 508 of file pci.h.

◆ PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS

typedef VOID(NTAPI * PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

Definition at line 516 of file pci.h.

◆ PCI_CONFIGURATOR_SAVE_LIMITS

typedef VOID(NTAPI * PCI_CONFIGURATOR_SAVE_LIMITS) (IN struct _PCI_CONFIGURATOR_CONTEXT *Context)

Definition at line 512 of file pci.h.

◆ PCI_DEBUGGING_DEVICE

typedef struct _PCI_DEBUGGING_DEVICE PCI_DEBUGGING_DEVICE

◆ PCI_DEVICE_TYPES

typedef enum _PCI_DEVICE_TYPES PCI_DEVICE_TYPES

◆ PCI_DISPATCH_FUNCTION

typedef NTSTATUS(NTAPI * PCI_DISPATCH_FUNCTION) (IN PIRP Irp, IN PIO_STACK_LOCATION IoStackLocation, IN PVOID DeviceExtension)

Definition at line 390 of file pci.h.

◆ PCI_DISPATCH_STYLE

typedef enum _PCI_DISPATCH_STYLE PCI_DISPATCH_STYLE

◆ PCI_FDO_EXTENSION

typedef struct _PCI_FDO_EXTENSION PCI_FDO_EXTENSION

◆ PCI_FUNCTION_RESOURCES

typedef struct _PCI_FUNCTION_RESOURCES PCI_FUNCTION_RESOURCES

◆ PCI_HACK_ENTRY

typedef struct _PCI_HACK_ENTRY PCI_HACK_ENTRY

◆ PCI_HEADER_TYPE_DEPENDENT

typedef union _PCI_HEADER_TYPE_DEPENDENT PCI_HEADER_TYPE_DEPENDENT

◆ PCI_ID_BUFFER

typedef struct _PCI_ID_BUFFER PCI_ID_BUFFER

◆ PCI_INTERFACE

typedef struct _PCI_INTERFACE PCI_INTERFACE

◆ PCI_INTERFACE_CONSTRUCTOR

typedef NTSTATUS(NTAPI * PCI_INTERFACE_CONSTRUCTOR) (IN PVOID DeviceExtension, IN PVOID Instance, IN PVOID InterfaceData, IN USHORT Version, IN USHORT Size, IN PINTERFACE Interface)

Definition at line 424 of file pci.h.

◆ PCI_INTERFACE_INITIALIZER

typedef NTSTATUS(NTAPI * PCI_INTERFACE_INITIALIZER) (IN PVOID Instance)

Definition at line 433 of file pci.h.

◆ PCI_IPI_CONTEXT

typedef struct _PCI_IPI_CONTEXT PCI_IPI_CONTEXT

◆ PCI_IPI_FUNCTION

typedef VOID(NTAPI * PCI_IPI_FUNCTION) (IN PVOID Reserved, IN PVOID Context)

Definition at line 566 of file pci.h.

◆ PCI_LEGACY_DEVICE

typedef struct _PCI_LEGACY_DEVICE PCI_LEGACY_DEVICE

◆ PCI_LOCK

typedef struct _PCI_LOCK PCI_LOCK

◆ PCI_MJ_DISPATCH_TABLE

typedef struct _PCI_MJ_DISPATCH_TABLE PCI_MJ_DISPATCH_TABLE

◆ PCI_MN_DISPATCH_TABLE

typedef struct _PCI_MN_DISPATCH_TABLE PCI_MN_DISPATCH_TABLE

◆ PCI_PDO_EXTENSION

typedef struct _PCI_PDO_EXTENSION PCI_PDO_EXTENSION

◆ PCI_POWER_STATE

typedef struct _PCI_POWER_STATE PCI_POWER_STATE

◆ PCI_RESIZABLE_BAR_STATE

typedef struct _PCI_RESIZABLE_BAR_STATE PCI_RESIZABLE_BAR_STATE

◆ PCI_SECONDARY_EXTENSION

typedef struct PCI_SECONDARY_EXTENSION PCI_SECONDARY_EXTENSION

◆ PCI_SIGNATURE

typedef enum _PCI_SIGNATURE PCI_SIGNATURE

◆ PCI_STATE

typedef enum _PCI_STATE PCI_STATE

◆ PCI_VERIFIER_DATA

typedef struct _PCI_VERIFIER_DATA PCI_VERIFIER_DATA

◆ PPCI_ARBITER_INSTANCE

typedef struct PCI_ARBITER_INSTANCE * PPCI_ARBITER_INSTANCE

◆ PPCI_CONFIGURATOR

typedef struct _PCI_CONFIGURATOR * PPCI_CONFIGURATOR

◆ PPCI_CONFIGURATOR_CONTEXT

typedef struct _PCI_CONFIGURATOR_CONTEXT * PPCI_CONFIGURATOR_CONTEXT

◆ PPCI_DEBUGGING_DEVICE

typedef struct _PCI_DEBUGGING_DEVICE * PPCI_DEBUGGING_DEVICE

◆ PPCI_FDO_EXTENSION

typedef struct _PCI_FDO_EXTENSION * PPCI_FDO_EXTENSION

◆ PPCI_FUNCTION_RESOURCES

typedef struct _PCI_FUNCTION_RESOURCES * PPCI_FUNCTION_RESOURCES

◆ PPCI_HACK_ENTRY

typedef struct _PCI_HACK_ENTRY * PPCI_HACK_ENTRY

◆ PPCI_HEADER_TYPE_DEPENDENT

typedef union _PCI_HEADER_TYPE_DEPENDENT * PPCI_HEADER_TYPE_DEPENDENT

◆ PPCI_ID_BUFFER

typedef struct _PCI_ID_BUFFER * PPCI_ID_BUFFER

◆ PPCI_INTERFACE

typedef struct _PCI_INTERFACE * PPCI_INTERFACE

◆ PPCI_IPI_CONTEXT

typedef struct _PCI_IPI_CONTEXT * PPCI_IPI_CONTEXT

◆ PPCI_LEGACY_DEVICE

typedef struct _PCI_LEGACY_DEVICE * PPCI_LEGACY_DEVICE

◆ PPCI_LOCK

typedef struct _PCI_LOCK * PPCI_LOCK

◆ PPCI_MJ_DISPATCH_TABLE

typedef struct _PCI_MJ_DISPATCH_TABLE * PPCI_MJ_DISPATCH_TABLE

◆ PPCI_MN_DISPATCH_TABLE

typedef struct _PCI_MN_DISPATCH_TABLE * PPCI_MN_DISPATCH_TABLE

◆ PPCI_PDO_EXTENSION

typedef struct _PCI_PDO_EXTENSION * PPCI_PDO_EXTENSION

◆ PPCI_POWER_STATE

typedef struct _PCI_POWER_STATE * PPCI_POWER_STATE

◆ PPCI_RESIZABLE_BAR_STATE

typedef struct _PCI_RESIZABLE_BAR_STATE * PPCI_RESIZABLE_BAR_STATE

◆ PPCI_SECONDARY_EXTENSION

typedef struct PCI_SECONDARY_EXTENSION * PPCI_SECONDARY_EXTENSION

◆ PPCI_SIGNATURE

typedef enum _PCI_SIGNATURE * PPCI_SIGNATURE

◆ PPCI_VERIFIER_DATA

typedef struct _PCI_VERIFIER_DATA * PPCI_VERIFIER_DATA

Enumeration Type Documentation

◆ _PCI_DEVICE_TYPES

enum _PCI_DEVICE_TYPES

Enumerator
PciTypeInvalid
PciTypeHostBridge
PciTypePciBridge
PciTypeCardbusBridge
PciTypeDevice

Definition at line 154 of file pci.h.

{
    PciTypeInvalid,
    PciTypeHostBridge,
    PciTypePciBridge,
    PciTypeCardbusBridge,
    PciTypeDevice
} PCI_DEVICE_TYPES;

◆ _PCI_DISPATCH_STYLE

enum _PCI_DISPATCH_STYLE

Enumerator
IRP_COMPLETE
IRP_DOWNWARD
IRP_UPWARD
IRP_DISPATCH

Definition at line 180 of file pci.h.

{
    IRP_COMPLETE,
    IRP_DOWNWARD,
    IRP_UPWARD,
    IRP_DISPATCH,
} PCI_DISPATCH_STYLE;

◆ _PCI_SIGNATURE

enum _PCI_SIGNATURE

Enumerator
PciPdoExtensionType
PciFdoExtensionType
PciArb_Io
PciArb_Memory
PciArb_Interrupt
PciArb_BusNumber
PciTrans_Interrupt
PciInterface_BusHandler
PciInterface_IntRouteHandler
PciInterface_PciCb
PciInterface_LegacyDeviceDetection
PciInterface_PmeHandler
PciInterface_DevicePresent
PciInterface_NativeIde
PciInterface_AgpTarget
PciInterface_Location

Definition at line 131 of file pci.h.

{
    PciPdoExtensionType = 'icP0',
    PciFdoExtensionType = 'icP1',
    PciArb_Io = 'icP2',
    PciArb_Memory = 'icP3',
    PciArb_Interrupt = 'icP4',
    PciArb_BusNumber = 'icP5',
    PciTrans_Interrupt = 'icP6',
    PciInterface_BusHandler = 'icP7',
    PciInterface_IntRouteHandler = 'icP8',
    PciInterface_PciCb = 'icP9',
    PciInterface_LegacyDeviceDetection = 'icP:',
    PciInterface_PmeHandler = 'icP;',
    PciInterface_DevicePresent = 'icP<',
    PciInterface_NativeIde = 'icP=',
    PciInterface_AgpTarget = 'icP>',
    PciInterface_Location  = 'icP?'
} PCI_SIGNATURE, *PPCI_SIGNATURE;

◆ _PCI_STATE

enum _PCI_STATE

Enumerator
PciNotStarted
PciStarted
PciDeleted
PciStopped
PciSurpriseRemoved
PciSynchronizedOperation
PciMaxObjectState

Definition at line 166 of file pci.h.

{
    PciNotStarted,
    PciStarted,
    PciDeleted,
    PciStopped,
    PciSurpriseRemoved,
    PciSynchronizedOperation,
    PciMaxObjectState
} PCI_STATE;

Function Documentation

◆ agpintrf_Constructor()

NTSTATUS NTAPI agpintrf_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 117 of file agpintrf.c.

{
    PPCI_PDO_EXTENSION PdoExtension = (PPCI_PDO_EXTENSION)DeviceExtension;
    PAGP_TARGET_BUS_INTERFACE_STANDARD AgpInterface;
    PPCI_PDO_EXTENSION Target;
    NTSTATUS Status;
 
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Size);
    PAGED_CODE();
 
    /* Only AGP bridges are supported (which are PCI-to-PCI Bridge Devices) */
    if ((PdoExtension->BaseClass != PCI_CLASS_BRIDGE_DEV) ||
        (PdoExtension->SubClass != PCI_SUBCLASS_BR_PCI_TO_PCI))
    {
        /* Fail any other PDO */
        return STATUS_NOT_SUPPORTED;
    }
 
    /* Without its own target capability the bridge relies on a host bridge beside it */
    Target = PdoExtension;
    if (!PdoExtension->TargetAgpCapabilityId)
    {
        if (!PCI_IS_ROOT_FDO(PdoExtension->ParentFdoExtension))
            return STATUS_NOT_SUPPORTED;
 
        Status = agpintrf_FindHostBridge(PdoExtension->ParentFdoExtension, &Target);
        if (!NT_SUCCESS(Status))
            return Status;
    }
 
    AgpInterface = (PAGP_TARGET_BUS_INTERFACE_STANDARD)Interface;
    AgpInterface->Size = sizeof(*AgpInterface);
    AgpInterface->Version = Version;
    AgpInterface->Context = Target;
    AgpInterface->InterfaceReference = agpintrf_Reference;
    AgpInterface->InterfaceDereference = agpintrf_Dereference;
    AgpInterface->SetBusData = PciBusInterface_SetBusData;
    AgpInterface->GetBusData = PciBusInterface_GetBusData;
    AgpInterface->CapabilityID = Target->TargetAgpCapabilityId;
 
    return STATUS_SUCCESS;
}

◆ agpintrf_Initializer()

NTSTATUS NTAPI agpintrf_Initializer ( IN PVOID Instance )

Definition at line 107 of file agpintrf.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI agpintrf_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ arbusno_Constructor()

NTSTATUS NTAPI arbusno_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 144 of file ar_busno.c.

{
    PPCI_FDO_EXTENSION FdoExtension = (PPCI_FDO_EXTENSION)DeviceExtension;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(PciInterface);
    UNREFERENCED_PARAMETER(Version);
    UNREFERENCED_PARAMETER(Size);
 
    /* This one only arbitrates bus numbers */
    if ((ULONG_PTR)InterfaceData != CmResourceTypeBusNumber)
    {
        return STATUS_INVALID_PARAMETER_5;
    }
 
    /* Hand out the instance that was built for this bus */
    return PciArbiterConstructor(FdoExtension,
                                 PciArb_BusNumber,
                                 (PARBITER_INTERFACE)Interface);
}

◆ arbusno_Initializer()

NTSTATUS NTAPI arbusno_Initializer ( IN PVOID Instance )

Definition at line 110 of file ar_busno.c.

{
    PPCI_ARBITER_INSTANCE Arbiter = Instance;
    PPCI_FDO_EXTENSION FdoExtension;
    NTSTATUS Status;
 
    PAGED_CODE();
 
    RtlZeroMemory(&Arbiter->CommonInstance, sizeof(Arbiter->CommonInstance));
 
    FdoExtension = Arbiter->BusFdoExtension;
 
    Arbiter->CommonInstance.UnpackRequirement = arbusno_UnpackRequirement;
    Arbiter->CommonInstance.PackResource = arbusno_PackResource;
    Arbiter->CommonInstance.UnpackResource = arbusno_UnpackResource;
    Arbiter->CommonInstance.ScoreRequirement = arbusno_ScoreRequirement;
    Arbiter->CommonInstance.PreprocessEntry = PciArbiter_PreprocessEntry;
 
    Status = ArbiterLibInitializeInstance(&Arbiter->CommonInstance,
                                          FdoExtension->FunctionalDeviceObject,
                                          CmResourceTypeBusNumber,
                                          Arbiter->InstanceName,
                                          L"Pci",
                                          NULL);
    if (!NT_SUCCESS(Status))
    {
        DPRINT1("PCIX - arbusno_Initializer: init arbiter return %X\n", Status);
    }
 
    return Status;
}

◆ arbusno_PackResource()

NTSTATUS NTAPI arbusno_PackResource	(	_In_ PIO_RESOURCE_DESCRIPTOR	Descriptor,
		_In_ ULONGLONG	Start,
		_Out_ PCM_PARTIAL_RESOURCE_DESCRIPTOR	Resource
	)

Definition at line 54 of file ar_busno.c.

{
    /* Turn the run of bus numbers the engine settled on into a resource */
    if (Descriptor->Type != CmResourceTypeBusNumber) return STATUS_INVALID_PARAMETER;
 
    Resource->Type = CmResourceTypeBusNumber;
    Resource->Flags = Descriptor->Flags;
    Resource->ShareDisposition = Descriptor->ShareDisposition;
    Resource->u.BusNumber.Start = (ULONG)Start;
    Resource->u.BusNumber.Length = Descriptor->u.BusNumber.Length;
    return STATUS_SUCCESS;
}

Referenced by arbusno_Initializer().

◆ arbusno_ScoreRequirement()

INT32 NTAPI arbusno_ScoreRequirement ( _In_ PIO_RESOURCE_DESCRIPTOR Descriptor )

Definition at line 85 of file ar_busno.c.

{
    ULONGLONG Minimum, Maximum, Length, Alignment;
 
    /* A requirement this arbiter cannot read is treated as unsatisfiable */
    if (!NT_SUCCESS(arbusno_UnpackRequirement(Descriptor,
                                              &Minimum,
                                              &Maximum,
                                              &Length,
                                              &Alignment)) ||
        (Maximum < Minimum))
    {
        return -1;
    }
 
    /*
     * The score is how many places the run could go, so that the engine places
     * the most constrained requirements first.
     */
    if ((Maximum - Minimum) >= MAXLONG) return MAXLONG;
    return (INT32)(Maximum - Minimum + 1);
}

Referenced by arbusno_Initializer().

◆ arbusno_UnpackRequirement()

NTSTATUS NTAPI arbusno_UnpackRequirement	(	_In_ PIO_RESOURCE_DESCRIPTOR	Descriptor,
		_Out_ PULONGLONG	Minimum,
		_Out_ PULONGLONG	Maximum,
		_Out_ PULONGLONG	Length,
		_Out_ PULONGLONG	Alignment
	)

Definition at line 35 of file ar_busno.c.

{
    /* This arbiter is only ever handed bus number descriptors */
    if (Descriptor->Type != CmResourceTypeBusNumber) return STATUS_INVALID_PARAMETER;
 
    /* Bus numbers are counted, not addressed, so they are always unit-aligned */
    *Minimum = Descriptor->u.BusNumber.MinBusNumber;
    *Maximum = Descriptor->u.BusNumber.MaxBusNumber;
    *Length = Descriptor->u.BusNumber.Length;
    *Alignment = 1;
    return STATUS_SUCCESS;
}

Referenced by arbusno_Initializer(), and arbusno_ScoreRequirement().

◆ arbusno_UnpackResource()

NTSTATUS NTAPI arbusno_UnpackResource	(	_In_ PCM_PARTIAL_RESOURCE_DESCRIPTOR	Resource,
		_Out_ PULONGLONG	Start,
		_Out_ PULONGLONG	Length
	)

Definition at line 71 of file ar_busno.c.

{
    /* Read a previously packed run of bus numbers back out */
    if (Resource->Type != CmResourceTypeBusNumber) return STATUS_INVALID_PARAMETER;
 
    *Start = Resource->u.BusNumber.Start;
    *Length = Resource->u.BusNumber.Length;
    return STATUS_SUCCESS;
}

Referenced by arbusno_Initializer().

◆ ario_ApplyBrokenVideoHack()

VOID NTAPI ario_ApplyBrokenVideoHack ( IN PPCI_FDO_EXTENSION FdoExtension )

Definition at line 184 of file ar_memio.c.

{
    PPCI_ARBITER_INSTANCE PciArbiter;
    PARBITER_INSTANCE CommonInstance;
    NTSTATUS Status;
 
    /* Only valid for root FDOs who are being applied the hack for the first time */
    ASSERT(!FdoExtension->BrokenVideoHackApplied);
    ASSERT(PCI_IS_ROOT_FDO(FdoExtension));
 
    /* Find the I/O arbiter */
    PciArbiter = (PVOID)PciFindNextSecondaryExtension(FdoExtension->
                                                      SecondaryExtension.Next,
                                                      PciArb_Io);
    ASSERT(PciArbiter);
    if (!PciArbiter) return;
 
    /* Get the Arb instance */
    CommonInstance = &PciArbiter->CommonInstance;
 
    /* Free the two lists, enabling full VGA access */
    ArbiterLibFreeOrderingList(&CommonInstance->OrderingList);
    ArbiterLibFreeOrderingList(&CommonInstance->ReservedList);
 
    /* Build the ordering for broken video PCI access */
    Status = ArbiterLibDefaultAssignmentOrdering(CommonInstance,
                                                 L"Pci",
                                                 L"BrokenVideo",
                                                 NULL);
    ASSERT(NT_SUCCESS(Status));
    if (!NT_SUCCESS(Status))
    {
        DPRINT1("PCIX - ario_ApplyBrokenVideoHack: ordering failed %X\n", Status);
    }
 
    /* Now the hack has been applied */
    FdoExtension->BrokenVideoHackApplied = TRUE;
}

Referenced by PciApplyHacks().

◆ ario_Constructor()

NTSTATUS NTAPI ario_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 156 of file ar_memio.c.

{
    PPCI_FDO_EXTENSION FdoExtension = (PPCI_FDO_EXTENSION)DeviceExtension;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(PciInterface);
    UNREFERENCED_PARAMETER(Version);
    UNREFERENCED_PARAMETER(Size);
 
    /* This one only arbitrates I/O ports */
    if ((ULONG_PTR)InterfaceData != CmResourceTypePort)
    {
        return STATUS_INVALID_PARAMETER_5;
    }
 
    /* Hand out the instance that was built for this bus */
    return PciArbiterConstructor(FdoExtension,
                                 PciArb_Io,
                                 (PARBITER_INTERFACE)Interface);
}

◆ ario_Initializer()

NTSTATUS NTAPI ario_Initializer ( IN PVOID Instance )

Definition at line 119 of file ar_memio.c.

{
    PPCI_ARBITER_INSTANCE Arbiter = Instance;
    PPCI_FDO_EXTENSION FdoExtension;
    NTSTATUS Status;
    PAGED_CODE();
 
    /* Start from a clean engine instance */
    RtlZeroMemory(&Arbiter->CommonInstance, sizeof(Arbiter->CommonInstance));
    FdoExtension = Arbiter->BusFdoExtension;
 
    /* Teach the engine how to read and write I/O port descriptors */
    Arbiter->CommonInstance.UnpackRequirement = ario_UnpackRequirement;
    Arbiter->CommonInstance.PackResource = ario_PackResource;
    Arbiter->CommonInstance.UnpackResource = ario_UnpackResource;
    Arbiter->CommonInstance.ScoreRequirement = ario_ScoreRequirement;
    Arbiter->CommonInstance.PreprocessEntry = PciArbiter_PreprocessEntry;
    Arbiter->CommonInstance.FindSuitableRange = PciArbiter_FindSuitableRange;
    Arbiter->CommonInstance.OverrideConflict = PciArbiter_OverrideConflict;
 
    /* The rest of the engine, and the PCI assignment ordering, is generic */
    Status = ArbiterLibInitializeInstance(&Arbiter->CommonInstance,
                                          FdoExtension->FunctionalDeviceObject,
                                          CmResourceTypePort,
                                          Arbiter->InstanceName,
                                          L"Pci",
                                          NULL);
    if (!NT_SUCCESS(Status))
    {
        DPRINT1("PCIX - ario_Initializer: init arbiter returned %X\n", Status);
    }
 
    return Status;
}

◆ ario_PackResource()

NTSTATUS NTAPI ario_PackResource	(	_In_ PIO_RESOURCE_DESCRIPTOR	Descriptor,
		_In_ ULONGLONG	Start,
		_Out_ PCM_PARTIAL_RESOURCE_DESCRIPTOR	Resource
	)

Definition at line 67 of file ar_memio.c.

{
    /* Turn the placement the engine settled on back into an I/O port resource */
    if (Descriptor->Type != CmResourceTypePort) return STATUS_INVALID_PARAMETER;
 
    Resource->Type = CmResourceTypePort;
    Resource->Flags = Descriptor->Flags;
    Resource->ShareDisposition = Descriptor->ShareDisposition;
    Resource->u.Port.Start.QuadPart = (LONGLONG)Start;
    Resource->u.Port.Length = Descriptor->u.Port.Length;
    return STATUS_SUCCESS;
}

Referenced by ario_Initializer().

◆ ario_ScoreRequirement()

INT32 NTAPI ario_ScoreRequirement ( _In_ PIO_RESOURCE_DESCRIPTOR Descriptor )

Definition at line 98 of file ar_memio.c.

{
    ULONGLONG Minimum, Maximum, Length, Alignment;
 
    /* A requirement this arbiter cannot read is treated as unsatisfiable */
    if (!NT_SUCCESS(ario_UnpackRequirement(Descriptor,
                                           &Minimum,
                                           &Maximum,
                                           &Length,
                                           &Alignment)) ||
        (Maximum < Minimum))
    {
        return -1;
    }
 
    if ((Maximum - Minimum) >= MAXLONG) return MAXLONG;
    return (INT32)(Maximum - Minimum + 1);
}

Referenced by ario_Initializer().

◆ ario_UnpackRequirement()

NTSTATUS NTAPI ario_UnpackRequirement	(	_In_ PIO_RESOURCE_DESCRIPTOR	Descriptor,
		_Out_ PULONGLONG	Minimum,
		_Out_ PULONGLONG	Maximum,
		_Out_ PULONGLONG	Length,
		_Out_ PULONGLONG	Alignment
	)

Definition at line 48 of file ar_memio.c.

{
    /* This arbiter is only ever handed I/O port descriptors */
    if (Descriptor->Type != CmResourceTypePort) return STATUS_INVALID_PARAMETER;
 
    /* An alignment of zero would place the range nowhere, so make it one byte */
    *Minimum = (ULONGLONG)Descriptor->u.Port.MinimumAddress.QuadPart;
    *Maximum = (ULONGLONG)Descriptor->u.Port.MaximumAddress.QuadPart;
    *Length = Descriptor->u.Port.Length;
    *Alignment = Descriptor->u.Port.Alignment ? Descriptor->u.Port.Alignment : 1;
    return STATUS_SUCCESS;
}

Referenced by ario_Initializer(), and ario_ScoreRequirement().

◆ ario_UnpackResource()

NTSTATUS NTAPI ario_UnpackResource	(	_In_ PCM_PARTIAL_RESOURCE_DESCRIPTOR	Resource,
		_Out_ PULONGLONG	Start,
		_Out_ PULONGLONG	Length
	)

Definition at line 84 of file ar_memio.c.

{
    /* Read a previously packed I/O port resource back out */
    if (Resource->Type != CmResourceTypePort) return STATUS_INVALID_PARAMETER;
 
    *Start = (ULONGLONG)Resource->u.Port.Start.QuadPart;
    *Length = Resource->u.Port.Length;
    return STATUS_SUCCESS;
}

Referenced by ario_Initializer().

◆ armem_Constructor()

NTSTATUS NTAPI armem_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 345 of file ar_memio.c.

{
    PPCI_FDO_EXTENSION FdoExtension = (PPCI_FDO_EXTENSION)DeviceExtension;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(PciInterface);
    UNREFERENCED_PARAMETER(Version);
    UNREFERENCED_PARAMETER(Size);
 
    /* This one only arbitrates device memory */
    if ((ULONG_PTR)InterfaceData != CmResourceTypeMemory)
    {
        return STATUS_INVALID_PARAMETER_5;
    }
 
    /* Hand out the instance that was built for this bus */
    return PciArbiterConstructor(FdoExtension,
                                 PciArb_Memory,
                                 (PARBITER_INTERFACE)Interface);
}

◆ armem_Initializer()

NTSTATUS NTAPI armem_Initializer ( IN PVOID Instance )

Definition at line 308 of file ar_memio.c.

{
    PPCI_ARBITER_INSTANCE Arbiter = Instance;
    PPCI_FDO_EXTENSION FdoExtension;
    NTSTATUS Status;
    PAGED_CODE();
 
    /* Start from a clean engine instance */
    RtlZeroMemory(&Arbiter->CommonInstance, sizeof(Arbiter->CommonInstance));
    FdoExtension = Arbiter->BusFdoExtension;
 
    /* Teach the engine how to read and write memory descriptors */
    Arbiter->CommonInstance.UnpackRequirement = armem_UnpackRequirement;
    Arbiter->CommonInstance.PackResource = armem_PackResource;
    Arbiter->CommonInstance.UnpackResource = armem_UnpackResource;
    Arbiter->CommonInstance.ScoreRequirement = armem_ScoreRequirement;
    Arbiter->CommonInstance.PreprocessEntry = PciArbiter_PreprocessEntry;
    Arbiter->CommonInstance.FindSuitableRange = PciArbiter_FindSuitableRange;
    Arbiter->CommonInstance.OverrideConflict = PciArbiter_OverrideConflict;
 
    /* The rest of the engine, and the PCI assignment ordering, is generic */
    Status = ArbiterLibInitializeInstance(&Arbiter->CommonInstance,
                                          FdoExtension->FunctionalDeviceObject,
                                          CmResourceTypeMemory,
                                          Arbiter->InstanceName,
                                          L"Pci",
                                          NULL);
    if (!NT_SUCCESS(Status))
    {
        DPRINT1("PCIX - armem_Initializer: init arbiter returned %X\n", Status);
    }
 
    return Status;
}

◆ armem_PackResource()

NTSTATUS NTAPI armem_PackResource	(	_In_ PIO_RESOURCE_DESCRIPTOR	Descriptor,
		_In_ ULONGLONG	Start,
		_Out_ PCM_PARTIAL_RESOURCE_DESCRIPTOR	Resource
	)

Definition at line 248 of file ar_memio.c.

{
    /* Turn the placement the engine settled on back into a memory resource */
    if ((Descriptor->Type != CmResourceTypeMemory) &&
        (Descriptor->Type != CmResourceTypeMemoryLarge))
    {
        return STATUS_INVALID_PARAMETER;
    }
 
    /* The flags say how a large length is scaled, so both come across unchanged */
    Resource->Type = Descriptor->Type;
    Resource->Flags = Descriptor->Flags;
    Resource->ShareDisposition = Descriptor->ShareDisposition;
    Resource->u.Memory.Start.QuadPart = (LONGLONG)Start;
    Resource->u.Memory.Length = Descriptor->u.Memory.Length;
    return STATUS_SUCCESS;
}

Referenced by armem_Initializer().

◆ armem_ScoreRequirement()

INT32 NTAPI armem_ScoreRequirement ( _In_ PIO_RESOURCE_DESCRIPTOR Descriptor )

Definition at line 287 of file ar_memio.c.

{
    ULONGLONG Minimum, Maximum, Length, Alignment;
 
    /* A requirement this arbiter cannot read is treated as unsatisfiable */
    if (!NT_SUCCESS(armem_UnpackRequirement(Descriptor,
                                            &Minimum,
                                            &Maximum,
                                            &Length,
                                            &Alignment)) ||
        (Maximum < Minimum))
    {
        return -1;
    }
 
    if ((Maximum - Minimum) >= MAXLONG) return MAXLONG;
    return (INT32)(Maximum - Minimum + 1);
}

Referenced by armem_Initializer().

◆ armem_UnpackRequirement()

NTSTATUS NTAPI armem_UnpackRequirement	(	_In_ PIO_RESOURCE_DESCRIPTOR	Descriptor,
		_Out_ PULONGLONG	Minimum,
		_Out_ PULONGLONG	Maximum,
		_Out_ PULONGLONG	Length,
		_Out_ PULONGLONG	Alignment
	)

Definition at line 225 of file ar_memio.c.

{
    /* This arbiter is only ever handed device memory descriptors, large ones included */
    if ((Descriptor->Type != CmResourceTypeMemory) &&
        (Descriptor->Type != CmResourceTypeMemoryLarge))
    {
        return STATUS_INVALID_PARAMETER;
    }
 
    /* An alignment of zero would place the range nowhere, so make it one byte */
    *Length = RtlIoDecodeMemIoResource(Descriptor, Alignment, Minimum, Maximum);
    if (!*Alignment)
        *Alignment = 1;
 
    return STATUS_SUCCESS;
}

Referenced by armem_Initializer(), and armem_ScoreRequirement().

◆ armem_UnpackResource()

NTSTATUS NTAPI armem_UnpackResource	(	_In_ PCM_PARTIAL_RESOURCE_DESCRIPTOR	Resource,
		_Out_ PULONGLONG	Start,
		_Out_ PULONGLONG	Length
	)

Definition at line 270 of file ar_memio.c.

{
    /* Read a previously packed memory resource back out */
    if ((Resource->Type != CmResourceTypeMemory) &&
        (Resource->Type != CmResourceTypeMemoryLarge))
    {
        return STATUS_INVALID_PARAMETER;
    }
 
    *Length = RtlCmDecodeMemIoResource(Resource, Start);
    return STATUS_SUCCESS;
}

Referenced by armem_Initializer().

◆ busintrf_Constructor()

NTSTATUS NTAPI busintrf_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 142 of file busintrf.c.

{
    PBUS_INTERFACE_STANDARD BusInterface;
    PPCI_PDO_EXTENSION PdoExtension;
 
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Version);
    PAGED_CODE();
 
    if (Size < sizeof(BUS_INTERFACE_STANDARD))
    {
        return STATUS_UNSUCCESSFUL;
    }
 
    BusInterface = (PBUS_INTERFACE_STANDARD)Interface;
    PdoExtension = (PPCI_PDO_EXTENSION)DeviceExtension;
 
    BusInterface->Size = sizeof(*BusInterface);
    BusInterface->Version = 1;
    BusInterface->Context = PdoExtension;
    BusInterface->InterfaceReference = PciBusInterface_Reference;
    BusInterface->InterfaceDereference = PciBusInterface_Dereference;
 
    BusInterface->TranslateBusAddress = PciBusInterface_TranslateBusAddress;
    BusInterface->GetDmaAdapter = PciBusInterface_GetDmaAdapter;
    BusInterface->SetBusData = PciBusInterface_SetBusData;
    BusInterface->GetBusData = PciBusInterface_GetBusData;
 
    return STATUS_SUCCESS;
}

◆ busintrf_Initializer()

NTSTATUS NTAPI busintrf_Initializer ( IN PVOID Instance )

Definition at line 132 of file busintrf.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI busintrf_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ Cardbus_ChangeResourceSettings()

NTSTATUS NTAPI Cardbus_ChangeResourceSettings	(	_In_ PPCI_PDO_EXTENSION	PdoExtension,
		_Inout_ PPCI_COMMON_HEADER	PciData
	)

Definition at line 149 of file cardbus.c.

{
    PPCI_FUNCTION_RESOURCES Resources;
    ULONG Bar, BarMask;
 
    /* The socket register BAR gets its assigned address, or zero when it was given none */
    Resources = PdoExtension->Resources;
    if ((Resources) && (Resources->Limit[0].Type != CmResourceTypeNull))
    {
        Bar = PciData->u.type2.SocketRegistersBaseAddress;
        if (Bar & PCI_ADDRESS_IO_SPACE)
        {
            BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
        }
        else
        {
            BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
        }
 
        Bar &= ~BarMask;
        if (Resources->Current[0].Type != CmResourceTypeNull)
            Bar |= Resources->Current[0].u.Generic.Start.LowPart & BarMask;
 
        PciData->u.type2.SocketRegistersBaseAddress = Bar;
    }
 
    /* The windows stay as read, only what a power loss would wipe is written again */
    PciData->u.type2.PrimaryBus = PdoExtension->Dependent.type1.PrimaryBus;
    PciData->u.type2.SecondaryBus = PdoExtension->Dependent.type1.SecondaryBus;
    PciData->u.type2.SubordinateBus = PdoExtension->Dependent.type1.SubordinateBus;
 
    if (PdoExtension->Dependent.type1.VgaBitSet)
        PciData->u.type2.BridgeControl |= PCI_ENABLE_BRIDGE_VGA;
 
    return STATUS_SUCCESS;
}

◆ Cardbus_GetAdditionalResourceDescriptors()

VOID NTAPI Cardbus_GetAdditionalResourceDescriptors	(	IN PPCI_CONFIGURATOR_CONTEXT	Context,
		IN PPCI_COMMON_HEADER	PciData,
		IN PIO_RESOURCE_DESCRIPTOR	IoDescriptor
	)

Definition at line 128 of file cardbus.c.

{
    /* The VGA enable is the same bit as on a PCI-to-PCI bridge */
    PPBridge_GetAdditionalResourceDescriptors(Context, PciData, IoDescriptor);
}

◆ Cardbus_MassageHeaderForLimitsDetermination()

VOID NTAPI Cardbus_MassageHeaderForLimitsDetermination ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 102 of file cardbus.c.

{
    PPCI_COMMON_HEADER Current, PciData;
 
    Current = Context->Current;
    PciData = Context->PciData;
 
    /* Only the socket register BAR is sized, the windows keep what the firmware wrote */
    PciData->u.type2.SocketRegistersBaseAddress = 0xFFFFFFFF;
 
    /* Writing the error bits back would clear them, so keep them out of the probe */
    Context->SecondaryStatus = Current->u.type2.SecondaryStatus;
    Current->u.type2.SecondaryStatus = 0;
    PciData->u.type2.SecondaryStatus = 0;
}

◆ Cardbus_ResetDevice()

VOID NTAPI Cardbus_ResetDevice	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN PPCI_COMMON_HEADER	PciData
	)

Definition at line 138 of file cardbus.c.

{
    UNREFERENCED_PARAMETER(PdoExtension);
    UNREFERENCED_PARAMETER(PciData);
 
    /* The socket reset bit belongs to the socket driver, so it goes back as it was read */
}

◆ Cardbus_RestoreCurrent()

VOID NTAPI Cardbus_RestoreCurrent ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 120 of file cardbus.c.

{
    /* Put back the secondary status that was held out of the probe */
    Context->Current->u.type2.SecondaryStatus = Context->SecondaryStatus;
}

◆ Cardbus_SaveCurrentSettings()

VOID NTAPI Cardbus_SaveCurrentSettings ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 39 of file cardbus.c.

{
    PPCI_PDO_EXTENSION PdoExtension;
    PPCI_COMMON_HEADER Current;
    PIO_RESOURCE_DESCRIPTOR Limit;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR Partial;
    ULONG Address;
 
    PdoExtension = Context->PdoExtension;
    Current = Context->Current;
    Limit = &PdoExtension->Resources->Limit[0];
    Partial = &PdoExtension->Resources->Current[0];
 
    /* Only the socket register BAR is tracked, the four windows are left to the socket driver */
    Partial->Type = Limit->Type;
    if (Limit->Type != CmResourceTypeNull)
    {
        Address = Current->u.type2.SocketRegistersBaseAddress;
        if (Limit->Type == CmResourceTypePort)
        {
            Address &= PCI_ADDRESS_IO_ADDRESS_MASK;
        }
        else
        {
            Address &= PCI_ADDRESS_MEMORY_ADDRESS_MASK;
        }
 
        Partial->Flags = Limit->Flags;
        Partial->ShareDisposition = Limit->ShareDisposition;
        Partial->u.Generic.Start.QuadPart = Address;
        Partial->u.Generic.Length = Limit->u.Generic.Length;
 
        /* A BAR the firmware never placed decodes nothing yet */
        if (!Address)
            Partial->Type = CmResourceTypeNull;
    }
 
    /* Remember the bus numbers so they survive the function losing power */
    PdoExtension->Dependent.type1.PrimaryBus = Current->u.type2.PrimaryBus;
    PdoExtension->Dependent.type1.SecondaryBus = Current->u.type2.SecondaryBus;
    PdoExtension->Dependent.type1.SubordinateBus = Current->u.type2.SubordinateBus;
 
    /* A bridge that forwards VGA also claims the legacy video ranges */
    if (Current->u.type2.BridgeControl & PCI_ENABLE_BRIDGE_VGA)
    {
        PdoExtension->Dependent.type1.VgaBitSet = TRUE;
        PdoExtension->AdditionalResourceCount = 4;
    }
}

◆ Cardbus_SaveLimits()

VOID NTAPI Cardbus_SaveLimits ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 91 of file cardbus.c.

{
    /* The socket register BAR is 32-bit only, so it never takes a high half from the next field */
    PciCreateIoDescriptorFromBarLimit(&Context->PdoExtension->Resources->Limit[0],
                                      Context->PciData->u.type2.SocketRegistersBaseAddress,
                                      0,
                                      FALSE);
}

◆ Device_ChangeResourceSettings()

NTSTATUS NTAPI Device_ChangeResourceSettings	(	_In_ PPCI_PDO_EXTENSION	PdoExtension,
		_Inout_ PPCI_COMMON_HEADER	PciData
	)

Puts the ranges assigned to a function into its BARs and ROM BAR.

Parameters

[in]	PdoExtension	The PDO extension of the function.
[in,out]	PciData	The header that will be written to the function.

Returns: STATUS_INVALID_PARAMETER if a BAR would decode an address nobody assigned to it.

Definition at line 308 of file device.c.

{
    PPCI_FUNCTION_RESOURCES Resources;
    PIO_RESOURCE_DESCRIPTOR Limit;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
    PULONG BarArray;
    ULONG Bar, BarMask, i;
    USHORT Decode;
    BOOLEAN IsVga, HasUpperHalf;
 
    Resources = PdoExtension->Resources;
    if (!Resources)
        return STATUS_SUCCESS;
 
    /* VGA decodes are forced on at start, so a BAR it was not given may stay empty */
    IsVga = ((PdoExtension->BaseClass == PCI_CLASS_PRE_20) &&
             (PdoExtension->SubClass == PCI_SUBCLASS_PRE_20_VGA)) ||
            ((PdoExtension->BaseClass == PCI_CLASS_DISPLAY_CTLR) &&
             (PdoExtension->SubClass == PCI_SUBCLASS_VID_VGA_CTLR));
 
    BarArray = PciData->u.type0.BaseAddresses;
    for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
    {
        Limit = &Resources->Limit[i];
        CmDescriptor = &Resources->Current[i];
 
        if (CmDescriptor->Type == CmResourceTypeNull)
        {
            /* A requested BAR left without a range must not decode while its space is on */
            Decode = (Limit->Type == CmResourceTypePort) ? PCI_ENABLE_IO_SPACE :
                                                           PCI_ENABLE_MEMORY_SPACE;
            if (PciIsRequirementDescriptor(Limit) &&
                (PdoExtension->CommandEnables & Decode) &&
                !IsVga)
            {
                DPRINT1("PCIX - pdox %p BAR %lu has no range but its decode stays on\n",
                        PdoExtension,
                        i);
                return STATUS_INVALID_PARAMETER;
            }
 
            BarArray[i] = 0;
            continue;
        }
 
        /* The limit says what the BAR decodes, its read-only low bits say how wide it is */
        Bar = BarArray[i];
        HasUpperHalf = FALSE;
        if (Limit->Type == CmResourceTypePort)
        {
            BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
        }
        else if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
        {
            BarMask = 0xFFFF0;
        }
        else
        {
            BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
            HasUpperHalf = ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT) &&
                           ((i + 1) < PCI_TYPE0_ADDRESSES);
        }
 
        if (!HasUpperHalf && CmDescriptor->u.Generic.Start.HighPart)
        {
            DPRINT1("PCIX - pdox %p BAR %lu cannot hold address %I64x\n",
                    PdoExtension,
                    i,
                    CmDescriptor->u.Generic.Start.QuadPart);
            return STATUS_INVALID_PARAMETER;
        }
 
        BarArray[i] = (Bar & ~BarMask) | (CmDescriptor->u.Generic.Start.LowPart & BarMask);
        if (HasUpperHalf)
        {
            i++;
            BarArray[i] = CmDescriptor->u.Generic.Start.HighPart;
        }
    }
 
    /* The ROM decodes only while its enable bit is set, and reads zero when it has no range */
    CmDescriptor = &Resources->Current[PCI_TYPE0_ADDRESSES];
    if (CmDescriptor->Type == CmResourceTypeNull)
    {
        PciData->u.type0.ROMBaseAddress = 0;
    }
    else
    {
        Bar = PciData->u.type0.ROMBaseAddress & ~PCI_ADDRESS_ROM_ADDRESS_MASK;
        PciData->u.type0.ROMBaseAddress = Bar |
                                          (CmDescriptor->u.Generic.Start.LowPart &
                                           PCI_ADDRESS_ROM_ADDRESS_MASK) |
                                          PCI_ROMADDRESS_ENABLED;
    }
 
    return STATUS_SUCCESS;
}

◆ Device_GetAdditionalResourceDescriptors()

VOID NTAPI Device_GetAdditionalResourceDescriptors	(	IN PPCI_CONFIGURATOR_CONTEXT	Context,
		IN PPCI_COMMON_HEADER	PciData,
		IN PIO_RESOURCE_DESCRIPTOR	IoDescriptor
	)

Definition at line 271 of file device.c.

{
    UNREFERENCED_PARAMETER(Context);
    UNREFERENCED_PARAMETER(PciData);
    UNREFERENCED_PARAMETER(IoDescriptor);
 
    /* A device decodes nothing beyond its BARs, only bridges add ranges here */
}

◆ Device_MassageHeaderForLimitsDetermination()

VOID NTAPI Device_MassageHeaderForLimitsDetermination ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 230 of file device.c.

{
    PPCI_COMMON_HEADER PciData;
    PPCI_PDO_EXTENSION PdoExtension;
    PULONG BarArray;
    ULONG i = 0;
 
    /* Get pointers from context data */
    PdoExtension = Context->PdoExtension;
    PciData = Context->PciData;
 
    /* Get the array of BARs */
    BarArray = PciData->u.type0.BaseAddresses;
 
    /* Check for IDE controllers that are not in native mode */
    if ((PdoExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
        (PdoExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR) &&
        (PdoExtension->ProgIf & 5) != 5)
    {
        /* These controllers only use legacy resources */
        i = 4;
    }
 
    /* Set all the bits on, which will allow us to recover the limit data */
    for (i = 0; i < PCI_TYPE0_ADDRESSES; i++) BarArray[i] = 0xFFFFFFFF;
 
    /* Do the same for the PCI ROM BAR */
    PciData->u.type0.ROMBaseAddress = PCI_ADDRESS_ROM_ADDRESS_MASK;
}

◆ Device_ResetDevice()

VOID NTAPI Device_ResetDevice	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN PPCI_COMMON_HEADER	PciData
	)

Definition at line 284 of file device.c.

{
    UNREFERENCED_PARAMETER(PdoExtension);
    UNREFERENCED_PARAMETER(PciData);
 
    /* Nothing to undo, the caller writes the whole header back */
}

◆ Device_RestoreCurrent()

VOID NTAPI Device_RestoreCurrent ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 262 of file device.c.

{
    UNREFERENCED_PARAMETER(Context);
    /* Nothing to do for devices */
    return;
}

◆ Device_SaveCurrentSettings()

VOID NTAPI Device_SaveCurrentSettings ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 20 of file device.c.

{
    PPCI_COMMON_HEADER PciData;
    PIO_RESOURCE_DESCRIPTOR IoDescriptor;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
    PPCI_FUNCTION_RESOURCES Resources;
    PULONG BarArray;
    ULONG Bar, BarMask, i;
 
    /* Get variables from context */
    PciData = Context->Current;
    Resources = Context->PdoExtension->Resources;
 
    /* Loop all the PCI BARs */
    BarArray = PciData->u.type0.BaseAddresses;
    for (i = 0; i <= PCI_TYPE0_ADDRESSES; i++)
    {
        /* Get the resource descriptor and limit descriptor for this BAR */
        CmDescriptor = &Resources->Current[i];
        IoDescriptor = &Resources->Limit[i];
 
        /* Build the resource descriptor based on the limit descriptor */
        CmDescriptor->Type = IoDescriptor->Type;
        if (CmDescriptor->Type == CmResourceTypeNull) continue;
        CmDescriptor->Flags = IoDescriptor->Flags;
        CmDescriptor->ShareDisposition = IoDescriptor->ShareDisposition;
        CmDescriptor->u.Generic.Start.HighPart = 0;
        CmDescriptor->u.Generic.Length = IoDescriptor->u.Generic.Length;
 
        /* Check if we're handling PCI BARs, or the ROM BAR */
        if (i < PCI_TYPE0_ADDRESSES)
        {
            /* Read the actual BAR value */
            Bar = BarArray[i];
 
            /* Check if this is an I/O BAR */
            if (Bar & PCI_ADDRESS_IO_SPACE)
            {
                /* Use the right mask to get the I/O port base address */
                ASSERT(CmDescriptor->Type == CmResourceTypePort);
                BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
            }
            else
            {
                /* It's a RAM BAR, use the right mask to get the base address */
                ASSERT((CmDescriptor->Type == CmResourceTypeMemory) ||
                       (CmDescriptor->Type == CmResourceTypeMemoryLarge));
                BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
 
                /* Check if it's a 64-bit BAR, the last BAR has no register for a high half */
                if (((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT) &&
                    ((i + 1) < PCI_TYPE0_ADDRESSES))
                {
                    /* The next BAR value is actually the high 32-bits */
                    CmDescriptor->u.Memory.Start.HighPart = BarArray[i + 1];
                }
                else if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
                {
                    /* Legacy BAR, don't read more than 20 bits of the address */
                    BarMask = 0xFFFF0;
                }
            }
        }
        else
        {
            /* Actually a ROM BAR, so read the correct register */
            Bar = PciData->u.type0.ROMBaseAddress;
 
            /* Apply the correct mask for ROM BARs */
            BarMask = PCI_ADDRESS_ROM_ADDRESS_MASK;
 
            /* Make sure it's enabled */
            if (!(Bar & PCI_ROMADDRESS_ENABLED))
            {
                /* If it isn't, then a descriptor won't be built for it */
                CmDescriptor->Type = CmResourceTypeNull;
                continue;
            }
        }
 
        /* Now we have the right mask, read the actual address from the BAR */
        Bar &= BarMask;
        CmDescriptor->u.Memory.Start.LowPart = Bar;
 
        /* And check for invalid BAR addresses */
        if (!(CmDescriptor->u.Memory.Start.HighPart | Bar))
        {
            /* Skip these descriptors */
            CmDescriptor->Type = CmResourceTypeNull;
            DPRINT1("PCIX - Invalid BAR\n");
        }
    }
 
    /* Also save the sub-IDs that came directly from the PCI header */
    Context->PdoExtension->SubsystemVendorId = PciData->u.type0.SubVendorID;
    Context->PdoExtension->SubsystemId = PciData->u.type0.SubSystemID;
}

◆ Device_SaveLimits()

VOID NTAPI Device_SaveLimits ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 120 of file device.c.

{
    PPCI_COMMON_HEADER Current, PciData;
    PPCI_PDO_EXTENSION PdoExtension;
    PULONG BarArray;
    PIO_RESOURCE_DESCRIPTOR Limit;
    ULONG i;
 
    /* Get pointers from the context */
    PdoExtension = Context->PdoExtension;
    Current = Context->Current;
    PciData = Context->PciData;
 
    /* And get the array of bARs */
    BarArray = PciData->u.type0.BaseAddresses;
 
    /* First, check for IDE controllers that are not in native mode */
    if ((PdoExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
        (PdoExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR) &&
        (PdoExtension->ProgIf & 5) != 5)
    {
        /* They should not be using any non-legacy resources */
        BarArray[0] = 0;
        BarArray[1] = 0;
        BarArray[2] = 0;
        BarArray[3] = 0;
    }
    else if ((PdoExtension->VendorId == 0x5333) &&
             ((PdoExtension->DeviceId == 0x88F0) ||
              (PdoExtension->DeviceId == 0x8880)))
    {
        /*
         * The problem is caused by the S3 Vision 968/868 video controller which
         * is used on the Diamond Stealth 64 Video 3000 series, Number Nine 9FX
         * motion 771, and other popular video cards, all containing a memory bug.
         * The 968/868 claims to require 32 MB of memory, but it actually decodes
         * 64 MB of memory.
         */
        for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
        {
            /* Find its 32MB RAM BAR */
            if (BarArray[i] == 0xFE000000)
            {
                /* Increase it to 64MB to make sure nobody touches the buffer */
                BarArray[i] = 0xFC000000;
                DPRINT1("PCIX - Adjusted broken S3 requirement from 32MB to 64MB\n");
            }
        }
    }
 
    /* Check for Cirrus Logic GD5430/5440 cards */
    if ((PdoExtension->VendorId == 0x1013) && (PdoExtension->DeviceId == 0xA0))
    {
        /* Check for the I/O port requirement */
        if (BarArray[1] == 0xFC01)
        {
            /* Check for completely bogus BAR */
            if (Current->u.type0.BaseAddresses[1] == 1)
            {
                /* Ignore it */
                BarArray[1] = 0;
                DPRINT1("PCIX - Ignored Cirrus GD54xx broken IO requirement (400 ports)\n");
            }
            else
            {
                /* Otherwise, this BAR seems okay */
                DPRINT1("PCIX - Cirrus GD54xx 400 port IO requirement has a valid setting (%08x)\n",
                        Current->u.type0.BaseAddresses[1]);
            }
        }
        else if (BarArray[1])
        {
            /* Strange, the I/O BAR was not found as expected (or at all) */
            DPRINT1("PCIX - Warning Cirrus Adapter 101300a0 has unexpected resource requirement (%08x)\n",
                    BarArray[1]);
        }
    }
 
    /* Finally, process all the limit descriptors */
    Limit = PdoExtension->Resources->Limit;
    for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
    {
        /* And build them based on the BARs, the last one has no BAR after it for a high half */
        ULONG NextBar = ((i + 1) < PCI_TYPE0_ADDRESSES) ? BarArray[i + 1] : 0;
 
        if (!PciCreateIoDescriptorFromBarLimit(&Limit[i], BarArray[i], NextBar, FALSE))
            continue;
 
        /* A 64-bit BAR in the last slot has nowhere to put its high half, so it stays below 4GB */
        if ((i + 1) == PCI_TYPE0_ADDRESSES)
        {
            DPRINT1("PCIX - 64-bit BAR %lu has no upper register, decoding it as 32-bit\n", i);
            continue;
        }
 
        /* The high half of a 64-bit BAR is not a BAR of its own */
        i++;
        Limit[i].Type = CmResourceTypeNull;
    }
 
    /* Create the last descriptor based on the ROM address */
    PciCreateIoDescriptorFromBarLimit(&Limit[i], PciData->u.type0.ROMBaseAddress, 0, TRUE);
 
    /* A ROM the firmware left disabled is not given a window */
    if (!(Current->u.type0.ROMBaseAddress & PCI_ROMADDRESS_ENABLED))
        Limit[i].Type = CmResourceTypeNull;
}

◆ devpresent_Constructor()

NTSTATUS NTAPI devpresent_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 270 of file devhere.c.

{
    PPCI_DEVICE_PRESENT_INTERFACE PresentInterface = (PPCI_DEVICE_PRESENT_INTERFACE)Interface;
    BOOLEAN HasEx;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Version);
 
    /* Callers built before IsDevicePresentEx existed pass the shorter size */
    HasEx = (Size >= sizeof(*PresentInterface));
 
    PresentInterface->IsDevicePresent = devpresent_IsDevicePresent;
    if (HasEx)
        PresentInterface->IsDevicePresentEx = devpresent_IsDevicePresentEx;
 
    PresentInterface->InterfaceReference = devpresent_Reference;
    PresentInterface->InterfaceDereference = devpresent_Dereference;
    PresentInterface->Context = DeviceExtension;
    PresentInterface->Version = PCI_DEVICE_PRESENT_INTERFACE_VERSION;
    PresentInterface->Size = (USHORT)(HasEx ? sizeof(*PresentInterface) :
                                      FIELD_OFFSET(PCI_DEVICE_PRESENT_INTERFACE, IsDevicePresentEx));
 
    return STATUS_SUCCESS;
}

◆ devpresent_Initializer()

NTSTATUS NTAPI devpresent_Initializer ( IN PVOID Instance )

Definition at line 35 of file devhere.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI devpresent_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ lddintrf_Constructor()

NTSTATUS NTAPI lddintrf_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 45 of file lddintrf.c.

{
    UNREFERENCED_PARAMETER(DeviceExtension);
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Version);
    UNREFERENCED_PARAMETER(Size);
    UNREFERENCED_PARAMETER(Interface);
 
    /* Not provided, so the query fails and the caller goes without it */
    return STATUS_NOT_SUPPORTED;
}

◆ lddintrf_Initializer()

NTSTATUS NTAPI lddintrf_Initializer ( IN PVOID Instance )

Definition at line 35 of file lddintrf.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI lddintrf_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ locintrf_Constructor()

NTSTATUS NTAPI locintrf_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 116 of file locintrf.c.

{
    PPNP_LOCATION_INTERFACE LocationInterface = (PPNP_LOCATION_INTERFACE)Interface;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Version);
    UNREFERENCED_PARAMETER(Size);
 
    LocationInterface->Size = sizeof(*LocationInterface);
    LocationInterface->Version = PNP_LOCATION_INTERFACE_VERSION;
    LocationInterface->Context = DeviceExtension;
    LocationInterface->InterfaceReference = locintrf_Reference;
    LocationInterface->InterfaceDereference = locintrf_Dereference;
    LocationInterface->GetLocationString = locintrf_GetLocationString;
    return STATUS_SUCCESS;
}

◆ locintrf_Initializer()

NTSTATUS NTAPI locintrf_Initializer ( IN PVOID Instance )

Definition at line 35 of file locintrf.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI locintrf_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ PciAddDevice()

NTSTATUS NTAPI PciAddDevice	(	IN PDRIVER_OBJECT	DriverObject,
		IN PDEVICE_OBJECT	PhysicalDeviceObject
	)

Definition at line 707 of file fdo.c.

{
    PCM_RESOURCE_LIST Descriptor;
    PDEVICE_OBJECT AttachedTo;
    PPCI_FDO_EXTENSION FdoExtension;
    PPCI_FDO_EXTENSION ParentExtension;
    PPCI_PDO_EXTENSION PdoExtension;
    PDEVICE_OBJECT DeviceObject;
    UCHAR Buffer[sizeof(KEY_VALUE_PARTIAL_INFORMATION) + sizeof(ULONG)];
    PKEY_VALUE_PARTIAL_INFORMATION ValueInfo = (PKEY_VALUE_PARTIAL_INFORMATION)Buffer;
    NTSTATUS Status;
    HANDLE KeyHandle;
    UNICODE_STRING ValueName;
    ULONG ResultLength;
    PAGED_CODE();
    DPRINT1("PCIX - AddDevice (a new bus). PDO: %p (Driver: %wZ)\n",
            PhysicalDeviceObject, &PhysicalDeviceObject->DriverObject->DriverName);
 
    /* Zero out variables so failure path knows what to do */
    AttachedTo = NULL;
    FdoExtension = NULL;
    PdoExtension = NULL;
    DeviceObject = NULL;
 
    do
    {
        /* Check if there's already a device extension for this bus */
        ParentExtension = PciFindParentPciFdoExtension(PhysicalDeviceObject,
                                                       &PciGlobalLock);
        if (ParentExtension)
        {
            /* Make sure we find a real PDO */
            PdoExtension = PhysicalDeviceObject->DeviceExtension;
            ASSERT_PDO(PdoExtension);
 
            /* Make sure it's a PCI-to-PCI bridge */
            if ((PdoExtension->BaseClass != PCI_CLASS_BRIDGE_DEV) ||
                (PdoExtension->SubClass != PCI_SUBCLASS_BR_PCI_TO_PCI))
            {
                /* This should never happen */
                DPRINT1("PCIX - PciAddDevice for Non-Root/Non-PCI-PCI bridge,\n"
                        "      Class %02x, SubClass %02x, will not add.\n",
                        PdoExtension->BaseClass,
                        PdoExtension->SubClass);
                ASSERT((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
                       (PdoExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI));
 
                /* Enter the failure path */
                Status = STATUS_INVALID_DEVICE_REQUEST;
                break;
            }
 
            /* Subordinate bus on the bridge */
            DPRINT1("PCIX - AddDevice (new bus is child of bus 0x%x).\n",
                    ParentExtension->BaseBus);
 
            /* Make sure PCI bus numbers are configured */
            if (!PciAreBusNumbersConfigured(PdoExtension))
            {
                /* This is a critical failure */
                DPRINT1("PCIX - Bus numbers not configured for bridge (0x%x.0x%x.0x%x)\n",
                        ParentExtension->BaseBus,
                        PdoExtension->Slot.u.bits.DeviceNumber,
                        PdoExtension->Slot.u.bits.FunctionNumber);
 
                /* Enter the failure path */
                Status = STATUS_INVALID_DEVICE_REQUEST;
                break;
            }
        }
 
        /* Create the FDO for the bus */
        Status = IoCreateDevice(DriverObject,
                                sizeof(PCI_FDO_EXTENSION),
                                NULL,
                                FILE_DEVICE_BUS_EXTENDER,
                                0,
                                0,
                                &DeviceObject);
        if (!NT_SUCCESS(Status)) break;
 
        /* Initialize the extension for the FDO */
        FdoExtension = DeviceObject->DeviceExtension;
        PciInitializeFdoExtensionCommonFields(DeviceObject->DeviceExtension,
                                              DeviceObject,
                                              PhysicalDeviceObject);
 
        /* Attach to the root PDO */
        Status = STATUS_NO_SUCH_DEVICE;
        AttachedTo = IoAttachDeviceToDeviceStack(DeviceObject,
                                                 PhysicalDeviceObject);
        ASSERT(AttachedTo != NULL);
        if (!AttachedTo) break;
        FdoExtension->AttachedDeviceObject = AttachedTo;
 
        /* Check if this is a child bus, or the root */
        if (ParentExtension)
        {
            /* The child inherits root data */
            FdoExtension->BaseBus = PdoExtension->Dependent.type1.SecondaryBus;
            FdoExtension->BusRootFdoExtension = ParentExtension->BusRootFdoExtension;
            PdoExtension->BridgeFdoExtension = FdoExtension;
            FdoExtension->ParentFdoExtension = ParentExtension;
        }
        else
        {
            /* Query the boot configuration */
            Status = PciGetDeviceProperty(PhysicalDeviceObject,
                                          DevicePropertyBootConfiguration,
                                          (PVOID*)&Descriptor);
            if (!NT_SUCCESS(Status))
            {
                /* No configuration has been set */
                Descriptor = NULL;
            }
 
            /* The firmware reports the bus numbers this root decodes in its boot config */
            if (Descriptor &&
                PciGetRootBusRange(Descriptor,
                                   &FdoExtension->BaseBus,
                                   &FdoExtension->MaxSubordinateBus))
            {
                DPRINT1("PCIX - Root bus range 0x%x to 0x%x.\n",
                        FdoExtension->BaseBus,
                        FdoExtension->MaxSubordinateBus);
            }
            else
            {
                /* Default configuration isn't the normal path on Windows */
                if (PciBreakOnDefault)
                {
                    /* If a second bus is found and there's still no data, crash */
                    KeBugCheckEx(PCI_BUS_DRIVER_INTERNAL,
                                 0xDEAD0010u,
                                 (ULONG_PTR)DeviceObject,
                                 0,
                                 0);
                }
 
                /* Warn that a default configuration will be used, and set bus 0 */
                DPRINT1("PCIX - Will use default configuration.\n");
                PciBreakOnDefault = TRUE;
                FdoExtension->BaseBus = 0;
                FdoExtension->MaxSubordinateBus = 0xFF;
            }
 
            if (Descriptor)
                ExFreePoolWithTag(Descriptor, 0);
 
            /* This is the root bus */
            FdoExtension->BusRootFdoExtension = FdoExtension;
        }
 
        /* Get the HAL or ACPI Bus Handler Callbacks for Configuration Access */
        Status = PciGetConfigHandlers(FdoExtension);
        if (!NT_SUCCESS(Status)) break;
 
        /* Map this bus for extended configuration space access */
        PciInitializeEcam(FdoExtension);
 
        /* Initialize all the supported PCI arbiters */
        Status = PciInitializeArbiters(FdoExtension);
        if (!NT_SUCCESS(Status)) break;
 
        /* This is a real FDO, insert it into the list */
        FdoExtension->Fake = FALSE;
        PciInsertEntryAtTail(&PciFdoExtensionListHead,
                             FdoExtension,
                             &PciGlobalLock);
 
        /* Open the device registry key so that we can query the errata flags */
        IoOpenDeviceRegistryKey(DeviceObject,
                                PLUGPLAY_REGKEY_DEVICE,
                                KEY_ALL_ACCESS,
                                &KeyHandle),
 
        /* Open the value that contains errata flags for this bus instance */
        RtlInitUnicodeString(&ValueName, L"HackFlags");
        Status = ZwQueryValueKey(KeyHandle,
                                 &ValueName,
                                 KeyValuePartialInformation,
                                 ValueInfo,
                                 sizeof(Buffer),
                                 &ResultLength);
        ZwClose(KeyHandle);
        if (NT_SUCCESS(Status))
        {
            /* Make sure the data is of expected type and size */
            if ((ValueInfo->Type == REG_DWORD) &&
                (ValueInfo->DataLength == sizeof(ULONG)))
            {
                /* Read the flags for this bus */
                FdoExtension->BusHackFlags = *(PULONG)&ValueInfo->Data;
            }
        }
 
        /* Query ACPI for PCI HotPlug Support */
        PciGetHotPlugParameters(FdoExtension);
 
        /* The Bus FDO is now initialized */
        DeviceObject->Flags &= ~DO_DEVICE_INITIALIZING;
        return STATUS_SUCCESS;
    } while (FALSE);
 
    /* This is the failure path */
    ASSERT(!NT_SUCCESS(Status));
 
    /* Check if the FDO extension exists */
    if (FdoExtension) DPRINT1("PCIX - Should destroy secondaries\n");
 
    /* Delete device objects */
    if (AttachedTo) IoDetachDevice(AttachedTo);
    if (DeviceObject) IoDeleteDevice(DeviceObject);
    return Status;
}

◆ PciAddResizableBarRequirements()

ULONG NTAPI PciAddResizableBarRequirements	(	_In_ PPCI_PDO_EXTENSION	PdoExtension,
		_In_ ULONG	BarIndex,
		_In_ PIO_RESOURCE_DESCRIPTOR	Limit,
		_Out_writes_opt_(2) PIO_RESOURCE_DESCRIPTOR	Descriptors
	)

Writes the requirements for the sizes a resizable BAR can grow to. They go ahead of the default requirement, which the caller then lists as the alternative. The largest size is preferred, and the smallest supported size follows it when that is also bigger than the default.

Parameters

[in]	PdoExtension	The PDO extension of the function.
[in]	BarIndex	The BAR the default requirement describes.
[in]	Limit	The default requirement of the BAR.
[out]	Descriptors	Receives up to two descriptors, or NULL to only count them.

Returns: The number of descriptors written, which is 0 when the BAR cannot grow.

Definition at line 142 of file rbar.c.

{
    IO_RESOURCE_DESCRIPTOR Resized[2];
    ULONGLONG Largest, Smallest;
    ULONG SizeMask, Count;
    PAGED_CODE();
 
    /* Only a memory BAR asking for less than 4GB is offered other sizes */
    if ((BarIndex >= PCI_RBAR_MAX_ENTRIES) || (Limit->Type != CmResourceTypeMemory))
        return 0;
 
    SizeMask = PdoExtension->ResizableBarState.SizeMask[BarIndex];
    if (!SizeMask)
        return 0;
 
    /* Built even when only counting, so a size that cannot be described is never counted */
    Largest = PCI_RBAR_SIZE_TO_LENGTH(RtlFindMostSignificantBit(SizeMask));
    if ((Largest <= Limit->u.Memory.Length) ||
        !PciFillResizedBarRequirement(&Resized[0], Limit, Largest, IO_RESOURCE_PREFERRED))
    {
        return 0;
    }
    Count = 1;
 
    Smallest = PCI_RBAR_SIZE_TO_LENGTH(RtlFindLeastSignificantBit(SizeMask));
    if ((Smallest > Limit->u.Memory.Length) &&
        (Smallest < Largest) &&
        PciFillResizedBarRequirement(&Resized[1], Limit, Smallest, IO_RESOURCE_ALTERNATIVE))
    {
        Count++;
    }
 
    if (Descriptors)
        RtlCopyMemory(Descriptors, Resized, Count * sizeof(IO_RESOURCE_DESCRIPTOR));
 
    return Count;
}

Referenced by PciBuildRequirementsList().

◆ PciApplyResizableBarSizes()

VOID NTAPI PciApplyResizableBarSizes ( _In_ PPCI_PDO_EXTENSION PdoExtension )

Sets every resizable BAR to the length it was assigned. The memory decode has to be off, since the size field changes what the BAR decodes. Critical devices call this from the IPI that updates their hardware.

Parameters

[in] PdoExtension The PDO extension of the function whose resources are being set.

Definition at line 229 of file rbar.c.

{
    PCM_PARTIAL_RESOURCE_DESCRIPTOR Current;
    USHORT Command;
    ULONG BarIndex;
 
    if (!PdoExtension->ResizableBarState.CapabilityPtr || !PdoExtension->Resources)
        return;
 
    /* A function whose decodes could not be turned off keeps the sizes it has */
    PciReadDeviceConfig(PdoExtension,
                        &Command,
                        FIELD_OFFSET(PCI_COMMON_HEADER, Command),
                        sizeof(Command));
    if (Command & PCI_ENABLE_MEMORY_SPACE)
    {
        DPRINT("PCIX - Memory decode of %p is still on, not resizing BARs\n", PdoExtension);
        return;
    }
 
    for (BarIndex = 0; BarIndex < PCI_RBAR_MAX_ENTRIES; BarIndex++)
    {
        if (!PdoExtension->ResizableBarState.SizeMask[BarIndex])
            continue;
 
        Current = &PdoExtension->Resources->Current[BarIndex];
        if ((Current->Type != CmResourceTypeMemory) &&
            (Current->Type != CmResourceTypeMemoryLarge))
        {
            continue;
        }
 
        PciSelectResizableBarSize(PdoExtension,
                                  BarIndex,
                                  RtlCmDecodeMemIoResource(Current, NULL));
    }
}

Referenced by PcipUpdateHardware().

◆ PciArbiter_Dereference()

VOID NTAPI PciArbiter_Dereference ( _In_ PVOID Context )

Definition at line 191 of file arb_comn.c.

{
    PARBITER_INSTANCE Arbiter = (PARBITER_INSTANCE)Context;
 
    InterlockedDecrement((PLONG)&Arbiter->ReferenceCount);
}

Referenced by PciArbiterConstructor().

◆ PciArbiter_FindSuitableRange()

BOOLEAN NTAPI PciArbiter_FindSuitableRange	(	_In_ PARBITER_INSTANCE	Arbiter,
		_Inout_ PARBITER_ALLOCATION_STATE	State
	)

Searches for a placement, remembering on the range whether it came from a fixed alternative.

Parameters

[in]	Arbiter	The arbiter instance placing the entry.
[in,out]	State	The allocation state of the entry.

Returns: TRUE if a placement was found, FALSE otherwise.

Definition at line 97 of file arb_comn.c.

{
    PAGED_CODE();
 
    State->RangeAttributes &= (UCHAR)~PCI_RANGE_FIXED_PLACEMENT;
    if (State->CurrentAlternative &&
        (State->CurrentAlternative->Flags & ARBITER_ALTERNATIVE_FLAG_FIXED))
    {
        State->RangeAttributes |= PCI_RANGE_FIXED_PLACEMENT;
    }
 
    return ArbiterLibFindSuitableRange(Arbiter, State);
}

Referenced by ario_Initializer(), and armem_Initializer().

◆ PciArbiter_OverrideConflict()

BOOLEAN NTAPI PciArbiter_OverrideConflict	(	_In_ PARBITER_INSTANCE	Arbiter,
		_Inout_ PARBITER_ALLOCATION_STATE	State
	)

Lets a fixed requirement overlap ranges its own device was given by other fixed requirements.

Parameters

[in]	Arbiter	The arbiter instance placing the entry.
[in,out]	State	The allocation state of the entry. On success Start and End receive the requested window.

Returns: TRUE if every conflicting range is a fixed placement of the same device, FALSE otherwise.

Remarks: A resized BAR that landed on top of another BAR's firmware address is a movable placement, so the fixed BAR fails and the resized one has to back off to another alternative.

Definition at line 136 of file arb_comn.c.

{
    RTL_RANGE_LIST_ITERATOR Iterator;
    PRTL_RANGE Range;
    BOOLEAN Overridden = FALSE;
 
    PAGED_CODE();
 
    if (!State->Entry ||
        !State->CurrentAlternative ||
        !(State->CurrentAlternative->Flags & ARBITER_ALTERNATIVE_FLAG_FIXED))
    {
        return FALSE;
    }
 
    if (!NT_SUCCESS(RtlGetFirstRange(Arbiter->PossibleAllocation, &Iterator, &Range)))
        return FALSE;
 
    while (Range)
    {
        if ((Range->Start <= State->CurrentMaximum) &&
            (Range->End >= State->CurrentMinimum) &&
            !(Range->Attributes & State->RangeAvailableAttributes))
        {
            if ((Range->Owner != State->Entry->PhysicalDeviceObject) ||
                !(Range->Attributes & PCI_RANGE_FIXED_PLACEMENT))
            {
                return FALSE;
            }
 
            Overridden = TRUE;
            State->Start = State->CurrentMinimum;
            State->End = State->CurrentMaximum;
        }
 
        if (!NT_SUCCESS(RtlGetNextRange(&Iterator, &Range, TRUE)))
            break;
    }
 
    return Overridden;
}

Referenced by ario_Initializer(), and armem_Initializer().

◆ PciArbiter_PreprocessEntry()

NTSTATUS NTAPI PciArbiter_PreprocessEntry	(	_In_ PARBITER_INSTANCE	Arbiter,
		_Inout_ PARBITER_ALLOCATION_STATE	State
	)

Sets the range attributes of one arbitration entry before the engine looks for a placement for it.

Parameters

[in]	Arbiter	The arbiter instance placing the entry.
[in,out]	State	The allocation state of the entry.

Returns: STATUS_SUCCESS.

Remarks: Boot configs and legacy claims treat boot reservations as free. Positive decode ports ignore ISA alias ranges.

Definition at line 51 of file arb_comn.c.

{
    PIO_RESOURCE_DESCRIPTOR Descriptor;
 
    UNREFERENCED_PARAMETER(Arbiter);
 
    PAGED_CODE();
 
    if (!State->Entry)
        return STATUS_SUCCESS;
 
    if ((State->Entry->Flags & ARBITER_FLAG_BOOT_CONFIG) ||
        (State->Entry->RequestSource == ArbiterRequestLegacyReported) ||
        (State->Entry->RequestSource == ArbiterRequestLegacyAssigned))
    {
        State->RangeAvailableAttributes |= ARBITER_RANGE_BOOT_ALLOCATED;
    }
 
    /* CurrentAlternative is not set yet, use the first alternative */
    Descriptor = State->Alternatives ? State->Alternatives->Descriptor : NULL;
    if (Descriptor &&
        (Descriptor->Type == CmResourceTypePort) &&
        (Descriptor->Flags & CM_RESOURCE_PORT_POSITIVE_DECODE))
        State->RangeAvailableAttributes |= ARBITER_RANGE_PORT_ALIAS;
 
    return STATUS_SUCCESS;
}

Referenced by arbusno_Initializer(), ario_Initializer(), and armem_Initializer().

◆ PciArbiter_Reference()

VOID NTAPI PciArbiter_Reference ( _In_ PVOID Context )

Definition at line 182 of file arb_comn.c.

{
    PARBITER_INSTANCE Arbiter = (PARBITER_INSTANCE)Context;
 
    InterlockedIncrement((PLONG)&Arbiter->ReferenceCount);
}

Referenced by PciArbiterConstructor().

◆ PciArbiterConstructor()

NTSTATUS NTAPI PciArbiterConstructor	(	_In_ PPCI_FDO_EXTENSION	FdoExtension,
		_In_ PCI_SIGNATURE	ArbiterType,
		_Out_ PARBITER_INTERFACE	Interface
	)

Definition at line 200 of file arb_comn.c.

{
    PPCI_ARBITER_INSTANCE Arbiter;
    PAGED_CODE();
 
    if (!FdoExtension->ArbitersInitialized) return STATUS_NOT_SUPPORTED;
 
    /* Find the instance this bus built for the requested resource type */
    Arbiter = (PVOID)PciFindNextSecondaryExtension(FdoExtension->
                                                   SecondaryExtension.Next,
                                                   ArbiterType);
    if (!Arbiter)
    {
        DPRINT1("PCIX - FDO ext 0x%p has no %s arbiter to hand out.\n",
                FdoExtension,
                PciArbiterNames[ArbiterType - PciArb_Io]);
        return STATUS_NOT_SUPPORTED;
    }
 
    Interface->Size = sizeof(ARBITER_INTERFACE);
    Interface->Version = ARBITER_INTERFACE_VERSION;
    Interface->Context = &Arbiter->CommonInstance;
    Interface->InterfaceReference = PciArbiter_Reference;
    Interface->InterfaceDereference = PciArbiter_Dereference;
    Interface->ArbiterHandler = ArbiterLibHandler;
    Interface->Flags = 0;
    return STATUS_SUCCESS;
}

Referenced by arbusno_Constructor(), ario_Constructor(), and armem_Constructor().

◆ PciAreBusNumbersConfigured()

BOOLEAN NTAPI PciAreBusNumbersConfigured ( IN PPCI_PDO_EXTENSION PdoExtension )

Definition at line 20 of file busno.c.

{
    UCHAR PrimaryBus, BaseBus, SecondaryBus, SubordinateBus;
 
    PAGED_CODE();
 
    /* Get all relevant bus number details */
    PrimaryBus = PdoExtension->Dependent.type1.PrimaryBus;
    BaseBus = PdoExtension->ParentFdoExtension->BaseBus;
    SecondaryBus = PdoExtension->Dependent.type1.SecondaryBus;
    SubordinateBus = PdoExtension->Dependent.type1.SubordinateBus;
 
    /* The primary bus should be the base bus of the parent */
    if ((PrimaryBus != BaseBus) || (SecondaryBus <= PrimaryBus)) return FALSE;
 
    /* The subordinate should be a higher bus number than the secondary */
    return SubordinateBus >= SecondaryBus;
}

Referenced by PciAddDevice(), and PciProcessBus().

◆ PciBeginStateTransition()

NTSTATUS NTAPI PciBeginStateTransition	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PCI_STATE	NewState
	)

Definition at line 97 of file state.c.

{
    PCI_STATE CurrentState;
    NTSTATUS Status;
    DPRINT1("PCIX - Request to begin transition of Extension %p to %s ->",
            DeviceExtension,
            PciTransitionText[NewState]);
 
    /* Assert the device isn't already in a pending transition */
    ASSERT(DeviceExtension->TentativeNextState == DeviceExtension->DeviceState);
 
    /* Assert this is a valid state */
    CurrentState = DeviceExtension->DeviceState;
    ASSERT(CurrentState < PciMaxObjectState);
    ASSERT(NewState < PciMaxObjectState);
 
    /* Lookup if this state transition is valid */
    Status = PnpStateTransitionArray[CurrentState + 6 * NewState];
    if (Status == STATUS_FAIL_CHECK)
    {
        /* Invalid transition (logical fault) */
        DPRINT1("ERROR\nPCIX - Error trying to enter state \"%s\" "
                "from state \"%s\"\n",
                PciTransitionText[NewState],
                PciTransitionText[CurrentState]);
        DbgBreakPoint();
    }
    else if (Status == STATUS_INVALID_DEVICE_REQUEST)
    {
        /* Invalid transition (illegal request) */
        DPRINT1("ERROR\nPCIX - Illegal request to try to enter state \"%s\" "
                "from state \"%s\", rejecting",
                PciTransitionText[NewState],
                PciTransitionText[CurrentState]);
    }
 
    /* New state must be different from current, unless request is at fault */
    ASSERT((NewState != DeviceExtension->DeviceState) || (!NT_SUCCESS(Status)));
 
    /* Enter the new state if successful, and return state status */
    if (NT_SUCCESS(Status)) DeviceExtension->TentativeNextState = NewState;
    DbgPrint("%x\n", Status);
    return Status;
}

Referenced by PciFdoIrpQueryRemoveDevice(), PciFdoIrpQueryStopDevice(), PciFdoIrpRemoveDevice(), PciFdoIrpStartDevice(), PciFdoIrpSurpriseRemoval(), PciPdoIrpQueryRemoveDevice(), PciPdoIrpQueryStopDevice(), PciPdoIrpRemoveDevice(), PciPdoIrpStartDevice(), PciPdoIrpSurpriseRemoval(), and PciQueryDeviceRelations().

◆ PciBuildDefaultExclusionLists()

NTSTATUS NTAPI PciBuildDefaultExclusionLists ( VOID )

Definition at line 276 of file utils.c.

{
    ULONG Start;
    NTSTATUS Status;
    ASSERT(PciIsaBitExclusionList.Count == 0);
    ASSERT(PciVgaAndIsaBitExclusionList.Count == 0);
 
    /* Initialize the range lists */
    RtlInitializeRangeList(&PciIsaBitExclusionList);
    RtlInitializeRangeList(&PciVgaAndIsaBitExclusionList);
 
    /* Loop x86 I/O ranges */
    for (Start = 0x100; Start <= 0xFEFF; Start += 0x400)
    {
        /* Add the ISA I/O ranges */
        Status = RtlAddRange(&PciIsaBitExclusionList,
                             Start,
                             Start + 0x2FF,
                             0,
                             RTL_RANGE_LIST_ADD_IF_CONFLICT,
                             NULL,
                             NULL);
        if (!NT_SUCCESS(Status)) break;
 
        /* Add the ISA I/O ranges */
        Status = RtlAddRange(&PciVgaAndIsaBitExclusionList,
                             Start,
                             Start + 0x2AF,
                             0,
                             RTL_RANGE_LIST_ADD_IF_CONFLICT,
                             NULL,
                             NULL);
        if (!NT_SUCCESS(Status)) break;
 
        /* Add the VGA I/O range for Monochrome Video */
        Status = RtlAddRange(&PciVgaAndIsaBitExclusionList,
                             Start + 0x2BC,
                             Start + 0x2BF,
                             0,
                             RTL_RANGE_LIST_ADD_IF_CONFLICT,
                             NULL,
                             NULL);
        if (!NT_SUCCESS(Status)) break;
 
        /* Add the VGA I/O range for certain CGA adapters */
        Status = RtlAddRange(&PciVgaAndIsaBitExclusionList,
                             Start + 0x2E0,
                             Start + 0x2FF,
                             0,
                             RTL_RANGE_LIST_ADD_IF_CONFLICT,
                             NULL,
                             NULL);
        if (!NT_SUCCESS(Status)) break;
 
        /* Success, ranges added done */
    };
 
    RtlFreeRangeList(&PciIsaBitExclusionList);
    RtlFreeRangeList(&PciVgaAndIsaBitExclusionList);
    return Status;
}

Referenced by DriverEntry().

◆ PciBuildRequirementsList()

NTSTATUS NTAPI PciBuildRequirementsList	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN PPCI_COMMON_HEADER	PciData,
		OUT PIO_RESOURCE_REQUIREMENTS_LIST *	Buffer
	)

Definition at line 756 of file enum.c.

{
    PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList;
    PIO_RESOURCE_DESCRIPTOR Descriptor, Limit, First, Next;
    PCI_CONFIGURATOR_CONTEXT Context;
    ULONG Count, i;
    BOOLEAN HaveInterrupt;
 
    PAGED_CODE();
 
    /* Count the BAR limits that resource discovery found for this function */
    Count = 0;
    if (PdoExtension->Resources)
    {
        for (i = 0; i < (PCI_TYPE0_ADDRESSES + 1); i++)
        {
            if (!PciIsRequirementDescriptor(&PdoExtension->Resources->Limit[i]))
                continue;
 
            /* A resizable BAR also asks for the larger sizes it can decode */
            Count++;
            Count += PciAddResizableBarRequirements(PdoExtension,
                                                    i,
                                                    &PdoExtension->Resources->Limit[i],
                                                    NULL);
 
            /* And a BAR that already decodes a range also asks to keep it */
            Count += PciAddCurrentPlacementRequirement(PdoExtension, PciData->Command, i, NULL);
        }
    }
 
    /* A device with an interrupt pin also needs a line routed to it */
    HaveInterrupt = (PdoExtension->InterruptPin) &&
                    !(PdoExtension->HackFlags & PCI_HACK_NO_ENUM_AT_ALL);
    if (HaveInterrupt)
        Count++;
 
    /* And a bridge with legacy decodes enabled needs those ranges locked down */
    Count += PdoExtension->AdditionalResourceCount;
 
    /* Check if the function turned out to need nothing after all */
    if (!Count)
    {
        /* There aren't, so use the zero descriptor */
        RequirementsList = PciZeroIoResourceRequirements;
 
        /* Does it actually exist yet? */
        if (!PciZeroIoResourceRequirements)
        {
            /* Allocate it, and use it for future use */
            RequirementsList = PciAllocateIoRequirementsList(0, 0, 0);
            PciZeroIoResourceRequirements = RequirementsList;
            if (!PciZeroIoResourceRequirements) return STATUS_INSUFFICIENT_RESOURCES;
        }
 
        *Buffer = RequirementsList;
        DPRINT1("PCIX - build resource reqs - early out, 0 resources\n");
        return STATUS_SUCCESS;
    }
 
    RequirementsList = PciAllocateIoRequirementsList(Count,
                                                     PdoExtension->ParentFdoExtension->BaseBus,
                                                     PdoExtension->Slot.u.AsULONG);
    if (!RequirementsList)
        return STATUS_INSUFFICIENT_RESOURCES;
 
    Descriptor = RequirementsList->List[0].Descriptors;
 
    /* Emit the requirements of each BAR that decoded something during discovery */
    if (PdoExtension->Resources)
    {
        Limit = PdoExtension->Resources->Limit;
        for (i = 0; i < (PCI_TYPE0_ADDRESSES + 1); i++)
        {
            /* Skip unimplemented BARs and bridge windows, neither asks for a range */
            if (!PciIsRequirementDescriptor(&Limit[i]))
                continue;
 
            /* Larger resizable sizes, then the current placement, then the default size */
            First = Descriptor;
            Descriptor += PciAddResizableBarRequirements(PdoExtension, i, &Limit[i], Descriptor);
            Descriptor += PciAddCurrentPlacementRequirement(PdoExtension,
                                                            PciData->Command,
                                                            i,
                                                            Descriptor);
 
            /* A BAR decodes for one function only, so it cannot be shared */
            *Descriptor = Limit[i];
            Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
            Descriptor++;
 
            /* The first choice for the BAR is preferred and every later one is its alternative */
            First->Option |= IO_RESOURCE_PREFERRED;
            for (Next = First + 1; Next < Descriptor; Next++)
                Next->Option |= IO_RESOURCE_ALTERNATIVE;
        }
    }
 
    if (HaveInterrupt)
    {
        Descriptor->Type = CmResourceTypeInterrupt;
        Descriptor->ShareDisposition = CmResourceShareShared;
        Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
        Descriptor->u.Interrupt.MinimumVector = 0;
        Descriptor->u.Interrupt.MaximumVector = MAXULONG;
        Descriptor++;
    }
 
    /* And finally any extra ranges this kind of function decodes on the side */
    if (PdoExtension->AdditionalResourceCount)
    {
        RtlZeroMemory(&Context, sizeof(Context));
        Context.PdoExtension = PdoExtension;
        Context.Current = PciData;
        PciConfigurators[PdoExtension->HeaderType].
            GetAdditionalResourceDescriptors(&Context, PciData, Descriptor);
    }
 
    *Buffer = RequirementsList;
    return STATUS_SUCCESS;
}

Referenced by PciAssignAndProgramLegacy(), and PciQueryRequirements().

◆ PciBusInterface_GetBusData()

ULONG NTAPI PciBusInterface_GetBusData	(	_In_ PVOID	Context,
		_In_ ULONG	WhichSpace,
		_Out_writes_bytes_(Length) PVOID	Buffer,
		_In_ ULONG	Offset,
		_In_ ULONG	Length
	)

◆ PciBusInterface_SetBusData()

ULONG NTAPI PciBusInterface_SetBusData	(	_In_ PVOID	Context,
		_In_ ULONG	WhichSpace,
		_In_reads_bytes_(Length) PVOID	Buffer,
		_In_ ULONG	Offset,
		_In_ ULONG	Length
	)

◆ PciCacheLegacyDeviceRouting()

NTSTATUS NTAPI PciCacheLegacyDeviceRouting	(	IN PDEVICE_OBJECT	DeviceObject,
		IN ULONG	BusNumber,
		IN ULONG	SlotNumber,
		IN UCHAR	InterruptLine,
		IN UCHAR	InterruptPin,
		IN UCHAR	BaseClass,
		IN UCHAR	SubClass,
		IN PDEVICE_OBJECT	PhysicalDeviceObject,
		IN PPCI_PDO_EXTENSION	PdoExtension,
		OUT PDEVICE_OBJECT *	pFoundDeviceObject
	)

Definition at line 266 of file routintf.c.

{
    PPCI_LEGACY_DEVICE *Link;
    PPCI_LEGACY_DEVICE LegacyDevice;
    PDEVICE_OBJECT FoundDeviceObject;
    PAGED_CODE();
 
    /* Scan current registered devices */
    LegacyDevice = PciLegacyDeviceHead;
    Link = &PciLegacyDeviceHead;
    while (LegacyDevice)
    {
        /* Find a match */
        if ((BusNumber == LegacyDevice->BusNumber) &&
            (SlotNumber == LegacyDevice->SlotNumber))
        {
            /* We already know about this routing */
            break;
        }
 
        /* We know about device already, but for a different location */
        if (LegacyDevice->DeviceObject == DeviceObject)
        {
            /* Free the existing structure, move to the next one */
            *Link = LegacyDevice->Next;
            ExFreePoolWithTag(LegacyDevice, 0);
            LegacyDevice = *Link;
        }
        else
        {
            /* Keep going */
            Link = &LegacyDevice->Next;
            LegacyDevice = LegacyDevice->Next;
        }
    }
 
    /* Did we find a match? */
    if (!LegacyDevice)
    {
        /* Allocate a new cache structure */
        LegacyDevice = ExAllocatePoolWithTag(PagedPool,
                                             sizeof(PCI_LEGACY_DEVICE),
                                             TAG_PCI_ROUTING);
        if (!LegacyDevice) return STATUS_INSUFFICIENT_RESOURCES;
 
        /* Save all the data in it */
        RtlZeroMemory(LegacyDevice, sizeof(PCI_LEGACY_DEVICE));
        LegacyDevice->BusNumber = BusNumber;
        LegacyDevice->SlotNumber = SlotNumber;
        LegacyDevice->InterruptLine = InterruptLine;
        LegacyDevice->InterruptPin = InterruptPin;
        LegacyDevice->BaseClass = BaseClass;
        LegacyDevice->SubClass = SubClass;
        LegacyDevice->PhysicalDeviceObject = PhysicalDeviceObject;
        LegacyDevice->DeviceObject = DeviceObject;
        LegacyDevice->PdoExtension = PdoExtension;
 
        /* Link it in the list */
        LegacyDevice->Next = PciLegacyDeviceHead;
        PciLegacyDeviceHead = LegacyDevice;
    }
 
    /* Check if we found, or created, a matching caching structure */
    FoundDeviceObject = LegacyDevice->DeviceObject;
    if (FoundDeviceObject == DeviceObject)
    {
        /* Return the device object and success */
        if (pFoundDeviceObject) *pFoundDeviceObject = DeviceObject;
        return STATUS_SUCCESS;
    }
 
    /* Otherwise, this is a new device object for this location */
    LegacyDevice->DeviceObject = DeviceObject;
    if (pFoundDeviceObject) *pFoundDeviceObject = FoundDeviceObject;
    return STATUS_SUCCESS;
}

Referenced by PciAssignSlotResources().

◆ PciCallDownIrpStack()

NTSTATUS NTAPI PciCallDownIrpStack	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PIRP	Irp
	)

Definition at line 39 of file dispatch.c.

{
    NTSTATUS Status;
    KEVENT Event;
    PAGED_CODE();
    DPRINT("PCIX - PciCallDownIrpStack ...\n");
    ASSERT_FDO(DeviceExtension);
 
    /* Initialize the wait event */
    KeInitializeEvent(&Event, SynchronizationEvent, 0);
 
    /* Setup a completion routine */
    IoCopyCurrentIrpStackLocationToNext(Irp);
    IoSetCompletionRoutine(Irp, PciSetEventCompletion, &Event, TRUE, TRUE, TRUE);
 
    /* Call the attached device */
    Status = IoCallDriver(DeviceExtension->AttachedDeviceObject, Irp);
    if (Status == STATUS_PENDING)
    {
        /* Wait for it to complete the request, and get its status */
        KeWaitForSingleObject(&Event, Executive, KernelMode, FALSE, NULL);
        Status = Irp->IoStatus.Status;
    }
 
    /* Return that status back to the caller */
    return Status;
}

Referenced by PciDispatchIrp(), and PciFdoIrpQueryInterface().

◆ PciCancelStateTransition()

NTSTATUS NTAPI PciCancelStateTransition	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PCI_STATE	NewState
	)

Definition at line 145 of file state.c.

{
    NTSTATUS Status;
    DPRINT1("PCIX - Request to cancel transition of Extension %p to %s ->",
            DeviceExtension,
            PciTransitionText[StateNotEntered]);
 
    /* The next state can't be the state the device is already in */
    if (DeviceExtension->TentativeNextState == DeviceExtension->DeviceState)
    {
        /* It's too late since the state was already committed */
        ASSERT(StateNotEntered < PciMaxObjectState);
        ASSERT(PnpStateCancelArray[StateNotEntered] != STATUS_FAIL_CHECK);
 
        /* Return failure */
        Status = STATUS_INVALID_DEVICE_STATE;
        DbgPrint("%x\n", Status);
    }
    else
    {
        /* The device hasn't yet entered the state, so it's still possible to cancel */
        ASSERT(DeviceExtension->TentativeNextState == StateNotEntered);
        DeviceExtension->TentativeNextState = DeviceExtension->DeviceState;
 
        /* Return success */
        Status = STATUS_SUCCESS;
        DbgPrint("%x\n", Status);
    }
 
    /* Return the cancel state */
    return Status;
}

Referenced by PciFdoIrpCancelRemoveDevice(), PciFdoIrpCancelStopDevice(), PciFdoIrpStartDevice(), PciPdoIrpCancelRemoveDevice(), PciPdoIrpCancelStopDevice(), PciPdoIrpStartDevice(), and PciQueryDeviceRelations().

◆ PciCanDisableDecodes()

BOOLEAN NTAPI PciCanDisableDecodes	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		IN PPCI_COMMON_HEADER	Config,
		IN ULONGLONG	HackFlags,
		IN BOOLEAN	ForPowerDown
	)

Definition at line 1027 of file utils.c.

{
    UCHAR BaseClass, SubClass;
    BOOLEAN IsVga, KeepPower = FALSE;
 
    /* Is there a device extension or should the PCI header be used? */
    if (DeviceExtension)
    {
        /* Never disable decodes for a debug PCI Device */
        if (DeviceExtension->OnDebugPath) return FALSE;
 
        /* Hack flags will be obtained from the extension, not the caller */
        ASSERT(HackFlags == 0);
 
        /* Get hacks and classification from the device extension */
        HackFlags = DeviceExtension->HackFlags;
        SubClass = DeviceExtension->SubClass;
        BaseClass = DeviceExtension->BaseClass;
        KeepPower = DeviceExtension->DisablePowerDown;
    }
    else
    {
        /* There must be a PCI header, go read the classification information */
        ASSERT(Config != NULL);
        BaseClass = Config->BaseClass;
        SubClass = Config->SubClass;
    }
 
    /* Check for hack flags that prevent disabling the decodes */
    if (HackFlags & (PCI_HACK_PRESERVE_COMMAND |
                     PCI_HACK_NEVER_DISCONNECT |
                     PCI_HACK_DONT_DISABLE |
                     PCI_HACK_CB_SHARE_CMD_BITS))
    {
        /* Don't do it */
        return FALSE;
    }
 
    if (ForPowerDown)
    {
        /* IDE controllers, legacy bridges and flagged functions may stop but not power down */
        if (KeepPower || (HackFlags & PCI_HACK_NEVER_POWER_DOWN))
            return FALSE;
    }
    else if (HackFlags & PCI_HACK_KEEP_DECODES_ON_STOP)
    {
        /* Flagged functions may power down, but keep decoding while stopped or removed */
        return FALSE;
    }
 
    /* VGA adapters keep decoding unless they are being powered down */
    if (((BaseClass == PCI_CLASS_DISPLAY_CTLR) && (SubClass == PCI_SUBCLASS_VID_VGA_CTLR)) ||
        ((BaseClass == PCI_CLASS_PRE_20) && (SubClass == PCI_SUBCLASS_PRE_20_VGA)))
    {
        return ForPowerDown;
    }
 
    if (BaseClass == PCI_CLASS_BRIDGE_DEV)
    {
        /* Check for legacy bridges */
        if ((SubClass == PCI_SUBCLASS_BR_ISA) ||
            (SubClass == PCI_SUBCLASS_BR_EISA) ||
            (SubClass == PCI_SUBCLASS_BR_MCA) ||
            (SubClass == PCI_SUBCLASS_BR_HOST) ||
            (SubClass == PCI_SUBCLASS_BR_OTHER))
        {
            /* Never disable these */
            return FALSE;
        }
        else if ((SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) ||
                 (SubClass == PCI_SUBCLASS_BR_CARDBUS))
        {
            /* This is a supported bridge, but does it have a VGA card? */
            if (!DeviceExtension)
            {
                /* Read the bridge control flag from the PCI header */
                IsVga = Config->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA;
            }
            else
            {
                /* Read the cached flag in the device extension */
                IsVga = DeviceExtension->Dependent.type1.VgaBitSet;
            }
 
            /* A bridge forwarding VGA follows the same rule as the adapter behind it */
            if (IsVga)
                return ForPowerDown;
        }
    }
 
    /* Nothing else has to keep decoding */
    return TRUE;
}

Referenced by PciDecodeEnable(), PciPdoCanPowerDown(), PciPdoCanTurnOff(), PciPdoTurnOff(), and PciSetPowerManagedDevicePowerState().

◆ pcicbintrf_Constructor()

NTSTATUS NTAPI pcicbintrf_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 200 of file cardbus.c.

{
    UNREFERENCED_PARAMETER(DeviceExtension);
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Version);
    UNREFERENCED_PARAMETER(Size);
    UNREFERENCED_PARAMETER(Interface);
 
    /* Not provided, so the query fails and the socket driver goes without it */
    return STATUS_NOT_SUPPORTED;
}

◆ pcicbintrf_Initializer()

NTSTATUS NTAPI pcicbintrf_Initializer ( IN PVOID Instance )

Definition at line 190 of file cardbus.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI pcicbintrf_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ PciClassifyDeviceType()

PCI_DEVICE_TYPES NTAPI PciClassifyDeviceType ( IN PPCI_PDO_EXTENSION PdoExtension )

Definition at line 1126 of file utils.c.

{
    ASSERT(PdoExtension->ExtensionType == PciPdoExtensionType);
 
    /* Differentiate between devices and bridges */
    if (PdoExtension->BaseClass != PCI_CLASS_BRIDGE_DEV) return PciTypeDevice;
 
    /* The PCI Bus driver handles only CardBus and PCI bridges (plus host) */
    if (PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST) return PciTypeHostBridge;
    if (PdoExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) return PciTypePciBridge;
    if (PdoExtension->SubClass == PCI_SUBCLASS_BR_CARDBUS) return PciTypeCardbusBridge;
 
    /* Any other kind of bridge is treated like a device */
    return PciTypeDevice;
}

Referenced by PciProcessBus().

◆ PciCommitStateTransition()

VOID NTAPI PciCommitStateTransition	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PCI_STATE	NewState
	)

Definition at line 181 of file state.c.

{
    DPRINT1("PCIX - Commit transition of Extension %p to %s\n",
            DeviceExtension, PciTransitionText[NewState]);
 
    /* Make sure this is a valid commit */
    ASSERT(NewState != PciSynchronizedOperation);
    ASSERT(DeviceExtension->TentativeNextState == NewState);
 
    /* Enter the new state */
    DeviceExtension->DeviceState = NewState;
}

Referenced by PciFdoIrpRemoveDevice(), PciFdoIrpStartDevice(), PciFdoIrpStopDevice(), PciFdoIrpSurpriseRemoval(), PciPdoIrpRemoveDevice(), PciPdoIrpStartDevice(), PciPdoIrpStopDevice(), and PciPdoIrpSurpriseRemoval().

◆ PciComputeNewCurrentSettings()

BOOLEAN NTAPI PciComputeNewCurrentSettings	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN PCM_RESOURCE_LIST	ResourceList
	)

Definition at line 55 of file enum.c.

{
    PCM_PARTIAL_RESOURCE_DESCRIPTOR Partial, InterruptResource;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR CurrentDescriptor;
    CM_PARTIAL_RESOURCE_DESCRIPTOR ResourceArray[7];
    ULONG BarIndex;
    PCM_FULL_RESOURCE_DESCRIPTOR FullList;
    BOOLEAN RangeChange;
    ULONG DrainPartial;
    ULONG i, j;
    PPCI_FUNCTION_RESOURCES PciResources;
    PAGED_CODE();
 
    /* Make sure we have either no resources, or at least one */
    ASSERT((ResourceList == NULL) || (ResourceList->Count == 1));
 
    /* Initialize no partial, interrupt descriptor, or range change */
    Partial = NULL;
    InterruptResource = NULL;
    RangeChange = FALSE;
    BarIndex = 0;
 
    /* The limits say which BARs this function implements, so the walk below
     * can tell which BAR each assigned descriptor belongs to */
    PciResources = PdoExtension->Resources;
 
    /* Check if there's not actually any resources */
    if (!(ResourceList) || !(ResourceList->Count))
    {
        /* Then just return the hardware update state */
        return PdoExtension->UpdateHardware;
    }
 
    /* Print the new specified resource list */
    PciDebugPrintCmResList(ResourceList);
 
    /* Zero all fields, an unassigned entry still gets copied into the current settings */
    RtlZeroMemory(ResourceArray, sizeof(ResourceArray));
 
    /* Loop the full resource descriptor */
    FullList = ResourceList->List;
    for (i = 0; i < ResourceList->Count; i++)
    {
        /* Initialize loop variables */
        DrainPartial = 0;
 
        /* Loop the partial descriptors */
        Partial = FullList->PartialResourceList.PartialDescriptors;
        for (j = 0; j < FullList->PartialResourceList.Count; j++)
        {
            /* Check if we were supposed to drain a partial due to device data */
            if (DrainPartial)
            {
                DrainPartial--;
                Partial = CmiGetNextPartialDescriptor(Partial);
                continue;
            }
 
            /* Check what kind of descriptor this was */
            switch (Partial->Type)
            {
                /* Base BAR resources */
                case CmResourceTypePort:
                case CmResourceTypeMemory:
                case CmResourceTypeMemoryLarge:
                {
                    /*
                     * Skip legacy/shared resources (e.g., VGA ports 0x3B0-0x3DF, memory 0xA0000).
                     * should not be placed in the ResourceArray.
                     */
                    if (Partial->ShareDisposition != CmResourceShareDeviceExclusive && Partial->ShareDisposition != CmResourceShareDriverExclusive)
                    {
                        break;
                    }
 
                    /*
                     * The assigned descriptors come back in the order the
                     * requirements list asked for them, so walking the limits
                     * in that same order says which BAR this one satisfies.
                     */
                    if (PciResources)
                    {
                        while ((BarIndex < RTL_NUMBER_OF(ResourceArray)) &&
                               !PciIsRequirementDescriptor(&PciResources->Limit[BarIndex]))
                        {
                            BarIndex++;
                        }
 
                        if (BarIndex < RTL_NUMBER_OF(ResourceArray))
                            ResourceArray[BarIndex++] = *Partial;
                    }
                    break;
                }
                /* Interrupt resource */
                case CmResourceTypeInterrupt:
 
                    /* Make sure it's the only PCI interrupt */
                    ASSERT(InterruptResource == NULL);
                    InterruptResource = Partial;
 
                    /* A message grant packs its message count into the level and
                     * has no line to report, it gets programmed at start instead */
                    if (Partial->Flags & CM_RESOURCE_INTERRUPT_MESSAGE)
                        break;
 
                    /* Make sure it's a compatible line-based interrupt */
                    ASSERT(Partial->u.Interrupt.Level == Partial->u.Interrupt.Vector);
 
                    /* Only 255 interrupts on x86/x64 hardware */
                    if (Partial->u.Interrupt.Level < 256)
                    {
                        /* Use the passed interrupt line */
                        PdoExtension->AdjustedInterruptLine = Partial->u.Interrupt.Level;
                    }
                    else
                    {
                        /* Invalid vector, so ignore it */
                        PdoExtension->AdjustedInterruptLine = 0;
                    }
 
                    break;
 
                /* Check for specific device data */
                case CmResourceTypeDevicePrivate:
 
                    /* Check what kind of data this was */
                    switch (Partial->u.DevicePrivate.Data[0])
                    {
                        /* Not used in the driver yet */
                        case 1:
                        case 2:
                            DPRINT1("PCIX - ignoring device-private data type %u\n",
                                    Partial->u.DevicePrivate.Data[0]);
                            break;
 
                        /* A drain request */
                        case 3:
                            DrainPartial = Partial->u.DevicePrivate.Data[1];
                            break;
                    }
                    break;
            }
 
            /* Move to the next descriptor */
            Partial = CmiGetNextPartialDescriptor(Partial);
        }
 
        /* We should be starting a new list now */
        FullList = (PVOID)Partial;
    }
 
    /* A function with no discovered resources has nothing to update */
    if (!PciResources) return FALSE;
 
    /* Loop all the PCI function resources */
    for (i = 0; i < RTL_NUMBER_OF(ResourceArray); i++)
    {
        /* A bridge window is never asked for, so it keeps the range the firmware gave it */
        if (!PciIsRequirementDescriptor(&PciResources->Limit[i]))
            continue;
 
        /* Get the current function resource descriptor, and the new one */
        CurrentDescriptor = &PciResources->Current[i];
        Partial = &ResourceArray[i];
 
        /* Check if this new descriptor is different than the old one */
        if ((Partial->Type != CurrentDescriptor->Type) ||
            ((Partial->Type != CmResourceTypeNull) &&
             ((Partial->u.Generic.Start.QuadPart !=
               CurrentDescriptor->u.Generic.Start.QuadPart) ||
              (RtlCmDecodeMemIoResource(Partial, NULL) !=
               RtlCmDecodeMemIoResource(CurrentDescriptor, NULL)))))
        {
            /* Record a change */
            RangeChange = TRUE;
 
            /* Was there a range before? */
            if (CurrentDescriptor->Type != CmResourceTypeNull)
            {
                /* Print it */
                DbgPrint("      Old range-\n");
                PciDebugPrintPartialResource(CurrentDescriptor);
            }
            else
            {
                /* There was no range */
                DbgPrint("      Previously unset range\n");
            }
 
            /* Print new one */
            DbgPrint("      changed to\n");
            PciDebugPrintPartialResource(Partial);
 
            /* Update to new range */
            CurrentDescriptor->Type = Partial->Type;
            CurrentDescriptor->Flags = Partial->Flags;
            CurrentDescriptor->u.Generic.Start = Partial->u.Generic.Start;
            CurrentDescriptor->u.Generic.Length = Partial->u.Generic.Length;
        }
    }
 
    /* Either the hardware was updated, or a resource range changed */
    return ((RangeChange) || (PdoExtension->UpdateHardware));
}

Referenced by PciAssignAndProgramLegacy(), and PciPdoIrpStartDevice().

◆ PciCreateIoDescriptorFromBarLimit()

BOOLEAN NTAPI PciCreateIoDescriptorFromBarLimit	(	_Out_ PIO_RESOURCE_DESCRIPTOR	ResourceDescriptor,
		_In_ ULONG	Bar,
		_In_ ULONG	NextBar,
		_In_ BOOLEAN	Rom
	)

Builds the requirement of a BAR from the value it reads back after all ones were written to it.

Parameters

[out]	ResourceDescriptor	Receives the requirement, or a null descriptor when the BAR is not implemented.
[in]	Bar	The probed BAR.
[in]	NextBar	The probed BAR after it, which holds the high half of a 64-bit BAR. 0 when there is none.
[in]	Rom	TRUE when Bar is an expansion ROM BAR.

Returns: TRUE when the BAR is 64-bit, so the BAR after it is not a BAR of its own.

Definition at line 1252 of file utils.c.

{
    ULONGLONG AddressBits, Length, Alignment;
    ULONGLONG MinimumAddress, MaximumAddress;
    UCHAR Type;
    BOOLEAN Is64BitBar = FALSE;
 
    /* Check if the BAR is nor I/O nor memory */
    if (!(Bar & ~PCI_ADDRESS_IO_SPACE))
    {
        /* Fail this descriptor */
        ResourceDescriptor->Type = CmResourceTypeNull;
        return FALSE;
    }
 
    /* Set default flag */
    ResourceDescriptor->Flags = 0;
 
    /* Check for ROM AddressBits */
    if (Rom)
    {
        /* Clean up the BAR to get just the address */
        Bar &= PCI_ADDRESS_ROM_ADDRESS_MASK;
        if (!Bar)
        {
            /* Invalid ar, fail this descriptor */
            ResourceDescriptor->Type = CmResourceTypeNull;
            return FALSE;
        }
 
        /* ROM Addresses are always read only */
        ResourceDescriptor->Flags = CM_RESOURCE_MEMORY_READ_ONLY;
    }
 
    /* Check what kind of BAR this is */
    if (Bar & PCI_ADDRESS_IO_SPACE)
    {
        /* Set this as an I/O Port descriptor */
        Type = CmResourceTypePort;
        ResourceDescriptor->Flags = CM_RESOURCE_PORT_IO;
        AddressBits = Bar & PCI_ADDRESS_IO_ADDRESS_MASK;
    }
    else
    {
        /* Set this as a memory descriptor */
        Type = CmResourceTypeMemory;
        AddressBits = Bar & PCI_ADDRESS_MEMORY_ADDRESS_MASK;
 
        /* A 64-bit BAR takes the high half of its address from the next BAR */
        if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
        {
            AddressBits |= (ULONGLONG)NextBar << 32;
            Is64BitBar = TRUE;
        }
 
        /* Check if the BAR is listed as prefetchable memory */
        if (Bar & PCI_ADDRESS_MEMORY_PREFETCHABLE)
        {
            /* Mark the descriptor in the same way */
            ResourceDescriptor->Flags |= CM_RESOURCE_MEMORY_PREFETCHABLE;
        }
    }
 
    /* The probe leaves only the bits the BAR implements, so the lowest one is its length */
    Length = AddressBits & (~AddressBits + 1);
 
    /* A BAR that implements no address bits is not there */
    if (!Length)
    {
        ResourceDescriptor->Type = CmResourceTypeNull;
        return FALSE;
    }
 
    /* A legacy memory BAR can only be placed below 1MB */
    if ((Type == CmResourceTypeMemory) &&
        ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT))
    {
        AddressBits &= 0xFFFFF;
    }
 
    /* A BAR aligns to its own length and decodes nothing above the bits it implements */
    Alignment = Length;
    MinimumAddress = 0;
    MaximumAddress = AddressBits | (Length - 1);
 
    /* A length of 4GB or more takes the large memory form */
    if (!NT_SUCCESS(RtlIoEncodeMemIoResource(ResourceDescriptor,
                                             Type,
                                             Length,
                                             Alignment,
                                             MinimumAddress,
                                             MaximumAddress)))
    {
        /* Fail this descriptor */
        ResourceDescriptor->Type = CmResourceTypeNull;
    }
 
    /* Return if this is a 64-bit BAR, so the loop code knows to skip the next one */
    return Is64BitBar;
}

Referenced by Cardbus_SaveLimits(), Device_SaveLimits(), and PPBridge_SaveLimits().

◆ PciDebugDumpCommonConfig()

VOID NTAPI PciDebugDumpCommonConfig ( IN PPCI_COMMON_HEADER PciData )

Definition at line 207 of file debug.c.

{
    USHORT i;
 
    /* Loop the PCI header */
    for (i = 0; i < PCI_COMMON_HDR_LENGTH; i += 4)
    {
        /* Dump each DWORD and its offset */
        DPRINT1("  %02x - %08x\n", i, *(PULONG)((ULONG_PTR)PciData + i));
    }
}

Referenced by PcipGetFunctionLimits(), and PciScanBus().

◆ PciDebugDumpQueryCapabilities()

VOID NTAPI PciDebugDumpQueryCapabilities ( IN PDEVICE_CAPABILITIES DeviceCaps )

Definition at line 221 of file debug.c.

{
    ULONG i;
 
    /* Dump the capabilities */
    DPRINT1("PCIX - Capabilities\n  Lock:%u, Eject:%u, Remove:%u, Dock:%u, UniqueId:%u\n",
            DeviceCaps->LockSupported,
            DeviceCaps->EjectSupported,
            DeviceCaps->Removable,
            DeviceCaps->DockDevice,
            DeviceCaps->UniqueID);
    DbgPrint("  SilentInstall:%u, RawOk:%u, SurpriseOk:%u\n",
             DeviceCaps->SilentInstall,
             DeviceCaps->RawDeviceOK,
             DeviceCaps->SurpriseRemovalOK);
    DbgPrint("  Address %08x, UINumber %08x, Latencies D1 %u, D2 %u, D3 %u\n",
             DeviceCaps->Address,
             DeviceCaps->UINumber,
             DeviceCaps->D1Latency,
             DeviceCaps->D2Latency,
             DeviceCaps->D3Latency);
 
    /* Dump and convert the wake levels */
    DbgPrint("  System Wake: %s, Device Wake: %s\n  DeviceState[PowerState] [",
             SystemPowerStates[min(DeviceCaps->SystemWake, PowerSystemMaximum)],
             DevicePowerStates[min(DeviceCaps->DeviceWake, PowerDeviceMaximum)]);
 
    /* Dump and convert the power state mappings */
    for (i = PowerSystemWorking; i < PowerSystemMaximum; i++)
        DbgPrint(" %s", DevicePowerStates[DeviceCaps->DeviceState[i]]);
 
    /* Finish the dump */
    DbgPrint(" ]\n");
}

Referenced by PciFdoIrpQueryCapabilities(), and PciQueryCapabilities().

◆ PciDebugIrpDispatchDisplay()

BOOLEAN NTAPI PciDebugIrpDispatchDisplay	(	IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN USHORT	MaxMinor
	)

Definition at line 124 of file debug.c.

{
    PPCI_PDO_EXTENSION PdoDeviceExtension;
    ULONG BreakMask;
    //ULONG DebugLevel = 0;
    PCHAR IrpString;
 
    /* Only two functions are recognized */
    switch (IoStackLocation->MajorFunction)
    {
        case IRP_MJ_POWER:
 
            /* Get the string and the correct break mask for the extension */
            BreakMask = (DeviceExtension->ExtensionType == PciPdoExtensionType) ?
                         PciBreakOnPdoPowerIrp : PciBreakOnFdoPowerIrp;
            IrpString = PciDebugPoIrpTypeToText(IoStackLocation->MinorFunction);
            break;
 
        case IRP_MJ_PNP:
 
            /* Get the string and the correct break mask for the extension */
            BreakMask = (DeviceExtension->ExtensionType == PciFdoExtensionType) ?
                         PciBreakOnPdoPnpIrp : PciBreakOnFdoPnpIrp;
            IrpString = PciDebugPnpIrpTypeToText(IoStackLocation->MinorFunction);
            break;
 
        default:
 
            /* Other functions are not decoded */
            BreakMask = FALSE;
            IrpString = "";
            break;
    }
 
    /* Check if this is a PDO */
    if (DeviceExtension->ExtensionType == PciPdoExtensionType)
    {
        /* Choose the correct debug level based on which function this is */
        if (IoStackLocation->MajorFunction == IRP_MJ_POWER)
        {
            //DebugLevel = 0x500;
        }
        else if (IoStackLocation->MajorFunction == IRP_MJ_PNP)
        {
            //DebugLevel = 0x200;
        }
 
        /* For a PDO, print out the bus, device, and function number */
        PdoDeviceExtension = (PVOID)DeviceExtension;
        DPRINT1("PCIX - PDO(b=0x%x, d=0x%x, f=0x%x)<-%s\n",
                PdoDeviceExtension->ParentFdoExtension->BaseBus,
                PdoDeviceExtension->Slot.u.bits.DeviceNumber,
                PdoDeviceExtension->Slot.u.bits.FunctionNumber,
                IrpString);
    }
    else if (DeviceExtension->ExtensionType == PciFdoExtensionType)
    {
        /* Choose the correct debug level based on which function this is */
        if (IoStackLocation->MajorFunction == IRP_MJ_POWER)
        {
            //DebugLevel = 0x400;
        }
        else if (IoStackLocation->MajorFunction == IRP_MJ_PNP)
        {
            //DebugLevel = 0x100;
        }
 
        /* For an FDO, just dump the extension pointer and IRP string */
        DPRINT1("PCIX - FDO(%p)<-%s\n", DeviceExtension, IrpString);
    }
 
    /* If the function is illegal for this extension, complain */
    if (IoStackLocation->MinorFunction > MaxMinor)
        DPRINT1("PCIX - Unknown IRP, minor = 0x%x\n", IoStackLocation->MinorFunction);
 
    /* Return whether or not the debugger should be broken into for this IRP */
    return ((1 << IoStackLocation->MinorFunction) & BreakMask);
}

Referenced by PciDispatchIrp().

◆ PciDebugPrintCmResList()

VOID NTAPI PciDebugPrintCmResList ( IN PCM_RESOURCE_LIST ResourceList )

Definition at line 365 of file debug.c.

{
    PCM_FULL_RESOURCE_DESCRIPTOR FullDescriptor;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptor;
    ULONG Count, i, ListCount;
 
    /* Make sure there's something to dump */
    if (!PartialList) return;
 
    /* Get the full list count */
    ListCount = PartialList->Count;
    FullDescriptor = PartialList->List;
    DPRINT1("  CM_RESOURCE_LIST (PCI Bus Driver) (List Count = %u)\n", PartialList->Count);
 
    /* Loop full list */
    for (i = 0; i < ListCount; i++)
    {
        /* Loop full descriptor */
        DPRINT1("     InterfaceType        %d\n", FullDescriptor->InterfaceType);
        DPRINT1("     BusNumber            0x%x\n", FullDescriptor->BusNumber);
 
        /* Get partial count and loop partials */
        Count = FullDescriptor->PartialResourceList.Count;
        for (PartialDescriptor = FullDescriptor->PartialResourceList.PartialDescriptors;
             Count;
             PartialDescriptor = CmiGetNextPartialDescriptor(PartialDescriptor))
        {
            /* Print each partial */
            PciDebugPrintPartialResource(PartialDescriptor);
            Count--;
        }
 
        /* Go to the next full descriptor */
        FullDescriptor = (PCM_FULL_RESOURCE_DESCRIPTOR)PartialDescriptor;
    }
 
    /* Done printing data */
    DPRINT1("\n");
}

Referenced by PciComputeNewCurrentSettings().

◆ PciDebugPrintIoResReqList()

VOID NTAPI PciDebugPrintIoResReqList ( IN PIO_RESOURCE_REQUIREMENTS_LIST Requirements )

Definition at line 303 of file debug.c.

{
    ULONG AlternativeLists;
    PIO_RESOURCE_LIST List;
    ULONG Count;
    PIO_RESOURCE_DESCRIPTOR Descriptor;
 
    /* Make sure there's a list */
    if (!Requirements) return;
 
    /* Grab the main list and the alternates as well */
    AlternativeLists = Requirements->AlternativeLists;
    List = Requirements->List;
 
    /* Print out the initial header*/
    DPRINT1("  IO_RESOURCE_REQUIREMENTS_LIST (PCI Bus Driver)\n");
    DPRINT1("     InterfaceType        %d\n", Requirements->InterfaceType);
    DPRINT1("     BusNumber            0x%x\n", Requirements->BusNumber);
    DPRINT1("     SlotNumber           %d (0x%x), (d/f = 0x%x/0x%x)\n",
            Requirements->SlotNumber,
            Requirements->SlotNumber,
            ((PCI_SLOT_NUMBER*)&Requirements->SlotNumber)->u.bits.DeviceNumber,
            ((PCI_SLOT_NUMBER*)&Requirements->SlotNumber)->u.bits.FunctionNumber);
    DPRINT1("     AlternativeLists     %u\n", AlternativeLists);
 
    /* Scan alternative lists */
    while (AlternativeLists--)
    {
        /* Get the descriptor array, and the count of descriptors */
        Descriptor = List->Descriptors;
        Count = List->Count;
 
        /* Print out each descriptor */
        DPRINT1("\n     List[%u].Count = %u\n", AlternativeLists, Count);
        while (Count--) PciDebugPrintIoResource(Descriptor++);
 
        /* Should've reached a new list now */
        List = (PIO_RESOURCE_LIST)Descriptor;
    }
 
    /* Terminate the dump */
    DPRINT1("\n");
}

Referenced by PciQueryRequirements().

◆ PciDebugPrintPartialResource()

VOID NTAPI PciDebugPrintPartialResource ( IN PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialResource )

Definition at line 349 of file debug.c.

{
    /* Dump all the data in the partial */
    DPRINT1("     Partial Resource Descriptor @0x%p\n", PartialResource);
    DPRINT1("        Type             = %u (%s)\n", PartialResource->Type, PciDebugCmResourceTypeToText(PartialResource->Type));
    DPRINT1("        ShareDisposition = %u\n", PartialResource->ShareDisposition);
    DPRINT1("        Flags            = 0x%04X\n", PartialResource->Flags);
    DPRINT1("        Data[%d] = %08x  %08x  %08x\n",
            0,
            PartialResource->u.Generic.Start.LowPart,
            PartialResource->u.Generic.Start.HighPart,
            PartialResource->u.Generic.Length);
}

Referenced by PciComputeNewCurrentSettings(), and PciDebugPrintCmResList().

◆ PciDecodeEnable()

VOID NTAPI PciDecodeEnable	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN BOOLEAN	Enable,
		OUT PUSHORT	Command
	)

Definition at line 1359 of file utils.c.

{
    USHORT CommandValue;
 
    /*
     * If decodes are being disabled, make sure it's allowed, and in both cases,
     * make sure that a hackflag isn't preventing touching the decodes at all.
     */
    if (((Enable) || (PciCanDisableDecodes(PdoExtension, 0, 0, 0))) &&
        !(PdoExtension->HackFlags & PCI_HACK_PRESERVE_COMMAND))
    {
        /* Did the caller already have a command word? */
        if (Command)
        {
            /* Use the caller's */
            CommandValue = *Command;
        }
        else
        {
            /* Otherwise, read the current command */
            PciReadDeviceConfig(PdoExtension,
                                &CommandValue,
                                FIELD_OFFSET(PCI_COMMON_HEADER, Command),
                                sizeof(USHORT));
        }
 
        /* Turn off decodes by default */
        CommandValue &= ~(PCI_ENABLE_IO_SPACE |
                          PCI_ENABLE_MEMORY_SPACE |
                          PCI_ENABLE_BUS_MASTER);
 
        /* If requested, enable the decodes that were enabled at init time */
        if (Enable) CommandValue |= PdoExtension->CommandEnables &
                                    (PCI_ENABLE_IO_SPACE |
                                     PCI_ENABLE_MEMORY_SPACE |
                                     PCI_ENABLE_BUS_MASTER);
 
        /* Update the command word */
        PciWriteDeviceConfig(PdoExtension,
                             &CommandValue,
                             FIELD_OFFSET(PCI_COMMON_HEADER, Command),
                             sizeof(USHORT));
    }
}

Referenced by PciApplyHacks(), PciConfigureIdeController(), PciPdoTurnOff(), and PcipUpdateHardware().

◆ PciDispatchIrp()

NTSTATUS NTAPI PciDispatchIrp	(	IN PDEVICE_OBJECT	DeviceObject,
		IN PIRP	Irp
	)

Definition at line 99 of file dispatch.c.

{
    PPCI_FDO_EXTENSION DeviceExtension;
    PIO_STACK_LOCATION IoStackLocation;
    PPCI_MJ_DISPATCH_TABLE IrpDispatchTable;
    BOOLEAN PassToPdo;
    NTSTATUS Status;
    PPCI_MN_DISPATCH_TABLE TableArray = NULL, Table;
    USHORT MaxMinor;
    PCI_DISPATCH_STYLE DispatchStyle = 0;
    PCI_DISPATCH_FUNCTION DispatchFunction = NULL;
    DPRINT("PCIX - Dispatch IRP\n");
 
    /* Get the extension and I/O stack location for this IRP */
    DeviceExtension = (PPCI_FDO_EXTENSION)DeviceObject->DeviceExtension;
    IoStackLocation = IoGetCurrentIrpStackLocation(Irp);
    ASSERT((DeviceExtension->ExtensionType == PciPdoExtensionType) ||
           (DeviceExtension->ExtensionType == PciFdoExtensionType));
 
    /* Deleted extensions don't respond to IRPs */
    if (DeviceExtension->DeviceState == PciDeleted)
    {
        /* Fail this IRP */
        Status = STATUS_NO_SUCH_DEVICE;
        PassToPdo = FALSE;
    }
    else
    {
        /* Otherwise, get the dispatch table for the extension */
        IrpDispatchTable = DeviceExtension->IrpDispatchTable;
 
        /* And choose which function table to use */
        switch (IoStackLocation->MajorFunction)
        {
            case IRP_MJ_POWER:
 
                /* Power Manager IRPs */
                TableArray = IrpDispatchTable->PowerIrpDispatchTable;
                MaxMinor = IrpDispatchTable->PowerIrpMaximumMinorFunction;
                break;
 
            case IRP_MJ_PNP:
 
                /* Plug-and-Play Manager IRPs */
                TableArray = IrpDispatchTable->PnpIrpDispatchTable;
                MaxMinor = IrpDispatchTable->PnpIrpMaximumMinorFunction;
                break;
 
            case IRP_MJ_SYSTEM_CONTROL:
 
                /* WMI IRPs */
                DispatchFunction = IrpDispatchTable->SystemControlIrpDispatchFunction;
                DispatchStyle = IrpDispatchTable->SystemControlIrpDispatchStyle;
                MaxMinor = 0xFFFF;
                break;
 
            default:
 
                /* Unrecognized IRPs */
                DispatchFunction = IrpDispatchTable->OtherIrpDispatchFunction;
                DispatchStyle = IrpDispatchTable->OtherIrpDispatchStyle;
                MaxMinor = 0xFFFF;
                break;
        }
 
        /* Only deal with recognized IRPs */
        if (MaxMinor != 0xFFFF)
        {
            /* Make sure the function is recognized */
            if (IoStackLocation->MinorFunction > MaxMinor)
            {
                /* Pick the terminator, which should return unrecognized */
                Table = &TableArray[MaxMinor + 1];
            }
            else
            {
                /* Pick the appropriate table for this function */
                Table = &TableArray[IoStackLocation->MinorFunction];
            }
 
            /* From that table, get the function code and dispatch style */
            DispatchStyle = Table->DispatchStyle;
            DispatchFunction = Table->DispatchFunction;
        }
 
        /* Print out debugging information, and see if we should break */
        if (PciDebugIrpDispatchDisplay(IoStackLocation,
                                       DeviceExtension,
                                       MaxMinor))
        {
            /* The developer/user wants us to break for this IRP, do it */
            DbgBreakPoint();
        }
 
        /* Check if this IRP should be sent up the stack first */
        if (DispatchStyle == IRP_UPWARD)
        {
            /* Do it now before handling it ourselves */
            PciCallDownIrpStack(DeviceExtension, Irp);
        }
 
        /* Call the our driver's handler for this IRP and deal with the IRP */
        Status = DispatchFunction(Irp, IoStackLocation, DeviceExtension);
        switch (DispatchStyle)
        {
            /* Complete IRPs are completely immediately by our driver */
            case IRP_COMPLETE:
                PassToPdo = FALSE;
                break;
 
            /* Downward IRPs are send to the attached FDO */
            case IRP_DOWNWARD:
                PassToPdo = TRUE;
                break;
 
            /* Upward IRPs are completed immediately by our driver */
            case IRP_UPWARD:
                PassToPdo = FALSE;
                break;
 
            /* Dispatch IRPs are immediately returned */
            case IRP_DISPATCH:
                return Status;
 
            /* There aren't any other dispatch styles! */
            default:
                ASSERT(FALSE);
                return Status;
        }
    }
 
    /* Pending IRPs are returned immediately */
    if (Status == STATUS_PENDING) return Status;
 
    /* Handled IRPs return their status in the status block */
    if (Status != STATUS_NOT_SUPPORTED) Irp->IoStatus.Status = Status;
 
    /* Successful, or unhandled IRPs that are "DOWNWARD" are sent to the PDO */
    if ((PassToPdo) && ((NT_SUCCESS(Status)) || (Status == STATUS_NOT_SUPPORTED)))
    {
        /* Let the PDO deal with it */
        Status = PciPassIrpFromFdoToPdo(DeviceExtension, Irp);
    }
    else
    {
        /* Otherwise, the IRP is returned with its status */
        Status = Irp->IoStatus.Status;
 
        /* Power IRPs need to notify the Power Manager that the next IRP can go */
        if (IoStackLocation->MajorFunction == IRP_MJ_POWER) PoStartNextPowerIrp(Irp);
 
        /* And now this IRP can be completed */
        IoCompleteRequest(Irp, IO_NO_INCREMENT);
    }
 
    /* And the status returned back to the caller */
    return Status;
}

◆ PciEcamReadWriteConfig()

BOOLEAN NTAPI PciEcamReadWriteConfig	(	_In_ ULONG	Bus,
		_In_ PCI_SLOT_NUMBER	Slot,
		_Inout_updates_bytes_(Length) PVOID	Buffer,
		_In_ ULONG	Offset,
		_In_ ULONG	Length,
		_In_ BOOLEAN	Read
	)

Performs a configuration space access through the ECAM window.

Returns: FALSE if the window cannot serve the access, in which case the caller falls back to the legacy mechanism.

Definition at line 401 of file ecam.c.

{
    PUCHAR Function;
 
    if (!PciEcamVerified) return FALSE;
 
    if ((Offset >= PCI_EXTENDED_CONFIG_LENGTH) ||
        (Length > (PCI_EXTENDED_CONFIG_LENGTH - Offset)))
    {
        return FALSE;
    }
 
    Function = PciEcamFunctionBase(Bus, Slot);
    if (!Function) return FALSE;
 
    PciEcamTransfer(Function, Buffer, Offset, Length, Read);
    return TRUE;
}

Referenced by PciReadWriteConfigSpace().

◆ PciExecuteCriticalSystemRoutine()

ULONG_PTR NTAPI PciExecuteCriticalSystemRoutine ( IN ULONG_PTR IpiContext )

Definition at line 1144 of file utils.c.

{
    PPCI_IPI_CONTEXT Context = (PPCI_IPI_CONTEXT)IpiContext;
 
    /* Check if the IPI is already running */
    if (!InterlockedDecrement(&Context->RunCount))
    {
        /* Nope, this is the first instance, so execute the IPI function */
        Context->Function(Context->DeviceExtension, Context->Context);
 
        /* Notify anyone that was spinning that they can stop now */
        Context->Barrier = 0;
    }
    else
    {
        /* Spin until it has finished running */
        while (Context->Barrier);
    }
 
    /* Done */
    return 0;
}

◆ PciFdoIrpCancelRemoveDevice()

NTSTATUS NTAPI PciFdoIrpCancelRemoveDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 322 of file fdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* The remove is off, so the bus stays where it was */
    PciCancelStateTransition(DeviceExtension, PciDeleted);
    return STATUS_SUCCESS;
}

◆ PciFdoIrpCancelStopDevice()

NTSTATUS NTAPI PciFdoIrpCancelStopDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 382 of file fdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* The stop is off, so the bus keeps its windows */
    PciCancelStateTransition(DeviceExtension, PciStopped);
    return STATUS_SUCCESS;
}

◆ PciFdoIrpDeviceUsageNotification()

NTSTATUS NTAPI PciFdoIrpDeviceUsageNotification	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 527 of file fdo.c.

{
    PAGED_CODE();
 
    /* A failure from below stands, but a lower driver that ignored it does not count */
    if (!NT_SUCCESS(Irp->IoStatus.Status) &&
        (Irp->IoStatus.Status != STATUS_NOT_SUPPORTED))
    {
        return Irp->IoStatus.Status;
    }
 
    return PciUpdateDeviceUsage(&DeviceExtension->PowerState, IoStackLocation);
}

◆ PciFdoIrpQueryCapabilities()

NTSTATUS NTAPI PciFdoIrpQueryCapabilities	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 500 of file fdo.c.

{
    PDEVICE_CAPABILITIES Capabilities;
    PAGED_CODE();
    ASSERT_FDO(DeviceExtension);
 
    UNREFERENCED_PARAMETER(Irp);
 
    /* Get the capabilities */
    Capabilities = IoStackLocation->Parameters.DeviceCapabilities.Capabilities;
 
    /* Inherit wake levels and power mappings from the higher-up capabilities */
    DeviceExtension->PowerState.SystemWakeLevel = Capabilities->SystemWake;
    DeviceExtension->PowerState.DeviceWakeLevel = Capabilities->DeviceWake;
    RtlCopyMemory(DeviceExtension->PowerState.SystemStateMapping,
                  Capabilities->DeviceState,
                  sizeof(DeviceExtension->PowerState.SystemStateMapping));
 
    /* Dump the capabilities and return success */
    PciDebugDumpQueryCapabilities(Capabilities);
    return STATUS_SUCCESS;
}

◆ PciFdoIrpQueryDeviceRelations()

NTSTATUS NTAPI PciFdoIrpQueryDeviceRelations	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 398 of file fdo.c.

{
    NTSTATUS Status;
    PAGED_CODE();
 
    /* Are bus relations being queried? */
    if (IoStackLocation->Parameters.QueryDeviceRelations.Type != BusRelations)
    {
        /* The FDO is a bus, so only bus relations can be obtained */
        Status = STATUS_NOT_SUPPORTED;
    }
    else
    {
        /* Scan the PCI bus and build the device relations for the caller */
        Status = PciQueryDeviceRelations(DeviceExtension,
                                         (PDEVICE_RELATIONS*)
                                         &Irp->IoStatus.Information);
    }
 
    /* Return the enumeration status back */
    return Status;
}

◆ PciFdoIrpQueryInterface()

NTSTATUS NTAPI PciFdoIrpQueryInterface	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 425 of file fdo.c.

{
    NTSTATUS Status;
    PAGED_CODE();
    ASSERT(DeviceExtension->ExtensionType == PciFdoExtensionType);
 
    /* Deleted extensions don't respond to IRPs */
    if (DeviceExtension->DeviceState == PciDeleted)
    {
        /* Hand it back to try to deal with it */
        return PciPassIrpFromFdoToPdo(DeviceExtension, Irp);
    }
 
    /* Query our driver for this interface */
    Status = PciQueryInterface(DeviceExtension,
                               IoStackLocation->Parameters.QueryInterface.
                               InterfaceType,
                               IoStackLocation->Parameters.QueryInterface.
                               Size,
                               IoStackLocation->Parameters.QueryInterface.
                               Version,
                               IoStackLocation->Parameters.QueryInterface.
                               InterfaceSpecificData,
                               IoStackLocation->Parameters.QueryInterface.
                               Interface,
                               FALSE);
    if (NT_SUCCESS(Status))
    {
        /* We found it, let the PDO handle it */
        Irp->IoStatus.Status = Status;
        return PciPassIrpFromFdoToPdo(DeviceExtension, Irp);
    }
    else if (Status == STATUS_NOT_SUPPORTED)
    {
        /* Otherwise, we can't handle it, let someone else down the stack try */
        Status = PciCallDownIrpStack(DeviceExtension, Irp);
        if (Status == STATUS_NOT_SUPPORTED)
        {
            /* They can't either, try a last-resort interface lookup */
            Status = PciQueryInterface(DeviceExtension,
                                       IoStackLocation->Parameters.QueryInterface.
                                       InterfaceType,
                                       IoStackLocation->Parameters.QueryInterface.
                                       Size,
                                       IoStackLocation->Parameters.QueryInterface.
                                       Version,
                                       IoStackLocation->Parameters.QueryInterface.
                                       InterfaceSpecificData,
                                       IoStackLocation->Parameters.QueryInterface.
                                       Interface,
                                       TRUE);
        }
    }
 
    /* Has anyone claimed this interface yet? */
    if (Status == STATUS_NOT_SUPPORTED)
    {
        /* No, return the original IRP status */
        Status = Irp->IoStatus.Status;
    }
    else
    {
        /* Yes, set the new IRP status */
        Irp->IoStatus.Status = Status;
    }
 
    /* Complete this IRP */
    IoCompleteRequest(Irp, IO_NO_INCREMENT);
    return Status;
}

◆ PciFdoIrpQueryLegacyBusInformation()

NTSTATUS NTAPI PciFdoIrpQueryLegacyBusInformation	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 567 of file fdo.c.

{
    PLEGACY_BUS_INFORMATION BusInformation;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* The PnP manager frees this once it has recorded the bus */
    BusInformation = ExAllocatePoolWithTag(PagedPool,
                                           sizeof(*BusInformation),
                                           PCI_POOL_TAG);
    if (!BusInformation)
        return STATUS_INSUFFICIENT_RESOURCES;
 
    BusInformation->BusTypeGuid = GUID_BUS_TYPE_PCI;
    BusInformation->LegacyBusType = PCIBus;
    BusInformation->BusNumber = DeviceExtension->BaseBus;
 
    Irp->IoStatus.Information = (ULONG_PTR)BusInformation;
    return STATUS_SUCCESS;
}

◆ PciFdoIrpQueryPower()

NTSTATUS NTAPI PciFdoIrpQueryPower	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 351 of file power.c.

{
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
    UNREFERENCED_PARAMETER(DeviceExtension);
 
    /* Refusing states that would break an armed wake is not implemented yet */
    DPRINT1("PCIX - Wake-aware power queries are not implemented, accepting the state\n");
    return STATUS_SUCCESS;
}

◆ PciFdoIrpQueryRemoveDevice()

NTSTATUS NTAPI PciFdoIrpQueryRemoveDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 236 of file fdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Paging, hibernation and dump files behind this bus cannot lose their path */
    if (DeviceExtension->PowerState.Paging ||
        DeviceExtension->PowerState.Hibernate ||
        DeviceExtension->PowerState.CrashDump)
    {
        return STATUS_DEVICE_BUSY;
    }
 
    /* The remove that follows commits this */
    return PciBeginStateTransition(DeviceExtension, PciDeleted);
}

◆ PciFdoIrpQueryStopDevice()

NTSTATUS NTAPI PciFdoIrpQueryStopDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 356 of file fdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Paging, hibernation and dump files behind this bus cannot lose their path */
    if (DeviceExtension->PowerState.Paging ||
        DeviceExtension->PowerState.Hibernate ||
        DeviceExtension->PowerState.CrashDump)
    {
        return STATUS_DEVICE_BUSY;
    }
 
    /* Root bus ranges are fixed, and children would sit outside new bridge windows */
    if (PCI_IS_ROOT_FDO(DeviceExtension) || DeviceExtension->ChildPdoList)
        return STATUS_UNSUCCESSFUL;
 
    return PciBeginStateTransition(DeviceExtension, PciStopped);
}

◆ PciFdoIrpRemoveDevice()

NTSTATUS NTAPI PciFdoIrpRemoveDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 259 of file fdo.c.

{
    PDEVICE_OBJECT DeviceObject, AttachedDeviceObject;
    PPCI_PDO_EXTENSION BridgeExtension;
    PSINGLE_LIST_ENTRY Entry;
    NTSTATUS Status;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* A remove with no query before it, such as after a failed start, begins the deletion here */
    if (DeviceExtension->TentativeNextState != PciDeleted)
        PciBeginStateTransition(DeviceExtension, PciDeleted);
 
    PciCommitStateTransition(DeviceExtension, PciDeleted);
 
    /* Unlink the bus first so no lookup can reach it while it comes apart */
    KeEnterCriticalRegion();
    KeWaitForSingleObject(&PciGlobalLock, Executive, KernelMode, FALSE, NULL);
 
    for (Entry = &PciFdoExtensionListHead; Entry->Next; Entry = Entry->Next)
    {
        if (Entry->Next == &DeviceExtension->List)
        {
            Entry->Next = DeviceExtension->List.Next;
            break;
        }
    }
 
    if (!PCI_IS_ROOT_FDO(DeviceExtension))
    {
        BridgeExtension = DeviceExtension->PhysicalDeviceObject->DeviceExtension;
        ASSERT_PDO(BridgeExtension);
 
        if (BridgeExtension->BridgeFdoExtension == DeviceExtension)
            BridgeExtension->BridgeFdoExtension = NULL;
    }
 
    KeSetEvent(&PciGlobalLock, IO_NO_INCREMENT, FALSE);
    KeLeaveCriticalRegion();
 
    PciDeleteBusChildren(DeviceExtension);
    PciFreeBusSecondaryExtensions(DeviceExtension);
 
    if (DeviceExtension->PreservedConfig)
        ExFreePoolWithTag(DeviceExtension->PreservedConfig, TAG_PCI_PRESERVED);
 
    /* The lower drivers see the remove before this device leaves the stack */
    DeviceObject = DeviceExtension->FunctionalDeviceObject;
    AttachedDeviceObject = DeviceExtension->AttachedDeviceObject;
 
    Irp->IoStatus.Status = STATUS_SUCCESS;
    Status = PciPassIrpFromFdoToPdo(DeviceExtension, Irp);
 
    IoDetachDevice(AttachedDeviceObject);
    IoDeleteDevice(DeviceObject);
    return Status;
}

◆ PciFdoIrpStartDevice()

NTSTATUS NTAPI PciFdoIrpStartDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 202 of file fdo.c.

{
    NTSTATUS Status;
    PCM_RESOURCE_LIST Resources;
    PAGED_CODE();
 
    /* The device stack must be starting the FDO in a success path */
    if (!NT_SUCCESS(Irp->IoStatus.Status)) return STATUS_NOT_SUPPORTED;
 
    /* Attempt to switch the state machine to the started state */
    Status = PciBeginStateTransition(DeviceExtension, PciStarted);
    if (!NT_SUCCESS(Status)) return Status;
 
    /* Only a root bus seeds its arbiters from these, a bus behind a bridge uses its windows */
    Resources = IoStackLocation->Parameters.StartDevice.AllocatedResources;
 
    /* Initialize the arbiter for this FDO */
    Status = PciInitializeArbiterRanges(DeviceExtension, Resources);
    if (!NT_SUCCESS(Status))
    {
        /* Cancel the transition if this failed */
        PciCancelStateTransition(DeviceExtension, PciStarted);
        return Status;
    }
 
    /* Commit the transition to the started state */
    PciCommitStateTransition(DeviceExtension, PciStarted);
    return STATUS_SUCCESS;
}

◆ PciFdoIrpStopDevice()

NTSTATUS NTAPI PciFdoIrpStopDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 338 of file fdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    PciCommitStateTransition(DeviceExtension, PciStopped);
 
    /* The next start seeds the arbiters again from the windows it is given */
    DeviceExtension->ArbitersInitialized = FALSE;
    return STATUS_SUCCESS;
}

◆ PciFdoIrpSurpriseRemoval()

NTSTATUS NTAPI PciFdoIrpSurpriseRemoval	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 545 of file fdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Only the remove that follows is left, and it commits the deletion */
    if (NT_SUCCESS(PciBeginStateTransition(DeviceExtension, PciSurpriseRemoved)))
    {
        PciCommitStateTransition(DeviceExtension, PciSurpriseRemoved);
        PciBeginStateTransition(DeviceExtension, PciDeleted);
    }
 
    /* Failing this would keep it from reaching the PDO below */
    return STATUS_SUCCESS;
}

◆ PciFdoSetPowerState()

NTSTATUS NTAPI PciFdoSetPowerState	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 318 of file power.c.

{
    POWER_STATE State = IoStackLocation->Parameters.Power.State;
 
    /* Bridge hardware is handled by the PDO below, so only the state is kept */
    if (IoStackLocation->Parameters.Power.Type == DevicePowerState)
    {
        DeviceExtension->PowerState.CurrentDeviceState = State.DeviceState;
        return STATUS_SUCCESS;
    }
 
    DeviceExtension->PowerState.CurrentSystemState = State.SystemState;
    if (DeviceExtension->DeviceState != PciStarted)
        return STATUS_SUCCESS;
 
    /* The bus owns its power policy and follows up with a device state request */
    Irp->IoStatus.Status = STATUS_SUCCESS;
    IoMarkIrpPending(Irp);
    IoCopyCurrentIrpStackLocationToNext(Irp);
    IoSetCompletionRoutine(Irp,
                           PciFdoSystemPowerCompletion,
                           DeviceExtension,
                           TRUE,
                           TRUE,
                           TRUE);
    PoCallDriver(DeviceExtension->AttachedDeviceObject, Irp);
    return STATUS_PENDING;
}

◆ PciFdoWaitWake()

NTSTATUS NTAPI PciFdoWaitWake	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 305 of file power.c.

{
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Arming the bus for its children's wake requests is not implemented yet */
    DPRINT1("PCIX - Bus wake arming is not implemented, passing wait-wake down\n");
    return PciPassIrpFromFdoToPdo(DeviceExtension, Irp);
}

◆ PciFindNextSecondaryExtension()

PPCI_SECONDARY_EXTENSION NTAPI PciFindNextSecondaryExtension	(	IN PSINGLE_LIST_ENTRY	ListHead,
		IN PCI_SIGNATURE	ExtensionType
	)

Definition at line 584 of file utils.c.

{
    PSINGLE_LIST_ENTRY NextEntry;
    PPCI_SECONDARY_EXTENSION Extension;
 
    /* Scan the list */
    for (NextEntry = ListHead; NextEntry; NextEntry = NextEntry->Next)
    {
        /* Grab each extension and check if it's the one requested */
        Extension = CONTAINING_RECORD(NextEntry, PCI_SECONDARY_EXTENSION, List);
        if (Extension->ExtensionType == ExtensionType) return Extension;
    }
 
    /* Nothing was found */
    return NULL;
}

Referenced by ario_ApplyBrokenVideoHack(), PciArbiterConstructor(), and PciInitializeArbiterRanges().

◆ PciFindParentPciFdoExtension()

PPCI_FDO_EXTENSION NTAPI PciFindParentPciFdoExtension	(	IN PDEVICE_OBJECT	DeviceObject,
		IN PKEVENT	Lock
	)

Definition at line 340 of file utils.c.

{
    PPCI_FDO_EXTENSION DeviceExtension;
    PPCI_PDO_EXTENSION SearchExtension, FoundExtension;
 
    /* Assume we'll find nothing */
    SearchExtension = DeviceObject->DeviceExtension;
    FoundExtension = NULL;
 
    /* Check if a lock was specified */
    if (Lock)
    {
        /* Wait for the lock to be released */
        KeEnterCriticalRegion();
        KeWaitForSingleObject(Lock, Executive, KernelMode, FALSE, NULL);
    }
 
    /* Now search for the extension */
    DeviceExtension = (PPCI_FDO_EXTENSION)PciFdoExtensionListHead.Next;
    while (DeviceExtension)
    {
        /* Acquire this device's lock */
        KeEnterCriticalRegion();
        KeWaitForSingleObject(&DeviceExtension->ChildListLock,
                              Executive,
                              KernelMode,
                              FALSE,
                              NULL);
 
        /* Scan all children PDO, stop when no more PDOs, or found it */
        for (FoundExtension = DeviceExtension->ChildPdoList;
             ((FoundExtension) && (FoundExtension != SearchExtension));
             FoundExtension = FoundExtension->Next);
 
        /* Release this device's lock */
        KeSetEvent(&DeviceExtension->ChildListLock, IO_NO_INCREMENT, FALSE);
        KeLeaveCriticalRegion();
 
        /* If we found it, break out */
        if (FoundExtension) break;
 
        /* Move to the next device */
        DeviceExtension = (PPCI_FDO_EXTENSION)DeviceExtension->List.Next;
    }
 
    /* Check if we had acquired a lock previously */
    if (Lock)
    {
        /* Release it */
        KeSetEvent(Lock, IO_NO_INCREMENT, FALSE);
        KeLeaveCriticalRegion();
    }
 
    /* Return which extension was found, if any */
    return DeviceExtension;
}

Referenced by PciAddDevice().

◆ PciFindPdoByFunction()

PPCI_PDO_EXTENSION NTAPI PciFindPdoByFunction	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN ULONG	FunctionNumber,
		IN PPCI_COMMON_HEADER	PciData
	)

Definition at line 695 of file utils.c.

{
    KIRQL Irql;
    PPCI_PDO_EXTENSION PdoExtension;
 
    /* Get the current IRQL when this call was made */
    Irql = KeGetCurrentIrql();
 
    /* Is this a low-IRQL call? */
    if (Irql < DISPATCH_LEVEL)
    {
        /* Acquire this device's lock */
        KeEnterCriticalRegion();
        KeWaitForSingleObject(&DeviceExtension->ChildListLock,
                              Executive,
                              KernelMode,
                              FALSE,
                              NULL);
    }
 
    /* Loop every child PDO */
    for (PdoExtension = DeviceExtension->ChildPdoList;
         PdoExtension;
         PdoExtension = PdoExtension->Next)
    {
        /* Find only enumerated PDOs */
        if (!PdoExtension->ReportedMissing)
        {
            /* Same slot, and the IDs match as the device's hack flags allow */
            if ((FunctionNumber == PdoExtension->Slot.u.AsULONG) &&
                (PcipIsSameDevice(PdoExtension, PciData)))
            {
                /* This is considered to be the same PDO */
                break;
            }
        }
    }
 
    /* Was this a low-IRQL call? */
    if (Irql < DISPATCH_LEVEL)
    {
        /* Release this device's lock */
        KeSetEvent(&DeviceExtension->ChildListLock, IO_NO_INCREMENT, FALSE);
        KeLeaveCriticalRegion();
    }
 
    /* If the search found something, this is non-NULL, otherwise it's NULL */
    return PdoExtension;
}

Referenced by PciScanBus().

◆ PciFreeLegacyDeviceCache()

VOID NTAPI PciFreeLegacyDeviceCache ( VOID )

Frees the routing cached for slots claimed by legacy drivers.

Definition at line 357 of file routintf.c.

{
    PPCI_LEGACY_DEVICE LegacyDevice;
    PAGED_CODE();
 
    while (PciLegacyDeviceHead)
    {
        LegacyDevice = PciLegacyDeviceHead;
        PciLegacyDeviceHead = LegacyDevice->Next;
        ExFreePoolWithTag(LegacyDevice, TAG_PCI_ROUTING);
    }
}

Referenced by PciDriverUnload().

◆ PciGetAdjustedInterruptLine()

UCHAR NTAPI PciGetAdjustedInterruptLine ( IN PPCI_PDO_EXTENSION PdoExtension )

Definition at line 24 of file config.c.

{
    UCHAR InterruptLine = 0, PciInterruptLine;
    ULONG Length;
 
    /* Does the device have an interrupt pin? */
    if (PdoExtension->InterruptPin)
    {
        /* Find the associated line on the parent bus */
        Length = HalGetBusDataByOffset(PCIConfiguration,
                                       PdoExtension->ParentFdoExtension->BaseBus,
                                       PdoExtension->Slot.u.AsULONG,
                                       &PciInterruptLine,
                                       FIELD_OFFSET(PCI_COMMON_HEADER,
                                                    u.type0.InterruptLine),
                                       sizeof(UCHAR));
        if (Length) InterruptLine = PciInterruptLine;
    }
 
    /* Either keep the original interrupt line, or the one on the master bus */
    return InterruptLine ? PdoExtension->RawInterruptLine : InterruptLine;
}

Referenced by PciScanBus().

◆ PciGetBiosConfig()

NTSTATUS NTAPI PciGetBiosConfig	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		OUT PPCI_COMMON_HEADER	PciData
	)

Definition at line 840 of file utils.c.

{
    HANDLE KeyHandle, SubKeyHandle;
    OBJECT_ATTRIBUTES ObjectAttributes;
    UNICODE_STRING KeyName, KeyValue;
    WCHAR Buffer[32];
    WCHAR DataBuffer[sizeof(KEY_VALUE_PARTIAL_INFORMATION) + PCI_COMMON_HDR_LENGTH];
    PKEY_VALUE_PARTIAL_INFORMATION PartialInfo = (PVOID)DataBuffer;
    NTSTATUS Status;
    ULONG ResultLength;
    PAGED_CODE();
 
    /* Open the PCI key */
    Status = IoOpenDeviceRegistryKey(DeviceExtension->ParentFdoExtension->
                                     PhysicalDeviceObject,
                                     TRUE,
                                     KEY_ALL_ACCESS,
                                     &KeyHandle);
    if (!NT_SUCCESS(Status)) return Status;
 
    /* Create a volatile BIOS configuration key */
    RtlInitUnicodeString(&KeyName, L"BiosConfig");
    InitializeObjectAttributes(&ObjectAttributes,
                               &KeyName,
                               OBJ_KERNEL_HANDLE,
                               KeyHandle,
                               NULL);
    Status = ZwCreateKey(&SubKeyHandle,
                         KEY_READ,
                         &ObjectAttributes,
                         0,
                         NULL,
                         REG_OPTION_VOLATILE,
                         NULL);
    ZwClose(KeyHandle);
    if (!NT_SUCCESS(Status)) return Status;
 
    /* Create the key value based on the device and function number */
    _swprintf(Buffer,
              L"DEV_%02x&FUN_%02x",
              DeviceExtension->Slot.u.bits.DeviceNumber,
              DeviceExtension->Slot.u.bits.FunctionNumber);
    RtlInitUnicodeString(&KeyValue, Buffer);
 
    /* Query the value information (PCI BIOS configuration header) */
    Status = ZwQueryValueKey(SubKeyHandle,
                             &KeyValue,
                             KeyValuePartialInformation,
                             PartialInfo,
                             sizeof(DataBuffer),
                             &ResultLength);
    ZwClose(SubKeyHandle);
    if (!NT_SUCCESS(Status)) return Status;
 
    /* If any information was returned, go ahead and copy its data */
    ASSERT(PartialInfo->DataLength == PCI_COMMON_HDR_LENGTH);
    RtlCopyMemory(PciData, PartialInfo->Data, PCI_COMMON_HDR_LENGTH);
    return Status;
}

Referenced by PciGetBiosBusRange(), PciScanBus(), PPBridge_SaveCurrentSettings(), and routeintrf_UpdateInterruptLine().

◆ PciGetConfigHandlers()

NTSTATUS NTAPI PciGetConfigHandlers ( IN PPCI_FDO_EXTENSION FdoExtension )

Definition at line 266 of file config.c.

{
    PPCI_BUS_INTERFACE_STANDARD PciInterface;
    PBUS_HANDLER BusHandler;
    NTSTATUS Status;
 
    ASSERT(FdoExtension->BusHandler == NULL);
 
    /* Check if this is the FDO for the root bus */
    if (PCI_IS_ROOT_FDO(FdoExtension))
    {
        /* Query the PCI Bus Interface that ACPI exposes */
        ASSERT(FdoExtension->PciBusInterface == NULL);
        Status = PciQueryForPciBusInterface(FdoExtension);
        if (!NT_SUCCESS(Status))
        {
            /* No ACPI, so Bus Numbers should be maintained by BIOS */
            ASSERT(!PciAssignBusNumbers);
        }
        else
        {
            /* ACPI detected, PCI Bus Driver will reconfigure bus numbers*/
            PciAssignBusNumbers = TRUE;
 
            /* The driver below owns _OSC and reports what the firmware granted */
            PciInterface = FdoExtension->PciBusInterface;
            if ((PciInterface->Size >= RTL_SIZEOF_THROUGH_FIELD(PCI_BUS_INTERFACE_STANDARD,
                                                                RootBusCapability)) &&
                PciInterface->RootBusCapability)
            {
                PciInterface->RootBusCapability(PciInterface->Context,
                                                &FdoExtension->RootBusHardwareCapability);
 
                DPRINT1("PCIX - Root bus interface %d, _OSC support 0x%08lx, granted 0x%08lx\n",
                        FdoExtension->RootBusHardwareCapability.SecondaryInterface,
                        FdoExtension->RootBusHardwareCapability.OscFeatureSupport.u.AsULONG,
                        FdoExtension->RootBusHardwareCapability.OscControlGranted.u.AsULONG);
            }
        }
    }
    else
    {
        /* Check if the root bus already has the interface set up */
        if (FdoExtension->BusRootFdoExtension->PciBusInterface)
        {
            /* Nothing for this FDO to do */
            return STATUS_SUCCESS;
        }
 
        /* Fail into case below so we can query the HAL interface */
        Status = STATUS_NOT_SUPPORTED;
    }
 
    /* If the ACPI PCI Bus Interface couldn't be obtained, try the HAL */
    if (!NT_SUCCESS(Status))
    {
        /* Bus number assignment should be static */
        ASSERT(Status == STATUS_NOT_SUPPORTED);
        ASSERT(!PciAssignBusNumbers);
 
        /* Call the HAL to obtain the bus handler for PCI */
        BusHandler = HalReferenceHandlerForBus(PCIBus, FdoExtension->BaseBus);
        FdoExtension->BusHandler = BusHandler;
 
        /* Fail if the HAL does not have a PCI Bus Handler for this bus */
        if (!BusHandler) return STATUS_INVALID_DEVICE_REQUEST;
    }
 
    /* Appropriate interface was obtained */
    return STATUS_SUCCESS;
}

Referenced by PciAddDevice().

◆ PciGetDeviceDescriptionMessage()

PWCHAR NTAPI PciGetDeviceDescriptionMessage	(	IN UCHAR	BaseClass,
		IN UCHAR	SubClass
	)

Definition at line 105 of file id.c.

{
    PWCHAR Message;
    ULONG Identifier;
 
    /* The message identifier in the table is encoded based on the PCI class */
    Identifier = (BaseClass << 8) | SubClass;
 
    /* Go grab the description message for this device */
    Message = PciGetDescriptionMessage(Identifier, NULL);
    if (!Message)
    {
        /* It wasn't found, allocate a buffer for a generic description */
        Message = ExAllocatePoolWithTag(PagedPool, sizeof(L"PCI Device"), 'bicP');
        if (Message) RtlCopyMemory(Message, L"PCI Device", sizeof(L"PCI Device"));
    }
 
    /* Return the description message */
    return Message;
}

Referenced by PciQueryDeviceText(), and PciScanBus().

◆ PciGetDeviceProperty()

NTSTATUS NTAPI PciGetDeviceProperty	(	IN PDEVICE_OBJECT	DeviceObject,
		IN DEVICE_REGISTRY_PROPERTY	DeviceProperty,
		OUT PVOID *	OutputBuffer
	)

Definition at line 475 of file utils.c.

{
    NTSTATUS Status;
    ULONG BufferLength, ResultLength;
    PVOID Buffer;
    do
    {
        /* Query the requested property size */
        Status = IoGetDeviceProperty(DeviceObject,
                                     DeviceProperty,
                                     0,
                                     NULL,
                                     &BufferLength);
        if (Status != STATUS_BUFFER_TOO_SMALL)
        {
            /* Call should've failed with buffer too small! */
            DPRINT1("PCIX - Unexpected status from GetDeviceProperty, saw %08X, expected %08X.\n",
                    Status,
                    STATUS_BUFFER_TOO_SMALL);
            *OutputBuffer = NULL;
            ASSERTMSG("PCI Successfully did the impossible!\n", FALSE);
            break;
        }
 
        /* Allocate the required buffer */
        Buffer = ExAllocatePoolWithTag(PagedPool, BufferLength, 'BicP');
        if (!Buffer)
        {
            /* No memory, fail the request */
            DPRINT1("PCIX - Failed to allocate DeviceProperty buffer (%u bytes).\n", BufferLength);
            Status = STATUS_INSUFFICIENT_RESOURCES;
            break;
        }
 
        /* Do the actual property query call */
        Status = IoGetDeviceProperty(DeviceObject,
                                     DeviceProperty,
                                     BufferLength,
                                     Buffer,
                                     &ResultLength);
        if (!NT_SUCCESS(Status)) break;
 
        /* Return the buffer to the caller */
        ASSERT(BufferLength == ResultLength);
        *OutputBuffer = Buffer;
        return STATUS_SUCCESS;
    } while (FALSE);
 
    /* Failure path */
    return STATUS_UNSUCCESSFUL;
}

Referenced by PciAddDevice().

◆ PciGetExpressCapabilities()

VOID NTAPI PciGetExpressCapabilities ( _Inout_ PPCI_PDO_EXTENSION PdoExtension )

Records the Express capability of a new function and whether its extended configuration space can be reached.

Parameters

[in,out] PdoExtension The PDO extension of the function being enumerated.

Definition at line 99 of file express.c.

{
    PCI_EXPRESS_CAPABILITY Express;
    PPCI_FDO_EXTENSION ParentFdo;
    PPCI_PDO_EXTENSION ParentBridge;
    UCHAR Offset;
    PAGED_CODE();
 
    PdoExtension->ExpressCapabilityPtr = 0;
    PdoExtension->ExpressDeviceType = 0;
    PdoExtension->IsExtendedConfigReachable = FALSE;
 
    if (!PdoExtension->CapabilitiesPtr)
        return;
 
    if (PdoExtension->HackFlags & PCI_HACK_NO_EXPRESS_CAP)
        return;
 
    /* Only the capabilities register is needed */
    Offset = PciReadDeviceCapability(PdoExtension,
                                     PdoExtension->CapabilitiesPtr,
                                     PCI_CAPABILITY_ID_PCI_EXPRESS,
                                     &Express.Header,
                                     RTL_SIZEOF_THROUGH_FIELD(PCI_EXPRESS_CAPABILITY,
                                                              ExpressCapabilities));
    if (!Offset)
        return;
 
    PdoExtension->ExpressCapabilityPtr = Offset;
    PdoExtension->ExpressDeviceType = (UCHAR)Express.ExpressCapabilities.DeviceType;
 
    /* Every bridge between the root and this function has to pass extended config cycles */
    ParentFdo = PdoExtension->ParentFdoExtension;
    if (PCI_IS_ROOT_FDO(ParentFdo))
    {
        PdoExtension->IsExtendedConfigReachable = PciEcamVerified;
    }
    else
    {
        ParentBridge = (PPCI_PDO_EXTENSION)ParentFdo->PhysicalDeviceObject->DeviceExtension;
        ASSERT_PDO(ParentBridge);
        PdoExtension->IsExtendedConfigReachable = ParentBridge->IsExtendedConfigReachable;
    }
 
    DPRINT1("PCIX - Express capability at 0x%x, port type %u, version %u\n",
            PdoExtension->ExpressCapabilityPtr,
            PdoExtension->ExpressDeviceType,
            Express.ExpressCapabilities.CapabilityVersion);
}

Referenced by PciGetEnhancedCapabilities().

◆ PciGetHackFlags()

ULONGLONG NTAPI PciGetHackFlags	(	IN USHORT	VendorId,
		IN USHORT	DeviceId,
		IN USHORT	SubVendorId,
		IN USHORT	SubSystemId,
		IN UCHAR	RevisionId
	)

Definition at line 604 of file utils.c.

{
    PPCI_HACK_ENTRY HackEntry;
    ULONGLONG HackFlags;
    ULONG LastWeight, MatchWeight;
    ULONG EntryFlags;
 
    /* ReactOS SetupLDR Hack */
    if (!PciHackTable) return 0;
 
    /* Initialize the variables before looping */
    LastWeight = 0;
    HackFlags = 0;
    ASSERT(PciHackTable);
 
    /* Scan the hack table */
    for (HackEntry = PciHackTable;
         HackEntry->VendorID != PCI_INVALID_VENDORID;
         ++HackEntry)
    {
        /* Check if there's an entry for this device */
        if ((HackEntry->DeviceID == DeviceId) &&
            (HackEntry->VendorID == VendorId))
        {
            /* This is a basic match */
            EntryFlags = HackEntry->Flags;
            MatchWeight = 1;
 
            /* Does the entry have revision information? */
            if (EntryFlags & PCI_HACK_HAS_REVISION_INFO)
            {
                /* Check if the revision matches, if so, this is a better match */
                if (HackEntry->RevisionID != RevisionId) continue;
                MatchWeight = 3;
            }
 
            /* Does the netry have subsystem information? */
            if (EntryFlags & PCI_HACK_HAS_SUBSYSTEM_INFO)
            {
                /* Check if it matches, if so, this is the best possible match */
                if ((HackEntry->SubVendorID != SubVendorId) ||
                    (HackEntry->SubSystemID != SubSystemId))
                {
                    continue;
                }
                MatchWeight += 4;
            }
 
            /* Is this the best match yet? */
            if (MatchWeight > LastWeight)
            {
                /* This is the best match for now, use this as the hack flags */
                HackFlags = HackEntry->HackFlags;
                LastWeight = MatchWeight;
            }
        }
    }
 
    /* Return the best match */
    return HackFlags;
}

Referenced by PciScanBus().

◆ PciGetRegistryValue()

NTSTATUS NTAPI PciGetRegistryValue	(	IN PWCHAR	ValueName,
		IN PWCHAR	KeyName,
		IN HANDLE	RootHandle,
		IN ULONG	Type,
		OUT PVOID *	OutputBuffer,
		OUT PULONG	OutputLength
	)

Definition at line 193 of file utils.c.

{
    NTSTATUS Status;
    PKEY_VALUE_PARTIAL_INFORMATION PartialInfo;
    ULONG NeededLength, ActualLength;
    UNICODE_STRING ValueString;
    HANDLE KeyHandle;
    BOOLEAN Result;
 
    /* So we know what to free at the end of the body */
    PartialInfo = NULL;
    KeyHandle = NULL;
    do
    {
        /* Open the key by name, rooted off the handle passed */
        Result = PciOpenKey(KeyName,
                            RootHandle,
                            KEY_QUERY_VALUE,
                            &KeyHandle,
                            &Status);
        if (!Result) break;
 
        /* Query for the size that's needed for the value that was passed in */
        RtlInitUnicodeString(&ValueString, ValueName);
        Status = ZwQueryValueKey(KeyHandle,
                                 &ValueString,
                                 KeyValuePartialInformation,
                                 NULL,
                                 0,
                                 &NeededLength);
        ASSERT(!NT_SUCCESS(Status));
        if (Status != STATUS_BUFFER_TOO_SMALL) break;
 
        /* Allocate an appropriate buffer for the size that was returned */
        ASSERT(NeededLength != 0);
        Status = STATUS_INSUFFICIENT_RESOURCES;
        PartialInfo = ExAllocatePoolWithTag(PagedPool,
                                            NeededLength,
                                            PCI_POOL_TAG);
        if (!PartialInfo) break;
 
        /* Query the actual value information now that the size is known */
        Status = ZwQueryValueKey(KeyHandle,
                                 &ValueString,
                                 KeyValuePartialInformation,
                                 PartialInfo,
                                 NeededLength,
                                 &ActualLength);
        if (!NT_SUCCESS(Status)) break;
 
        /* Make sure it's of the type that the caller expects */
        Status = STATUS_INVALID_PARAMETER;
        if (PartialInfo->Type != Type) break;
 
        ASSERT(NeededLength == ActualLength);
        NeededLength = PartialInfo->DataLength;
 
        /* Allocate a buffer to hold the data and return it to the caller */
        Status = STATUS_INSUFFICIENT_RESOURCES;
        *OutputBuffer = ExAllocatePoolWithTag(PagedPool,
                                              NeededLength,
                                              PCI_POOL_TAG);
        if (!*OutputBuffer) break;
 
        /* Copy the data into the buffer and return its length to the caller */
        RtlCopyMemory(*OutputBuffer, PartialInfo->Data, NeededLength);
        if (OutputLength) *OutputLength = NeededLength;
        Status = STATUS_SUCCESS;
    } while (0);
 
    /* Close any opened keys and free temporary allocations */
    if (KeyHandle) ZwClose(KeyHandle);
    if (PartialInfo) ExFreePoolWithTag(PartialInfo, 0);
    return Status;
}

Referenced by DriverEntry(), PciAcpiFindRsdt(), PciGetDebugPorts(), PciGetIrqRoutingTableFromRegistry(), and PciIsDatacenter().

◆ PciGetResizableBarCapability()

VOID NTAPI PciGetResizableBarCapability ( _Inout_ PPCI_PDO_EXTENSION PdoExtension )

Records which BARs of a new function can be resized and the sizes each of them supports.

Parameters

[in,out] PdoExtension The PDO extension of the function being enumerated.

Definition at line 31 of file rbar.c.

{
    PPCI_RESIZABLE_BAR_STATE State = &PdoExtension->ResizableBarState;
    PCI_EXPRESS_ENHANCED_CAPABILITY_HEADER Header;
    ULONG Offset, Entry, EntryCount, Control, SizeMask, BarIndex;
 
    PAGED_CODE();
 
    RtlZeroMemory(State, sizeof(*State));
 
    /* Bridges keep their windows after the first two BARs, so only endpoints are resized */
    if (PdoExtension->HeaderType != PCI_DEVICE_TYPE)
        return;
 
    Offset = PciReadDeviceExtendedCapability(PdoExtension,
                                             PCI_RBAR_EXTENDED_CAP_ID,
                                             &Header,
                                             sizeof(Header));
    if (!Offset)
        return;
 
    /* Only the first control register holds the number of entries */
    PciReadDeviceConfig(PdoExtension,
                        &Control,
                        Offset + PCI_RBAR_ENTRY_CONTROL(0),
                        sizeof(Control));
    EntryCount = (Control & PCI_RBAR_CONTROL_COUNT_MASK) >> PCI_RBAR_CONTROL_COUNT_SHIFT;
    if (EntryCount > PCI_RBAR_MAX_ENTRIES)
        EntryCount = PCI_RBAR_MAX_ENTRIES;
 
    State->CapabilityPtr = (USHORT)Offset;
 
    for (Entry = 0; Entry < EntryCount; Entry++)
    {
        PciReadDeviceConfig(PdoExtension,
                            &SizeMask,
                            Offset + PCI_RBAR_ENTRY_CAPABILITY(Entry),
                            sizeof(SizeMask));
        PciReadDeviceConfig(PdoExtension,
                            &Control,
                            Offset + PCI_RBAR_ENTRY_CONTROL(Entry),
                            sizeof(Control));
 
        SizeMask >>= PCI_RBAR_CAPABILITY_SIZES_SHIFT;
        BarIndex = Control & PCI_RBAR_CONTROL_BAR_INDEX_MASK;
 
        /* Skip entries with no sizes, a BAR that cannot exist, or a BAR already seen */
        if (!SizeMask ||
            (BarIndex >= PCI_RBAR_MAX_ENTRIES) ||
            State->SizeMask[BarIndex])
        {
            continue;
        }
 
        State->SizeMask[BarIndex] = SizeMask;
        State->EntryIndex[BarIndex] = (UCHAR)Entry;
 
        DPRINT1("PCIX - BAR %lu of %p is resizable, sizes 0x%08lx\n",
                BarIndex, PdoExtension, SizeMask);
    }
}

Referenced by PciGetEnhancedCapabilities().

◆ PciHookHal()

VOID NTAPI PciHookHal ( VOID )

Definition at line 319 of file hookhal.c.

{
    /* Save the old HAL routines */
    ASSERT(PcipSavedAssignSlotResources == NULL);
    ASSERT(PcipSavedTranslateBusAddress == NULL);
    PcipSavedAssignSlotResources = HalPciAssignSlotResources;
    PcipSavedTranslateBusAddress = HalPciTranslateBusAddress;
 
    /* Take over the HAL's Bus Handler functions */
    HalPciAssignSlotResources = PciAssignSlotResources;
    HalPciTranslateBusAddress = PciTranslateBusAddress;
}

Referenced by DriverEntry().

◆ PciInitializeArbiterRanges()

NTSTATUS NTAPI PciInitializeArbiterRanges	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PCM_RESOURCE_LIST	Resources
	)

Definition at line 447 of file arb_comn.c.

{
    PPCI_PDO_EXTENSION PdoExtension;
    PPCI_ARBITER_INSTANCE Instance;
    PCM_RESOURCE_LIST Ranges;
    PCI_SIGNATURE ArbiterType;
    NTSTATUS Status;
 
    /* Arbiters should not already be initialized */
    if (DeviceExtension->ArbitersInitialized)
    {
        /* Duplicated start request, fail initialization */
        DPRINT1("PCIX - Warning hot start FDOx %p, resource ranges not checked.\n", DeviceExtension);
        return STATUS_INVALID_DEVICE_REQUEST;
    }
 
    /* A root bus decodes the ranges it was started with */
    Ranges = Resources;
 
    /* Check for non-root FDO */
    if (!PCI_IS_ROOT_FDO(DeviceExtension))
    {
        /* Grab the PDO */
        PdoExtension = (PPCI_PDO_EXTENSION)DeviceExtension->PhysicalDeviceObject->DeviceExtension;
        ASSERT_PDO(PdoExtension);
 
        /* Check if this is a subtractive bus */
        if (PdoExtension->Dependent.type1.SubtractiveDecode)
        {
            /* There is nothing to do regarding arbitration of resources */
            DPRINT1("PCIX - Skipping arbiter initialization for subtractive bridge FDOX %p\n", DeviceExtension);
            return STATUS_SUCCESS;
        }
 
        /* The start resources hold the bridge's own BARs, the bus only gets what it forwards */
        Ranges = PciCollectForwardedRanges(PdoExtension);
        if (!Ranges)
            return STATUS_INSUFFICIENT_RESOURCES;
    }
 
    /* Loop the arbiters that hand out the ranges a bus decodes */
    for (ArbiterType = PciArb_Io; ArbiterType <= PciArb_Memory; ArbiterType++)
    {
        /* Find an arbiter of this type */
        Instance = (PVOID)PciFindNextSecondaryExtension(DeviceExtension->
                                                        SecondaryExtension.Next,
                                                        ArbiterType);
        if (Instance)
        {
            /* The decoded ranges bound what the arbiter may hand out */
            Status = Instance->CommonInstance.StartArbiter(&Instance->CommonInstance,
                                                           Ranges);
            if (!NT_SUCCESS(Status))
            {
                DPRINT1("PCIX - FDO ext 0x%p %s arbiter failed to start: %X\n",
                        DeviceExtension,
                        PciArbiterNames[ArbiterType - PciArb_Io],
                        Status);
                goto Exit;
            }
 
            /* An empty seed leaves everything open, but a bridge without the range forwards none */
            if (!PCI_IS_ROOT_FDO(DeviceExtension) &&
                !PciHasRangeOfType(Ranges, (UCHAR)Instance->CommonInstance.ResourceType))
            {
                ArbiterLibReserveRange(&Instance->CommonInstance,
                                       0,
                                       ARBITER_MAXIMUM_ADDRESS,
                                       NULL,
                                       FALSE);
            }
        }
        else
        {
            /* The arbiter was not found, this is an error! */
            DPRINT1("PCIX - FDO ext 0x%p %s arbiter (REQUIRED) is missing.\n",
                    DeviceExtension,
                    PciArbiterNames[ArbiterType - PciArb_Io]);
        }
    }
 
    /* Arbiters are now initialized */
    DeviceExtension->ArbitersInitialized = TRUE;
    Status = STATUS_SUCCESS;
 
Exit:
    if (Ranges != Resources)
        ExFreePoolWithTag(Ranges, PCI_POOL_TAG);
 
    return Status;
}

Referenced by PciFdoIrpStartDevice().

◆ PciInitializeArbiters()

NTSTATUS NTAPI PciInitializeArbiters ( IN PPCI_FDO_EXTENSION FdoExtension )

Definition at line 242 of file arb_comn.c.

{
    PPCI_INTERFACE CurrentInterface, *Interfaces;
    PPCI_PDO_EXTENSION PdoExtension;
    PPCI_ARBITER_INSTANCE ArbiterInterface;
    NTSTATUS Status;
    PCI_SIGNATURE ArbiterType;
    ASSERT_FDO(FdoExtension);
 
    /* A bus that ends up needing no arbiter at all is not a failure */
    Status = STATUS_SUCCESS;
 
    /* A subtractive bus has no arbiters of its own, requests fall through to the parent's */
    if (!PCI_IS_ROOT_FDO(FdoExtension))
    {
        /* Get the PDO extension */
        PdoExtension = FdoExtension->PhysicalDeviceObject->DeviceExtension;
        ASSERT_PDO(PdoExtension);
 
        if (PdoExtension->Dependent.type1.SubtractiveDecode)
        {
            DPRINT1("PCIX - Not creating arbiters for subtractive bus 0x%x\n",
                    FdoExtension->BaseBus);
            return STATUS_SUCCESS;
        }
    }
 
    /* Loop all the arbiters */
    for (ArbiterType = PciArb_Io; ArbiterType <= PciArb_BusNumber; ArbiterType++)
    {
        /* Query all the registered arbiter interfaces */
        Interfaces = PciInterfaces;
        while (*Interfaces)
        {
            /* Find the one that matches the arbiter currently being setup */
            CurrentInterface = *Interfaces;
            if (CurrentInterface->Signature == ArbiterType) break;
            Interfaces++;
        }
 
        /* Check if the required arbiter was not found in the list */
        if (!*Interfaces)
        {
            /* Skip this arbiter and try the next one */
            DPRINT1("PCIX - FDO ext 0x%p no %s arbiter.\n",
                    FdoExtension,
                    PciArbiterNames[ArbiterType - PciArb_Io]);
            continue;
        }
 
        /* An arbiter was found, allocate an instance for it */
        Status = STATUS_INSUFFICIENT_RESOURCES;
        ArbiterInterface = ExAllocatePoolWithTag(PagedPool,
                                                 sizeof(PCI_ARBITER_INSTANCE),
                                                 PCI_POOL_TAG);
        if (!ArbiterInterface) break;
 
        /* Setup the instance */
        ArbiterInterface->BusFdoExtension = FdoExtension;
        ArbiterInterface->Interface = CurrentInterface;
        _swprintf(ArbiterInterface->InstanceName,
                  L"PCI %S (b=%02x)",
                  PciArbiterNames[ArbiterType - PciArb_Io],
                  FdoExtension->BaseBus);
 
        /* Call the interface initializer for it */
        Status = CurrentInterface->Initializer(ArbiterInterface);
        if (!NT_SUCCESS(Status)) break;
 
        /* Link it with this FDO */
        PcipLinkSecondaryExtension(&FdoExtension->SecondaryExtension,
                                   &FdoExtension->SecondaryExtLock,
                                   &ArbiterInterface->Header,
                                   ArbiterType,
                                   PciArbiterDestructor);
 
        /* This arbiter is now initialized, move to the next one */
        DPRINT1("PCIX - FDO ext 0x%p %S arbiter initialized (context 0x%p).\n",
                FdoExtension,
                L"ARBITER HEADER MISSING", //ArbiterInterface->CommonInstance.Name,
                ArbiterInterface);
        Status = STATUS_SUCCESS;
    }
 
    /* Return to caller */
    return Status;
}

Referenced by PciAddDevice().

◆ PciInitializeEcam()

VOID NTAPI PciInitializeEcam ( _In_ PPCI_FDO_EXTENSION FdoExtension )

Maps the bus an FDO decodes into the ECAM window and verifies the window the first time a bus with devices on it is seen.

Parameters

[in] FdoExtension The FDO extension of the bus being started.

Definition at line 336 of file ecam.c.

{
    NTSTATUS Status;
    PAGED_CODE();
 
    if (!PciEcamWindowQueried)
    {
        PciEcamWindowQueried = TRUE;
 
        Status = PciEcamQueryWindow();
        if (!NT_SUCCESS(Status))
        {
            DPRINT1("PCIX - No ECAM window available (0x%lx)\n", Status);
            return;
        }
 
#if defined(_M_IX86) || defined(_M_AMD64)
        PciEcamSkipK8Northbridge = PciEcamIsAmdK8();
#endif
        DPRINT1("PCIX - ECAM window at 0x%I64x for 0x%lx buses\n",
                PciEcamWindowStart,
                PciEcamWindowBuses);
    }
 
    if (!PciEcamMapBus(FdoExtension->BaseBus) || PciEcamVerified) return;
 
    /* An empty bus proves nothing, so leave it to the next one */
    Status = PciEcamVerifyBus(FdoExtension);
    if (Status == STATUS_DEVICE_CONFIGURATION_ERROR)
    {
        PciEcamDiscardWindow();
    }
    else if (NT_SUCCESS(Status))
    {
        PciEcamVerified = TRUE;
        DPRINT1("PCIX - ECAM verified on bus 0x%lx\n", FdoExtension->BaseBus);
    }
}

Referenced by PciAddDevice().

◆ PciInitializeState()

VOID NTAPI PciInitializeState ( IN PPCI_FDO_EXTENSION DeviceExtension )

Definition at line 88 of file state.c.

{
    /* Set the initial state */
    DeviceExtension->DeviceState = PciNotStarted;
    DeviceExtension->TentativeNextState = PciNotStarted;
}

Referenced by PciInitializeFdoExtensionCommonFields(), and PciPdoCreate().

◆ PciInsertEntryAtTail()

VOID NTAPI PciInsertEntryAtTail	(	IN PSINGLE_LIST_ENTRY	ListHead,
		IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PKEVENT	Lock
	)

Definition at line 400 of file utils.c.

{
    PSINGLE_LIST_ENTRY NextEntry;
    PAGED_CODE();
 
    /* Check if a lock was specified */
    if (Lock)
    {
        /* Wait for the lock to be released */
        KeEnterCriticalRegion();
        KeWaitForSingleObject(Lock, Executive, KernelMode, FALSE, NULL);
    }
 
    /* Loop the list until we get to the end, then insert this entry there */
    for (NextEntry = ListHead; NextEntry->Next; NextEntry = NextEntry->Next);
    NextEntry->Next = &DeviceExtension->List;
 
    /* Check if we had acquired a lock previously */
    if (Lock)
    {
        /* Release it */
        KeSetEvent(Lock, IO_NO_INCREMENT, FALSE);
        KeLeaveCriticalRegion();
    }
}

Referenced by PciAddDevice(), and PciPdoCreate().

◆ PciIrpInvalidDeviceRequest()

NTSTATUS NTAPI PciIrpInvalidDeviceRequest	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 277 of file dispatch.c.

{
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
    UNREFERENCED_PARAMETER(DeviceExtension);
 
    /* Not supported */
    return STATUS_INVALID_DEVICE_REQUEST;
}

◆ PciIrpNotSupported()

NTSTATUS NTAPI PciIrpNotSupported	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_FDO_EXTENSION	DeviceExtension
	)

Definition at line 261 of file dispatch.c.

{
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
    UNREFERENCED_PARAMETER(DeviceExtension);
 
    /* Not supported */
    DPRINT1("PCIX - Received unsupported IRP!\n");
    //DbgBreakPoint();
    return STATUS_NOT_SUPPORTED;
}

◆ PciIsCriticalDeviceClass()

BOOLEAN NTAPI PciIsCriticalDeviceClass	(	IN UCHAR	BaseClass,
		IN UCHAR	SubClass
	)

Definition at line 672 of file utils.c.

{
    /* Check for system or bridge devices */
    if (BaseClass == PCI_CLASS_BASE_SYSTEM_DEV)
    {
        /* Interrupt controllers are critical */
        return SubClass == PCI_SUBCLASS_SYS_INTERRUPT_CTLR;
    }
    else if (BaseClass == PCI_CLASS_BRIDGE_DEV)
    {
        /* ISA Bridges are critical */
        return SubClass == PCI_SUBCLASS_BR_ISA;
    }
    else
    {
        /* All display controllers are critical */
        return BaseClass == PCI_CLASS_DISPLAY_CTLR;
    }
}

Referenced by PciScanBus().

◆ PciIsDatacenter()

BOOLEAN NTAPI PciIsDatacenter ( VOID )

Definition at line 132 of file utils.c.

{
    BOOLEAN Result;
    PVOID Value;
    ULONG ResultLength;
    NTSTATUS Status;
 
    /* Assume this isn't Datacenter */
    Result = FALSE;
 
    /* First, try opening the setup key */
    Status = PciGetRegistryValue(L"",
                                 L"\\REGISTRY\\MACHINE\\SYSTEM\\CurrentControlSet\\Services\\setupdd",
                                 0,
                                 REG_BINARY,
                                 &Value,
                                 &ResultLength);
    if (!NT_SUCCESS(Status))
    {
        /* This is not an in-progress Setup boot, so query the suite version */
        Result = PciIsSuiteVersion(VER_SUITE_DATACENTER);
    }
    else
    {
        /* This scenario shouldn't happen yet, since SetupDD isn't used */
        UNIMPLEMENTED_FATAL("ReactOS doesn't use SetupDD for its installation program. Therefore this scenario must not happen!\n");
    }
 
    /* Return if this is Datacenter or not */
    return Result;
}

Referenced by DriverEntry().

◆ PciIsDeviceOnDebugPath()

BOOLEAN NTAPI PciIsDeviceOnDebugPath ( IN PPCI_PDO_EXTENSION DeviceExtension )

Referenced by PciScanBus().

◆ PciIsRequirementDescriptor()

BOOLEAN NTAPI PciIsRequirementDescriptor ( _In_ PIO_RESOURCE_DESCRIPTOR Limit )

Tells whether a discovered limit asks the arbiter for a range.

Parameters

[in] Limit The limit of one BAR or bridge window.

Returns: TRUE when the limit has a type and a length. A bridge window has no length of its own.

Definition at line 671 of file enum.c.

{
    if (Limit->Type == CmResourceTypeNull)
        return FALSE;
 
    return (Limit->u.Generic.Length != 0);
}

Referenced by Device_ChangeResourceSettings(), PciBuildRequirementsList(), and PciComputeNewCurrentSettings().

◆ PciIsSlotPresentInParentMethod()

BOOLEAN NTAPI PciIsSlotPresentInParentMethod	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN ULONG	Method
	)

Definition at line 1169 of file utils.c.

{
    BOOLEAN FoundSlot;
    PACPI_METHOD_ARGUMENT Argument;
    ACPI_EVAL_INPUT_BUFFER InputBuffer;
    PACPI_EVAL_OUTPUT_BUFFER OutputBuffer;
    ULONG i, Length;
    NTSTATUS Status;
    PAGED_CODE();
 
    /* Assume slot is not part of the parent method */
    FoundSlot = FALSE;
 
    /* Allocate a 2KB buffer for the method return parameters */
    Length = sizeof(ACPI_EVAL_OUTPUT_BUFFER) + 2048;
    OutputBuffer = ExAllocatePoolWithTag(PagedPool, Length, 'BicP');
    if (OutputBuffer)
    {
        /* Clear out the output buffer */
        RtlZeroMemory(OutputBuffer, Length);
 
        /* Initialize the input buffer with the method requested */
        InputBuffer.Signature = 0;
        *(PULONG)InputBuffer.MethodName = Method;
        InputBuffer.Signature = ACPI_EVAL_INPUT_BUFFER_SIGNATURE;
 
        /* Send it to the ACPI driver */
        Status = PciSendIoctl(PdoExtension->ParentFdoExtension->PhysicalDeviceObject,
                              IOCTL_ACPI_EVAL_METHOD,
                              &InputBuffer,
                              sizeof(ACPI_EVAL_INPUT_BUFFER),
                              OutputBuffer,
                              Length);
        if (NT_SUCCESS(Status))
        {
            /* Scan all output arguments */
            for (i = 0; i < OutputBuffer->Count; i++)
            {
                /* Make sure it's an integer */
                Argument = &OutputBuffer->Argument[i];
                if (Argument->Type != ACPI_METHOD_ARGUMENT_INTEGER) continue;
 
                /* Check if the argument matches this PCI slot structure */
                if (Argument->Argument == ((PdoExtension->Slot.u.bits.DeviceNumber) |
                                           ((PdoExtension->Slot.u.bits.FunctionNumber) << 16)))
                {
                    /* This slot has been found, return it */
                    FoundSlot = TRUE;
                    break;
                }
            }
        }
 
        /* Finished with the buffer, free it */
        ExFreePoolWithTag(OutputBuffer, 0);
    }
 
    /* Return if the slot was found */
    return FoundSlot;
}

Referenced by PciApplyHacks(), and PciBridgeIsPositiveDecode().

◆ PciOpenKey()

BOOLEAN NTAPI PciOpenKey	(	IN PWCHAR	KeyName,
		IN HANDLE	RootKey,
		IN ACCESS_MASK	DesiredAccess,
		OUT PHANDLE	KeyHandle,
		OUT PNTSTATUS	KeyStatus
	)

Definition at line 166 of file utils.c.

{
    NTSTATUS Status;
    OBJECT_ATTRIBUTES ObjectAttributes;
    UNICODE_STRING KeyString;
    PAGED_CODE();
 
    /* Initialize the object attributes */
    RtlInitUnicodeString(&KeyString, KeyName);
    InitializeObjectAttributes(&ObjectAttributes,
                               &KeyString,
                               OBJ_CASE_INSENSITIVE | OBJ_KERNEL_HANDLE,
                               RootKey,
                               NULL);
 
    /* Open the key, returning a boolean, and the status, if requested */
    Status = ZwOpenKey(KeyHandle, DesiredAccess, &ObjectAttributes);
    if (KeyStatus) *KeyStatus = Status;
    return NT_SUCCESS(Status);
}

Referenced by DriverEntry(), PciAcpiFindRsdt(), PciEcamQueryWindow(), PciGetIrqRoutingTableFromRegistry(), and PciGetRegistryValue().

◆ PciPassIrpFromFdoToPdo()

NTSTATUS NTAPI PciPassIrpFromFdoToPdo	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PIRP	Irp
	)

Definition at line 70 of file dispatch.c.

{
    PIO_STACK_LOCATION IoStackLocation;
    NTSTATUS Status;
    DPRINT("PCIX - PassIrp ...\n");
 
    /* Get the stack location to check which function this is */
    IoStackLocation = IoGetCurrentIrpStackLocation(Irp);
    if (IoStackLocation->MajorFunction == IRP_MJ_POWER)
    {
        /* Power IRPs are special since we have to notify the Power Manager */
        IoCopyCurrentIrpStackLocationToNext(Irp);
        PoStartNextPowerIrp(Irp);
        Status = PoCallDriver(DeviceExtension->AttachedDeviceObject, Irp);
    }
    else
    {
        /* For a normal IRP, just call the next driver in the stack */
        IoSkipCurrentIrpStackLocation(Irp);
        Status = IoCallDriver(DeviceExtension->AttachedDeviceObject, Irp);
    }
 
    /* Return the status back to the caller */
    return Status;
}

Referenced by PciDispatchIrp(), PciFdoIrpQueryInterface(), PciFdoIrpRemoveDevice(), and PciFdoWaitWake().

◆ PciPdoCreate()

NTSTATUS NTAPI PciPdoCreate	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PCI_SLOT_NUMBER	Slot,
		OUT PDEVICE_OBJECT *	PdoDeviceObject
	)

Definition at line 1022 of file pdo.c.

{
    WCHAR DeviceName[32];
    UNICODE_STRING DeviceString;
    NTSTATUS Status;
    PDEVICE_OBJECT DeviceObject;
    PPCI_PDO_EXTENSION PdoExtension;
    ULONG SequenceNumber;
    PAGED_CODE();
 
    /* Pick an atomically unique sequence number for this device */
    SequenceNumber = InterlockedIncrement(&PciPdoSequenceNumber);
 
    /* Create the standard PCI device name for a PDO */
    _swprintf(DeviceName, L"\\Device\\NTPNP_PCI%04d", SequenceNumber);
    RtlInitUnicodeString(&DeviceString, DeviceName);
 
    /* Create the actual device now */
    Status = IoCreateDevice(DeviceExtension->FunctionalDeviceObject->DriverObject,
                            sizeof(PCI_PDO_EXTENSION),
                            &DeviceString,
                            FILE_DEVICE_BUS_EXTENDER,
                            0,
                            0,
                            &DeviceObject);
    ASSERT(NT_SUCCESS(Status));
 
    /* Get the extension for it */
    PdoExtension = (PPCI_PDO_EXTENSION)DeviceObject->DeviceExtension;
    DPRINT1("PCIX - New PDO (b=0x%x, d=0x%x, f=0x%x) @ %p, ext @ %p\n",
            DeviceExtension->BaseBus,
            Slot.u.bits.DeviceNumber,
            Slot.u.bits.FunctionNumber,
            DeviceObject,
            DeviceObject->DeviceExtension);
 
    /* Configure the extension */
    PdoExtension->ExtensionType = PciPdoExtensionType;
    PdoExtension->IrpDispatchTable = &PciPdoDispatchTable;
    PdoExtension->PhysicalDeviceObject = DeviceObject;
    PdoExtension->Slot = Slot;
    PdoExtension->PowerState.CurrentSystemState = PowerSystemWorking;
    PdoExtension->PowerState.CurrentDeviceState = PowerDeviceD0;
    PdoExtension->ParentFdoExtension = DeviceExtension;
 
    /* Initialize the lock for arbiters and other interfaces */
    KeInitializeEvent(&PdoExtension->SecondaryExtLock, SynchronizationEvent, TRUE);
 
    /* Initialize the state machine */
    PciInitializeState((PPCI_FDO_EXTENSION)PdoExtension);
 
    /* Add the PDO to the parent's list */
    PdoExtension->Next = NULL;
    PciInsertEntryAtTail((PSINGLE_LIST_ENTRY)&DeviceExtension->ChildPdoList,
                         (PPCI_FDO_EXTENSION)PdoExtension,
                         &DeviceExtension->ChildListLock);
 
    /* And finally return it to the caller */
    *PdoDeviceObject = DeviceObject;
    return STATUS_SUCCESS;
}

Referenced by PciScanBus().

◆ PciPdoIrpCancelRemoveDevice()

NTSTATUS NTAPI PciPdoIrpCancelRemoveDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 597 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* The remove is off, so the device stays where it was */
    PciCancelStateTransition((PVOID)DeviceExtension, PciNotStarted);
    return STATUS_SUCCESS;
}

◆ PciPdoIrpCancelStopDevice()

NTSTATUS NTAPI PciPdoIrpCancelStopDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 655 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* The stop is off, so the device keeps what it has */
    PciCancelStateTransition((PVOID)DeviceExtension, PciStopped);
    return STATUS_SUCCESS;
}

◆ PciPdoIrpDeviceUsageNotification()

NTSTATUS NTAPI PciPdoIrpDeviceUsageNotification	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 956 of file pdo.c.

{
    NTSTATUS Status;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
 
    /* Every bus up to the root has to hold on to the path, so it goes up first */
    Status = PciSendDeviceUsageToParent(DeviceExtension->ParentFdoExtension,
                                        IoStackLocation);
    if (!NT_SUCCESS(Status))
        return Status;
 
    return PciUpdateDeviceUsage(&DeviceExtension->PowerState, IoStackLocation);
}

◆ PciPdoIrpQueryBusInformation()

NTSTATUS NTAPI PciPdoIrpQueryBusInformation	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 809 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Call the worker function */
    return PciQueryBusInformation(DeviceExtension,
                                  (PPNP_BUS_INFORMATION*)&Irp->
                                  IoStatus.Information);
}

◆ PciPdoIrpQueryCapabilities()

NTSTATUS NTAPI PciPdoIrpQueryCapabilities	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 731 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
 
    /* Call the worker function */
    return PciQueryCapabilities(DeviceExtension,
                                IoStackLocation->
                                Parameters.DeviceCapabilities.Capabilities);
}

◆ PciPdoIrpQueryDeviceRelations()

NTSTATUS NTAPI PciPdoIrpQueryDeviceRelations	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 697 of file pdo.c.

{
    NTSTATUS Status;
    PAGED_CODE();
 
    /* Are ejection relations being queried? */
    if (IoStackLocation->Parameters.QueryDeviceRelations.Type == EjectionRelations)
    {
        /* Call the worker function */
        Status = PciQueryEjectionRelations(DeviceExtension,
                                           (PDEVICE_RELATIONS*)&Irp->
                                           IoStatus.Information);
    }
    else if (IoStackLocation->Parameters.QueryDeviceRelations.Type == TargetDeviceRelation)
    {
        /* The only other relation supported is the target device relation */
        Status = PciQueryTargetDeviceRelations(DeviceExtension,
                                               (PDEVICE_RELATIONS*)&Irp->
                                               IoStatus.Information);
    }
    else
    {
        /* All other relations are unsupported */
        Status = STATUS_NOT_SUPPORTED;
    }
 
    /* Return either the result of the worker function, or unsupported status */
    return Status;
}

◆ PciPdoIrpQueryDeviceState()

NTSTATUS NTAPI PciPdoIrpQueryDeviceState	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 930 of file pdo.c.

{
    PNP_DEVICE_STATE State;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Whatever the rest of the stack decided about this device still holds */
    State = (PNP_DEVICE_STATE)Irp->IoStatus.Information;
 
    /* Host bridges, and anything a query remove would refuse, must not be offered for disabling */
    if (((DeviceExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
         (DeviceExtension->SubClass == PCI_SUBCLASS_BR_HOST)) ||
        (!NT_SUCCESS(PciPdoValidateRelease(DeviceExtension))))
    {
        State |= PNP_DEVICE_NOT_DISABLEABLE;
    }
 
    Irp->IoStatus.Information = State;
    return STATUS_SUCCESS;
}

◆ PciPdoIrpQueryDeviceText()

NTSTATUS NTAPI PciPdoIrpQueryDeviceText	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 778 of file pdo.c.

{
    PAGED_CODE();
 
    /* Call the worker function */
    return PciQueryDeviceText(DeviceExtension,
                              IoStackLocation->
                              Parameters.QueryDeviceText.DeviceTextType,
                              IoStackLocation->
                              Parameters.QueryDeviceText.LocaleId,
                              (PWCHAR*)&Irp->IoStatus.Information);
}

◆ PciPdoIrpQueryId()

NTSTATUS NTAPI PciPdoIrpQueryId	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 795 of file pdo.c.

{
    PAGED_CODE();
 
    /* Call the worker function */
    return PciQueryId(DeviceExtension,
                      IoStackLocation->Parameters.QueryId.IdType,
                      (PWCHAR*)&Irp->IoStatus.Information);
}

◆ PciPdoIrpQueryInterface()

NTSTATUS NTAPI PciPdoIrpQueryInterface	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 671 of file pdo.c.

{
    NTSTATUS Status;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
 
    /* Query the interface from the PCI driver */
    Status = PciQueryInterface(
                (PPCI_FDO_EXTENSION)DeviceExtension,
                IoStackLocation->Parameters.QueryInterface.InterfaceType,
                IoStackLocation->Parameters.QueryInterface.Size,
                IoStackLocation->Parameters.QueryInterface.Version,
                IoStackLocation->Parameters.QueryInterface.InterfaceSpecificData,
                IoStackLocation->Parameters.QueryInterface.Interface,
                FALSE);
 
    /* TODO: There's more to this story, but NOT TODAY! */
 
    return Status;
}

◆ PciPdoIrpQueryLegacyBusInformation()

NTSTATUS NTAPI PciPdoIrpQueryLegacyBusInformation	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 1006 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
    UNREFERENCED_PARAMETER(DeviceExtension);
 
    /* A bridge's FDO answers above this, so keep its bus number and buffer intact */
    return STATUS_NOT_SUPPORTED;
}

◆ PciPdoIrpQueryPower()

NTSTATUS NTAPI PciPdoIrpQueryPower	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 144 of file pdo.c.

{
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
    UNREFERENCED_PARAMETER(DeviceExtension);
 
    /* Every device state is accepted when set, so none is refused here */
    return STATUS_SUCCESS;
}

◆ PciPdoIrpQueryRemoveDevice()

NTSTATUS NTAPI PciPdoIrpQueryRemoveDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 534 of file pdo.c.

{
    NTSTATUS Status;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    if (DeviceExtension->HackFlags & PCI_HACK_FAIL_QUERY_REMOVE)
        return STATUS_DEVICE_BUSY;
 
    Status = PciPdoValidateRelease(DeviceExtension);
    if (!NT_SUCCESS(Status))
        return Status;
 
    /* A function that was never started has no state to leave */
    if (DeviceExtension->DeviceState == PciNotStarted)
        return STATUS_SUCCESS;
 
    return PciBeginStateTransition((PVOID)DeviceExtension, PciNotStarted);
}

◆ PciPdoIrpQueryResourceRequirements()

NTSTATUS NTAPI PciPdoIrpQueryResourceRequirements	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 762 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Call the worker function */
    return PciQueryRequirements(DeviceExtension,
                                (PIO_RESOURCE_REQUIREMENTS_LIST*)&Irp->
                                IoStatus.Information);
}

◆ PciPdoIrpQueryResources()

NTSTATUS NTAPI PciPdoIrpQueryResources	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 747 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* Call the worker function */
    return PciQueryResources(DeviceExtension,
                            (PCM_RESOURCE_LIST*)&Irp->IoStatus.Information);
}

◆ PciPdoIrpQueryStopDevice()

NTSTATUS NTAPI PciPdoIrpQueryStopDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 632 of file pdo.c.

{
    NTSTATUS Status;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    Status = PciPdoValidateRelease(DeviceExtension);
    if (!NT_SUCCESS(Status))
        return Status;
 
    /* New resources are useless if the old ranges keep decoding */
    if (!PciPdoCanTurnOff(DeviceExtension))
        return STATUS_INVALID_DEVICE_REQUEST;
 
    return PciBeginStateTransition((PVOID)DeviceExtension, PciStopped);
}

◆ PciPdoIrpReadConfig()

NTSTATUS NTAPI PciPdoIrpReadConfig	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 908 of file pdo.c.

{
    PAGED_CODE();
 
    return PciPdoReadWriteConfig(Irp, IoStackLocation, DeviceExtension, TRUE);
}

◆ PciPdoIrpRemoveDevice()

NTSTATUS NTAPI PciPdoIrpRemoveDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 560 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    if (PciPdoIsPresent(DeviceExtension))
        PciPdoTurnOff(DeviceExtension, TRUE);
 
    /* A remove without a query still has to take a started function out of that state */
    if ((DeviceExtension->DeviceState == PciStarted) &&
        (DeviceExtension->TentativeNextState == PciStarted))
    {
        PciBeginStateTransition((PVOID)DeviceExtension, PciNotStarted);
    }
 
    if ((DeviceExtension->DeviceState != PciNotStarted) &&
        (DeviceExtension->TentativeNextState == PciNotStarted))
    {
        PciCommitStateTransition((PVOID)DeviceExtension, PciNotStarted);
    }
 
    /* A function that left the bus will not come back through this PDO */
    if ((DeviceExtension->ReportedMissing) &&
        (NT_SUCCESS(PciBeginStateTransition((PVOID)DeviceExtension, PciDeleted))))
    {
        PciCommitStateTransition((PVOID)DeviceExtension, PciDeleted);
    }
 
    return STATUS_SUCCESS;
}

◆ PciPdoIrpStartDevice()

NTSTATUS NTAPI PciPdoIrpStartDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 158 of file pdo.c.

{
    NTSTATUS Status;
    BOOLEAN Changed, DoReset;
    POWER_STATE PowerState;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
 
    DoReset = FALSE;
 
    /* Begin entering the start phase */
    Status = PciBeginStateTransition((PVOID)DeviceExtension, PciStarted);
    if (!NT_SUCCESS(Status)) return Status;
 
    /* Check if this is a VGA device */
    if (((DeviceExtension->BaseClass == PCI_CLASS_PRE_20) &&
         (DeviceExtension->SubClass == PCI_SUBCLASS_PRE_20_VGA)) ||
        ((DeviceExtension->BaseClass == PCI_CLASS_DISPLAY_CTLR) &&
         (DeviceExtension->SubClass == PCI_SUBCLASS_VID_VGA_CTLR)))
    {
        /* Always force it on */
        DeviceExtension->CommandEnables |= (PCI_ENABLE_IO_SPACE |
                                            PCI_ENABLE_MEMORY_SPACE);
    }
 
    /* Check if native IDE is enabled and it owns the I/O ports */
    if (DeviceExtension->IoSpaceUnderNativeIdeControl)
    {
        /* Then don't allow I/O access */
        DeviceExtension->CommandEnables &= ~PCI_ENABLE_IO_SPACE;
    }
 
    /* Always enable bus mastering */
    DeviceExtension->CommandEnables |= PCI_ENABLE_BUS_MASTER;
 
    /* Check if the OS assigned resources differ from the PCI configuration */
    Changed = PciComputeNewCurrentSettings(DeviceExtension,
                                           IoStackLocation->Parameters.
                                           StartDevice.AllocatedResources);
    if (Changed)
    {
        /* Remember this for later */
        DeviceExtension->MovedDevice = TRUE;
    }
    else
    {
        /* All good */
        DPRINT1("PCIX - START not changing resource settings.\n");
    }
 
    /* Check if the device was sleeping */
    if (DeviceExtension->PowerState.CurrentDeviceState != PowerDeviceD0)
    {
        /* Power it up */
        Status = PciSetPowerManagedDevicePowerState(DeviceExtension,
                                                    PowerDeviceD0,
                                                    FALSE);
        if (!NT_SUCCESS(Status))
        {
            /* Powerup fail, fail the request */
            PciCancelStateTransition((PVOID)DeviceExtension, PciStarted);
            return STATUS_DEVICE_POWER_FAILURE;
        }
 
        /* Tell the power manager that the device is powered up */
        PowerState.DeviceState = PowerDeviceD0;
        PoSetPowerState(DeviceExtension->PhysicalDeviceObject,
                        DevicePowerState,
                        PowerState);
 
        /* Update internal state */
        DeviceExtension->PowerState.CurrentDeviceState = PowerDeviceD0;
 
        /* This device's resources and decodes will need to be reset */
        DoReset = TRUE;
    }
 
    /* Update resource information now that the device is powered up and active */
    Status = PciSetResources(DeviceExtension, DoReset, TRUE);
    if (!NT_SUCCESS(Status))
    {
        /* That failed, so cancel the transition */
        PciCancelStateTransition((PVOID)DeviceExtension, PciStarted);
    }
    else
    {
        /* Fully commit, as the device is now started up and ready to go */
        PciCommitStateTransition((PVOID)DeviceExtension, PciStarted);
    }
 
    /* Return the result of the start request */
    return Status;
}

◆ PciPdoIrpStopDevice()

NTSTATUS NTAPI PciPdoIrpStopDevice	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 613 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* The device is losing its resources, so it must stop using them first */
    PciPdoTurnOff(DeviceExtension, FALSE);
 
    /* The query stop that has to come first already began the transition */
    PciCommitStateTransition((PVOID)DeviceExtension, PciStopped);
    return STATUS_SUCCESS;
}

◆ PciPdoIrpSurpriseRemoval()

NTSTATUS NTAPI PciPdoIrpSurpriseRemoval	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 976 of file pdo.c.

{
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Irp);
    UNREFERENCED_PARAMETER(IoStackLocation);
 
    /* This also comes after a failed start, with the function still in its slot */
    if (PciPdoIsPresent(DeviceExtension))
        PciPdoTurnOff(DeviceExtension, TRUE);
 
    if (DeviceExtension->ReportedMissing)
    {
        /* The slot is empty, so only the remove is left to come */
        if (NT_SUCCESS(PciBeginStateTransition((PVOID)DeviceExtension, PciSurpriseRemoved)))
            PciCommitStateTransition((PVOID)DeviceExtension, PciSurpriseRemoved);
    }
    else if (DeviceExtension->DeviceState != PciNotStarted)
    {
        /* The remove that follows commits this */
        PciBeginStateTransition((PVOID)DeviceExtension, PciNotStarted);
    }
 
    return STATUS_SUCCESS;
}

◆ PciPdoIrpWriteConfig()

NTSTATUS NTAPI PciPdoIrpWriteConfig	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 919 of file pdo.c.

{
    PAGED_CODE();
 
    return PciPdoReadWriteConfig(Irp, IoStackLocation, DeviceExtension, FALSE);
}

◆ PciPdoSetPowerState()

NTSTATUS NTAPI PciPdoSetPowerState	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 104 of file pdo.c.

{
    POWER_STATE State = IoStackLocation->Parameters.Power.State;
    PIO_WORKITEM WorkItem;
 
    /* The function driver follows a system state with a device state request of its own */
    if (IoStackLocation->Parameters.Power.Type == SystemPowerState)
    {
        DeviceExtension->PowerState.CurrentSystemState = State.SystemState;
        return STATUS_SUCCESS;
    }
 
    if ((State.DeviceState < PowerDeviceD0) || (State.DeviceState > PowerDeviceD3))
        return STATUS_INVALID_PARAMETER;
 
    if (State.DeviceState == DeviceExtension->PowerState.CurrentDeviceState)
        return STATUS_SUCCESS;
 
    /* Configuration cycles cannot reach a function on a bus that is not running */
    if (DeviceExtension->ParentFdoExtension->DeviceState != PciStarted)
        return STATUS_NO_SUCH_DEVICE;
 
    if (KeGetCurrentIrql() < DISPATCH_LEVEL)
        return PciPdoEnterDevicePowerState(DeviceExtension, State.DeviceState);
 
    /* D0 may be sent at DISPATCH_LEVEL, and reprogramming the function needs PASSIVE_LEVEL */
    WorkItem = IoAllocateWorkItem(DeviceExtension->PhysicalDeviceObject);
    if (!WorkItem)
        return STATUS_INSUFFICIENT_RESOURCES;
 
    Irp->Tail.Overlay.DriverContext[0] = WorkItem;
    IoMarkIrpPending(Irp);
    IoQueueWorkItem(WorkItem, PciPdoDevicePowerWorker, DelayedWorkQueue, Irp);
    return STATUS_PENDING;
}

◆ PciPdoWaitWake()

NTSTATUS NTAPI PciPdoWaitWake	(	IN PIRP	Irp,
		IN PIO_STACK_LOCATION	IoStackLocation,
		IN PPCI_PDO_EXTENSION	DeviceExtension
	)

Definition at line 88 of file pdo.c.

{
    UNREFERENCED_PARAMETER(IoStackLocation);
    UNREFERENCED_PARAMETER(DeviceExtension);
 
    /* PME is never armed, so the function cannot wake the system */
    Irp->IoStatus.Status = STATUS_NOT_SUPPORTED;
    PoStartNextPowerIrp(Irp);
    IoCompleteRequest(Irp, IO_NO_INCREMENT);
    return STATUS_NOT_SUPPORTED;
}

◆ PcipIsSameDevice()

BOOLEAN NTAPI PcipIsSameDevice	(	_In_ PPCI_PDO_EXTENSION	DeviceExtension,
		_In_ PPCI_COMMON_HEADER	PciData
	)

◆ PcipLinkSecondaryExtension()

VOID NTAPI PcipLinkSecondaryExtension	(	IN PSINGLE_LIST_ENTRY	List,
		IN PVOID	Lock,
		IN PPCI_SECONDARY_EXTENSION	SecondaryExtension,
		IN PCI_SIGNATURE	ExtensionType,
		IN PVOID	Destructor
	)

Definition at line 459 of file utils.c.

{
    PAGED_CODE();
 
    /* Setup the extension data, and insert it into the primary's list */
    SecondaryExtension->ExtensionType = ExtensionType;
    SecondaryExtension->Destructor = Destructor;
    PciInsertEntryAtHead(List, &SecondaryExtension->List, Lock);
}

Referenced by PciInitializeArbiters().

◆ PciPmeInterfaceConstructor()

NTSTATUS NTAPI PciPmeInterfaceConstructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 74 of file pmeintf.c.

{
    PPCI_PME_INTERFACE PmeInterface;
 
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Version);
 
    PAGED_CODE();
 
    if (Size < sizeof(PCI_PME_INTERFACE))
    {
        return STATUS_UNSUCCESSFUL;
    }
 
    PmeInterface = (PPCI_PME_INTERFACE)Interface;
    PmeInterface->Size = sizeof(*PmeInterface);
    PmeInterface->Version = PCI_PME_INTRF_STANDARD_VER;
    PmeInterface->Context = DeviceExtension;
    PmeInterface->InterfaceReference = PciPmeInterface_Reference;
    PmeInterface->InterfaceDereference = PciPmeInterface_Dereference;
    PmeInterface->UpdateEnable = PciPmeInterface_UpdateEnable;
 
    return STATUS_SUCCESS;
}

◆ PciPmeInterfaceInitializer()

NTSTATUS NTAPI PciPmeInterfaceInitializer ( IN PVOID Instance )

Definition at line 35 of file pmeintf.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI PciPmeInterfaceInitializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ PciQueryBusInformation()

NTSTATUS NTAPI PciQueryBusInformation	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		OUT PPNP_BUS_INFORMATION *	Buffer
	)

Definition at line 1408 of file utils.c.

{
    PPNP_BUS_INFORMATION BusInfo;
 
    /* Allocate a structure for the bus information */
    BusInfo = ExAllocatePoolWithTag(PagedPool,
                                    sizeof(PNP_BUS_INFORMATION),
                                    'BicP');
    if (!BusInfo) return STATUS_INSUFFICIENT_RESOURCES;
 
    /* Write the correct GUID and bus type identifier, and fill the bus number */
    BusInfo->BusTypeGuid = GUID_BUS_TYPE_PCI;
    BusInfo->LegacyBusType = PCIBus;
    BusInfo->BusNumber = PdoExtension->ParentFdoExtension->BaseBus;
 
    *Buffer = BusInfo;
 
    return STATUS_SUCCESS;
}

Referenced by PciPdoIrpQueryBusInformation().

◆ PciQueryCapabilities()

NTSTATUS NTAPI PciQueryCapabilities	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN OUT PDEVICE_CAPABILITIES	DeviceCapability
	)

Definition at line 1820 of file utils.c.

{
    NTSTATUS Status;
 
    /* A PDO ID is never unique, and its address is its function and device */
    DeviceCapability->UniqueID = FALSE;
    DeviceCapability->Address = PdoExtension->Slot.u.bits.FunctionNumber |
                                (PdoExtension->Slot.u.bits.DeviceNumber << 16);
 
    /* Check for host bridges */
    if ((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
        (PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST))
    {
        /* Raw device opens to a host bridge are acceptable */
        DeviceCapability->RawDeviceOK = TRUE;
    }
    else
    {
        /* Otherwise, other PDOs cannot be directly opened */
        DeviceCapability->RawDeviceOK = FALSE;
    }
 
    /* PCI PDOs are pretty fixed things */
    DeviceCapability->LockSupported = FALSE;
    DeviceCapability->EjectSupported = FALSE;
    DeviceCapability->Removable = FALSE;
    DeviceCapability->DockDevice = FALSE;
 
    /* The slot number is stored as a device property, go query it */
    PciDetermineSlotNumber(PdoExtension, &DeviceCapability->UINumber);
 
    /* Finally, query and power capabilities and convert them for PnP usage */
    Status = PciQueryPowerCapabilities(PdoExtension, DeviceCapability);
 
    /* Dump the capabilities if it all worked, and return the status */
    if (NT_SUCCESS(Status)) PciDebugDumpQueryCapabilities(DeviceCapability);
    return Status;
}

Referenced by PciPdoIrpQueryCapabilities().

◆ PciQueryDeviceRelations()

NTSTATUS NTAPI PciQueryDeviceRelations	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN OUT PDEVICE_RELATIONS *	pDeviceRelations
	)

Definition at line 2366 of file enum.c.

{
    NTSTATUS Status;
    PPCI_PDO_EXTENSION PdoExtension;
    ULONG PdoCount = 0;
    PDEVICE_RELATIONS DeviceRelations, NewRelations;
    SIZE_T Size;
    PDEVICE_OBJECT DeviceObject, *ObjectArray;
    PAGED_CODE();
 
    /* Make sure the FDO is started */
    ASSERT(DeviceExtension->DeviceState == PciStarted);
 
    /* Synchronize while we enumerate the bus */
    Status = PciBeginStateTransition(DeviceExtension, PciSynchronizedOperation);
    if (!NT_SUCCESS(Status)) return Status;
 
    /* Scan all children PDO */
    for (PdoExtension = DeviceExtension->ChildPdoList;
         PdoExtension;
         PdoExtension = PdoExtension->Next)
    {
        /* Invalidate them */
        PdoExtension->NotPresent = TRUE;
    }
 
    /* Scan the PCI Bus */
    Status = PciScanBus(DeviceExtension);
    ASSERT(NT_SUCCESS(Status));
 
    /* Enumerate all children PDO again */
    for (PdoExtension = DeviceExtension->ChildPdoList;
         PdoExtension;
         PdoExtension = PdoExtension->Next)
    {
        /* Check for PDOs that are still invalidated */
        if (PdoExtension->NotPresent)
        {
            /* This means this PDO existed before, but not anymore */
            PdoExtension->ReportedMissing = TRUE;
            DPRINT1("PCIX - Old device (pdox) %p not found on rescan.\n",
                    PdoExtension);
        }
        else
        {
            /* Increase count of detected PDOs */
            PdoCount++;
        }
    }
 
    /* Read the current relations and add the newly discovered relations */
    DeviceRelations = *pDeviceRelations;
    Size = FIELD_OFFSET(DEVICE_RELATIONS, Objects) +
           PdoCount * sizeof(PDEVICE_OBJECT);
    if (DeviceRelations) Size += sizeof(PDEVICE_OBJECT) * DeviceRelations->Count;
 
    /* Allocate the device relations */
    NewRelations = (PDEVICE_RELATIONS)ExAllocatePoolWithTag(0, Size, 'BicP');
    if (!NewRelations)
    {
        /* Out of space, cancel the operation */
        PciCancelStateTransition(DeviceExtension, PciSynchronizedOperation);
        return STATUS_INSUFFICIENT_RESOURCES;
    }
 
    /* Check if there were any older relations */
    NewRelations->Count = 0;
    if (DeviceRelations)
    {
        /* Copy the old relations into the new buffer, then free the old one */
        RtlCopyMemory(NewRelations,
                      DeviceRelations,
                      FIELD_OFFSET(DEVICE_RELATIONS, Objects) +
                      DeviceRelations->Count * sizeof(PDEVICE_OBJECT));
        ExFreePoolWithTag(DeviceRelations, 0);
    }
 
    /* Print out that we're ready to dump relations */
    DPRINT("PCIX - QueryDeviceRelations/BusRelations FDOx %p (bus 0x%02x)\n",
           DeviceExtension,
           DeviceExtension->BaseBus);
 
    /* Loop the current PDO children and the device relation object array */
    PdoExtension = DeviceExtension->ChildPdoList;
    ObjectArray = &NewRelations->Objects[NewRelations->Count];
    while (PdoExtension)
    {
        /* Dump this relation */
        DPRINT("  QDR PDO %p (x %p)%s\n",
               PdoExtension->PhysicalDeviceObject,
               PdoExtension,
               PdoExtension->NotPresent ?
               "<Omitted, device flaged not present>" : "");
 
        /* Is this PDO present? */
        if (!PdoExtension->NotPresent)
        {
            /* Reference it and add it to the array */
            DeviceObject = PdoExtension->PhysicalDeviceObject;
            ObReferenceObject(DeviceObject);
            *ObjectArray++ = DeviceObject;
        }
 
        /* Go to the next PDO */
        PdoExtension = PdoExtension->Next;
    }
 
    /* Terminate dumping the relations */
    DPRINT("  QDR Total PDO count = %u (%u already in list)\n",
           NewRelations->Count + PdoCount,
           NewRelations->Count);
 
    /* Return the final count and the new buffer */
    NewRelations->Count += PdoCount;
    *pDeviceRelations = NewRelations;
 
    /* Let later rescans and PnP state changes begin their own transitions */
    PciCancelStateTransition(DeviceExtension, PciSynchronizedOperation);
    return STATUS_SUCCESS;
}

Referenced by PciFdoIrpQueryDeviceRelations().

◆ PciQueryDeviceText()

NTSTATUS NTAPI PciQueryDeviceText	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN DEVICE_TEXT_TYPE	QueryType,
		IN ULONG	Locale,
		OUT PWCHAR *	Buffer
	)

Definition at line 422 of file id.c.

{
    PWCHAR MessageBuffer, LocationBuffer;
    ULONG Length;
    NTSTATUS Status;
 
    UNREFERENCED_PARAMETER(Locale);
 
    /* Check what the caller is requesting */
    switch (QueryType)
    {
        case DeviceTextDescription:
 
            /* Get the message from the resource section */
            MessageBuffer = PciGetDeviceDescriptionMessage(PdoExtension->BaseClass,
                                                           PdoExtension->SubClass);
 
            /* Return it to the caller, and select proper status code */
            *Buffer = MessageBuffer;
            Status = MessageBuffer ? STATUS_SUCCESS : STATUS_NOT_SUPPORTED;
            break;
 
        case DeviceTextLocationInformation:
 
            /* Get the message from the resource section */
            MessageBuffer = PciGetDescriptionMessage(0x10000, &Length);
            if (!MessageBuffer)
            {
                /* It should be there, but fail if it wasn't found for some reason */
                Status = STATUS_NOT_SUPPORTED;
                break;
            }
 
            /* Add space for a null-terminator, and allocate the buffer */
            Length += 2 * sizeof(UNICODE_NULL);
            LocationBuffer = ExAllocatePoolWithTag(PagedPool,
                                                   Length * sizeof(WCHAR),
                                                   'BicP');
            *Buffer = LocationBuffer;
 
            /* Check if the allocation succeeded */
            if (LocationBuffer)
            {
                /* Build the location string based on bus, function, and device */
                _swprintf(LocationBuffer,
                          MessageBuffer,
                          PdoExtension->ParentFdoExtension->BaseBus,
                          PdoExtension->Slot.u.bits.FunctionNumber,
                          PdoExtension->Slot.u.bits.DeviceNumber);
            }
 
            /* Free the original string from the resource section */
            ExFreePoolWithTag(MessageBuffer, 0);
 
            /* Select the correct status */
            Status = LocationBuffer ? STATUS_SUCCESS : STATUS_INSUFFICIENT_RESOURCES;
            break;
 
        default:
 
            /* Anything else is unsupported */
            Status = STATUS_NOT_SUPPORTED;
            break;
    }
 
    /* Return whether or not a device text string was indeed found */
    return Status;
}

Referenced by PciPdoIrpQueryDeviceText().

◆ PciQueryEjectionRelations()

NTSTATUS NTAPI PciQueryEjectionRelations	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN OUT PDEVICE_RELATIONS *	pDeviceRelations
	)

Definition at line 614 of file enum.c.

{
    PPCI_FDO_EXTENSION FdoExtension = PdoExtension->ParentFdoExtension;
    PDEVICE_RELATIONS OldRelations = *pDeviceRelations;
    PDEVICE_RELATIONS NewRelations = NULL;
    ULONG OldCount = OldRelations ? OldRelations->Count : 0;
    ULONG FunctionCount;
    PAGED_CODE();
 
    KeEnterCriticalRegion();
    KeWaitForSingleObject(&FdoExtension->ChildListLock, Executive, KernelMode, FALSE, NULL);
 
    /* The other functions of the same device leave the machine with this one */
    FunctionCount = PciGatherOtherFunctions(PdoExtension, NULL);
    if (FunctionCount)
    {
        NewRelations = ExAllocatePoolWithTag(NonPagedPool,
                                             FIELD_OFFSET(DEVICE_RELATIONS, Objects) +
                                             (OldCount + FunctionCount) * sizeof(*NewRelations->Objects),
                                             PCI_POOL_TAG);
    }
 
    /* Without memory the list from above is kept as it is */
    if (NewRelations)
    {
        if (OldRelations)
        {
            RtlCopyMemory(NewRelations->Objects,
                          OldRelations->Objects,
                          OldCount * sizeof(*OldRelations->Objects));
            ExFreePoolWithTag(OldRelations, 0);
        }
 
        NewRelations->Count = OldCount +
                              PciGatherOtherFunctions(PdoExtension, &NewRelations->Objects[OldCount]);
        ASSERT(NewRelations->Count == OldCount + FunctionCount);
        *pDeviceRelations = NewRelations;
    }
 
    KeSetEvent(&FdoExtension->ChildListLock, IO_NO_INCREMENT, FALSE);
    KeLeaveCriticalRegion();
    return STATUS_SUCCESS;
}

Referenced by PciPdoIrpQueryDeviceRelations().

◆ PciQueryId()

NTSTATUS NTAPI PciQueryId	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		IN BUS_QUERY_ID_TYPE	QueryType,
		OUT PWCHAR *	Buffer
	)

Definition at line 217 of file id.c.

{
    ULONG SubsysId;
    CHAR VendorString[22];
    PPCI_PDO_EXTENSION PdoExtension;
    PPCI_FDO_EXTENSION ParentExtension;
    PWCHAR StringBuffer;
    ULONG i, Size;
    NTSTATUS Status;
    PANSI_STRING NextString;
    UNICODE_STRING DestinationString;
    PCI_ID_BUFFER IdBuffer;
    PAGED_CODE();
 
    /* Assume failure */
    Status = STATUS_SUCCESS;
    *Buffer = NULL;
 
    /* Start with the genric vendor string, which is the vendor ID + device ID */
    sprintf(VendorString,
            "PCI\\VEN_%04X&DEV_%04X",
            DeviceExtension->VendorId,
            DeviceExtension->DeviceId);
 
    /* Initialize the PCI ID Buffer */
    PciInitIdBuffer(&IdBuffer);
 
    /* Build the subsystem ID as shown in PCI ID Strings */
    SubsysId = DeviceExtension->SubsystemVendorId | (DeviceExtension->SubsystemId << 16);
 
    /* Check what the caller is requesting */
    switch (QueryType)
    {
        case BusQueryDeviceID:
 
            /* A single ID, the vendor string + the revision ID */
            PciIdPrintf(&IdBuffer,
                        "%s&SUBSYS_%08X&REV_%02X",
                        VendorString,
                        SubsysId,
                        DeviceExtension->RevisionId);
            break;
 
        case BusQueryHardwareIDs:
 
            /* First the vendor string + the subsystem ID + the revision ID */
            PciIdPrintf(&IdBuffer,
                        "%s&SUBSYS_%08X&REV_%02X",
                        VendorString,
                        SubsysId,
                        DeviceExtension->RevisionId);
 
            /* Next, without the revision */
            PciIdPrintf(&IdBuffer,
                        "%s&SUBSYS_%08X",
                        VendorString,
                        SubsysId);
 
            /* Next, the vendor string + the base class + sub class + progif */
            PciIdPrintf(&IdBuffer,
                        "%s&CC_%02X%02X%02X",
                        VendorString,
                        DeviceExtension->BaseClass,
                        DeviceExtension->SubClass,
                        DeviceExtension->ProgIf);
 
            /* Next, without the progif */
            PciIdPrintf(&IdBuffer,
                        "%s&CC_%02X%02X",
                        VendorString,
                        DeviceExtension->BaseClass,
                        DeviceExtension->SubClass);
 
            /* And finally, a terminator */
            PciIdPrintf(&IdBuffer, "\0");
            break;
 
        case BusQueryCompatibleIDs:
 
            /* First, the vendor + revision ID only */
            PciIdPrintf(&IdBuffer,
                        "%s&REV_%02X",
                        VendorString,
                        DeviceExtension->RevisionId);
 
            /* Next, the vendor string alone */
            PciIdPrintf(&IdBuffer, "%s", VendorString);
 
            /* Next, the vendor ID + the base class + the sub class + progif */
            PciIdPrintf(&IdBuffer,
                         "PCI\\VEN_%04X&CC_%02X%02X%02X",
                         DeviceExtension->VendorId,
                         DeviceExtension->BaseClass,
                         DeviceExtension->SubClass,
                         DeviceExtension->ProgIf);
 
            /* Now without the progif */
            PciIdPrintf(&IdBuffer,
                        "PCI\\VEN_%04X&CC_%02X%02X",
                        DeviceExtension->VendorId,
                        DeviceExtension->BaseClass,
                        DeviceExtension->SubClass);
 
            /* And then just the vendor ID itself */
            PciIdPrintf(&IdBuffer,
                        "PCI\\VEN_%04X",
                        DeviceExtension->VendorId);
 
            /* Then the base class + subclass + progif, without any vendor */
            PciIdPrintf(&IdBuffer,
                        "PCI\\CC_%02X%02X%02X",
                        DeviceExtension->BaseClass,
                        DeviceExtension->SubClass,
                        DeviceExtension->ProgIf);
 
            /* Next, without the progif */
            PciIdPrintf(&IdBuffer,
                        "PCI\\CC_%02X%02X",
                        DeviceExtension->BaseClass,
                        DeviceExtension->SubClass);
 
            /* And finally, a terminator */
            PciIdPrintf(&IdBuffer, "\0");
            break;
 
        case BusQueryInstanceID:
 
            /* Start with a terminator */
            PciIdPrintf(&IdBuffer, "\0");
 
            /* And then encode the device and function number */
            PciIdPrintfAppend(&IdBuffer,
                              "%02X",
                              (DeviceExtension->Slot.u.bits.DeviceNumber << 3) |
                              DeviceExtension->Slot.u.bits.FunctionNumber);
 
            /* Loop every parent until the root */
            ParentExtension = DeviceExtension->ParentFdoExtension;
            while (!PCI_IS_ROOT_FDO(ParentExtension))
            {
                /* Two more digits and their terminator have to fit */
                if ((IdBuffer.CharBuffer + 2) >
                    (IdBuffer.BufferData + sizeof(IdBuffer.BufferData)))
                {
                    DPRINT1("PCIX - Bridge chain too deep for an instance ID\n");
                    return STATUS_BUFFER_OVERFLOW;
                }
 
                /* And encode the parent's device and function number as well */
                PdoExtension = ParentExtension->PhysicalDeviceObject->DeviceExtension;
                PciIdPrintfAppend(&IdBuffer,
                                  "%02X",
                                  (PdoExtension->Slot.u.bits.DeviceNumber << 3) |
                                  PdoExtension->Slot.u.bits.FunctionNumber);
 
                /* Move up to the next bridge */
                ParentExtension = PdoExtension->ParentFdoExtension;
            }
            break;
 
        default:
 
            /* Unknown query type */
            DPRINT1("PCIX - PciQueryId expected ID type = %d\n", QueryType);
            return STATUS_NOT_SUPPORTED;
    }
 
    /* Something should've been generated if this has been reached */
    ASSERT(IdBuffer.Count > 0);
 
    /* Allocate the final string buffer to hold the ID */
    StringBuffer = ExAllocatePoolWithTag(PagedPool, IdBuffer.TotalLength, 'BicP');
    if (!StringBuffer) return STATUS_INSUFFICIENT_RESOURCES;
 
    /* Build the UNICODE_STRING structure for it */
    DPRINT("PCIX - PciQueryId(%d)\n", QueryType);
    DestinationString.Buffer = StringBuffer;
    DestinationString.MaximumLength = IdBuffer.TotalLength;
 
    /* Loop every ID in the buffer */
    for (i = 0; i < IdBuffer.Count; i++)
    {
        /* Select the ANSI_STRING for the ID */
        NextString = &IdBuffer.Strings[i];
        DPRINT("    <- \"%s\"\n", NextString->Buffer);
 
        /* Convert it to a UNICODE_STRING */
        Status = RtlAnsiStringToUnicodeString(&DestinationString, NextString, FALSE);
        ASSERT(NT_SUCCESS(Status));
 
        /* Add it into the final destination buffer */
        Size = IdBuffer.StringSize[i];
        DestinationString.MaximumLength -= Size;
        DestinationString.Buffer += (Size / sizeof(WCHAR));
    }
 
    /* Return the buffer to the caller and return status (should be success) */
    *Buffer = StringBuffer;
    return Status;
}

Referenced by PciPdoIrpQueryId().

◆ PciQueryInterface()

NTSTATUS NTAPI PciQueryInterface	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN CONST GUID *	InterfaceType,
		IN ULONG	Size,
		IN ULONG	Version,
		IN PVOID	InterfaceData,
		IN PINTERFACE	Interface,
		IN BOOLEAN	LastChance
	)

Definition at line 45 of file intrface.c.

{
    UNICODE_STRING GuidString;
    NTSTATUS Status;
    PPCI_INTERFACE *InterfaceList;
    PPCI_INTERFACE PciInterface;
    RtlStringFromGUID(InterfaceType, &GuidString);
    DPRINT("PCIX - PciQueryInterface TYPE = %wZ\n", &GuidString);
    RtlFreeUnicodeString(&GuidString);
    DPRINT("     Size = %u, Version = %u, InterfaceData = %p, LastChance = %s\n",
           Size,
           Version,
           InterfaceData,
           LastChance ? "TRUE" : "FALSE");
 
    /* Loop all the available interfaces */
    for (InterfaceList = LastChance ? PciInterfacesLastResort : PciInterfaces;
         *InterfaceList;
         InterfaceList++)
    {
        /* Get the current interface */
        PciInterface = *InterfaceList;
 
        /* For debugging, construct the GUID string */
        RtlStringFromGUID(PciInterface->InterfaceType, &GuidString);
 
        /* Check if this is an FDO or PDO */
        if (DeviceExtension->ExtensionType == PciFdoExtensionType)
        {
            /* Check if the interface is for FDOs */
            if (!(PciInterface->Flags & PCI_INTERFACE_FDO))
            {
                /* This interface is not for FDOs, skip it */
                DPRINT("PCIX - PciQueryInterface guid = %wZ not for FDOs\n",
                       &GuidString);
                RtlFreeUnicodeString(&GuidString);
                continue;
            }
 
            /* Check if the interface is for root FDO only */
            if ((PciInterface->Flags & PCI_INTERFACE_ROOT) &&
                (!PCI_IS_ROOT_FDO(DeviceExtension)))
            {
                /* This FDO isn't the root, skip the interface */
                DPRINT("PCIX - PciQueryInterface guid = %wZ only for ROOT\n",
                       &GuidString);
                RtlFreeUnicodeString(&GuidString);
                continue;
            }
        }
        else
        {
            /* This is a PDO, check if the interface is for PDOs too */
            if (!(PciInterface->Flags & PCI_INTERFACE_PDO))
            {
                /* It isn't, skip it */
                DPRINT("PCIX - PciQueryInterface guid = %wZ not for PDOs\n",
                       &GuidString);
                RtlFreeUnicodeString(&GuidString);
                continue;
            }
        }
 
        /* Print the GUID for debugging, and then free the string */
        DPRINT("PCIX - PciQueryInterface looking at guid = %wZ\n", &GuidString);
        RtlFreeUnicodeString(&GuidString);
 
        /* Check if the GUID, version, and size all match */
        if ((IsEqualGUIDAligned(PciInterface->InterfaceType, InterfaceType)) &&
            (Version >= PciInterface->MinVersion) &&
            (Version <= PciInterface->MaxVersion) &&
            (Size >= PciInterface->MinSize))
        {
            /* Call the interface's constructor */
            Status = PciInterface->Constructor(DeviceExtension,
                                               PciInterface,
                                               InterfaceData,
                                               Version,
                                               Size,
                                               Interface);
            if (!NT_SUCCESS(Status))
            {
                /* This interface was not initialized correctly, skip it */
                DPRINT("PCIX - PciQueryInterface constructor %p returned %08lx\n",
                       PciInterface->Constructor, Status);
                continue;
            }
 
            /* Reference the interface and return success, all is good */
            Interface->InterfaceReference(Interface->Context);
            DPRINT("PCIX - PciQueryInterface returning SUCCESS\n");
            return Status;
        }
    }
 
    /* No match is not an error, the FDO path still asks the lower drivers */
    DPRINT("PCIX - PciQueryInterface found no matching interface\n");
    return STATUS_NOT_SUPPORTED;
}

Referenced by PciFdoIrpQueryInterface(), and PciPdoIrpQueryInterface().

◆ PciQueryRequirements()

NTSTATUS NTAPI PciQueryRequirements	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *	RequirementsList
	)

Definition at line 882 of file enum.c.

{
    NTSTATUS Status;
    PCI_COMMON_HEADER PciHeader;
    PAGED_CODE();
 
    /* Build even without a BAR or a pin, bridge legacy decodes need ranges too */
    PciReadDeviceConfig(PdoExtension, &PciHeader, 0, PCI_COMMON_HDR_LENGTH);
    Status = PciBuildRequirementsList(PdoExtension, &PciHeader, RequirementsList);
    if (!NT_SUCCESS(Status))
        return Status;
 
    /* Is this a Compaq PCI Hotplug Controller (r17) on a PAE system ? */
    if ((PciHeader.VendorID == 0xE11) &&
        (PciHeader.DeviceID == 0xA0F7) &&
        (PciHeader.RevisionID == 17) &&
        (ExIsProcessorFeaturePresent(PF_PAE_ENABLED)))
    {
        /* No fixup is applied for this controller under PAE */
        DPRINT1("PCIX - Compaq hotplug controller PDO ext 0x%p has an unhandled PAE quirk\n",
                PdoExtension);
    }
 
    /* The shared zero list must never reach PnP, which frees what it is given */
    if (*RequirementsList == PciZeroIoResourceRequirements)
    {
        *RequirementsList = NULL;
        DPRINT("PCIX - Returning NULL requirements list\n");
    }
    else
    {
        PciDebugPrintIoResReqList(*RequirementsList);
    }
 
    /* This call always succeeds (but maybe with no requirements) */
    return STATUS_SUCCESS;
}

Referenced by PciPdoIrpQueryResourceRequirements().

◆ PciQueryResources()

NTSTATUS NTAPI PciQueryResources	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		OUT PCM_RESOURCE_LIST *	Buffer
	)

Definition at line 389 of file enum.c.

{
    PPCI_FUNCTION_RESOURCES PciResources;
    BOOLEAN HaveVga, HaveMemSpace, HaveIoSpace;
    USHORT BridgeControl, PciCommand;
    ULONG Count, i;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR Partial, Resource, LastResource;
    PCM_RESOURCE_LIST ResourceList;
    UCHAR InterruptLine;
    PAGED_CODE();
 
    /* Assume failure */
    Count = 0;
    HaveVga = FALSE;
    *Buffer = NULL;
 
    /* Make sure there's some resources to query */
    PciResources = PdoExtension->Resources;
    if (!PciResources) return STATUS_SUCCESS;
 
    /* Read the decodes */
    PciReadDeviceConfig(PdoExtension,
                        &PciCommand,
                        FIELD_OFFSET(PCI_COMMON_HEADER, Command),
                        sizeof(USHORT));
 
    /* Check which ones are turned on */
    HaveIoSpace = PciCommand & PCI_ENABLE_IO_SPACE;
    HaveMemSpace = PciCommand & PCI_ENABLE_MEMORY_SPACE;
 
    /* Loop maximum possible descriptors */
    for (i = 0; i < 7; i++)
    {
        /* Check if the decode for this descriptor is actually turned on */
        Partial = &PciResources->Current[i];
        if ((HaveMemSpace &&
             ((Partial->Type == CmResourceTypeMemory) ||
              (Partial->Type == CmResourceTypeMemoryLarge))) ||
            (HaveIoSpace && (Partial->Type == CmResourceTypePort)))
        {
            /* One more fully active descriptor */
            Count++;
        }
    }
 
    /* If there's an interrupt pin associated, check at least one decode is on */
    if ((PdoExtension->InterruptPin) && ((HaveMemSpace) || (HaveIoSpace)))
    {
        /* Read the interrupt line for the pin, add a descriptor if it's valid */
        InterruptLine = PdoExtension->AdjustedInterruptLine;
        if ((InterruptLine) && (InterruptLine != PCI_INTERRUPT_LINE_UNKNOWN))
            Count++;
    }
 
    /* Check for a PCI-to-PCI or CardBus bridge, both keep the VGA enable at the same place */
    if ((PdoExtension->HeaderType == PCI_BRIDGE_TYPE) ||
        (PdoExtension->HeaderType == PCI_CARDBUS_BRIDGE_TYPE))
    {
        /* Read bridge settings, check if VGA is present */
        PciReadDeviceConfig(PdoExtension,
                            &BridgeControl,
                            FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.BridgeControl),
                            sizeof(USHORT));
        if (BridgeControl & PCI_ENABLE_BRIDGE_VGA)
        {
            /* Remember for later */
            HaveVga = TRUE;
 
            /* One memory descriptor for 0xA0000, plus the two I/O port ranges */
            if (HaveMemSpace) Count++;
            if (HaveIoSpace) Count += 2;
        }
    }
 
    /* If there's no descriptors in use, there's no resources, so return */
    if (!Count) return STATUS_SUCCESS;
 
    /* Allocate a resource list to hold the resources */
    ResourceList = PciAllocateCmResourceList(Count,
                                             PdoExtension->ParentFdoExtension->BaseBus);
    if (!ResourceList) return STATUS_INSUFFICIENT_RESOURCES;
 
    /* This is where the descriptors will be copied into */
    Resource = ResourceList->List[0].PartialResourceList.PartialDescriptors;
    LastResource = Resource + Count + 1;
 
    /* Loop maximum possible descriptors */
    for (i = 0; i < 7; i++)
    {
        /* Check if the decode for this descriptor is actually turned on */
        Partial = &PciResources->Current[i];
        if ((HaveMemSpace &&
             ((Partial->Type == CmResourceTypeMemory) ||
              (Partial->Type == CmResourceTypeMemoryLarge))) ||
            (HaveIoSpace && (Partial->Type == CmResourceTypePort)))
        {
            /* Copy the descriptor into the resource list */
            *Resource++ = *Partial;
        }
    }
 
    /* Check if earlier the code detected this was a PCI bridge with VGA on it */
    if (HaveVga)
    {
        /* Are the memory decodes enabled? */
        if (HaveMemSpace)
        {
            /* Build a memory descriptor for a 128KB framebuffer at 0xA0000 */
            Resource->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
            Resource->u.Generic.Start.HighPart = 0;
            Resource->Type = CmResourceTypeMemory;
            Resource->u.Generic.Start.LowPart = 0xA0000;
            Resource->u.Generic.Length = 0x20000;
            Resource++;
        }
 
        /* Are the I/O decodes enabled? */
        if (HaveIoSpace)
        {
            /* Build an I/O descriptor for the graphic ports at 0x3B0 */
            Resource->Type = CmResourceTypePort;
            Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
            Resource->u.Port.Start.QuadPart = 0x3B0u;
            Resource->u.Port.Length = 0xC;
            Resource++;
 
            /* Build an I/O descriptor for the graphic ports at 0x3C0 */
            Resource->Type = CmResourceTypePort;
            Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
            Resource->u.Port.Start.QuadPart = 0x3C0u;
            Resource->u.Port.Length = 0x20;
            Resource++;
        }
    }
 
    /* If there's an interrupt pin associated, check at least one decode is on */
    if ((PdoExtension->InterruptPin) && ((HaveMemSpace) || (HaveIoSpace)))
    {
         /* Read the interrupt line for the pin, check if it's valid */
         InterruptLine = PdoExtension->AdjustedInterruptLine;
         if ((InterruptLine) && (InterruptLine != PCI_INTERRUPT_LINE_UNKNOWN))
         {
             /* Make sure there's still space */
             ASSERT(Resource < LastResource);
 
             /* Add the interrupt descriptor */
             Resource->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
             Resource->Type = CmResourceTypeInterrupt;
             Resource->ShareDisposition = CmResourceShareShared;
             Resource->u.Interrupt.Affinity = -1;
             Resource->u.Interrupt.Level = InterruptLine;
             Resource->u.Interrupt.Vector = InterruptLine;
        }
    }
 
    /* Return the resource list */
    *Buffer = ResourceList;
    return STATUS_SUCCESS;
}

Referenced by PciPdoIrpQueryResources().

◆ PciQueryTargetDeviceRelations()

NTSTATUS NTAPI PciQueryTargetDeviceRelations	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN OUT PDEVICE_RELATIONS *	pDeviceRelations
	)

Definition at line 552 of file enum.c.

{
    PDEVICE_RELATIONS DeviceRelations;
    PAGED_CODE();
 
    /* If there were existing relations, free them */
    if (*pDeviceRelations) ExFreePoolWithTag(*pDeviceRelations, 0);
 
    /* Allocate a new structure for the relations */
    DeviceRelations = ExAllocatePoolWithTag(NonPagedPool,
                                            sizeof(DEVICE_RELATIONS),
                                            'BicP');
    if (!DeviceRelations) return STATUS_INSUFFICIENT_RESOURCES;
 
    /* Only one relation: the PDO */
    DeviceRelations->Count = 1;
    DeviceRelations->Objects[0] = PdoExtension->PhysicalDeviceObject;
    ObReferenceObject(DeviceRelations->Objects[0]);
 
    /* Return the new relations */
    *pDeviceRelations = DeviceRelations;
    return STATUS_SUCCESS;
}

Referenced by PciPdoIrpQueryDeviceRelations().

◆ PciReadDeviceCapability()

UCHAR NTAPI PciReadDeviceCapability	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		IN UCHAR	Offset,
		IN ULONG	CapabilityId,
		OUT PPCI_CAPABILITIES_HEADER	Buffer,
		IN ULONG	Length
	)

Definition at line 958 of file utils.c.

{
    ULONG CapabilityCount = 0;
 
    /* If the device has no capabilility list, fail */
    if (!Offset) return 0;
 
    /* Validate a PDO with capabilities, a valid buffer, and a valid length */
    ASSERT(DeviceExtension->ExtensionType == PciPdoExtensionType);
    ASSERT(DeviceExtension->CapabilitiesPtr != 0);
    ASSERT(Buffer);
    ASSERT(Length >= sizeof(PCI_CAPABILITIES_HEADER));
 
    /* Loop all capabilities */
    while (Offset)
    {
        /* Make sure the pointer is spec-aligned and spec-sized */
        ASSERT((Offset >= PCI_COMMON_HDR_LENGTH) && ((Offset & 0x3) == 0));
 
        /* Read the capability header */
        PciReadDeviceConfig(DeviceExtension,
                            Buffer,
                            Offset,
                            sizeof(PCI_CAPABILITIES_HEADER));
 
        /* Check if this is the capability being looked up */
        if ((Buffer->CapabilityID == CapabilityId) || !(CapabilityId))
        {
            /* Check if was at a valid offset and length */
            if ((Offset) && (Length > sizeof(PCI_CAPABILITIES_HEADER)))
            {
                /* Sanity check */
                ASSERT(Length <= (sizeof(PCI_COMMON_CONFIG) - Offset));
 
                /* Now read the whole capability data into the buffer */
                PciReadDeviceConfig(DeviceExtension,
                                    (PVOID)((ULONG_PTR)Buffer +
                                    sizeof(PCI_CAPABILITIES_HEADER)),
                                    Offset + sizeof(PCI_CAPABILITIES_HEADER),
                                    Length - sizeof(PCI_CAPABILITIES_HEADER));
            }
 
            /* Return the offset where the capability was found */
            return Offset;
        }
 
        /* Try the next capability instead */
        CapabilityCount++;
        Offset = Buffer->Next;
 
        /* There can't be more than 48 capabilities (256 bytes max) */
        if (CapabilityCount > 48)
        {
            /* Fail, since this is basically a broken PCI device */
            DPRINT1("PCIX - Device %p capabilities list is broken.\n", DeviceExtension);
            return 0;
        }
    }
 
    /* Capability wasn't found, fail */
    return 0;
}

Referenced by PciGetEnhancedCapabilities(), PciGetExpressCapabilities(), PciScanBus(), and PciSetPowerManagedDevicePowerState().

◆ PciReadDeviceConfig()

VOID NTAPI PciReadDeviceConfig	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 149 of file config.c.

{
    /* Call the generic worker function */
    PciReadWriteConfigSpace(DeviceExtension->ParentFdoExtension,
                            DeviceExtension->Slot,
                            Buffer,
                            Offset,
                            Length,
                            TRUE);
}

Referenced by PciApplyHacks(), PciApplyResizableBarSizes(), PciAssignSlotResources(), PciConfigureIdeController(), PciDecodeEnable(), PciGetResizableBarCapability(), PciPdoIsPresent(), PciPdoReadWriteConfig(), PciPdoTurnOff(), PcipGetFunctionLimits(), PciQueryRequirements(), PciQueryResources(), PciReadDeviceCapability(), PciReadDeviceExtendedCapability(), PciScanBus(), PciSelectResizableBarSize(), PciSetResources(), PciStallForPowerChange(), PciVerifierCheckBridgeBusNumbers(), and PciWriteLimitsAndRestoreCurrent().

◆ PciReadDeviceExtendedCapability()

ULONG NTAPI PciReadDeviceExtendedCapability	(	_In_ PPCI_PDO_EXTENSION	DeviceExtension,
		_In_ ULONG	CapabilityId,
		_Out_writes_bytes_(Length) PPCI_EXPRESS_ENHANCED_CAPABILITY_HEADER	Buffer,
		_In_ ULONG	Length
	)

Finds an extended capability and reads it into the caller's buffer.

Returns: The offset of the capability, or 0 if it was not found.

Definition at line 39 of file express.c.

{
    PCI_EXPRESS_ENHANCED_CAPABILITY_HEADER Header;
    ULONG Offset, EntriesLeft;
 
    ASSERT(DeviceExtension->ExtensionType == PciPdoExtensionType);
    ASSERT(Length >= sizeof(PCI_EXPRESS_ENHANCED_CAPABILITY_HEADER));
 
    if (!DeviceExtension->IsExtendedConfigReachable)
        return 0;
 
    /* More entries than aligned offsets means the list loops */
    EntriesLeft = (PCI_EXTENDED_CONFIG_LENGTH - PCI_LEGACY_CONFIG_LENGTH) / sizeof(ULONG);
 
    for (Offset = PCI_LEGACY_CONFIG_LENGTH; Offset != 0; Offset = Header.Next)
    {
        if (!PciIsExtendedCapabilityOffsetValid(Offset))
            return 0;
 
        if (EntriesLeft == 0)
        {
            DPRINT1("PCIX - Device %p extended capabilities list is broken\n",
                    DeviceExtension);
            return 0;
        }
        EntriesLeft--;
 
        PciReadDeviceConfig(DeviceExtension, &Header, Offset, sizeof(Header));
 
        /* A function that does not decode extended space reads back all ones */
        if (Header.CapabilityID == 0xFFFF)
            return 0;
 
        if (Header.CapabilityID != CapabilityId)
            continue;
 
        if (Length > (PCI_EXTENDED_CONFIG_LENGTH - Offset))
            return 0;
 
        PciReadDeviceConfig(DeviceExtension, Buffer, Offset, Length);
        return Offset;
    }
 
    return 0;
}

Referenced by PciGetResizableBarCapability().

◆ PciReadSlotConfig()

VOID NTAPI PciReadSlotConfig	(	IN PPCI_FDO_EXTENSION	DeviceExtension,
		IN PCI_SLOT_NUMBER	Slot,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 165 of file config.c.

{
    /* Call the generic worker function */
    PciReadWriteConfigSpace(DeviceExtension, Slot, Buffer, Offset, Length, TRUE);
}

Referenced by PciEcamVerifyBus(), and PciScanBus().

◆ PciReleaseEcam()

VOID NTAPI PciReleaseEcam ( VOID )

Unmaps every bus mapped through the ECAM window.

Definition at line 381 of file ecam.c.

{
    PAGED_CODE();
 
    /* Config access falls back to the legacy mechanism before the mappings go away */
    PciEcamVerified = FALSE;
    PciEcamDiscardWindow();
    PciEcamWindowQueried = FALSE;
}

Referenced by PciDriverUnload().

◆ PciRestoreHalHooks()

VOID NTAPI PciRestoreHalHooks ( VOID )

Gives the HAL back the routines PciHookHal replaced.

Definition at line 337 of file hookhal.c.

{
    PAGED_CODE();
    ASSERT(PcipSavedTranslateBusAddress != NULL);
    ASSERT(PcipSavedAssignSlotResources != NULL);
 
    /* Restore the HAL table before dropping the only copies of its routines */
    HalPciTranslateBusAddress = PcipSavedTranslateBusAddress;
    HalPciAssignSlotResources = PcipSavedAssignSlotResources;
 
    PcipSavedTranslateBusAddress = NULL;
    PcipSavedAssignSlotResources = NULL;
}

Referenced by PciDriverUnload().

◆ PciSaveBiosConfig()

NTSTATUS NTAPI PciSaveBiosConfig	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		OUT PPCI_COMMON_HEADER	PciData
	)

Referenced by PciScanBus(), and routeintrf_UpdateInterruptLine().

◆ PciSendDeviceUsageToParent()

NTSTATUS NTAPI PciSendDeviceUsageToParent	(	_In_ PPCI_FDO_EXTENSION	ParentFdoExtension,
		_In_ PIO_STACK_LOCATION	IoStackLocation
	)

Sends a device usage notification to the top of the stack of a parent bus.

Parameters

[in]	ParentFdoExtension	The FDO extension of the bus the function is on.
[in]	IoStackLocation	The stack location of the notification the function received.

Returns: The status the parent stack completed the notification with.

Definition at line 94 of file usage.c.

{
    PDEVICE_OBJECT TopDevice;
    PIO_STACK_LOCATION NextStack;
    IO_STATUS_BLOCK IoStatus;
    KEVENT Event;
    NTSTATUS Status;
    PIRP Irp;
 
    PAGED_CODE();
 
    TopDevice = IoGetAttachedDeviceReference(ParentFdoExtension->PhysicalDeviceObject);
 
    KeInitializeEvent(&Event, SynchronizationEvent, FALSE);
    Irp = IoBuildSynchronousFsdRequest(IRP_MJ_PNP,
                                       TopDevice,
                                       NULL,
                                       0,
                                       NULL,
                                       &Event,
                                       &IoStatus);
    if (!Irp)
    {
        ObDereferenceObject(TopDevice);
        return STATUS_INSUFFICIENT_RESOURCES;
    }
 
    /* A PnP IRP nobody handles must come back as not supported */
    Irp->IoStatus.Status = STATUS_NOT_SUPPORTED;
    Irp->IoStatus.Information = 0;
 
    NextStack = IoGetNextIrpStackLocation(Irp);
    NextStack->MinorFunction = IRP_MN_DEVICE_USAGE_NOTIFICATION;
    NextStack->Parameters.UsageNotification = IoStackLocation->Parameters.UsageNotification;
 
    Status = IoCallDriver(TopDevice, Irp);
    if (Status == STATUS_PENDING)
    {
        KeWaitForSingleObject(&Event, Executive, KernelMode, FALSE, NULL);
        Status = IoStatus.Status;
    }
 
    ObDereferenceObject(TopDevice);
    return Status;
}

Referenced by PciPdoIrpDeviceUsageNotification().

◆ PciSendIoctl()

NTSTATUS NTAPI PciSendIoctl	(	IN PDEVICE_OBJECT	DeviceObject,
		IN ULONG	IoControlCode,
		IN PVOID	InputBuffer,
		IN ULONG	InputBufferLength,
		IN PVOID	OutputBuffer,
		IN ULONG	OutputBufferLength
	)

Definition at line 531 of file utils.c.

{
    PIRP Irp;
    NTSTATUS Status;
    KEVENT Event;
    IO_STATUS_BLOCK IoStatusBlock;
    PDEVICE_OBJECT AttachedDevice;
    PAGED_CODE();
 
    /* Initialize the pending IRP event */
    KeInitializeEvent(&Event, SynchronizationEvent, FALSE);
 
    /* Get a reference to the root PDO (ACPI) */
    AttachedDevice = IoGetAttachedDeviceReference(DeviceObject);
    if (!AttachedDevice) return STATUS_INVALID_PARAMETER;
 
    /* Build the requested IOCTL IRP */
    Irp = IoBuildDeviceIoControlRequest(IoControlCode,
                                        AttachedDevice,
                                        InputBuffer,
                                        InputBufferLength,
                                        OutputBuffer,
                                        OutputBufferLength,
                                        0,
                                        &Event,
                                        &IoStatusBlock);
    if (!Irp) return STATUS_INSUFFICIENT_RESOURCES;
 
    /* Send the IOCTL to the driver */
    Status = IoCallDriver(AttachedDevice, Irp);
    if (Status == STATUS_PENDING)
    {
        /* Wait for a response */
        KeWaitForSingleObject(&Event,
                              Executive,
                              KernelMode,
                              FALSE,
                              NULL);
        Status = Irp->IoStatus.Status;
    }
 
    /* Take away the reference we took and return the result to the caller */
    ObDereferenceObject(AttachedDevice);
    return Status;
}

Referenced by PciGetHotPlugParameters(), and PciIsSlotPresentInParentMethod().

◆ PciSetPowerManagedDevicePowerState()

NTSTATUS NTAPI PciSetPowerManagedDevicePowerState	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		IN DEVICE_POWER_STATE	DeviceState,
		IN BOOLEAN	IrpSet
	)

Definition at line 123 of file power.c.

{
    NTSTATUS Status;
    PCI_PM_CAPABILITY PmCaps;
    ULONG CapsOffset;
 
    /* Assume success */
    Status = STATUS_SUCCESS;
 
    /* Check if this device can support low power states */
    if (!(PciCanDisableDecodes(DeviceExtension, NULL, 0, TRUE)) &&
         (DeviceState != PowerDeviceD0))
    {
        /* Simply return success, ignoring this request */
        DPRINT1("PCIX - Cannot disable decodes on this device, ignoring PM request...\n");
        return Status;
    }
 
    /* Does the device support power management at all? */
    if (!(DeviceExtension->HackFlags & PCI_HACK_NO_PM_CAPS))
    {
        /* Get the PM capabilities register */
        CapsOffset = PciReadDeviceCapability(DeviceExtension,
                                             DeviceExtension->CapabilitiesPtr,
                                             PCI_CAPABILITY_ID_POWER_MANAGEMENT,
                                             &PmCaps.Header,
                                             sizeof(PCI_PM_CAPABILITY));
        ASSERT(CapsOffset);
        ASSERT(DeviceState != PowerDeviceUnspecified);
 
        /* Check if the device is being powered up */
        if (DeviceState == PowerDeviceD0)
        {
            /* Set full power state */
            PmCaps.PMCSR.ControlStatus.PowerState = 0;
 
            /* Check if the device supports Cold-D3 poweroff */
            if (PmCaps.PMC.Capabilities.Support.PMED3Cold)
            {
                /* If there was a pending PME, clear it */
                PmCaps.PMCSR.ControlStatus.PMEStatus = 1;
            }
        }
        else
        {
            /* Otherwise, just set the new power state, converting from NT */
            PmCaps.PMCSR.ControlStatus.PowerState = DeviceState - 1;
        }
 
        /* Write the new power state in the PMCSR */
        PciWriteDeviceConfig(DeviceExtension,
                             &PmCaps.PMCSR,
                             CapsOffset + FIELD_OFFSET(PCI_PM_CAPABILITY, PMCSR),
                             sizeof(PCI_PMCSR));
 
        /* Now wait for the change to "stick" based on the spec-mandated time */
        Status = PciStallForPowerChange(DeviceExtension, DeviceState, CapsOffset);
        if (!NT_SUCCESS(Status)) return Status;
    }
    else
    {
        /* Nothing to do! */
        DPRINT1("PCIX - No PM on this device, ignoring request\n");
    }
 
    /* Check if new resources have to be assigned */
    if (IrpSet)
    {
        /* Check if the new device state is lower (higher power) than now */
        if (DeviceState < DeviceExtension->PowerState.CurrentDeviceState)
        {
            /* Leaving D3 may reset the function, so write its configuration again */
            Status = PciSetResources(DeviceExtension, FALSE, FALSE);
        }
    }
 
    /* Return the power state change status */
    return Status;
}

Referenced by PciPdoEnterDevicePowerState(), PciPdoIrpStartDevice(), PciPdoTurnOff(), and PciScanBus().

◆ PciSetResources()

NTSTATUS NTAPI PciSetResources	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN BOOLEAN	DoReset,
		IN BOOLEAN	SomethingSomethingDarkSide
	)

Definition at line 2490 of file enum.c.

{
    PPCI_FDO_EXTENSION FdoExtension;
    UCHAR NewCacheLineSize, NewLatencyTimer, CacheLineReadBack;
    PCI_COMMON_HEADER PciData;
    BOOLEAN Native;
    PPCI_CONFIGURATOR Configurator;
    NTSTATUS Status;
 
    UNREFERENCED_PARAMETER(SomethingSomethingDarkSide);
 
    /* Get the FDO and read the configuration data */
    FdoExtension = PdoExtension->ParentFdoExtension;
    PciReadDeviceConfig(PdoExtension, &PciData, 0, PCI_COMMON_HDR_LENGTH);
 
    /* Make sure this is still the same device */
    if (!PcipIsSameDevice(PdoExtension, &PciData))
    {
        /* Fail */
        ASSERTMSG("PCI Set resources - not same device.\n", FALSE);
        return STATUS_DEVICE_DOES_NOT_EXIST;
    }
 
    /* Nothing to set for a host bridge */
    if ((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
        (PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST))
    {
        /* Fake success */
        return STATUS_SUCCESS;
    }
 
    /* Check if an IDE controller is being reset */
    if ((DoReset) &&
        (PdoExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
        (PdoExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
    {
        /* Turn off native mode */
        Native = PciConfigureIdeController(PdoExtension, &PciData, FALSE);
        ASSERT(Native == PdoExtension->IDEInNativeMode);
    }
 
    /* Check for update of a hotplug device, or first configuration of one */
    if ((PdoExtension->NeedsHotPlugConfiguration) &&
        (FdoExtension->HotPlugParameters.Acquired))
    {
        /* The firmware never configured this device, so use what _HPP asks for */
        PdoExtension->SavedLatencyTimer = FdoExtension->HotPlugParameters.LatencyTimer;
        PdoExtension->SavedCacheLineSize = FdoExtension->HotPlugParameters.CacheLineSize;
 
        PdoExtension->CommandEnables &= ~(PCI_ENABLE_PARITY | PCI_ENABLE_SERR);
        if (FdoExtension->HotPlugParameters.EnablePERR)
        {
            PdoExtension->CommandEnables |= PCI_ENABLE_PARITY;
        }
 
        if (FdoExtension->HotPlugParameters.EnableSERR)
        {
            PdoExtension->CommandEnables |= PCI_ENABLE_SERR;
        }
 
        /* Only turn on memory write and invalidate if the device keeps the cache line size */
        PciWriteDeviceConfig(PdoExtension,
                             &PdoExtension->SavedCacheLineSize,
                             FIELD_OFFSET(PCI_COMMON_HEADER, CacheLineSize),
                             sizeof(PdoExtension->SavedCacheLineSize));
        PciReadDeviceConfig(PdoExtension,
                            &CacheLineReadBack,
                            FIELD_OFFSET(PCI_COMMON_HEADER, CacheLineSize),
                            sizeof(CacheLineReadBack));
        if ((CacheLineReadBack != 0) &&
            (CacheLineReadBack == PdoExtension->SavedCacheLineSize))
        {
            PdoExtension->CommandEnables |= PCI_ENABLE_WRITE_AND_INVALIDATE;
        }
        else
        {
            DPRINT1("PCIX - pdox %p cache line size %02x rejected, MWI stays off\n",
                    PdoExtension, PdoExtension->SavedCacheLineSize);
        }
    }
 
    /* Locate the correct resource configurator for this type of device */
    Configurator = &PciConfigurators[PdoExtension->HeaderType];
 
    /* Apply the settings change, nothing reaches the hardware if it is refused */
    Status = Configurator->ChangeResourceSettings(PdoExtension, &PciData);
    if (!NT_SUCCESS(Status))
        return Status;
 
    /* Assume no update needed */
    PdoExtension->UpdateHardware = FALSE;
 
    /* Check if a reset is needed */
    if (DoReset)
    {
        /* Reset resources */
        Configurator->ResetDevice(PdoExtension, &PciData);
        PciData.u.type0.InterruptLine = PdoExtension->RawInterruptLine;
    }
 
    /* Check if the latency timer changed */
    NewLatencyTimer = PdoExtension->SavedLatencyTimer;
    if (PciData.LatencyTimer != NewLatencyTimer)
    {
        /* Debug notification */
        DPRINT1("PCIX - pdox %p changing latency from %02x to %02x.\n",
                PdoExtension,
                PciData.LatencyTimer,
                NewLatencyTimer);
    }
 
    /* Check if the cache line changed */
    NewCacheLineSize = PdoExtension->SavedCacheLineSize;
    if (PciData.CacheLineSize != NewCacheLineSize)
    {
        /* Debug notification */
        DPRINT1("PCIX - pdox %p changing cache line size from %02x to %02x.\n",
                PdoExtension,
                PciData.CacheLineSize,
                NewCacheLineSize);
    }
 
    /* Inherit data from PDO extension */
    PciData.LatencyTimer = PdoExtension->SavedLatencyTimer;
    PciData.CacheLineSize = PdoExtension->SavedCacheLineSize;
    PciData.u.type0.InterruptLine = PdoExtension->RawInterruptLine;
 
    /* Apply any resource hacks required */
    PciApplyHacks(FdoExtension,
                  &PciData,
                  PdoExtension->Slot,
                  PCI_HACK_FIXUP_BEFORE_UPDATE,
                  PdoExtension);
 
    /* Check if I/O space was disabled by administrator or driver */
    if (PdoExtension->IoSpaceNotRequired)
    {
        /* Don't turn on the decode */
        PdoExtension->CommandEnables &= ~PCI_ENABLE_IO_SPACE;
    }
 
    /* Update the device with the new settings */
    PciUpdateHardware(PdoExtension, &PciData);
 
    /* Update complete */
    PdoExtension->RawInterruptLine = PciData.u.type0.InterruptLine;
    PdoExtension->NeedsHotPlugConfiguration = FALSE;
    return STATUS_SUCCESS;
}

Referenced by PciAssignAndProgramLegacy(), PciPdoIrpStartDevice(), and PciSetPowerManagedDevicePowerState().

◆ PciStringToUSHORT()

BOOLEAN NTAPI PciStringToUSHORT	(	IN PWCHAR	String,
		OUT PUSHORT	Value
	)

Definition at line 62 of file utils.c.

{
    USHORT Short;
    ULONG Low, High, Length;
    WCHAR Char;
 
    /* Initialize everything to zero */
    Short = 0;
    Length = 0;
    while (TRUE)
    {
        /* Get the character and set the high byte based on the previous one */
        Char = *String++;
        High = 16 * Short;
 
        /* Check for numbers */
        if ( Char >= '0' && Char <= '9' )
        {
            /* Convert them to a byte */
            Low = Char - '0';
        }
        else if ( Char >= 'A' && Char <= 'F' )
        {
            /* Convert upper-case hex letters into a byte */
            Low = Char - '7';
        }
        else if ( Char >= 'a' && Char <= 'f' )
        {
            /* Convert lower-case hex letters into a byte */
            Low = Char - 'W';
        }
        else
        {
            /* Invalid string, fail the conversion */
            return FALSE;
        }
 
        /* Combine the high and low byte */
        Short = High | Low;
 
        /* If 4 letters have been reached, the 16-bit integer should exist */
        if (++Length >= 4)
        {
            /* Return it to the caller */
            *Value = Short;
            return TRUE;
        }
    }
}

Referenced by PciBuildHackTable().

◆ PciUnicodeStringStrStr()

BOOLEAN NTAPI PciUnicodeStringStrStr	(	IN PUNICODE_STRING	InputString,
		IN PCUNICODE_STRING	EqualString,
		IN BOOLEAN	CaseInSensitive
	)

Definition at line 28 of file utils.c.

{
    UNICODE_STRING PartialString;
    LONG EqualChars, TotalChars;
 
    /* Build a partial string with the smaller substring */
    PartialString.Length = EqualString->Length;
    PartialString.MaximumLength = InputString->MaximumLength;
    PartialString.Buffer = InputString->Buffer;
 
    /* Check how many characters that need comparing */
    EqualChars = 0;
    TotalChars = (InputString->Length - EqualString->Length) / sizeof(WCHAR);
 
    /* If the substring is bigger, just fail immediately */
    if (TotalChars < 0) return FALSE;
 
    /* Keep checking each character */
    while (!RtlEqualUnicodeString(EqualString, &PartialString, CaseInSensitive))
    {
        /* Continue checking until all the required characters are equal */
        PartialString.Buffer++;
        PartialString.MaximumLength -= sizeof(WCHAR);
        if (++EqualChars > TotalChars) return FALSE;
    }
 
    /* The string is equal */
    return TRUE;
}

Referenced by DriverEntry().

◆ PciUpdateDeviceUsage()

NTSTATUS NTAPI PciUpdateDeviceUsage	(	_Inout_ PPCI_POWER_STATE	PowerState,
		_In_ PIO_STACK_LOCATION	IoStackLocation
	)

Counts a paging, hibernation or dump file arriving on or leaving a device.

Parameters

[in,out]	PowerState	The power state of the extension that holds the counts.
[in]	IoStackLocation	The stack location of the device usage notification.

Returns: STATUS_SUCCESS for a usage the driver accepts, STATUS_NOT_SUPPORTED otherwise.

Definition at line 35 of file usage.c.

{
    PLONG Count;
 
    PAGED_CODE();
 
    switch (IoStackLocation->Parameters.UsageNotification.Type)
    {
        case DeviceUsageTypePaging:
            Count = &PowerState->Paging;
            break;
 
        case DeviceUsageTypeHibernation:
            Count = &PowerState->Hibernate;
            break;
 
        case DeviceUsageTypeDumpFile:
            Count = &PowerState->CrashDump;
            break;
 
        /* Accepted, but nothing is held back for the boot device */
        case DeviceUsageTypeBoot:
            return STATUS_SUCCESS;
 
        default:
            return STATUS_NOT_SUPPORTED;
    }
 
    /* Several files can share a device, so these are counts and not flags */
    if (IoStackLocation->Parameters.UsageNotification.InPath)
    {
        InterlockedIncrement(Count);
    }
    else
    {
        ASSERT(*Count > 0);
        InterlockedDecrement(Count);
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciFdoIrpDeviceUsageNotification(), and PciPdoIrpDeviceUsageNotification().

◆ PciVerifierInit()

VOID NTAPI PciVerifierInit ( IN PDRIVER_OBJECT DriverObject )

Definition at line 182 of file pcivrify.c.

{
    NTSTATUS Status;
 
    /* Check if the kernel driver verifier is enabled */
    if (VfIsVerificationEnabled(VFOBJTYPE_SYSTEM_BIOS, NULL))
    {
        /* Register a notification for changes, to keep track of the PCI tree */
        Status = IoRegisterPlugPlayNotification(EventCategoryHardwareProfileChange,
                                                0,
                                                NULL,
                                                DriverObject,
                                                PciVerifierProfileChangeCallback,
                                                NULL,
                                                &PciVerifierNotificationHandle);
        if (NT_SUCCESS(Status)) PciVerifierRegistered = TRUE;
    }
}

Referenced by DriverEntry().

◆ PciVerifierRelease()

VOID NTAPI PciVerifierRelease ( VOID )

Drops the hardware profile notification taken by PciVerifierInit.

Definition at line 206 of file pcivrify.c.

{
    PAGED_CODE();
 
    if (PciVerifierRegistered)
    {
        IoUnregisterPlugPlayNotification(PciVerifierNotificationHandle);
        PciVerifierNotificationHandle = NULL;
        PciVerifierRegistered = FALSE;
    }
}

Referenced by PciDriverUnload().

◆ PciVerifierRetrieveFailureData()

PPCI_VERIFIER_DATA NTAPI PciVerifierRetrieveFailureData ( IN ULONG FailureCode )

Definition at line 60 of file pcivrify.c.

{
    PPCI_VERIFIER_DATA VerifierData;
 
    /* Scan the verifier failure table for this code */
    VerifierData = PciVerifierFailureTable;
    while (VerifierData->FailureCode != FailureCode)
    {
        /* Keep searching */
        ++VerifierData;
        ASSERT(VerifierData < &PciVerifierFailureTable[PCI_VERIFIER_CODES]);
    }
 
    /* Return the entry for this code */
    return VerifierData;
}

Referenced by PciStallForPowerChange(), and PciVerifierCheckBridgeBusNumbers().

◆ PciWriteDeviceConfig()

VOID NTAPI PciWriteDeviceConfig	(	IN PPCI_PDO_EXTENSION	DeviceExtension,
		IN PVOID	Buffer,
		IN ULONG	Offset,
		IN ULONG	Length
	)

Definition at line 133 of file config.c.

{
    /* Call the generic worker function */
    PciReadWriteConfigSpace(DeviceExtension->ParentFdoExtension,
                            DeviceExtension->Slot,
                            Buffer,
                            Offset,
                            Length,
                            FALSE);
}

Referenced by PciApplyHacks(), PciConfigureIdeController(), PciDecodeEnable(), PciPdoReadWriteConfig(), PcipUpdateHardware(), PciScanBus(), PciSelectResizableBarSize(), PciSetPowerManagedDevicePowerState(), PciSetResources(), PciWriteLimitsAndRestoreCurrent(), and routeintrf_UpdateInterruptLine().

◆ PPBridge_ChangeResourceSettings()

NTSTATUS NTAPI PPBridge_ChangeResourceSettings	(	_In_ PPCI_PDO_EXTENSION	PdoExtension,
		_Inout_ PPCI_COMMON_HEADER	PciData
	)

Definition at line 831 of file ppbridge.c.

{
    //BOOLEAN IoActive;
    PPCI_COMMON_CONFIG SavedConfig;
    PPCI_FUNCTION_RESOURCES PciResources;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
    PHYSICAL_ADDRESS Address;
    PULONG BarArray;
    ULONG Bar, BarMask, i;
 
    /* Check if I/O Decodes are enabled */
    //IoActive = (PciData->u.type1.IOBase & 0xF) == 1;
 
    /* Close every window, only the ones with a range to forward get opened again */
    PciData->u.type1.MemoryBase = 0xFFFF;
    PciData->u.type1.PrefetchBase = 0xFFFF;
    PciData->u.type1.IOBase = 0xFF;
    PciData->u.type1.IOLimit = 0;
    PciData->u.type1.MemoryLimit = 0;
    PciData->u.type1.PrefetchLimit = 0;
    PciData->u.type1.PrefetchBaseUpper32 = 0;
    PciData->u.type1.PrefetchLimitUpper32 = 0;
    PciData->u.type1.IOBaseUpper16 = 0;
    PciData->u.type1.IOLimitUpper16 = 0;
 
    /* Only the bridges PPBridge_SaveCurrentSettings kept a header for have windows to restore */
    SavedConfig = NULL;
    if ((PdoExtension->Dependent.type1.SubtractiveDecode) &&
        (((PdoExtension->VendorId == 0x8086) &&
          ((PdoExtension->DeviceId == 0x2418) ||
           (PdoExtension->DeviceId == 0x2428) ||
           (PdoExtension->DeviceId == 0x244E) ||
           (PdoExtension->DeviceId == 0x2448))) ||
         (PdoExtension->HackFlags & PCI_HACK_BROKEN_SUBTRACTIVE_DECODE)))
    {
        SavedConfig = PdoExtension->ParentFdoExtension->PreservedConfig;
    }
 
    /* A subtractive bridge has no window limits, so the loop below leaves these alone */
    if (SavedConfig)
        PciBridgeRestoreOpenWindows(PciData, (PPCI_COMMON_HEADER)SavedConfig);
 
    /* Write back the BARs, windows and ROM with the ranges assigned to them */
    PciResources = PdoExtension->Resources;
    if (PciResources)
    {
        BarArray = PciData->u.type1.BaseAddresses;
        for (i = 0; i < 6; i++)
        {
            /* Nothing to write for what the bridge does not implement */
            if (PciResources->Limit[i].Type == CmResourceTypeNull)
                continue;
 
            CmDescriptor = &PciResources->Current[i];
            Address.QuadPart = 0;
            if (CmDescriptor->Type != CmResourceTypeNull)
                Address = CmDescriptor->u.Generic.Start;
 
            if (i < PCI_TYPE1_ADDRESSES)
            {
                /* Keep the type bits the BAR reports */
                Bar = BarArray[i];
                if (Bar & PCI_ADDRESS_IO_SPACE)
                    BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
                else
                    BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
 
                BarArray[i] = (Bar & ~BarMask) | (Address.LowPart & BarMask);
 
                /* A 64-bit BAR takes the high half of the address in the next BAR */
                if (!(Bar & PCI_ADDRESS_IO_SPACE) &&
                    ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT) &&
                    ((i + 1) < PCI_TYPE1_ADDRESSES))
                {
                    i++;
                    BarArray[i] = Address.HighPart;
                }
            }
            else if (i < 5)
            {
                PciBridgeOpenWindow(PciData, i, CmDescriptor);
            }
            else
            {
                /* The ROM decodes only while its enable bit is set */
                Bar = PciData->u.type1.ROMBaseAddress &
                      ~(PCI_ADDRESS_ROM_ADDRESS_MASK | PCI_ROMADDRESS_ENABLED);
                if (CmDescriptor->Type != CmResourceTypeNull)
                {
                    Bar |= (Address.LowPart & PCI_ADDRESS_ROM_ADDRESS_MASK) |
                           PCI_ROMADDRESS_ENABLED;
                }
 
                PciData->u.type1.ROMBaseAddress = Bar;
            }
        }
    }
 
    /* Copy the bus number data */
    PciData->u.type1.PrimaryBus = PdoExtension->Dependent.type1.PrimaryBus;
    PciData->u.type1.SecondaryBus = PdoExtension->Dependent.type1.SecondaryBus;
    PciData->u.type1.SubordinateBus = PdoExtension->Dependent.type1.SubordinateBus;
 
    /* Copy the decode flags */
    if (PdoExtension->Dependent.type1.IsaBitSet)
    {
        PciData->u.type1.BridgeControl |= PCI_ENABLE_BRIDGE_ISA;
    }
 
    if (PdoExtension->Dependent.type1.VgaBitSet)
    {
        PciData->u.type1.BridgeControl |= PCI_ENABLE_BRIDGE_VGA;
    }
 
    return STATUS_SUCCESS;
}

◆ PPBridge_GetAdditionalResourceDescriptors()

VOID NTAPI PPBridge_GetAdditionalResourceDescriptors	(	IN PPCI_CONFIGURATOR_CONTEXT	Context,
		IN PPCI_COMMON_HEADER	PciData,
		IN PIO_RESOURCE_DESCRIPTOR	IoDescriptor
	)

Definition at line 657 of file ppbridge.c.

{
 
    UNREFERENCED_PARAMETER(Context);
 
    /* Does this bridge have VGA decodes on it? */
    if (PciData->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA)
    {
        /* Build a private descriptor with 3 entries */
        IoDescriptor->Type = CmResourceTypeDevicePrivate;
        IoDescriptor->u.DevicePrivate.Data[0] = 3;
        IoDescriptor->u.DevicePrivate.Data[1] = 3;
 
        /* First, the VGA range at 0xA0000 */
        IoDescriptor[1].Type = CmResourceTypeMemory;
        IoDescriptor[1].Flags = CM_RESOURCE_MEMORY_READ_WRITE;
        IoDescriptor[1].u.Port.Length = 0x20000;
        IoDescriptor[1].u.Port.Alignment = 1;
        IoDescriptor[1].u.Port.MinimumAddress.QuadPart = 0xA0000;
        IoDescriptor[1].u.Port.MaximumAddress.QuadPart = 0xBFFFF;
 
        /* Then, the VGA registers at 0x3B0 */
        IoDescriptor[2].Type = CmResourceTypePort;
        IoDescriptor[2].Flags = CM_RESOURCE_PORT_POSITIVE_DECODE |
                                CM_RESOURCE_PORT_10_BIT_DECODE;
        IoDescriptor[2].u.Port.Length = 12;
        IoDescriptor[2].u.Port.Alignment = 1;
        IoDescriptor[2].u.Port.MinimumAddress.QuadPart = 0x3B0;
        IoDescriptor[2].u.Port.MaximumAddress.QuadPart = 0x3BB;
 
        /* And finally the VGA registers at 0x3C0 */
        IoDescriptor[3].Type = CmResourceTypePort;
        IoDescriptor[3].Flags = CM_RESOURCE_PORT_POSITIVE_DECODE |
                                CM_RESOURCE_PORT_10_BIT_DECODE;
        IoDescriptor[3].u.Port.Length = 32;
        IoDescriptor[3].u.Port.Alignment = 1;
        IoDescriptor[3].u.Port.MinimumAddress.QuadPart = 0x3C0;
        IoDescriptor[3].u.Port.MaximumAddress.QuadPart = 0x3DF;
    }
}

Referenced by Cardbus_GetAdditionalResourceDescriptors().

◆ PPBridge_MassageHeaderForLimitsDetermination()

VOID NTAPI PPBridge_MassageHeaderForLimitsDetermination ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 611 of file ppbridge.c.

{
    PPCI_COMMON_HEADER PciData, Current;
 
    /* Get pointers from context */
    PciData = Context->PciData;
    Current = Context->Current;
 
    /*
     * Write FFh everywhere so that the PCI bridge ignores what it can't handle.
     * Based on the bits that were ignored (still 0), this is how we can tell
     * what the limit is.
     */
    RtlFillMemory(PciData->u.type1.BaseAddresses,
                  FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.CapabilitiesPtr) -
                  FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.BaseAddresses),
                  0xFF);
 
    /* Copy the saved settings from the current context into the PCI header */
    PciData->u.type1.PrimaryBus = Current->u.type1.PrimaryBus;
    PciData->u.type1.SecondaryBus = Current->u.type1.SecondaryBus;
    PciData->u.type1.SubordinateBus = Current->u.type1.SubordinateBus;
    PciData->u.type1.SecondaryLatency = Current->u.type1.SecondaryLatency;
 
    /* No I/O limit or base. The bottom base bit specifies that FIXME */
    PciData->u.type1.IOBaseUpper16 = 0xFFFE;
    PciData->u.type1.IOLimitUpper16 = 0xFFFF;
 
    /* Save secondary status before it gets cleared */
    Context->SecondaryStatus = Current->u.type1.SecondaryStatus;
 
    /* Clear secondary status */
    Current->u.type1.SecondaryStatus = 0;
    PciData->u.type1.SecondaryStatus = 0;
}

◆ PPBridge_ResetDevice()

VOID NTAPI PPBridge_ResetDevice	(	IN PPCI_PDO_EXTENSION	PdoExtension,
		IN PPCI_COMMON_HEADER	PciData
	)

Definition at line 702 of file ppbridge.c.

{
    UNREFERENCED_PARAMETER(PdoExtension);
 
    /* Never write the header back with the secondary bus held in reset */
    PciData->u.type1.BridgeControl &= ~PCI_ASSERT_BRIDGE_RESET;
}

◆ PPBridge_RestoreCurrent()

VOID NTAPI PPBridge_RestoreCurrent ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 649 of file ppbridge.c.

{
    /* Copy back the secondary status register */
    Context->Current->u.type1.SecondaryStatus = Context->SecondaryStatus;
}

◆ PPBridge_SaveCurrentSettings()

VOID NTAPI PPBridge_SaveCurrentSettings ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 227 of file ppbridge.c.

{
    NTSTATUS Status;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
    PIO_RESOURCE_DESCRIPTOR IoDescriptor;
    PPCI_FUNCTION_RESOURCES Resources;
    PCI_COMMON_HEADER BiosData;
    PPCI_COMMON_HEADER Current;
    PPCI_COMMON_CONFIG SavedConfig;
    ULONG i, Bar, BarMask;
    PULONG BarArray;
    PHYSICAL_ADDRESS Limit, Base, Length;
    BOOLEAN HaveIoLimit, CheckAlignment;
    PPCI_PDO_EXTENSION PdoExtension;
 
    /* Get the pointers from the extension */
    PdoExtension = Context->PdoExtension;
    Resources = PdoExtension->Resources;
    Current = Context->Current;
 
    /* Check if decodes are disabled */
    if (!(Context->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE)))
    {
        /* Well, we're going to need them from somewhere, use the registry data */
        Status = PciGetBiosConfig(PdoExtension, &BiosData);
        if (NT_SUCCESS(Status)) Current = &BiosData;
    }
 
    /* Scan all current and limit descriptors for each BAR needed */
    BarArray = Current->u.type1.BaseAddresses;
    for (i = 0; i < 6; i++)
    {
        /* Get the current resource descriptor, and the limit requirement */
        CmDescriptor = &Resources->Current[i];
        IoDescriptor = &Resources->Limit[i];
 
        /* Copy descriptor data, skipping null descriptors */
        CmDescriptor->Type = IoDescriptor->Type;
        if (CmDescriptor->Type == CmResourceTypeNull) continue;
        CmDescriptor->Flags = IoDescriptor->Flags;
        CmDescriptor->ShareDisposition = IoDescriptor->ShareDisposition;
 
        /* Initialize the high-parts to zero, since most stuff is 32-bit only */
        Base.QuadPart = Limit.QuadPart = Length.QuadPart = 0;
 
        /* Check if we're handling PCI BARs, or the ROM BAR */
        if ((i < PCI_TYPE1_ADDRESSES) || (i == 5))
        {
            /* Is this the ROM BAR? */
            if (i == 5)
            {
                /* Read the correct bar, with the appropriate mask */
                Bar = Current->u.type1.ROMBaseAddress;
                BarMask = PCI_ADDRESS_ROM_ADDRESS_MASK;
 
                /* Decode the base address, and write down the length */
                Base.LowPart = Bar & BarMask;
                DPRINT1("PCIX - ROM BAR Base: %lx\n", Base.LowPart);
                CmDescriptor->u.Memory.Length = IoDescriptor->u.Memory.Length;
            }
            else
            {
                /* Otherwise, get the BAR from the array */
                Bar = BarArray[i];
 
                /* Is this an I/O BAR? */
                if (Bar & PCI_ADDRESS_IO_SPACE)
                {
                    /* Set the correct mask */
                    ASSERT(CmDescriptor->Type == CmResourceTypePort);
                    BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
                }
                else
                {
                    /* This is a memory BAR, set the correct base */
                    ASSERT((CmDescriptor->Type == CmResourceTypeMemory) ||
                           (CmDescriptor->Type == CmResourceTypeMemoryLarge));
                    BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
 
                    /* IS this a 64-bit BAR? */
                    if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
                    {
                        /* Read the next 32-bits as well, ie, the next BAR */
                        Base.HighPart = BarArray[i + 1];
                    }
                }
 
                /* Decode the base address, and write down the length */
                Base.LowPart = Bar & BarMask;
                DPRINT1("PCIX - BAR Base: %lx\n", Base.LowPart);
                CmDescriptor->u.Generic.Length = IoDescriptor->u.Generic.Length;
            }
        }
        else
        {
            /* Reset loop conditions */
            HaveIoLimit = FALSE;
            CheckAlignment = FALSE;
 
            /* Check which descriptor is being parsed */
            if (i == 2)
            {
                /* I/O Port Requirements */
                Base.LowPart = PciBridgeIoBase(Current);
                Limit.LowPart = PciBridgeIoLimit(Current);
                DPRINT1("PCIX - Bridge I/O Base and Limit: %lx %lx\n",
                         Base.LowPart, Limit.LowPart);
 
                /* Do we have any I/O Port data? */
                if (!(Base.LowPart) && (Current->u.type1.IOLimit))
                {
                    /* There's a limit */
                    HaveIoLimit = TRUE;
                }
            }
            else if (i == 3)
            {
                /* Memory requirements */
                Base.LowPart = PciBridgeMemoryBase(Current);
                Limit.LowPart = PciBridgeMemoryLimit(Current);
 
                /* These should always be there, so check their alignment */
                DPRINT1("PCIX - Bridge MEM Base and Limit: %lx %lx\n",
                         Base.LowPart, Limit.LowPart);
                CheckAlignment = TRUE;
            }
            else if (i == 4)
            {
                /* This should only be present for prefetch memory */
                ASSERT(CmDescriptor->Flags & CM_RESOURCE_MEMORY_PREFETCHABLE);
                Base = PciBridgePrefetchMemoryBase(Current);
                Limit = PciBridgePrefetchMemoryLimit(Current);
 
                /* If it's there, check the alignment */
                DPRINT1("PCIX - Bridge Prefetch MEM Base and Limit: %I64x %I64x\n", Base, Limit);
                CheckAlignment = TRUE;
            }
 
            /* Check for invalid base address */
            if (Base.QuadPart >= Limit.QuadPart)
            {
                /* Assume the descriptor is bogus */
                CmDescriptor->Type = CmResourceTypeNull;
                IoDescriptor->Type = CmResourceTypeNull;
                continue;
            }
 
            /* Check if there's no memory, and no I/O port either */
            if (!(Base.QuadPart) && !(HaveIoLimit))
            {
                /* This seems like a bogus requirement, ignore it */
                CmDescriptor->Type = CmResourceTypeNull;
                continue;
            }
 
            /* The window spans its base through its limit */
            Length.QuadPart = Limit.QuadPart - Base.QuadPart + 1;
 
            /* Junk in the upper prefetch limit would give a window no descriptor can hold */
            if (((ULONGLONG)Length.QuadPart > CM_RESOURCE_MEMORY_LARGE_48_MAXLEN) &&
                (Limit.HighPart > Base.HighPart) &&
                (Limit.LowPart > Base.LowPart))
            {
                DPRINT1("PCIX - Bridge prefetch limit %I64x has junk in its upper half\n",
                        Limit.QuadPart);
                Limit.HighPart = Base.HighPart;
                Length.QuadPart = Limit.QuadPart - Base.QuadPart + 1;
            }
 
            /* A prefetchable window of 4GB or more takes the large memory form */
            Status = RtlCmEncodeMemIoResource(CmDescriptor,
                                              CmDescriptor->Type,
                                              Length.QuadPart,
                                              Base.QuadPart);
            if (!NT_SUCCESS(Status))
            {
                CmDescriptor->Type = CmResourceTypeNull;
                continue;
            }
 
            /* Check if alignment should be set */
            if (CheckAlignment)
            {
                /* Compute the required alignment for this length, 2GB at most */
                if (Length.HighPart)
                {
                    IoDescriptor->u.Memory.Alignment = 0x80000000;
                }
                else
                {
                    IoDescriptor->u.Memory.Alignment =
                        PciBridgeMemoryWorstCaseAlignment(Length.LowPart);
                }
            }
        }
 
        /* Now set the base address */
        CmDescriptor->u.Generic.Start = Base;
    }
 
    /* Save PCI settings into the PDO extension for easy access later */
    PdoExtension->Dependent.type1.PrimaryBus = Current->u.type1.PrimaryBus;
    PdoExtension->Dependent.type1.SecondaryBus = Current->u.type1.SecondaryBus;
    PdoExtension->Dependent.type1.SubordinateBus = Current->u.type1.SubordinateBus;
 
    /* Check for subtractive decode bridges */
    if (PdoExtension->Dependent.type1.SubtractiveDecode)
    {
        /* Check if legacy VGA decodes are enabled */
        DPRINT1("PCIX - Subtractive decode bridge\n");
        if (Current->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA)
        {
            /* Save this setting for later */
            DPRINT1("PCIX - VGA Bridge\n");
            PdoExtension->Dependent.type1.VgaBitSet = TRUE;
        }
 
        /* Legacy ISA decoding is not compatible with subtractive decode */
        ASSERT(PdoExtension->Dependent.type1.IsaBitSet == FALSE);
    }
    else
    {
        /* Check if legacy VGA decodes are enabled */
        if (Current->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA)
        {
            /* Save this setting for later */
            DPRINT1("PCIX - VGA Bridge\n");
            PdoExtension->Dependent.type1.VgaBitSet = TRUE;
 
            /* And on positive decode, we'll also need extra resources locked */
            PdoExtension->AdditionalResourceCount = 4;
        }
 
        /* Check if legacy ISA decoding is enabled */
        if (Current->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_ISA)
        {
            /* Save this setting for later */
            DPRINT1("PCIX - ISA Bridge\n");
            PdoExtension->Dependent.type1.IsaBitSet = TRUE;
        }
    }
 
    /*
     * Check for Intel ICH PCI-to-PCI (i82801) bridges (used on the i810,
     * i820, i840, i845 Chipsets) that have subtractive decode broken.
     */
    if (((PdoExtension->VendorId == 0x8086) &&
         ((PdoExtension->DeviceId == 0x2418) ||
          (PdoExtension->DeviceId == 0x2428) ||
          (PdoExtension->DeviceId == 0x244E) ||
          (PdoExtension->DeviceId == 0x2448))) ||
        (PdoExtension->HackFlags & PCI_HACK_BROKEN_SUBTRACTIVE_DECODE))
    {
        /* Check if subtractive decode is actually enabled */
        if (PdoExtension->Dependent.type1.SubtractiveDecode)
        {
            /* We're going to need a copy of the configuration for later use */
            DPRINT1("PCIX - apply config save hack to ICH subtractive decode\n");
            SavedConfig = ExAllocatePoolWithTag(0, PCI_COMMON_HDR_LENGTH, TAG_PCI_PRESERVED);
            PdoExtension->ParentFdoExtension->PreservedConfig = SavedConfig;
            if (SavedConfig) RtlCopyMemory(SavedConfig, Current, PCI_COMMON_HDR_LENGTH);
        }
    }
}

◆ PPBridge_SaveLimits()

VOID NTAPI PPBridge_SaveLimits ( IN PPCI_CONFIGURATOR_CONTEXT Context )

Definition at line 494 of file ppbridge.c.

{
    PIO_RESOURCE_DESCRIPTOR Limit;
    PULONG BarArray;
    PHYSICAL_ADDRESS MemoryLimit;
    ULONG i;
    PPCI_COMMON_HEADER Working;
    PPCI_PDO_EXTENSION PdoExtension;
 
    /* Get the pointers from the context */
    Working = Context->PciData;
    PdoExtension = Context->PdoExtension;
 
    /* Scan the BARs into the limit descriptors */
    BarArray = Working->u.type1.BaseAddresses;
    Limit = PdoExtension->Resources->Limit;
 
    /* First of all, loop all the BARs */
    for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
    {
        /* Create a descriptor for their limits, the second BAR has no BAR after it */
        ULONG NextBar = ((i + 1) < PCI_TYPE1_ADDRESSES) ? BarArray[i + 1] : 0;
 
        if (PciCreateIoDescriptorFromBarLimit(&Limit[i], BarArray[i], NextBar, FALSE))
        {
            /* This was a 64-bit descriptor, make sure there's space */
            ASSERT((i + 1) < PCI_TYPE1_ADDRESSES);
 
            /* Skip the next descriptor since this one is double sized */
            i++;
            Limit[i].Type = CmResourceTypeNull;
        }
    }
 
    /* Check if this is a subtractive decode bridge */
    if (PciBridgeIsSubtractiveDecode(Context))
    {
        /* This bridge is subtractive */
        PdoExtension->Dependent.type1.SubtractiveDecode = TRUE;
 
        /* Subtractive bridges cannot use legacy ISA or VGA functionality */
        PdoExtension->Dependent.type1.IsaBitSet = FALSE;
        PdoExtension->Dependent.type1.VgaBitSet = FALSE;
    }
 
    /* For normal decode bridges, we'll need to find the bridge limits too */
    if (!PdoExtension->Dependent.type1.SubtractiveDecode)
    {
        /* Loop the descriptors that are left, to store the bridge limits */
        for (i = PCI_TYPE1_ADDRESSES; i < 5; i++)
        {
            /* No 64-bit memory addresses, and set the address to 0 to begin */
            MemoryLimit.HighPart = 0;
            (&Limit[i])->u.Port.MinimumAddress.QuadPart = 0;
 
            /* Are we getting the I/O limit? */
            if (i == 2)
            {
                /* There should be one, get it */
                ASSERT(Working->u.type1.IOLimit != 0);
                ASSERT((Working->u.type1.IOLimit & 0x0E) == 0);
                MemoryLimit.LowPart = PciBridgeIoLimit(Working);
 
                /* Build a descriptor for this limit */
                (&Limit[i])->Type = CmResourceTypePort;
                (&Limit[i])->Flags = CM_RESOURCE_PORT_WINDOW_DECODE |
                                     CM_RESOURCE_PORT_POSITIVE_DECODE;
                (&Limit[i])->u.Port.Alignment = 0x1000;
                (&Limit[i])->u.Port.MinimumAddress.QuadPart = 0;
                (&Limit[i])->u.Port.MaximumAddress = MemoryLimit;
                (&Limit[i])->u.Port.Length = 0;
            }
            else if (i == 3)
            {
                /* There should be a valid memory limit, get it */
                ASSERT((Working->u.type1.MemoryLimit & 0xF) == 0);
                MemoryLimit.LowPart = PciBridgeMemoryLimit(Working);
 
                /* Build the descriptor for it */
                (&Limit[i])->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
                (&Limit[i])->Type = CmResourceTypeMemory;
                (&Limit[i])->u.Memory.Alignment = 0x100000;
                (&Limit[i])->u.Memory.MinimumAddress.QuadPart = 0;
                (&Limit[i])->u.Memory.MaximumAddress = MemoryLimit;
                (&Limit[i])->u.Memory.Length = 0;
            }
            else if (Working->u.type1.PrefetchLimit)
            {
                /* Get the prefetch memory limit, if there is one */
                MemoryLimit = PciBridgePrefetchMemoryLimit(Working);
 
                /* Write out the descriptor for it */
                (&Limit[i])->Flags = CM_RESOURCE_MEMORY_PREFETCHABLE;
                (&Limit[i])->Type = CmResourceTypeMemory;
                (&Limit[i])->u.Memory.Alignment = 0x100000;
                (&Limit[i])->u.Memory.MinimumAddress.QuadPart = 0;
                (&Limit[i])->u.Memory.MaximumAddress = MemoryLimit;
                (&Limit[i])->u.Memory.Length = 0;
            }
            else
            {
                /* Blank descriptor */
                (&Limit[i])->Type = CmResourceTypeNull;
            }
        }
    }
 
    /* Does the ROM have its own BAR? */
    if (Working->u.type1.ROMBaseAddress & PCI_ROMADDRESS_ENABLED)
    {
        /* Build a limit for it as well */
        PciCreateIoDescriptorFromBarLimit(&Limit[i], Working->u.type1.ROMBaseAddress, 0, TRUE);
    }
}

◆ routeintrf_Constructor()

NTSTATUS NTAPI routeintrf_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 236 of file routintf.c.

{
    PINT_ROUTE_INTERFACE_STANDARD RouteInterface = (PINT_ROUTE_INTERFACE_STANDARD)Interface;
    PAGED_CODE();
 
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(InterfaceData);
    UNREFERENCED_PARAMETER(Size);
 
    /* Only version 1 is supported */
    if (Version != PCI_INT_ROUTE_INTRF_STANDARD_VER) return STATUS_NOINTERFACE;
 
    RouteInterface->Size = sizeof(*RouteInterface);
    RouteInterface->Version = PCI_INT_ROUTE_INTRF_STANDARD_VER;
    RouteInterface->Context = DeviceExtension;
    RouteInterface->InterfaceReference = routeintrf_Reference;
    RouteInterface->InterfaceDereference = routeintrf_Dereference;
    RouteInterface->GetInterruptRouting = routeintrf_GetInterruptRouting;
    RouteInterface->SetInterruptRoutingToken = routeintrf_SetInterruptRoutingToken;
    RouteInterface->UpdateInterruptLine = routeintrf_UpdateInterruptLine;
    return STATUS_SUCCESS;
}

◆ routeintrf_Initializer()

NTSTATUS NTAPI routeintrf_Initializer ( IN PVOID Instance )

Definition at line 37 of file routintf.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI routeintrf_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

◆ tranirq_Constructor()

NTSTATUS NTAPI tranirq_Constructor	(	IN PVOID	DeviceExtension,
		IN PVOID	Instance,
		IN PVOID	InterfaceData,
		IN USHORT	Version,
		IN USHORT	Size,
		IN PINTERFACE	Interface
	)

Definition at line 45 of file tr_irq.c.

{
    PPCI_FDO_EXTENSION FdoExtension = (PPCI_FDO_EXTENSION)DeviceExtension;
    ULONG BaseBus, ParentBus;
    INTERFACE_TYPE ParentInterface;
    ASSERT_FDO(FdoExtension);
 
    UNREFERENCED_PARAMETER(Instance);
    UNREFERENCED_PARAMETER(Version);
    UNREFERENCED_PARAMETER(Size);
 
    /* Make sure it's the right resource type */
    if ((ULONG_PTR)InterfaceData != CmResourceTypeInterrupt)
    {
        /* Fail this invalid request */
        DPRINT1("PCIX - IRQ trans constructor doesn't like %p in InterfaceSpecificData\n",
                InterfaceData);
        return STATUS_INVALID_PARAMETER_3;
    }
 
    /* Get the bus, and use this as the interface-specific data */
    BaseBus = FdoExtension->BaseBus;
    InterfaceData = UlongToPtr(BaseBus);
 
    /* Check if this is the root bus */
    if (PCI_IS_ROOT_FDO(FdoExtension))
    {
        /* It is, so there is no parent, and it's connected on the system bus */
        ParentBus = 0;
        ParentInterface = Internal;
        DPRINT1("      Is root FDO\n");
    }
    else
    {
        /* It's not, so the translator is rooted on the bus the bridge sits on */
        PPCI_PDO_EXTENSION PdoExtension = FdoExtension->PhysicalDeviceObject->DeviceExtension;
        ASSERT_PDO(PdoExtension);
        ParentBus = PdoExtension->ParentFdoExtension->BaseBus;
        ParentInterface = PCIBus;
        DPRINT1("      Is bridge FDO, parent bus %x, secondary bus %x\n",
                ParentBus, BaseBus);
    }
 
    /* Now call the legacy HAL interface to get the correct translator */
    return HalGetInterruptTranslator(ParentInterface,
                                     ParentBus,
                                     PCIBus,
                                     sizeof(TRANSLATOR_INTERFACE),
                                     0,
                                     (PTRANSLATOR_INTERFACE)Interface,
                                     (PULONG)&InterfaceData);
}

◆ tranirq_Initializer()

NTSTATUS NTAPI tranirq_Initializer ( IN PVOID Instance )

Definition at line 35 of file tr_irq.c.

{
    UNREFERENCED_PARAMETER(Instance);
    /* PnP Interfaces don't get Initialized */
    ASSERTMSG("PCI tranirq_Initializer, unexpected call.\n", FALSE);
    return STATUS_UNSUCCESSFUL;
}

Variable Documentation

◆ AgpTargetInterface

PCI_INTERFACE AgpTargetInterface

extern

Definition at line 20 of file agpintrf.c.

◆ ArbiterInterfaceBusNumber

PCI_INTERFACE ArbiterInterfaceBusNumber

extern

Definition at line 18 of file ar_busno.c.

◆ ArbiterInterfaceIo

PCI_INTERFACE ArbiterInterfaceIo

extern

Definition at line 31 of file ar_memio.c.

◆ ArbiterInterfaceMemory

PCI_INTERFACE ArbiterInterfaceMemory

extern

Definition at line 18 of file ar_memio.c.

◆ BusHandlerInterface

PCI_INTERFACE BusHandlerInterface

extern

Definition at line 18 of file busintrf.c.

◆ PciAddDevice

DRIVER_ADD_DEVICE PciAddDevice

Definition at line 683 of file pci.h.

◆ PciAssignBusNumbers

BOOLEAN PciAssignBusNumbers

extern

Definition at line 18 of file config.c.

Referenced by PciGetConfigHandlers(), PciProcessBus(), and PciReadWriteConfigSpace().

◆ PciCardbusPrivateInterface

PCI_INTERFACE PciCardbusPrivateInterface

extern

Definition at line 18 of file cardbus.c.

◆ PciDebuggingDevices

PCI_DEBUGGING_DEVICE PciDebuggingDevices[MAX_DEBUGGING_DEVICES_SUPPORTED]

extern

Definition at line 18 of file utils.c.

Referenced by PciGetDebugPorts(), and PciIsDeviceOnDebugPath().

◆ PciDebugPortsCount

ULONG PciDebugPortsCount

extern

Definition at line 19 of file utils.c.

Referenced by PciGetDebugPorts(), and PciIsDeviceOnDebugPath().

◆ PciDevicePresentInterface

PCI_INTERFACE PciDevicePresentInterface

extern

Definition at line 18 of file devhere.c.

Referenced by PdoQueryInterface(), and VideoPortCheckForDeviceExistence().

◆ PciDispatchIrp

DRIVER_DISPATCH PciDispatchIrp

Definition at line 605 of file pci.h.

Referenced by DriverEntry().

◆ PciDriverObject

PDRIVER_OBJECT PciDriverObject

extern

Definition at line 19 of file init.c.

Referenced by DriverEntry(), PciGetDescriptionMessage(), and routeintrf_FindDevice().

◆ PciEcamVerified

BOOLEAN PciEcamVerified

extern

Definition at line 20 of file ecam.c.

Referenced by PciEcamReadWriteConfig(), PciGetExpressCapabilities(), PciInitializeEcam(), and PciReleaseEcam().

◆ PciEnableNativeModeATA

BOOLEAN PciEnableNativeModeATA

extern

Definition at line 24 of file init.c.

Referenced by DriverEntry(), and PciApplyHacks().

◆ PciExecuteCriticalSystemRoutine

KIPI_BROADCAST_WORKER PciExecuteCriticalSystemRoutine

Definition at line 1204 of file pci.h.

Referenced by PcipGetFunctionLimits(), and PciUpdateHardware().

◆ PciFdoExtensionListHead

SINGLE_LIST_ENTRY PciFdoExtensionListHead

extern

Definition at line 18 of file fdo.c.

Referenced by _Requires_lock_held_(), devpresent_SearchAllBuses(), PciAddDevice(), PciDriverUnload(), PciFdoIrpRemoveDevice(), PciFindParentPciFdoExtension(), and PciVerifierCheckAllBridges().

◆ PciGlobalLock

KEVENT PciGlobalLock

extern

Definition at line 20 of file init.c.

Referenced by devpresent_SearchAllBuses(), DriverEntry(), PciAddDevice(), PciAssignSlotResources(), PciFdoIrpRemoveDevice(), and PciVerifierCheckAllBridges().

◆ PciHackTable

PPCI_HACK_ENTRY PciHackTable

extern

Definition at line 28 of file init.c.

Referenced by PciBuildHackTable(), PciDriverUnload(), and PciGetHackFlags().

◆ PciInterfaces

PPCI_INTERFACE PciInterfaces[]

extern

Definition at line 18 of file intrface.c.

Referenced by PciInitializeArbiters(), and PciQueryInterface().

◆ PciIrqRoutingTable

PPCI_IRQ_ROUTING_TABLE PciIrqRoutingTable

extern

Definition at line 26 of file init.c.

Referenced by DriverEntry(), PciDetermineSlotNumber(), and PciDriverUnload().

◆ PciIsaBitExclusionList

RTL_RANGE_LIST PciIsaBitExclusionList

extern

Definition at line 21 of file utils.c.

Referenced by PciBuildDefaultExclusionLists(), and PciDriverUnload().

◆ PciLegacyDeviceDetectionInterface

PCI_INTERFACE PciLegacyDeviceDetectionInterface

extern

Definition at line 18 of file lddintrf.c.

◆ PciLocationInterface

PCI_INTERFACE PciLocationInterface

extern

Definition at line 18 of file locintrf.c.

◆ PciPmeInterface

PCI_INTERFACE PciPmeInterface

extern

Definition at line 18 of file pmeintf.c.

◆ PciRoutingInterface

PCI_INTERFACE PciRoutingInterface

extern

Definition at line 20 of file routintf.c.

◆ PciRunningDatacenter

BOOLEAN PciRunningDatacenter

extern

Definition at line 18 of file init.c.

Referenced by DriverEntry().

◆ PciVgaAndIsaBitExclusionList

RTL_RANGE_LIST PciVgaAndIsaBitExclusionList

extern

Definition at line 22 of file utils.c.

Referenced by PciBuildDefaultExclusionLists(), and PciDriverUnload().

◆ PciZeroIoResourceRequirements

PIO_RESOURCE_REQUIREMENTS_LIST PciZeroIoResourceRequirements

extern

Definition at line 18 of file enum.c.

Referenced by PciAssignAndProgramLegacy(), PciBuildRequirementsList(), PciDriverUnload(), and PciQueryRequirements().

◆ TranslatorInterfaceInterrupt

PCI_INTERFACE TranslatorInterfaceInterrupt

extern

Definition at line 18 of file tr_irq.c.

◆ WdTable

PWATCHDOG_TABLE WdTable

extern

Definition at line 27 of file init.c.

Referenced by PciDriverUnload(), and PciScanBus().

Classes

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

◆ ARBITER_INTERFACE_VERSION

◆ ASSERT_FDO

◆ ASSERT_PDO

◆ MAX_ANSI_STRINGS

◆ MAX_DEBUGGING_DEVICES_SUPPORTED

◆ PCI_HACK_ENTRY_FULL_SIZE

◆ PCI_HACK_ENTRY_REV_SIZE

◆ PCI_HACK_ENTRY_SIZE

◆ PCI_HACK_ENTRY_SUBSYS_SIZE

◆ PCI_HACK_FIXUP_AFTER_CONFIGURATION

◆ PCI_HACK_FIXUP_BEFORE_CONFIGURATION

◆ PCI_HACK_FIXUP_BEFORE_UPDATE

◆ PCI_HACK_HAS_REVISION_INFO

◆ PCI_HACK_HAS_SUBSYSTEM_INFO

◆ PCI_INTERFACE_FDO

◆ PCI_INTERFACE_PDO

◆ PCI_INTERFACE_ROOT

◆ PCI_INTERRUPT_LINE_UNKNOWN

◆ PCI_IS_ROOT_FDO

◆ PCI_LEGACY_CONFIG_LENGTH

◆ PCI_POOL_TAG

◆ PCI_RBAR_CAPABILITY_SIZES_SHIFT

◆ PCI_RBAR_CONTROL_BAR_INDEX_MASK

◆ PCI_RBAR_CONTROL_COUNT_MASK

◆ PCI_RBAR_CONTROL_COUNT_SHIFT

◆ PCI_RBAR_CONTROL_SIZE_MASK

◆ PCI_RBAR_CONTROL_SIZE_SHIFT

◆ PCI_RBAR_ENTRY_CAPABILITY

◆ PCI_RBAR_ENTRY_CONTROL

◆ PCI_RBAR_EXTENDED_CAP_ID

◆ PCI_RBAR_MAX_ENTRIES

◆ PCI_SKIP_DEVICE_ENUMERATION

◆ PCI_SKIP_RESOURCE_ENUMERATION

◆ PCI_VERIFIER_CODES

◆ TAG_PCI_PRESERVED

◆ TAG_PCI_ROUTING

Typedef Documentation

◆ PCI_ARBITER_INSTANCE

◆ PCI_CONFIGURATOR

◆ PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS

◆ PCI_CONFIGURATOR_CONTEXT

◆ PCI_CONFIGURATOR_GET_ADDITIONAL_RESOURCE_DESCRIPTORS

◆ PCI_CONFIGURATOR_INITIALIZE

◆ PCI_CONFIGURATOR_RESET_DEVICE

◆ PCI_CONFIGURATOR_RESTORE_CURRENT

◆ PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS

◆ PCI_CONFIGURATOR_SAVE_LIMITS

◆ PCI_DEBUGGING_DEVICE

◆ PCI_DEVICE_TYPES

◆ PCI_DISPATCH_FUNCTION

◆ PCI_DISPATCH_STYLE

◆ PCI_FDO_EXTENSION

◆ PCI_FUNCTION_RESOURCES

◆ PCI_HACK_ENTRY

◆ PCI_HEADER_TYPE_DEPENDENT

◆ PCI_ID_BUFFER

◆ PCI_INTERFACE

◆ PCI_INTERFACE_CONSTRUCTOR

◆ PCI_INTERFACE_INITIALIZER

◆ PCI_IPI_CONTEXT

◆ PCI_IPI_FUNCTION

◆ PCI_LEGACY_DEVICE

◆ PCI_LOCK

◆ PCI_MJ_DISPATCH_TABLE

◆ PCI_MN_DISPATCH_TABLE

◆ PCI_PDO_EXTENSION

◆ PCI_POWER_STATE

◆ PCI_RESIZABLE_BAR_STATE

◆ PCI_SECONDARY_EXTENSION

◆ PCI_SIGNATURE

◆ PCI_STATE

◆ PCI_VERIFIER_DATA

◆ PPCI_ARBITER_INSTANCE