ReactOS 0.4.17-dev-966-gf06eace
enum.c
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1/*
2 * PROJECT: ReactOS PCI Bus Driver
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: drivers/bus/pci/enum.c
5 * PURPOSE: PCI Bus/Device Enumeration
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9/* INCLUDES *******************************************************************/
10
11#include <pci.h>
12
13#define NDEBUG
14#include <debug.h>
15
16/* GLOBALS ********************************************************************/
17
18PIO_RESOURCE_REQUIREMENTS_LIST PciZeroIoResourceRequirements;
19
20PCI_CONFIGURATOR PciConfigurators[] =
21{
22 {
23 Device_MassageHeaderForLimitsDetermination,
24 Device_RestoreCurrent,
25 Device_SaveLimits,
26 Device_SaveCurrentSettings,
27 Device_ChangeResourceSettings,
28 Device_GetAdditionalResourceDescriptors,
29 Device_ResetDevice
30 },
31 {
32 PPBridge_MassageHeaderForLimitsDetermination,
33 PPBridge_RestoreCurrent,
34 PPBridge_SaveLimits,
35 PPBridge_SaveCurrentSettings,
36 PPBridge_ChangeResourceSettings,
37 PPBridge_GetAdditionalResourceDescriptors,
38 PPBridge_ResetDevice
39 },
40 {
41 Cardbus_MassageHeaderForLimitsDetermination,
42 Cardbus_RestoreCurrent,
43 Cardbus_SaveLimits,
44 Cardbus_SaveCurrentSettings,
45 Cardbus_ChangeResourceSettings,
46 Cardbus_GetAdditionalResourceDescriptors,
47 Cardbus_ResetDevice
48 }
49};
50
51/* FUNCTIONS ******************************************************************/
52
53BOOLEAN
54NTAPI
55PciComputeNewCurrentSettings(IN PPCI_PDO_EXTENSION PdoExtension,
56 IN PCM_RESOURCE_LIST ResourceList)
57{
58 PCM_PARTIAL_RESOURCE_DESCRIPTOR Partial, InterruptResource;
59 PCM_PARTIAL_RESOURCE_DESCRIPTOR CurrentDescriptor;
60 CM_PARTIAL_RESOURCE_DESCRIPTOR ResourceArray[7];
61 ULONG BarIndex;
62 PCM_FULL_RESOURCE_DESCRIPTOR FullList;
63 BOOLEAN RangeChange;
64 ULONG DrainPartial;
65 ULONG i, j;
66 PPCI_FUNCTION_RESOURCES PciResources;
67 PAGED_CODE();
68
69 /* Make sure we have either no resources, or at least one */
70 ASSERT((ResourceList == NULL) || (ResourceList->Count == 1));
71
72 /* Initialize no partial, interrupt descriptor, or range change */
73 Partial = NULL;
74 InterruptResource = NULL;
75 RangeChange = FALSE;
76 BarIndex = 0;
77
78 /* The limits say which BARs this function implements, so the walk below
79 * can tell which BAR each assigned descriptor belongs to */
80 PciResources = PdoExtension->Resources;
81
82 /* Check if there's not actually any resources */
83 if (!(ResourceList) || !(ResourceList->Count))
84 {
85 /* Then just return the hardware update state */
86 return PdoExtension->UpdateHardware;
87 }
88
89 /* Print the new specified resource list */
90 PciDebugPrintCmResList(ResourceList);
91
92 /* Clear the temporary resource array */
93 for (i = 0; i < 7; i++) ResourceArray[i].Type = CmResourceTypeNull;
94
95 /* Loop the full resource descriptor */
96 FullList = ResourceList->List;
97 for (i = 0; i < ResourceList->Count; i++)
98 {
99 /* Initialize loop variables */
100 DrainPartial = 0;
101
102 /* Loop the partial descriptors */
103 Partial = FullList->PartialResourceList.PartialDescriptors;
104 for (j = 0; j < FullList->PartialResourceList.Count; j++)
105 {
106 /* Check if we were supposed to drain a partial due to device data */
107 if (DrainPartial)
108 {
109 DrainPartial--;
110 Partial = CmiGetNextPartialDescriptor(Partial);
111 continue;
112 }
113
114 /* Check what kind of descriptor this was */
115 switch (Partial->Type)
116 {
117 /* Base BAR resources */
118 case CmResourceTypePort:
119 case CmResourceTypeMemory:
120 case CmResourceTypeMemoryLarge:
121 {
122 /*
123 * Skip legacy/shared resources (e.g., VGA ports 0x3B0-0x3DF, memory 0xA0000).
124 * should not be placed in the ResourceArray.
125 */
126 if (Partial->ShareDisposition != CmResourceShareDeviceExclusive && Partial->ShareDisposition != CmResourceShareDriverExclusive)
127 {
128 break;
129 }
130
131 /*
132 * The assigned descriptors come back in the order the
133 * requirements list asked for them, so walking the limits
134 * in that same order says which BAR this one satisfies.
135 */
136 if (PciResources)
137 {
138 while ((BarIndex < RTL_NUMBER_OF(ResourceArray)) &&
139 (PciResources->Limit[BarIndex].Type == CmResourceTypeNull))
140 {
141 BarIndex++;
142 }
143
144 if (BarIndex < RTL_NUMBER_OF(ResourceArray))
145 ResourceArray[BarIndex++] = *Partial;
146 }
147 break;
148 }
149 /* Interrupt resource */
150 case CmResourceTypeInterrupt:
151
152 /* Make sure it's a compatible (and the only) PCI interrupt */
153 ASSERT(InterruptResource == NULL);
154 ASSERT(Partial->u.Interrupt.Level == Partial->u.Interrupt.Vector);
155 InterruptResource = Partial;
156
157 /* Only 255 interrupts on x86/x64 hardware */
158 if (Partial->u.Interrupt.Level < 256)
159 {
160 /* Use the passed interrupt line */
161 PdoExtension->AdjustedInterruptLine = Partial->u.Interrupt.Level;
162 }
163 else
164 {
165 /* Invalid vector, so ignore it */
166 PdoExtension->AdjustedInterruptLine = 0;
167 }
168
169 break;
170
171 /* Check for specific device data */
172 case CmResourceTypeDevicePrivate:
173
174 /* Check what kind of data this was */
175 switch (Partial->u.DevicePrivate.Data[0])
176 {
177 /* Not used in the driver yet */
178 case 1:
179 UNIMPLEMENTED_DBGBREAK();
180 break;
181
182 /* Not used in the driver yet */
183 case 2:
184 UNIMPLEMENTED_DBGBREAK();
185 break;
186
187 /* A drain request */
188 case 3:
189 DrainPartial = Partial->u.DevicePrivate.Data[1];
190 break;
191 }
192 break;
193 }
194
195 /* Move to the next descriptor */
196 Partial = CmiGetNextPartialDescriptor(Partial);
197 }
198
199 /* We should be starting a new list now */
200 FullList = (PVOID)Partial;
201 }
202
203 /* A function with no discovered resources has nothing to update */
204 if (!PciResources) return FALSE;
205
206 /* Loop all the PCI function resources */
207 for (i = 0; i < RTL_NUMBER_OF(ResourceArray); i++)
208 {
209 /* Get the current function resource descriptor, and the new one */
210 CurrentDescriptor = &PciResources->Current[i];
211 Partial = &ResourceArray[i];
212
213 /* Check if this new descriptor is different than the old one */
214 if ((Partial->Type != CurrentDescriptor->Type) ||
215 ((Partial->Type != CmResourceTypeNull) &&
216 ((Partial->u.Generic.Start.QuadPart !=
217 CurrentDescriptor->u.Generic.Start.QuadPart) ||
218 (RtlCmDecodeMemIoResource(Partial, NULL) !=
219 RtlCmDecodeMemIoResource(CurrentDescriptor, NULL)))))
220 {
221 /* Record a change */
222 RangeChange = TRUE;
223
224 /* Was there a range before? */
225 if (CurrentDescriptor->Type != CmResourceTypeNull)
226 {
227 /* Print it */
228 DbgPrint(" Old range-\n");
229 PciDebugPrintPartialResource(CurrentDescriptor);
230 }
231 else
232 {
233 /* There was no range */
234 DbgPrint(" Previously unset range\n");
235 }
236
237 /* Print new one */
238 DbgPrint(" changed to\n");
239 PciDebugPrintPartialResource(Partial);
240
241 /* Update to new range */
242 CurrentDescriptor->Type = Partial->Type;
243 CurrentDescriptor->Flags = Partial->Flags;
244 CurrentDescriptor->u.Generic.Start = Partial->u.Generic.Start;
245 CurrentDescriptor->u.Generic.Length = Partial->u.Generic.Length;
246 }
247 }
248
249 /* Either the hardware was updated, or a resource range changed */
250 return ((RangeChange) || (PdoExtension->UpdateHardware));
251}
252
253VOID
254NTAPI
255PcipUpdateHardware(IN PVOID Context,
256 IN PVOID Context2)
257{
258 PPCI_PDO_EXTENSION PdoExtension = Context;
259 PPCI_COMMON_HEADER PciData = Context2;
260
261 /* Check if we're allowed to disable decodes */
262 PciData->Command = PdoExtension->CommandEnables;
263 if (!(PdoExtension->HackFlags & PCI_HACK_PRESERVE_COMMAND))
264 {
265 /* Disable all decodes */
266 PciData->Command &= ~(PCI_ENABLE_IO_SPACE |
267 PCI_ENABLE_MEMORY_SPACE |
268 PCI_ENABLE_BUS_MASTER |
269 PCI_ENABLE_WRITE_AND_INVALIDATE);
270 }
271
272 /* Update the device configuration */
273 PciData->Status = 0;
274 PciWriteDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
275
276 /* Turn decodes back on */
277 PciDecodeEnable(PdoExtension, TRUE, &PdoExtension->CommandEnables);
278}
279
280VOID
281NTAPI
282PciUpdateHardware(IN PPCI_PDO_EXTENSION PdoExtension,
283 IN PPCI_COMMON_HEADER PciData)
284{
285 PCI_IPI_CONTEXT Context;
286
287 /* Check for critical devices and PCI Debugging devices */
288 if ((PdoExtension->HackFlags & PCI_HACK_CRITICAL_DEVICE) ||
289 (PdoExtension->OnDebugPath))
290 {
291 /* Build the context and send an IPI */
292 Context.RunCount = 1;
293 Context.Barrier = 1;
294 Context.Context = PciData;
295 Context.Function = PcipUpdateHardware;
296 Context.DeviceExtension = PdoExtension;
297 KeIpiGenericCall(PciExecuteCriticalSystemRoutine, (ULONG_PTR)&Context);
298 }
299 else
300 {
301 /* Just do the update inline */
302 PcipUpdateHardware(PdoExtension, PciData);
303 }
304}
305
306PIO_RESOURCE_REQUIREMENTS_LIST
307NTAPI
308PciAllocateIoRequirementsList(IN ULONG Count,
309 IN ULONG BusNumber,
310 IN ULONG SlotNumber)
311{
312 SIZE_T Size;
313 PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList;
314
315 /* Calculate the final size of the list, including each descriptor */
316 Size = sizeof(IO_RESOURCE_REQUIREMENTS_LIST);
317 if (Count > 1) Size = sizeof(IO_RESOURCE_DESCRIPTOR) * (Count - 1) +
318 sizeof(IO_RESOURCE_REQUIREMENTS_LIST);
319
320 /* Allocate the list */
321 RequirementsList = ExAllocatePoolWithTag(PagedPool, Size, 'BicP');
322 if (!RequirementsList) return NULL;
323
324 /* Initialize it */
325 RtlZeroMemory(RequirementsList, Size);
326 RequirementsList->AlternativeLists = 1;
327 RequirementsList->BusNumber = BusNumber;
328 RequirementsList->SlotNumber = SlotNumber;
329 RequirementsList->InterfaceType = PCIBus;
330 RequirementsList->ListSize = Size;
331 RequirementsList->List[0].Count = Count;
332 RequirementsList->List[0].Version = 1;
333 RequirementsList->List[0].Revision = 1;
334
335 /* Return it */
336 return RequirementsList;
337}
338
339PCM_RESOURCE_LIST
340NTAPI
341PciAllocateCmResourceList(IN ULONG Count,
342 IN ULONG BusNumber)
343{
344 SIZE_T Size;
345 PCM_RESOURCE_LIST ResourceList;
346
347 /* Calculate the final size of the list, including each descriptor */
348 Size = sizeof(CM_RESOURCE_LIST);
349 if (Count > 1) Size = sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR) * (Count - 1) +
350 sizeof(CM_RESOURCE_LIST);
351
352 /* Allocate the list */
353 ResourceList = ExAllocatePoolWithTag(PagedPool, Size, 'BicP');
354 if (!ResourceList) return NULL;
355
356 /* Initialize it */
357 RtlZeroMemory(ResourceList, Size);
358 ResourceList->Count = 1;
359 ResourceList->List[0].BusNumber = BusNumber;
360 ResourceList->List[0].InterfaceType = PCIBus;
361 ResourceList->List[0].PartialResourceList.Version = 1;
362 ResourceList->List[0].PartialResourceList.Revision = 1;
363 ResourceList->List[0].PartialResourceList.Count = Count;
364
365 /* Return it */
366 return ResourceList;
367}
368
369NTSTATUS
370NTAPI
371PciQueryResources(IN PPCI_PDO_EXTENSION PdoExtension,
372 OUT PCM_RESOURCE_LIST *Buffer)
373{
374 PPCI_FUNCTION_RESOURCES PciResources;
375 BOOLEAN HaveVga, HaveMemSpace, HaveIoSpace;
376 USHORT BridgeControl, PciCommand;
377 ULONG Count, i;
378 PCM_PARTIAL_RESOURCE_DESCRIPTOR Partial, Resource, LastResource;
379 PCM_RESOURCE_LIST ResourceList;
380 UCHAR InterruptLine;
381 PAGED_CODE();
382
383 /* Assume failure */
384 Count = 0;
385 HaveVga = FALSE;
386 *Buffer = NULL;
387
388 /* Make sure there's some resources to query */
389 PciResources = PdoExtension->Resources;
390 if (!PciResources) return STATUS_SUCCESS;
391
392 /* Read the decodes */
393 PciReadDeviceConfig(PdoExtension,
394 &PciCommand,
395 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
396 sizeof(USHORT));
397
398 /* Check which ones are turned on */
399 HaveIoSpace = PciCommand & PCI_ENABLE_IO_SPACE;
400 HaveMemSpace = PciCommand & PCI_ENABLE_MEMORY_SPACE;
401
402 /* Loop maximum possible descriptors */
403 for (i = 0; i < 7; i++)
404 {
405 /* Check if the decode for this descriptor is actually turned on */
406 Partial = &PciResources->Current[i];
407 if ((HaveMemSpace &&
408 ((Partial->Type == CmResourceTypeMemory) ||
409 (Partial->Type == CmResourceTypeMemoryLarge))) ||
410 (HaveIoSpace && (Partial->Type == CmResourceTypePort)))
411 {
412 /* One more fully active descriptor */
413 Count++;
414 }
415 }
416
417 /* If there's an interrupt pin associated, check at least one decode is on */
418 if ((PdoExtension->InterruptPin) && ((HaveMemSpace) || (HaveIoSpace)))
419 {
420 /* Read the interrupt line for the pin, add a descriptor if it's valid */
421 InterruptLine = PdoExtension->AdjustedInterruptLine;
422 if ((InterruptLine) && (InterruptLine != -1)) Count++;
423 }
424
425 /* Check for PCI bridge */
426 if (PdoExtension->HeaderType == PCI_BRIDGE_TYPE)
427 {
428 /* Read bridge settings, check if VGA is present */
429 PciReadDeviceConfig(PdoExtension,
430 &BridgeControl,
431 FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.BridgeControl),
432 sizeof(USHORT));
433 if (BridgeControl & PCI_ENABLE_BRIDGE_VGA)
434 {
435 /* Remember for later */
436 HaveVga = TRUE;
437
438 /* One memory descriptor for 0xA0000, plus the two I/O port ranges */
439 if (HaveMemSpace) Count++;
440 if (HaveIoSpace) Count += 2;
441 }
442 }
443
444 /* If there's no descriptors in use, there's no resources, so return */
445 if (!Count) return STATUS_SUCCESS;
446
447 /* Allocate a resource list to hold the resources */
448 ResourceList = PciAllocateCmResourceList(Count,
449 PdoExtension->ParentFdoExtension->BaseBus);
450 if (!ResourceList) return STATUS_INSUFFICIENT_RESOURCES;
451
452 /* This is where the descriptors will be copied into */
453 Resource = ResourceList->List[0].PartialResourceList.PartialDescriptors;
454 LastResource = Resource + Count + 1;
455
456 /* Loop maximum possible descriptors */
457 for (i = 0; i < 7; i++)
458 {
459 /* Check if the decode for this descriptor is actually turned on */
460 Partial = &PciResources->Current[i];
461 if ((HaveMemSpace &&
462 ((Partial->Type == CmResourceTypeMemory) ||
463 (Partial->Type == CmResourceTypeMemoryLarge))) ||
464 (HaveIoSpace && (Partial->Type == CmResourceTypePort)))
465 {
466 /* Copy the descriptor into the resource list */
467 *Resource++ = *Partial;
468 }
469 }
470
471 /* Check if earlier the code detected this was a PCI bridge with VGA on it */
472 if (HaveVga)
473 {
474 /* Are the memory decodes enabled? */
475 if (HaveMemSpace)
476 {
477 /* Build a memory descriptor for a 128KB framebuffer at 0xA0000 */
478 Resource->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
479 Resource->u.Generic.Start.HighPart = 0;
480 Resource->Type = CmResourceTypeMemory;
481 Resource->u.Generic.Start.LowPart = 0xA0000;
482 Resource->u.Generic.Length = 0x20000;
483 Resource++;
484 }
485
486 /* Are the I/O decodes enabled? */
487 if (HaveIoSpace)
488 {
489 /* Build an I/O descriptor for the graphic ports at 0x3B0 */
490 Resource->Type = CmResourceTypePort;
491 Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
492 Resource->u.Port.Start.QuadPart = 0x3B0u;
493 Resource->u.Port.Length = 0xC;
494 Resource++;
495
496 /* Build an I/O descriptor for the graphic ports at 0x3C0 */
497 Resource->Type = CmResourceTypePort;
498 Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
499 Resource->u.Port.Start.QuadPart = 0x3C0u;
500 Resource->u.Port.Length = 0x20;
501 Resource++;
502 }
503 }
504
505 /* If there's an interrupt pin associated, check at least one decode is on */
506 if ((PdoExtension->InterruptPin) && ((HaveMemSpace) || (HaveIoSpace)))
507 {
508 /* Read the interrupt line for the pin, check if it's valid */
509 InterruptLine = PdoExtension->AdjustedInterruptLine;
510 if ((InterruptLine) && (InterruptLine != -1))
511 {
512 /* Make sure there's still space */
513 ASSERT(Resource < LastResource);
514
515 /* Add the interrupt descriptor */
516 Resource->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
517 Resource->Type = CmResourceTypeInterrupt;
518 Resource->ShareDisposition = CmResourceShareShared;
519 Resource->u.Interrupt.Affinity = -1;
520 Resource->u.Interrupt.Level = InterruptLine;
521 Resource->u.Interrupt.Vector = InterruptLine;
522 }
523 }
524
525 /* Return the resource list */
526 *Buffer = ResourceList;
527 return STATUS_SUCCESS;
528}
529
530NTSTATUS
531NTAPI
532PciQueryTargetDeviceRelations(IN PPCI_PDO_EXTENSION PdoExtension,
533 IN OUT PDEVICE_RELATIONS *pDeviceRelations)
534{
535 PDEVICE_RELATIONS DeviceRelations;
536 PAGED_CODE();
537
538 /* If there were existing relations, free them */
539 if (*pDeviceRelations) ExFreePoolWithTag(*pDeviceRelations, 0);
540
541 /* Allocate a new structure for the relations */
542 DeviceRelations = ExAllocatePoolWithTag(NonPagedPool,
543 sizeof(DEVICE_RELATIONS),
544 'BicP');
545 if (!DeviceRelations) return STATUS_INSUFFICIENT_RESOURCES;
546
547 /* Only one relation: the PDO */
548 DeviceRelations->Count = 1;
549 DeviceRelations->Objects[0] = PdoExtension->PhysicalDeviceObject;
550 ObReferenceObject(DeviceRelations->Objects[0]);
551
552 /* Return the new relations */
553 *pDeviceRelations = DeviceRelations;
554 return STATUS_SUCCESS;
555}
556
557NTSTATUS
558NTAPI
559PciQueryEjectionRelations(IN PPCI_PDO_EXTENSION PdoExtension,
560 IN OUT PDEVICE_RELATIONS *pDeviceRelations)
561{
562 UNREFERENCED_PARAMETER(PdoExtension);
563 UNREFERENCED_PARAMETER(pDeviceRelations);
564
565 /* Not yet implemented */
566 UNIMPLEMENTED_DBGBREAK();
567 return STATUS_NOT_IMPLEMENTED;
568}
569
570NTSTATUS
571NTAPI
572PciBuildRequirementsList(IN PPCI_PDO_EXTENSION PdoExtension,
573 IN PPCI_COMMON_HEADER PciData,
574 OUT PIO_RESOURCE_REQUIREMENTS_LIST* Buffer)
575{
576 PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList;
577 PIO_RESOURCE_DESCRIPTOR Descriptor, Limit;
578 PCI_CONFIGURATOR_CONTEXT Context;
579 ULONG Count, i;
580 BOOLEAN HaveInterrupt;
581
582 PAGED_CODE();
583
584 /* Count the BAR limits that resource discovery found for this function */
585 Count = 0;
586 if (PdoExtension->Resources)
587 {
588 for (i = 0; i < (PCI_TYPE0_ADDRESSES + 1); i++)
589 {
590 if (PdoExtension->Resources->Limit[i].Type != CmResourceTypeNull)
591 Count++;
592 }
593 }
594
595 /* A device with an interrupt pin also needs a line routed to it */
596 HaveInterrupt = (PdoExtension->InterruptPin) &&
597 !(PdoExtension->HackFlags & PCI_HACK_NO_ENUM_AT_ALL);
598 if (HaveInterrupt)
599 Count++;
600
601 /* And a bridge with legacy decodes enabled needs those ranges locked down */
602 Count += PdoExtension->AdditionalResourceCount;
603
604 /* Check if the function turned out to need nothing after all */
605 if (!Count)
606 {
607 /* There aren't, so use the zero descriptor */
608 RequirementsList = PciZeroIoResourceRequirements;
609
610 /* Does it actually exist yet? */
611 if (!PciZeroIoResourceRequirements)
612 {
613 /* Allocate it, and use it for future use */
614 RequirementsList = PciAllocateIoRequirementsList(0, 0, 0);
615 PciZeroIoResourceRequirements = RequirementsList;
616 if (!PciZeroIoResourceRequirements) return STATUS_INSUFFICIENT_RESOURCES;
617 }
618
619 *Buffer = RequirementsList;
620 DPRINT1("PCI - build resource reqs - early out, 0 resources\n");
621 return STATUS_SUCCESS;
622 }
623
624 RequirementsList = PciAllocateIoRequirementsList(Count,
625 PdoExtension->ParentFdoExtension->BaseBus,
626 PdoExtension->Slot.u.AsULONG);
627 if (!RequirementsList)
628 return STATUS_INSUFFICIENT_RESOURCES;
629
630 Descriptor = RequirementsList->List[0].Descriptors;
631
632 /* Emit one descriptor per BAR that decoded something during discovery */
633 if (PdoExtension->Resources)
634 {
635 Limit = PdoExtension->Resources->Limit;
636 for (i = 0; i < (PCI_TYPE0_ADDRESSES + 1); i++)
637 {
638 /* Skip the BARs this function does not implement */
639 if (Limit[i].Type == CmResourceTypeNull)
640 continue;
641
642 /* A BAR decodes for one function only, so it cannot be shared */
643 *Descriptor = Limit[i];
644 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
645 Descriptor++;
646 }
647 }
648
649 if (HaveInterrupt)
650 {
651 Descriptor->Type = CmResourceTypeInterrupt;
652 Descriptor->ShareDisposition = CmResourceShareShared;
653 Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
654 Descriptor->u.Interrupt.MinimumVector = 0;
655 Descriptor->u.Interrupt.MaximumVector = MAXULONG;
656 Descriptor++;
657 }
658
659 /* And finally any extra ranges this kind of function decodes on the side */
660 if (PdoExtension->AdditionalResourceCount)
661 {
662 RtlZeroMemory(&Context, sizeof(Context));
663 Context.PdoExtension = PdoExtension;
664 Context.Current = PciData;
665 PciConfigurators[PdoExtension->HeaderType].
666 GetAdditionalResourceDescriptors(&Context, PciData, Descriptor);
667 }
668
669 *Buffer = RequirementsList;
670 return STATUS_SUCCESS;
671}
672
673NTSTATUS
674NTAPI
675PciQueryRequirements(IN PPCI_PDO_EXTENSION PdoExtension,
676 IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *RequirementsList)
677{
678 NTSTATUS Status;
679 PCI_COMMON_HEADER PciHeader;
680 PAGED_CODE();
681
682 /* Check if the PDO has any resources, or at least an interrupt pin */
683 if ((PdoExtension->Resources) || (PdoExtension->InterruptPin))
684 {
685 /* Read the current PCI header */
686 PciReadDeviceConfig(PdoExtension, &PciHeader, 0, PCI_COMMON_HDR_LENGTH);
687
688 /* Use it to build a list of requirements */
689 Status = PciBuildRequirementsList(PdoExtension, &PciHeader, RequirementsList);
690 if (!NT_SUCCESS(Status)) return Status;
691
692 /* Is this a Compaq PCI Hotplug Controller (r17) on a PAE system ? */
693 if ((PciHeader.VendorID == 0xE11) &&
694 (PciHeader.DeviceID == 0xA0F7) &&
695 (PciHeader.RevisionID == 17) &&
696 (ExIsProcessorFeaturePresent(PF_PAE_ENABLED)))
697 {
698 /* Have not tested this on eVb's machine yet */
699 UNIMPLEMENTED_DBGBREAK();
700 }
701
702 /* Check if the requirements are actually the zero list */
703 if (*RequirementsList == PciZeroIoResourceRequirements)
704 {
705 /* A simple NULL will suffice for the PnP Manager */
706 *RequirementsList = NULL;
707 DPRINT1("Returning NULL requirements list\n");
708 }
709 else
710 {
711 /* Otherwise, print out the requirements list */
712 PciDebugPrintIoResReqList(*RequirementsList);
713 }
714 }
715 else
716 {
717 /* There aren't any resources, so simply return NULL */
718 DPRINT1("PciQueryRequirements returning NULL requirements list\n");
719 *RequirementsList = NULL;
720 }
721
722 /* This call always succeeds (but maybe with no requirements) */
723 return STATUS_SUCCESS;
724}
725
726/*
727 * 7. The IO/MEM/Busmaster decodes are disabled for the device.
728 * 8. The PCI bus driver sets the operating mode bits of the Programming
729 * Interface byte to switch the controller to native mode.
730 *
731 * Important: When the controller is set to native mode, it must quiet itself
732 * and must not decode I/O resources or generate interrupts until the operating
733 * system has enabled the ports in the PCI configuration header.
734 * The IO/MEM/BusMaster bits will be disabled before the mode change, but it
735 * is not possible to disable interrupts on the device. The device must not
736 * generate interrupts (either legacy or native mode) while the decodes are
737 * disabled in the command register.
738 *
739 * This operation is expected to be instantaneous and the operating system does
740 * not stall afterward. It is also expected that the interrupt pin register in
741 * the PCI Configuration space for this device is accurate. The operating system
742 * re-reads this data after previously ignoring it.
743 */
744BOOLEAN
745NTAPI
746PciConfigureIdeController(IN PPCI_PDO_EXTENSION PdoExtension,
747 IN PPCI_COMMON_HEADER PciData,
748 IN BOOLEAN Initial)
749{
750 UCHAR MasterMode, SlaveMode, MasterFixed, SlaveFixed, ProgIf, NewProgIf;
751 BOOLEAN Switched;
752 USHORT Command;
753
754 /* Assume it won't work */
755 Switched = FALSE;
756
757 /* Get master and slave current settings, and programmability flag */
758 ProgIf = PciData->ProgIf;
759 MasterMode = (ProgIf & 1) == 1;
760 MasterFixed = (ProgIf & 2) == 0;
761 SlaveMode = (ProgIf & 4) == 4;
762 SlaveFixed = (ProgIf & 8) == 0;
763
764 /*
765 * [..] In order for Windows XP SP1 and Windows Server 2003 to switch an ATA
766 * ATA controller from compatible mode to native mode, the following must be
767 * true:
768 *
769 * - The controller must indicate in its programming interface that both channels
770 * can be switched to native mode. Windows XP SP1 and Windows Server 2003 do
771 * not support switching only one IDE channel to native mode. See the PCI IDE
772 * Controller Specification Revision 1.0 for details.
773 */
774 if ((MasterMode != SlaveMode) || (MasterFixed != SlaveFixed))
775 {
776 /* Windows does not support this configuration, fail */
777 DPRINT1("PCI: Warning unsupported IDE controller configuration for VEN_%04x&DEV_%04x!",
778 PdoExtension->VendorId,
779 PdoExtension->DeviceId);
780 return Switched;
781 }
782
783 /* Check if the controller is already in native mode */
784 if ((MasterMode) && (SlaveMode))
785 {
786 /* Check if I/O decodes should be disabled */
787 if ((Initial) || (PdoExtension->IoSpaceUnderNativeIdeControl))
788 {
789 /* Read the current command */
790 PciReadDeviceConfig(PdoExtension,
791 &Command,
792 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
793 sizeof(USHORT));
794
795 /* Disable I/O space decode */
796 Command &= ~PCI_ENABLE_IO_SPACE;
797
798 /* Update new command in PCI IDE controller */
799 PciWriteDeviceConfig(PdoExtension,
800 &Command,
801 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
802 sizeof(USHORT));
803
804 /* Save updated command value */
805 PciData->Command = Command;
806 }
807
808 /* The controller is now in native mode */
809 Switched = TRUE;
810 }
811 else if (!(MasterFixed) &&
812 !(SlaveFixed) &&
813 (PdoExtension->BIOSAllowsIDESwitchToNativeMode) &&
814 !(PdoExtension->HackFlags & PCI_HACK_DISABLE_IDE_NATIVE_MODE))
815 {
816 /* Turn off decodes */
817 PciDecodeEnable(PdoExtension, FALSE, NULL);
818
819 /* Update the current command */
820 PciReadDeviceConfig(PdoExtension,
821 &PciData->Command,
822 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
823 sizeof(USHORT));
824
825 /* Enable native mode */
826 ProgIf = PciData->ProgIf | 5;
827 PciWriteDeviceConfig(PdoExtension,
828 &ProgIf,
829 FIELD_OFFSET(PCI_COMMON_HEADER, ProgIf),
830 sizeof(UCHAR));
831
832 /* Verify the setting "stuck" */
833 PciReadDeviceConfig(PdoExtension,
834 &NewProgIf,
835 FIELD_OFFSET(PCI_COMMON_HEADER, ProgIf),
836 sizeof(UCHAR));
837 if (NewProgIf == ProgIf)
838 {
839 /* Update the header and PDO data with the new programming mode */
840 PciData->ProgIf = ProgIf;
841 PdoExtension->ProgIf = NewProgIf;
842
843 /* Clear the first four BARs to reset current BAR settings */
844 PciData->u.type0.BaseAddresses[0] = 0;
845 PciData->u.type0.BaseAddresses[1] = 0;
846 PciData->u.type0.BaseAddresses[2] = 0;
847 PciData->u.type0.BaseAddresses[3] = 0;
848 PciWriteDeviceConfig(PdoExtension,
849 PciData->u.type0.BaseAddresses,
850 FIELD_OFFSET(PCI_COMMON_HEADER,
851 u.type0.BaseAddresses),
852 4 * sizeof(ULONG));
853
854 /* Re-read the BARs to have the latest data for native mode IDE */
855 PciReadDeviceConfig(PdoExtension,
856 PciData->u.type0.BaseAddresses,
857 FIELD_OFFSET(PCI_COMMON_HEADER,
858 u.type0.BaseAddresses),
859 4 * sizeof(ULONG));
860
861 /* Re-read the interrupt pin used for native mode IDE */
862 PciReadDeviceConfig(PdoExtension,
863 &PciData->u.type0.InterruptPin,
864 FIELD_OFFSET(PCI_COMMON_HEADER,
865 u.type0.InterruptPin),
866 sizeof(UCHAR));
867
868 /* The IDE Controller is now in native mode */
869 Switched = TRUE;
870 }
871 else
872 {
873 /* Settings did not work, fail */
874 DPRINT1("PCI: Warning failed switch to native mode for IDE controller VEN_%04x&DEV_%04x!",
875 PciData->VendorID,
876 PciData->DeviceID);
877 }
878 }
879
880 /* Return whether or not native mode was enabled on the IDE controller */
881 return Switched;
882}
883
884VOID
885NTAPI
886PciApplyHacks(IN PPCI_FDO_EXTENSION DeviceExtension,
887 IN PPCI_COMMON_HEADER PciData,
888 IN PCI_SLOT_NUMBER SlotNumber,
889 IN ULONG OperationType,
890 PPCI_PDO_EXTENSION PdoExtension)
891{
892 ULONG LegacyBaseAddress;
893 USHORT Command;
894 UCHAR RegValue;
895
896 UNREFERENCED_PARAMETER(SlotNumber);
897
898 /* Check what kind of hack operation this is */
899 switch (OperationType)
900 {
901 /*
902 * This is mostly concerned with fixing up incorrect class data that can
903 * exist on certain PCI hardware before the 2.0 spec was ratified.
904 */
905 case PCI_HACK_FIXUP_BEFORE_CONFIGURATION:
906
907 /* Note that the i82375 PCI/EISA and the i82378 PCI/ISA bridges that
908 * are present on certain DEC/NT Alpha machines are pre-PCI 2.0 devices
909 * and appear as non-classified, so their correct class/subclass data
910 * is written here instead.
911 */
912 if ((PciData->VendorID == 0x8086) &&
913 ((PciData->DeviceID == 0x482) || (PciData->DeviceID == 0x484)))
914 {
915 /* Note that 0x482 is the i82375 (EISA), 0x484 is the i82378 (ISA) */
916 PciData->SubClass = PciData->DeviceID == 0x482 ?
917 PCI_SUBCLASS_BR_EISA : PCI_SUBCLASS_BR_ISA;
918 PciData->BaseClass = PCI_CLASS_BRIDGE_DEV;
919
920 /*
921 * Because the software is modifying the actual header data from
922 * the BIOS, this flag tells the driver to ignore failures when
923 * comparing the original BIOS data with the PCI data.
924 */
925 if (PdoExtension) PdoExtension->ExpectedWritebackFailure = TRUE;
926 }
927
928 /* Note that in this case, an immediate return is issued */
929 return;
930
931 /*
932 * This is concerned with setting up interrupts correctly for native IDE
933 * mode, but will also handle broken VGA decoding on older bridges as
934 * well as a PAE-specific hack for certain Compaq Hot-Plug Controllers.
935 */
936 case PCI_HACK_FIXUP_AFTER_CONFIGURATION:
937
938 /* There should always be a PDO extension passed in */
939 ASSERT(PdoExtension);
940
941 /*
942 * On the OPTi Viper-M IDE controller, Linux doesn't support IDE-DMA
943 * and FreeBSD bug reports indicate that the system crashes when the
944 * feature is enabled (so it's disabled on that OS as well). In the
945 * NT PCI Bus Driver, it seems Microsoft too, completely disables
946 * Native IDE functionality on this controller, so it would seem OPTi
947 * simply frelled up this controller.
948 */
949 if ((PciData->VendorID == 0x1045) && (PciData->DeviceID != 0xC621))
950 {
951 /* Disable native mode */
952 PciData->ProgIf &= ~5;
953 PciData->u.type0.InterruptPin = 0;
954
955 /*
956 * Because the software is modifying the actual header data from
957 * the BIOS, this flag tells the driver to ignore failures when
958 * comparing the original BIOS data with the PCI data.
959 */
960 PdoExtension->ExpectedWritebackFailure = TRUE;
961 }
962 else if ((PciData->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
963 (PciData->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
964 {
965 /* For other IDE controllers, start out in compatible mode */
966 PdoExtension->BIOSAllowsIDESwitchToNativeMode = FALSE;
967
968 /*
969 * Registry must have enabled native mode (typically as a result
970 * of an INF file directive part of the IDE controller's driver)
971 * and the system must not be booted in Safe Mode. If that checks
972 * out, then evaluate the ACPI NATA method to see if the platform
973 * supports this. See the section "BIOS and Platform Prerequisites
974 * for Switching a Native-Mode-Capable Controller" in the Storage
975 * section of the Windows Driver Kit for more details:
976 *
977 * 5. For each ATA controller enumerated, the PCI bus driver checks
978 * the Programming Interface register of the IDE controller to
979 * see if it supports switching both channels to native mode.
980 * 6. The PCI bus driver checks whether the BIOS/platform supports
981 * switching the controller by checking the NATA method described
982 * earlier in this article.
983 *
984 * If an ATA controller does not indicate that it is native
985 * mode-capable, or if the BIOS NATA control method is missing
986 * or does not list that device, the PCI bus driver does not
987 * switch the controller and it is assigned legacy resources.
988 *
989 * If both the controller and the BIOS indicate that the controller
990 * can be switched, the process of switching the controller begins
991 * with the next step.
992 */
993 if ((PciEnableNativeModeATA) &&
994 !(InitSafeBootMode) &&
995 (PciIsSlotPresentInParentMethod(PdoExtension, 'ATAN')))
996 {
997 /* The platform supports it, remember that */
998 PdoExtension->BIOSAllowsIDESwitchToNativeMode = TRUE;
999
1000 /*
1001 * Now switch the controller into native mode if both channels
1002 * support native IDE mode. See "How Windows Switches an ATA
1003 * Controller to Native Mode" in the Storage section of the
1004 * Windows Driver Kit for more details.
1005 */
1006 PdoExtension->IDEInNativeMode =
1007 PciConfigureIdeController(PdoExtension, PciData, TRUE);
1008 }
1009
1010 /* Is native mode enabled after all? */
1011 if ((PciData->ProgIf & 5) != 5)
1012 {
1013 /* Compatible mode, so force ISA-style IRQ14 and IRQ 15 */
1014 PciData->u.type0.InterruptPin = 0;
1015 }
1016 }
1017
1018 /* Is this a PCI device with legacy VGA card decodes on the root bus? */
1019 if ((PdoExtension->HackFlags & PCI_HACK_VIDEO_LEGACY_DECODE) &&
1020 (PCI_IS_ROOT_FDO(DeviceExtension)) &&
1021 !(DeviceExtension->BrokenVideoHackApplied))
1022 {
1023 /* Tell the arbiter to apply a hack for these older devices */
1024 ario_ApplyBrokenVideoHack(DeviceExtension);
1025 }
1026
1027 /* Is this a Compaq PCI Hotplug Controller (r17) on a PAE system ? */
1028 if ((PciData->VendorID == 0xE11) &&
1029 (PciData->DeviceID == 0xA0F7) &&
1030 (PciData->RevisionID == 17) &&
1031 (ExIsProcessorFeaturePresent(PF_PAE_ENABLED)))
1032 {
1033 /* Turn off the decodes immediately */
1034 PciData->Command &= ~(PCI_ENABLE_IO_SPACE |
1035 PCI_ENABLE_MEMORY_SPACE |
1036 PCI_ENABLE_BUS_MASTER);
1037 PciWriteDeviceConfig(PdoExtension,
1038 &PciData->Command,
1039 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
1040 sizeof(USHORT));
1041
1042 /* Do not EVER turn them on again, this will blow up the system */
1043 PdoExtension->CommandEnables &= ~(PCI_ENABLE_IO_SPACE |
1044 PCI_ENABLE_MEMORY_SPACE |
1045 PCI_ENABLE_BUS_MASTER);
1046 PdoExtension->HackFlags |= PCI_HACK_PRESERVE_COMMAND;
1047 }
1048 break;
1049
1050 /*
1051 * This is called whenever resources are changed and hardware needs to be
1052 * updated. It is concerned with two highly specific erratas on an IBM
1053 * hot-plug docking bridge used on the Thinkpad 600 Series and on Intel's
1054 * ICH PCI Bridges.
1055 */
1056 case PCI_HACK_FIXUP_BEFORE_UPDATE:
1057
1058 /* There should always be a PDO extension passed in */
1059 ASSERT(PdoExtension);
1060
1061 /* Is this an IBM 20H2999 PCI Docking Bridge, used on Thinkpads? */
1062 if ((PdoExtension->VendorId == 0x1014) &&
1063 (PdoExtension->DeviceId == 0x95))
1064 {
1065 /* Read the current command */
1066 PciReadDeviceConfig(PdoExtension,
1067 &Command,
1068 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
1069 sizeof(USHORT));
1070
1071 /* Turn off the decodes */
1072 PciDecodeEnable(PdoExtension, FALSE, &Command);
1073
1074 /* Apply the required IBM workaround */
1075 PciReadDeviceConfig(PdoExtension, &RegValue, 0xE0, sizeof(UCHAR));
1076 RegValue &= ~2;
1077 RegValue |= 1;
1078 PciWriteDeviceConfig(PdoExtension, &RegValue, 0xE0, sizeof(UCHAR));
1079
1080 /* Restore the command to its original value */
1081 PciWriteDeviceConfig(PdoExtension,
1082 &Command,
1083 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
1084 sizeof(USHORT));
1085
1086 }
1087
1088 /*
1089 * Check for Intel ICH PCI-to-PCI (i82801) bridges (used on the i810,
1090 * i820, i840, i845 Chipsets) that have subtractive decode enabled,
1091 * and whose hack flags do not specify that this support is broken.
1092 */
1093 if ((PdoExtension->HeaderType == PCI_BRIDGE_TYPE) &&
1094 (PdoExtension->Dependent.type1.SubtractiveDecode) &&
1095 ((PdoExtension->VendorId == 0x8086) &&
1096 ((PdoExtension->DeviceId == 0x2418) ||
1097 (PdoExtension->DeviceId == 0x2428) ||
1098 (PdoExtension->DeviceId == 0x244E) ||
1099 (PdoExtension->DeviceId == 0x2448))) &&
1100 !(PdoExtension->HackFlags & PCI_HACK_BROKEN_SUBTRACTIVE_DECODE))
1101 {
1102 /*
1103 * The positive decode window shouldn't be used, these values are
1104 * normally all read-only or initialized to 0 by the BIOS, but
1105 * it appears Intel doesn't do this, so the PCI Bus Driver will
1106 * do it in software instead. Note that this is used to prevent
1107 * certain non-compliant PCI devices from breaking down due to the
1108 * fact that these ICH bridges have a known "quirk" (which Intel
1109 * documents as a known "erratum", although it's not not really
1110 * an ICH bug since the PCI specification does allow for it) in
1111 * that they will sometimes send non-zero addresses during special
1112 * cycles (ie: non-zero data during the address phase). These
1113 * broken PCI cards will mistakenly attempt to claim the special
1114 * cycle and corrupt their I/O and RAM ranges. Again, in Intel's
1115 * defense, the PCI specification only requires stable data, not
1116 * necessarily zero data, during the address phase.
1117 */
1118 PciData->u.type1.MemoryBase = 0xFFFF;
1119 PciData->u.type1.PrefetchBase = 0xFFFF;
1120 PciData->u.type1.IOBase = 0xFF;
1121 PciData->u.type1.IOLimit = 0;
1122 PciData->u.type1.MemoryLimit = 0;
1123 PciData->u.type1.PrefetchLimit = 0;
1124 PciData->u.type1.PrefetchBaseUpper32 = 0;
1125 PciData->u.type1.PrefetchLimitUpper32 = 0;
1126 PciData->u.type1.IOBaseUpper16 = 0;
1127 PciData->u.type1.IOLimitUpper16 = 0;
1128 }
1129 break;
1130
1131 default:
1132 return;
1133 }
1134
1135 /* Finally, also check if this is this a CardBUS device? */
1136 if (PCI_CONFIGURATION_TYPE(PciData) == PCI_CARDBUS_BRIDGE_TYPE)
1137 {
1138 /*
1139 * At offset 44h the LegacyBaseAddress is stored, which is cleared by
1140 * ACPI-aware versions of Windows, to disable legacy-mode I/O access to
1141 * CardBus controllers. For more information, see "Supporting CardBus
1142 * Controllers under ACPI" in the "CardBus Controllers and Windows"
1143 * Whitepaper on WHDC.
1144 */
1145 LegacyBaseAddress = 0;
1146 PciWriteDeviceConfig(PdoExtension,
1147 &LegacyBaseAddress,
1148 sizeof(PCI_COMMON_HEADER) + sizeof(ULONG),
1149 sizeof(ULONG));
1150 }
1151}
1152
1153BOOLEAN
1154NTAPI
1155PcipIsSameDevice(IN PPCI_PDO_EXTENSION DeviceExtension,
1156 IN PPCI_COMMON_HEADER PciData)
1157{
1158 BOOLEAN IdMatch, RevMatch, SubsysMatch;
1159 ULONGLONG HackFlags = DeviceExtension->HackFlags;
1160
1161 /* Check if the IDs match */
1162 IdMatch = (PciData->VendorID == DeviceExtension->VendorId) &&
1163 (PciData->DeviceID == DeviceExtension->DeviceId);
1164 if (!IdMatch) return FALSE;
1165
1166 /* If the device has a valid revision, check if it matches */
1167 RevMatch = (HackFlags & PCI_HACK_NO_REVISION_AFTER_D3) ||
1168 (PciData->RevisionID == DeviceExtension->RevisionId);
1169 if (!RevMatch) return FALSE;
1170
1171 /* For multifunction devices, this is enough to assume they're the same */
1172 if (PCI_MULTIFUNCTION_DEVICE(PciData)) return TRUE;
1173
1174 /* For bridge devices, there's also nothing else that can be checked */
1175 if (DeviceExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) return TRUE;
1176
1177 /* Devices, on the other hand, have subsystem data that can be compared */
1178 SubsysMatch = (HackFlags & (PCI_HACK_NO_SUBSYSTEM |
1179 PCI_HACK_NO_SUBSYSTEM_AFTER_D3)) ||
1180 ((DeviceExtension->SubsystemVendorId ==
1181 PciData->u.type0.SubVendorID) &&
1182 (DeviceExtension->SubsystemId ==
1183 PciData->u.type0.SubSystemID));
1184 return SubsysMatch;
1185}
1186
1187BOOLEAN
1188NTAPI
1189PciSkipThisFunction(IN PPCI_COMMON_HEADER PciData,
1190 IN PCI_SLOT_NUMBER Slot,
1191 IN UCHAR OperationType,
1192 IN ULONGLONG HackFlags)
1193{
1194 do
1195 {
1196 /* Check if this is device enumeration */
1197 if (OperationType == PCI_SKIP_DEVICE_ENUMERATION)
1198 {
1199 /* Check if there's a hackflag saying not to enumerate this device */
1200 if (HackFlags & PCI_HACK_NO_ENUM_AT_ALL) break;
1201
1202 /* Check if this is the high end of a double decker device */
1203 if ((HackFlags & PCI_HACK_DOUBLE_DECKER) &&
1204 (Slot.u.bits.DeviceNumber >= 16))
1205 {
1206 /* It belongs to the same device, so skip it */
1207 DPRINT1(" Device (Ven %04x Dev %04x (d=0x%x, f=0x%x)) is a ghost.\n",
1208 PciData->VendorID,
1209 PciData->DeviceID,
1210 Slot.u.bits.DeviceNumber,
1211 Slot.u.bits.FunctionNumber);
1212 break;
1213 }
1214 }
1215 else if (OperationType == PCI_SKIP_RESOURCE_ENUMERATION)
1216 {
1217 /* Resource enumeration, check for a hackflag saying not to do it */
1218 if (HackFlags & PCI_HACK_ENUM_NO_RESOURCE) break;
1219 }
1220 else
1221 {
1222 /* Logic error in the driver */
1223 ASSERTMSG("PCI Skip Function - Operation type unknown.\n", FALSE);
1224 }
1225
1226 /* Check for legacy bridges during resource enumeration */
1227 if ((PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1228 (PciData->SubClass <= PCI_SUBCLASS_BR_MCA) &&
1229 (OperationType == PCI_SKIP_RESOURCE_ENUMERATION))
1230 {
1231 /* Their resources are not enumerated, only PCI and Cardbus/PCMCIA */
1232 break;
1233 }
1234 else if (PciData->BaseClass == PCI_CLASS_NOT_DEFINED)
1235 {
1236 /* Undefined base class (usually a PCI BIOS/ROM bug) */
1237 DPRINT1(" Vendor %04x, Device %04x has class code of PCI_CLASS_NOT_DEFINED\n",
1238 PciData->VendorID,
1239 PciData->DeviceID);
1240
1241 /*
1242 * The Alder has an Intel Extended Express System Support Controller
1243 * which presents apparently spurious BARs. When the PCI resource
1244 * code tries to reassign these BARs, the second IO-APIC gets
1245 * disabled (with disastrous consequences). The first BAR is the
1246 * actual IO-APIC, the remaining five bars seem to be spurious
1247 * resources, so ignore this device completely.
1248 */
1249 if ((PciData->VendorID == 0x8086) && (PciData->DeviceID == 8)) break;
1250 }
1251
1252 /* Other normal PCI cards and bridges are enumerated */
1253 if (PCI_CONFIGURATION_TYPE(PciData) <= PCI_CARDBUS_BRIDGE_TYPE) return FALSE;
1254 } while (FALSE);
1255
1256 /* Hit one of the known bugs/hackflags, or this is a new kind of PCI unit */
1257 DPRINT1(" Device skipped (not enumerated).\n");
1258 return TRUE;
1259}
1260
1261VOID
1262NTAPI
1263PciGetEnhancedCapabilities(IN PPCI_PDO_EXTENSION PdoExtension,
1264 IN PPCI_COMMON_HEADER PciData)
1265{
1266 ULONG HeaderType, CapPtr, TargetAgpCapabilityId;
1267 DEVICE_POWER_STATE WakeLevel;
1268 PCI_CAPABILITIES_HEADER AgpCapability;
1269 PCI_PM_CAPABILITY PowerCapabilities;
1270 PAGED_CODE();
1271
1272 /* Assume no known wake level */
1273 PdoExtension->PowerState.DeviceWakeLevel = PowerDeviceUnspecified;
1274
1275 /* Make sure the device has capabilities */
1276 if (!(PciData->Status & PCI_STATUS_CAPABILITIES_LIST))
1277 {
1278 /* If it doesn't, there will be no power management */
1279 PdoExtension->CapabilitiesPtr = 0;
1280 PdoExtension->HackFlags |= PCI_HACK_NO_PM_CAPS;
1281 }
1282 else
1283 {
1284 /* There's capabilities, need to figure out where to get the offset */
1285 HeaderType = PCI_CONFIGURATION_TYPE(PciData);
1286 if (HeaderType == PCI_CARDBUS_BRIDGE_TYPE)
1287 {
1288 /* Use the bridge's header */
1289 CapPtr = PciData->u.type2.CapabilitiesPtr;
1290 }
1291 else
1292 {
1293 /* Use the device header */
1294 ASSERT(HeaderType <= PCI_CARDBUS_BRIDGE_TYPE);
1295 CapPtr = PciData->u.type0.CapabilitiesPtr;
1296 }
1297
1298 /* Skip garbage capabilities pointer */
1299 if (((CapPtr & 0x3) != 0) || (CapPtr < PCI_COMMON_HDR_LENGTH))
1300 {
1301 /* Report no extended capabilities */
1302 PdoExtension->CapabilitiesPtr = 0;
1303 PdoExtension->HackFlags |= PCI_HACK_NO_PM_CAPS;
1304 }
1305 else
1306 {
1307 DPRINT1("Device has capabilities at: %lx\n", CapPtr);
1308 PdoExtension->CapabilitiesPtr = CapPtr;
1309
1310 /* Check for PCI-to-PCI Bridges and AGP bridges */
1311 if ((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1312 ((PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST) ||
1313 (PdoExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI)))
1314 {
1315 /* Query either the raw AGP capabilitity, or the Target AGP one */
1316 TargetAgpCapabilityId = (PdoExtension->SubClass ==
1317 PCI_SUBCLASS_BR_PCI_TO_PCI) ?
1318 PCI_CAPABILITY_ID_AGP_TARGET :
1319 PCI_CAPABILITY_ID_AGP;
1320 if (PciReadDeviceCapability(PdoExtension,
1321 PdoExtension->CapabilitiesPtr,
1322 TargetAgpCapabilityId,
1323 &AgpCapability,
1324 sizeof(PCI_CAPABILITIES_HEADER)))
1325 {
1326 /* AGP target ID was found, store it */
1327 DPRINT1("AGP ID: %lx\n", TargetAgpCapabilityId);
1328 PdoExtension->TargetAgpCapabilityId = TargetAgpCapabilityId;
1329 }
1330 }
1331
1332 /* Check for devices that are known not to have proper power management */
1333 if (!(PdoExtension->HackFlags & PCI_HACK_NO_PM_CAPS))
1334 {
1335 /* Query if this device supports power management */
1336 if (!PciReadDeviceCapability(PdoExtension,
1337 PdoExtension->CapabilitiesPtr,
1338 PCI_CAPABILITY_ID_POWER_MANAGEMENT,
1339 &PowerCapabilities.Header,
1340 sizeof(PCI_PM_CAPABILITY)))
1341 {
1342 /* No power management, so act as if it had the hackflag set */
1343 DPRINT1("No PM caps, disabling PM\n");
1344 PdoExtension->HackFlags |= PCI_HACK_NO_PM_CAPS;
1345 }
1346 else
1347 {
1348 /* Otherwise, pick the highest wake level that is supported */
1349 WakeLevel = PowerDeviceUnspecified;
1350 if (PowerCapabilities.PMC.Capabilities.Support.PMED0)
1351 WakeLevel = PowerDeviceD0;
1352 if (PowerCapabilities.PMC.Capabilities.Support.PMED1)
1353 WakeLevel = PowerDeviceD1;
1354 if (PowerCapabilities.PMC.Capabilities.Support.PMED2)
1355 WakeLevel = PowerDeviceD2;
1356 if (PowerCapabilities.PMC.Capabilities.Support.PMED3Hot)
1357 WakeLevel = PowerDeviceD3;
1358 if (PowerCapabilities.PMC.Capabilities.Support.PMED3Cold)
1359 WakeLevel = PowerDeviceD3;
1360 PdoExtension->PowerState.DeviceWakeLevel = WakeLevel;
1361
1362 /* Convert the PCI power state to the NT power state */
1363 PdoExtension->PowerState.CurrentDeviceState =
1364 PowerCapabilities.PMCSR.ControlStatus.PowerState + 1;
1365
1366 /* Save all the power capabilities */
1367 PdoExtension->PowerCapabilities = PowerCapabilities.PMC.Capabilities;
1368 DPRINT1("PM Caps Found! Wake Level: %d Power State: %d\n",
1369 WakeLevel, PdoExtension->PowerState.CurrentDeviceState);
1370 }
1371 }
1372 }
1373 }
1374
1375 /* Now find out whether this is an Express function, and what kind */
1376 PciGetExpressCapabilities(PdoExtension);
1377
1378 /* At the very end of all this, does this device not have power management? */
1379 if (PdoExtension->HackFlags & PCI_HACK_NO_PM_CAPS)
1380 {
1381 /* Then guess the current state based on whether the decodes are on */
1382 PdoExtension->PowerState.CurrentDeviceState =
1383 PciData->Command & (PCI_ENABLE_IO_SPACE |
1384 PCI_ENABLE_MEMORY_SPACE |
1385 PCI_ENABLE_BUS_MASTER) ?
1386 PowerDeviceD0: PowerDeviceD3;
1387 DPRINT1("PM is off, so assumed device is: %d based on enables\n",
1388 PdoExtension->PowerState.CurrentDeviceState);
1389 }
1390}
1391
1392VOID
1393NTAPI
1394PciWriteLimitsAndRestoreCurrent(IN PVOID Reserved,
1395 IN PVOID Context2)
1396{
1397 PPCI_CONFIGURATOR_CONTEXT Context = Context2;
1398 PPCI_COMMON_HEADER PciData, Current;
1399 PPCI_PDO_EXTENSION PdoExtension;
1400
1401 UNREFERENCED_PARAMETER(Reserved);
1402
1403 /* Grab all parameters from the context */
1404 PdoExtension = Context->PdoExtension;
1405 Current = Context->Current;
1406 PciData = Context->PciData;
1407
1408 /* Write the limit discovery header */
1409 PciWriteDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
1410
1411 /* Now read what the device indicated the limits are */
1412 PciReadDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
1413
1414 /* Then write back the original configuration header */
1415 PciWriteDeviceConfig(PdoExtension, Current, 0, PCI_COMMON_HDR_LENGTH);
1416
1417 /* Copy back the original command that was saved in the context */
1418 Current->Command = Context->Command;
1419 if (Context->Command)
1420 {
1421 /* Program it back into the device */
1422 PciWriteDeviceConfig(PdoExtension,
1423 &Context->Command,
1424 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
1425 sizeof(USHORT));
1426 }
1427
1428 /* Copy back the original status that was saved as well */
1429 Current->Status = Context->Status;
1430
1431 /* Call the configurator to restore any other data that might've changed */
1432 Context->Configurator->RestoreCurrent(Context);
1433}
1434
1435NTSTATUS
1436NTAPI
1437PcipGetFunctionLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
1438{
1439 PPCI_CONFIGURATOR Configurator;
1440 PPCI_COMMON_HEADER PciData, Current;
1441 PPCI_PDO_EXTENSION PdoExtension;
1442 PCI_IPI_CONTEXT IpiContext;
1443 PIO_RESOURCE_DESCRIPTOR IoDescriptor;
1444 ULONG Offset;
1445 PAGED_CODE();
1446
1447 /* Grab all parameters from the context */
1448 PdoExtension = Context->PdoExtension;
1449 Current = Context->Current;
1450 PciData = Context->PciData;
1451
1452 /* Save the current PCI Command and Status word */
1453 Context->Status = Current->Status;
1454 Context->Command = Current->Command;
1455
1456 /* Now that they're saved, clear the status, and disable all decodes */
1457 Current->Status = 0;
1458 Current->Command &= ~(PCI_ENABLE_IO_SPACE |
1459 PCI_ENABLE_MEMORY_SPACE |
1460 PCI_ENABLE_BUS_MASTER);
1461
1462 /* Make a copy of the current PCI configuration header (with decodes off) */
1463 RtlCopyMemory(PciData, Current, PCI_COMMON_HDR_LENGTH);
1464
1465 /* Locate the correct resource configurator for this type of device */
1466 Configurator = &PciConfigurators[PdoExtension->HeaderType];
1467 Context->Configurator = Configurator;
1468
1469 /* Initialize it, which will typically setup the BARs for limit discovery */
1470 Configurator->Initialize(Context);
1471
1472 /* Check for critical devices and PCI Debugging devices */
1473 if ((PdoExtension->HackFlags & PCI_HACK_CRITICAL_DEVICE) ||
1474 (PdoExtension->OnDebugPath))
1475 {
1476 /* Specifically check for a PCI Debugging device */
1477 if (PdoExtension->OnDebugPath)
1478 {
1479 /* Was it enabled for bus mastering? */
1480 if (Context->Command & PCI_ENABLE_BUS_MASTER)
1481 {
1482 /* This decode needs to be re-enabled so debugging can work */
1483 PciData->Command |= PCI_ENABLE_BUS_MASTER;
1484 Current->Command |= PCI_ENABLE_BUS_MASTER;
1485 }
1486
1487 /* Disable the debugger while the discovery is happening */
1488 KdDisableDebugger();
1489 }
1490
1491 /* For these devices, an IPI must be sent to force high-IRQL discovery */
1492 IpiContext.Barrier = 1;
1493 IpiContext.RunCount = 1;
1494 IpiContext.DeviceExtension = PdoExtension;
1495 IpiContext.Function = PciWriteLimitsAndRestoreCurrent;
1496 IpiContext.Context = Context;
1497 KeIpiGenericCall(PciExecuteCriticalSystemRoutine, (ULONG_PTR)&IpiContext);
1498
1499 /* Re-enable the debugger if this was a PCI Debugging Device */
1500 if (PdoExtension->OnDebugPath) KdEnableDebugger();
1501 }
1502 else
1503 {
1504 /* Otherwise, it's safe to do this inline at low IRQL */
1505 PciWriteLimitsAndRestoreCurrent(PdoExtension, Context);
1506 }
1507
1508 /*
1509 * Check if it's valid to compare the headers to see if limit discovery mode
1510 * has properly exited (the expected case is that the PCI header would now
1511 * be equal to what it was before). In some cases, it is known that this will
1512 * fail, because during PciApplyHacks (among other places), software hacks
1513 * had to be applied to the header, which the hardware-side will not see, and
1514 * thus the headers would appear "different".
1515 */
1516 if (!PdoExtension->ExpectedWritebackFailure)
1517 {
1518 /* Read the current PCI header now, after discovery has completed */
1519 PciReadDeviceConfig(PdoExtension, PciData + 1, 0, PCI_COMMON_HDR_LENGTH);
1520
1521 /* Check if the current header at entry, is equal to the header now */
1522 Offset = RtlCompareMemory(PciData + 1, Current, PCI_COMMON_HDR_LENGTH);
1523 if (Offset != PCI_COMMON_HDR_LENGTH)
1524 {
1525 /* It's not, which means configuration somehow changed, dump this */
1526 DPRINT1("PCI - CFG space write verify failed at offset 0x%x\n", Offset);
1527 PciDebugDumpCommonConfig(PciData + 1);
1528 DPRINT1("----------\n");
1529 PciDebugDumpCommonConfig(Current);
1530 }
1531 }
1532
1533 /* This PDO should not already have resources, since this is only done once */
1534 ASSERT(PdoExtension->Resources == NULL);
1535
1536 /* Allocate the structure that will hold the discovered resources and limits */
1537 PdoExtension->Resources = ExAllocatePoolWithTag(NonPagedPool,
1538 sizeof(PCI_FUNCTION_RESOURCES),
1539 'BicP');
1540 if (!PdoExtension->Resources) return STATUS_INSUFFICIENT_RESOURCES;
1541
1542 /* Clear it out for now */
1543 RtlZeroMemory(PdoExtension->Resources, sizeof(PCI_FUNCTION_RESOURCES));
1544
1545 /* Now call the configurator, which will first store the limits... */
1546 Configurator->SaveLimits(Context);
1547
1548 /* ...and then store the current resources being used */
1549 Configurator->SaveCurrentSettings(Context);
1550
1551 /* Loop all the limit descriptors backwards */
1552 IoDescriptor = &PdoExtension->Resources->Limit[PCI_TYPE0_ADDRESSES + 1];
1553 while (TRUE)
1554 {
1555 /* Keep going until a non-null descriptor is found */
1556 IoDescriptor--;
1557 if (IoDescriptor->Type != CmResourceTypeNull) break;
1558
1559 /* This is a null descriptor, have all of them been scanned now? */
1560 if (IoDescriptor == &PdoExtension->Resources->Limit[0])
1561 {
1562 /* This means the descriptor is NULL, which means discovery failed */
1563 DPRINT1("PCI Resources fail!\n");
1564
1565 /* No resources will be assigned for the device */
1566 ExFreePoolWithTag(PdoExtension->Resources, 0);
1567 PdoExtension->Resources = NULL;
1568 break;
1569 }
1570 }
1571
1572 /* Return success here, even if the device has no assigned resources */
1573 return STATUS_SUCCESS;
1574}
1575
1576NTSTATUS
1577NTAPI
1578PciGetFunctionLimits(IN PPCI_PDO_EXTENSION PdoExtension,
1579 IN PPCI_COMMON_HEADER Current,
1580 IN ULONGLONG HackFlags)
1581{
1582 NTSTATUS Status;
1583 PPCI_COMMON_HEADER PciData;
1584 PCI_CONFIGURATOR_CONTEXT Context;
1585 PAGED_CODE();
1586
1587 /* Do the hackflags indicate this device should be skipped? */
1588 if (PciSkipThisFunction(Current,
1589 PdoExtension->Slot,
1590 PCI_SKIP_RESOURCE_ENUMERATION,
1591 HackFlags))
1592 {
1593 /* Do not process its resources */
1594 return STATUS_SUCCESS;
1595 }
1596
1597 /* Allocate a buffer to hold two PCI configuration headers */
1598 PciData = ExAllocatePoolWithTag(0, 2 * PCI_COMMON_HDR_LENGTH, 'BicP');
1599 if (!PciData) return STATUS_INSUFFICIENT_RESOURCES;
1600
1601 /* Set up the context for the resource enumeration, and do it */
1602 Context.Current = Current;
1603 Context.PciData = PciData;
1604 Context.PdoExtension = PdoExtension;
1605 Status = PcipGetFunctionLimits(&Context);
1606
1607 /* Enumeration is completed, free the PCI headers and return the status */
1608 ExFreePoolWithTag(PciData, 0);
1609 return Status;
1610}
1611
1612VOID
1613NTAPI
1614PciProcessBus(IN PPCI_FDO_EXTENSION DeviceExtension)
1615{
1616 PPCI_PDO_EXTENSION PdoExtension;
1617 PDEVICE_OBJECT PhysicalDeviceObject;
1618 PAGED_CODE();
1619
1620 /* Get the PDO Extension */
1621 PhysicalDeviceObject = DeviceExtension->PhysicalDeviceObject;
1622 PdoExtension = (PPCI_PDO_EXTENSION)PhysicalDeviceObject->DeviceExtension;
1623
1624 /* Cheeck if this is the root bus */
1625 if (!PCI_IS_ROOT_FDO(DeviceExtension))
1626 {
1627 /* Not really handling this year */
1628 UNIMPLEMENTED_DBGBREAK();
1629
1630 /* Check for PCI bridges with the ISA bit set, or required */
1631 if ((PdoExtension) &&
1632 (PciClassifyDeviceType(PdoExtension) == PciTypePciBridge) &&
1633 ((PdoExtension->Dependent.type1.IsaBitRequired) ||
1634 (PdoExtension->Dependent.type1.IsaBitSet)))
1635 {
1636 /* We'll need to do some legacy support */
1637 UNIMPLEMENTED_DBGBREAK();
1638 }
1639 }
1640 else
1641 {
1642 /* Scan all of the root bus' children bridges */
1643 for (PdoExtension = DeviceExtension->ChildBridgePdoList;
1644 PdoExtension;
1645 PdoExtension = PdoExtension->NextBridge)
1646 {
1647 /* Find any that have the VGA decode bit on */
1648 if (PdoExtension->Dependent.type1.VgaBitSet)
1649 {
1650 /* Again, some more legacy support we'll have to do */
1651 UNIMPLEMENTED_DBGBREAK();
1652 }
1653 }
1654 }
1655
1656 /* Check for ACPI systems where the OS assigns bus numbers */
1657 if (PciAssignBusNumbers)
1658 {
1659 /* Not yet supported */
1660 UNIMPLEMENTED_DBGBREAK();
1661 }
1662}
1663
1664NTSTATUS
1665NTAPI
1666PciScanBus(IN PPCI_FDO_EXTENSION DeviceExtension)
1667{
1668 ULONG MaxDevice = PCI_MAX_DEVICES;
1669 BOOLEAN ProcessFlag = FALSE;
1670 ULONG i, j, k, Size;
1671 USHORT CapOffset, TempOffset;
1672 LONGLONG HackFlags;
1673 PDEVICE_OBJECT DeviceObject;
1674 UCHAR Buffer[PCI_COMMON_HDR_LENGTH];
1675 UCHAR BiosBuffer[PCI_COMMON_HDR_LENGTH];
1676 PPCI_COMMON_HEADER PciData = (PVOID)Buffer;
1677 PPCI_COMMON_HEADER BiosData = (PVOID)BiosBuffer;
1678 PCI_SLOT_NUMBER PciSlot;
1679 PCHAR Name;
1680 NTSTATUS Status;
1681 PPCI_PDO_EXTENSION PdoExtension, NewExtension;
1682 PPCI_PDO_EXTENSION* BridgeExtension;
1683 PWCHAR DescriptionText;
1684 USHORT SubVendorId, SubSystemId;
1685 PCI_CAPABILITIES_HEADER CapHeader, PcixCapHeader;
1686 UCHAR SecondaryBus;
1687 DPRINT1("PCI Scan Bus: FDO Extension @ 0x%p, Base Bus = 0x%x\n",
1688 DeviceExtension, DeviceExtension->BaseBus);
1689
1690 /* Is this the root FDO? */
1691 if (!PCI_IS_ROOT_FDO(DeviceExtension))
1692 {
1693 /* Get the PDO for the child bus */
1694 PdoExtension = DeviceExtension->PhysicalDeviceObject->DeviceExtension;
1695 ASSERT_PDO(PdoExtension);
1696
1697 /* Check for hack which only allows bus to have one child device */
1698 if (PdoExtension->HackFlags & PCI_HACK_ONE_CHILD) MaxDevice = 1;
1699
1700 /* Check if the secondary bus number has changed */
1701 PciReadDeviceConfig(PdoExtension,
1702 &SecondaryBus,
1703 FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.SecondaryBus),
1704 sizeof(UCHAR));
1705 if (SecondaryBus != PdoExtension->Dependent.type1.SecondaryBus)
1706 {
1707 UNIMPLEMENTED_DBGBREAK("PCI: Bus numbers have been changed! Restoring originals.\n");
1708 }
1709 }
1710
1711 /* Loop every device on the bus */
1712 PciSlot.u.bits.Reserved = 0;
1713 i = DeviceExtension->BaseBus;
1714 for (j = 0; j < MaxDevice; j++)
1715 {
1716 /* Loop every function of each device */
1717 PciSlot.u.bits.DeviceNumber = j;
1718 for (k = 0; k < PCI_MAX_FUNCTION; k++)
1719 {
1720 /* Build the final slot structure */
1721 PciSlot.u.bits.FunctionNumber = k;
1722
1723 /* Read the vendor for this slot */
1724 PciReadSlotConfig(DeviceExtension,
1725 PciSlot,
1726 PciData,
1727 0,
1728 sizeof(USHORT));
1729
1730 /* Skip invalid device */
1731 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
1732
1733 /* Now read the whole header */
1734 PciReadSlotConfig(DeviceExtension,
1735 PciSlot,
1736 &PciData->DeviceID,
1737 sizeof(USHORT),
1738 PCI_COMMON_HDR_LENGTH - sizeof(USHORT));
1739
1740 /* Apply any hacks before even analyzing the configuration header */
1741 PciApplyHacks(DeviceExtension,
1742 PciData,
1743 PciSlot,
1744 PCI_HACK_FIXUP_BEFORE_CONFIGURATION,
1745 NULL);
1746
1747 /* Dump device that was found */
1748 DPRINT1("Scan Found Device 0x%x (b=0x%x, d=0x%x, f=0x%x)\n",
1749 PciSlot.u.AsULONG,
1750 i,
1751 j,
1752 k);
1753
1754 /* Dump the device's header */
1755 PciDebugDumpCommonConfig(PciData);
1756
1757 /* Find description for this device for the debugger's sake */
1758 DescriptionText = PciGetDeviceDescriptionMessage(PciData->BaseClass,
1759 PciData->SubClass);
1760 DPRINT1("Device Description \"%S\".\n",
1761 DescriptionText ? DescriptionText : L"(NULL)");
1762 if (DescriptionText) ExFreePoolWithTag(DescriptionText, 0);
1763
1764 /* Check if there is an ACPI Watchdog Table */
1765 if (WdTable)
1766 {
1767 /* Check if this PCI device is the ACPI Watchdog Device... */
1768 UNIMPLEMENTED_DBGBREAK();
1769 }
1770
1771 /* Check for non-simple devices */
1772 if ((PCI_MULTIFUNCTION_DEVICE(PciData)) ||
1773 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV))
1774 {
1775 /* No subsystem data defined for these kinds of bridges */
1776 SubVendorId = 0;
1777 SubSystemId = 0;
1778 }
1779 else
1780 {
1781 /* Read the subsystem information from the PCI header */
1782 SubVendorId = PciData->u.type0.SubVendorID;
1783 SubSystemId = PciData->u.type0.SubSystemID;
1784 }
1785
1786 /* Get any hack flags for this device */
1787 HackFlags = PciGetHackFlags(PciData->VendorID,
1788 PciData->DeviceID,
1789 SubVendorId,
1790 SubSystemId,
1791 PciData->RevisionID);
1792
1793 /* Check if this device is considered critical by the OS */
1794 if (PciIsCriticalDeviceClass(PciData->BaseClass, PciData->SubClass))
1795 {
1796 /* The hack database can take a device out of its critical class */
1797 if (!(HackFlags & PCI_HACK_NOT_CRITICAL_DEVICE))
1798 {
1799 DPRINT1("Not allowing PM Because device is critical\n");
1800
1801 /* Probe it with the system held, and keep it decoding while stopped */
1802 HackFlags |= PCI_HACK_CRITICAL_DEVICE | PCI_HACK_KEEP_DECODES_ON_STOP;
1803
1804 /* Only the display can still be powered down */
1805 if (PciData->BaseClass != PCI_CLASS_DISPLAY_CTLR)
1806 HackFlags |= PCI_HACK_NEVER_POWER_DOWN;
1807 }
1808 }
1809
1810 /* PCI bridges with a VGA card are also considered critical */
1811 if ((PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1812 (PciData->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) &&
1813 (PciData->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA) &&
1814 !(HackFlags & PCI_HACK_NOT_CRITICAL_DEVICE))
1815 {
1816 /* They follow the adapter behind them, so they can still be powered down */
1817 DPRINT1("Not allowing PM because device is VGA\n");
1818 HackFlags |= PCI_HACK_CRITICAL_DEVICE | PCI_HACK_KEEP_DECODES_ON_STOP;
1819 }
1820
1821 /* Check if the device should be skipped for whatever reason */
1822 if (PciSkipThisFunction(PciData,
1823 PciSlot,
1824 PCI_SKIP_DEVICE_ENUMERATION,
1825 HackFlags))
1826 {
1827 /* Skip this device */
1828 continue;
1829 }
1830
1831 /* Check if a PDO has already been created for this device */
1832 PdoExtension = PciFindPdoByFunction(DeviceExtension,
1833 PciSlot.u.AsULONG,
1834 PciData);
1835 if (PdoExtension)
1836 {
1837 /* Rescan scenarios are not yet implemented */
1838 UNIMPLEMENTED_DBGBREAK();
1839 }
1840
1841 /* Bus processing will need to happen */
1842 ProcessFlag = TRUE;
1843
1844 /* Create the PDO for this device */
1845 Status = PciPdoCreate(DeviceExtension, PciSlot, &DeviceObject);
1846 ASSERT(NT_SUCCESS(Status));
1847 NewExtension = (PPCI_PDO_EXTENSION)DeviceObject->DeviceExtension;
1848
1849 /* Check for broken devices with wrong/no class codes */
1850 if (HackFlags & PCI_HACK_FAKE_CLASS_CODE)
1851 {
1852 /* Setup a default one */
1853 PciData->BaseClass = PCI_CLASS_BASE_SYSTEM_DEV;
1854 PciData->SubClass = PCI_SUBCLASS_SYS_OTHER;
1855
1856 /* Device will behave erratically when reading back data */
1857 NewExtension->ExpectedWritebackFailure = TRUE;
1858 }
1859
1860 /* Clone all the information from the header */
1861 NewExtension->VendorId = PciData->VendorID;
1862 NewExtension->DeviceId = PciData->DeviceID;
1863 NewExtension->RevisionId = PciData->RevisionID;
1864 NewExtension->ProgIf = PciData->ProgIf;
1865 NewExtension->SubClass = PciData->SubClass;
1866 NewExtension->BaseClass = PciData->BaseClass;
1867 NewExtension->HeaderType = PCI_CONFIGURATION_TYPE(PciData);
1868
1869 /* Check for modern bridge types, which are managed by the driver */
1870 if ((NewExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1871 ((NewExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) ||
1872 (NewExtension->SubClass == PCI_SUBCLASS_BR_CARDBUS)))
1873 {
1874 /* Acquire this device's lock */
1875 KeEnterCriticalRegion();
1876 KeWaitForSingleObject(&DeviceExtension->ChildListLock,
1877 Executive,
1878 KernelMode,
1879 FALSE,
1880 NULL);
1881
1882 /* Scan the bridge list until the first free entry */
1883 for (BridgeExtension = &DeviceExtension->ChildBridgePdoList;
1884 *BridgeExtension;
1885 BridgeExtension = &(*BridgeExtension)->NextBridge);
1886
1887 /* Add this PDO as a bridge */
1888 *BridgeExtension = NewExtension;
1889 ASSERT(NewExtension->NextBridge == NULL);
1890
1891 /* Release this device's lock */
1892 KeSetEvent(&DeviceExtension->ChildListLock,
1893 IO_NO_INCREMENT,
1894 FALSE);
1895 KeLeaveCriticalRegion();
1896 }
1897
1898 /* Get the PCI BIOS configuration saved in the registry */
1899 Status = PciGetBiosConfig(NewExtension, BiosData);
1900 if (NT_SUCCESS(Status))
1901 {
1902 /* This path has not yet been fully tested by eVb */
1903 DPRINT1("Have BIOS configuration!\n");
1904 UNIMPLEMENTED;
1905
1906 /* Check if the PCI BIOS configuration has changed */
1907 if (!PcipIsSameDevice(NewExtension, BiosData))
1908 {
1909 /* This is considered failure, and new data will be saved */
1910 Status = STATUS_UNSUCCESSFUL;
1911 }
1912 else
1913 {
1914 /* Data is still correct, check for interrupt line change */
1915 if (BiosData->u.type0.InterruptLine !=
1916 PciData->u.type0.InterruptLine)
1917 {
1918 /* Update the current BIOS with the saved interrupt line */
1919 PciWriteDeviceConfig(NewExtension,
1920 &BiosData->u.type0.InterruptLine,
1921 FIELD_OFFSET(PCI_COMMON_HEADER,
1922 u.type0.InterruptLine),
1923 sizeof(UCHAR));
1924 }
1925
1926 /* Save the BIOS interrupt line and the initial command */
1927 NewExtension->RawInterruptLine = BiosData->u.type0.InterruptLine;
1928 NewExtension->InitialCommand = BiosData->Command;
1929 }
1930 }
1931
1932 /* Check if no saved data was present or if it was a mismatch */
1933 if (!NT_SUCCESS(Status))
1934 {
1935 /* Save the new data */
1936 Status = PciSaveBiosConfig(NewExtension, PciData);
1937 ASSERT(NT_SUCCESS(Status));
1938
1939 /* Save the interrupt line and command from the device */
1940 NewExtension->RawInterruptLine = PciData->u.type0.InterruptLine;
1941 NewExtension->InitialCommand = PciData->Command;
1942 }
1943
1944 /* Save original command from the device and hack flags */
1945 NewExtension->CommandEnables = PciData->Command;
1946 NewExtension->HackFlags = HackFlags;
1947
1948 /* Get power, AGP, and other capability data */
1949 PciGetEnhancedCapabilities(NewExtension, PciData);
1950
1951 /* Now configure the BARs */
1952 Status = PciGetFunctionLimits(NewExtension, PciData, HackFlags);
1953
1954 /* Power up the device */
1955 PciSetPowerManagedDevicePowerState(NewExtension, PowerDeviceD0, FALSE);
1956
1957 /* Apply any device hacks required for enumeration */
1958 PciApplyHacks(DeviceExtension,
1959 PciData,
1960 PciSlot,
1961 PCI_HACK_FIXUP_AFTER_CONFIGURATION,
1962 NewExtension);
1963
1964 /* Save interrupt pin */
1965 NewExtension->InterruptPin = PciData->u.type0.InterruptPin;
1966
1967 /*
1968 * Use either this device's actual IRQ line or, if it's connected on
1969 * a master bus whose IRQ line is actually connected to the host, use
1970 * the HAL to query the bus' IRQ line and store that as the adjusted
1971 * interrupt line instead
1972 */
1973 NewExtension->AdjustedInterruptLine = PciGetAdjustedInterruptLine(NewExtension);
1974
1975 /* Check if this device is used for PCI debugger cards */
1976 NewExtension->OnDebugPath = PciIsDeviceOnDebugPath(NewExtension);
1977
1978 /* Check for devices with invalid/bogus subsystem data */
1979 if (HackFlags & PCI_HACK_NO_SUBSYSTEM)
1980 {
1981 /* Set the subsystem information to zero instead */
1982 NewExtension->SubsystemVendorId = 0;
1983 NewExtension->SubsystemId = 0;
1984 }
1985
1986 /* Scan all capabilities */
1987 CapOffset = NewExtension->CapabilitiesPtr;
1988 while (CapOffset)
1989 {
1990 /* Read this header */
1991 TempOffset = PciReadDeviceCapability(NewExtension,
1992 CapOffset,
1993 0,
1994 &CapHeader,
1995 sizeof(PCI_CAPABILITIES_HEADER));
1996 if (TempOffset != CapOffset)
1997 {
1998 /* This is a strange issue that shouldn't happen normally */
1999 DPRINT1("PCI - Failed to read PCI capability at offset 0x%02x\n",
2000 CapOffset);
2001 ASSERT(TempOffset == CapOffset);
2002 }
2003
2004 /* Check for capabilities that this driver cares about */
2005 switch (CapHeader.CapabilityID)
2006 {
2007 /* Power management capability is heavily used by the bus */
2008 case PCI_CAPABILITY_ID_POWER_MANAGEMENT:
2009
2010 /* Dump the capability */
2011 Name = "POWER";
2012 Size = sizeof(PCI_PM_CAPABILITY);
2013 break;
2014
2015 /* AGP capability is required for AGP bus functionality */
2016 case PCI_CAPABILITY_ID_AGP:
2017
2018 /* Dump the capability */
2019 Name = "AGP";
2020 Size = sizeof(PCI_AGP_CAPABILITY);
2021 break;
2022
2023 /* This driver doesn't really use anything other than that */
2024 default:
2025
2026 /* Windows prints this, we could do a translation later */
2027 Name = "UNKNOWN CAPABILITY";
2028 Size = 0;
2029 break;
2030 }
2031
2032 /* Check if this is a capability that should be dumped */
2033 if (Size)
2034 {
2035 /* Read the whole capability data */
2036 TempOffset = PciReadDeviceCapability(NewExtension,
2037 CapOffset,
2038 CapHeader.CapabilityID,
2039 &CapHeader,
2040 Size);
2041
2042 if (TempOffset != CapOffset)
2043 {
2044 /* Again, a strange issue that shouldn't be seen */
2045 DPRINT1("- Failed to read capability data. ***\n");
2046 ASSERT(TempOffset == CapOffset);
2047 }
2048 }
2049
2050 /* Dump this capability */
2051 DPRINT1("CAP @%02x ID %02x (%s)\n",
2052 CapOffset, CapHeader.CapabilityID, Name);
2053 for (i = 0; i < Size; i += 2)
2054 DPRINT1(" %04x\n", *(PUSHORT)((ULONG_PTR)&CapHeader + i));
2055 DPRINT1("\n");
2056
2057 /* Check the next capability */
2058 CapOffset = CapHeader.Next;
2059 }
2060
2061 /* Check for IDE controllers */
2062 if ((NewExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
2063 (NewExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
2064 {
2065 /* Do not allow them to power down completely */
2066 NewExtension->DisablePowerDown = TRUE;
2067 }
2068
2069 /*
2070 * Check if this is a legacy bridge. Note that the i82375 PCI/EISA
2071 * bridge that is present on certain NT Alpha machines appears as
2072 * non-classified so detect it manually by scanning for its VID/PID.
2073 */
2074 if (((NewExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
2075 ((NewExtension->SubClass == PCI_SUBCLASS_BR_ISA) ||
2076 (NewExtension->SubClass == PCI_SUBCLASS_BR_EISA) ||
2077 (NewExtension->SubClass == PCI_SUBCLASS_BR_MCA))) ||
2078 ((NewExtension->VendorId == 0x8086) &&
2079 (NewExtension->DeviceId == 0x482)))
2080 {
2081 /* Do not allow these legacy bridges to be powered down */
2082 NewExtension->DisablePowerDown = TRUE;
2083 }
2084
2085 /* Check if the BIOS did not configure a cache line size */
2086 if (!PciData->CacheLineSize)
2087 {
2088 /* Check if the device is disabled */
2089 if (!(NewExtension->CommandEnables & (PCI_ENABLE_IO_SPACE |
2090 PCI_ENABLE_MEMORY_SPACE |
2091 PCI_ENABLE_BUS_MASTER)))
2092 {
2093 /* Check if this is a PCI-X device*/
2094 TempOffset = PciReadDeviceCapability(NewExtension,
2095 NewExtension->CapabilitiesPtr,
2096 PCI_CAPABILITY_ID_PCIX,
2097 &PcixCapHeader,
2098 sizeof(PCI_CAPABILITIES_HEADER));
2099
2100 /*
2101 * A device with default cache line size and latency timer
2102 * settings is considered to be unconfigured. Note that on
2103 * PCI-X, the reset value of the latency timer field in the
2104 * header is 64, not 0, hence why the check for PCI-X caps
2105 * was required, and the value used here below.
2106 */
2107 if (!(PciData->LatencyTimer) ||
2108 ((TempOffset) && (PciData->LatencyTimer == 64)))
2109 {
2110 /* Keep track of the fact that it needs configuration */
2111 DPRINT1("PCI - ScanBus, PDOx %p found unconfigured\n",
2112 NewExtension);
2113 NewExtension->NeedsHotPlugConfiguration = TRUE;
2114 }
2115 }
2116 }
2117
2118 /* Save latency and cache size information */
2119 NewExtension->SavedLatencyTimer = PciData->LatencyTimer;
2120 NewExtension->SavedCacheLineSize = PciData->CacheLineSize;
2121
2122 /* The PDO is now ready to go */
2123 DeviceObject->Flags &= ~DO_DEVICE_INITIALIZING;
2124 }
2125 }
2126
2127 /* Enumeration completed, do a final pass now that all devices are found */
2128 if (ProcessFlag) PciProcessBus(DeviceExtension);
2129 return STATUS_SUCCESS;
2130}
2131
2132NTSTATUS
2133NTAPI
2134PciQueryDeviceRelations(IN PPCI_FDO_EXTENSION DeviceExtension,
2135 IN OUT PDEVICE_RELATIONS *pDeviceRelations)
2136{
2137 NTSTATUS Status;
2138 PPCI_PDO_EXTENSION PdoExtension;
2139 ULONG PdoCount = 0;
2140 PDEVICE_RELATIONS DeviceRelations, NewRelations;
2141 SIZE_T Size;
2142 PDEVICE_OBJECT DeviceObject, *ObjectArray;
2143 PAGED_CODE();
2144
2145 /* Make sure the FDO is started */
2146 ASSERT(DeviceExtension->DeviceState == PciStarted);
2147
2148 /* Synchronize while we enumerate the bus */
2149 Status = PciBeginStateTransition(DeviceExtension, PciSynchronizedOperation);
2150 if (!NT_SUCCESS(Status)) return Status;
2151
2152 /* Scan all children PDO */
2153 for (PdoExtension = DeviceExtension->ChildPdoList;
2154 PdoExtension;
2155 PdoExtension = PdoExtension->Next)
2156 {
2157 /* Invalidate them */
2158 PdoExtension->NotPresent = TRUE;
2159 }
2160
2161 /* Scan the PCI Bus */
2162 Status = PciScanBus(DeviceExtension);
2163 ASSERT(NT_SUCCESS(Status));
2164
2165 /* Enumerate all children PDO again */
2166 for (PdoExtension = DeviceExtension->ChildPdoList;
2167 PdoExtension;
2168 PdoExtension = PdoExtension->Next)
2169 {
2170 /* Check for PDOs that are still invalidated */
2171 if (PdoExtension->NotPresent)
2172 {
2173 /* This means this PDO existed before, but not anymore */
2174 PdoExtension->ReportedMissing = TRUE;
2175 DPRINT1("PCI - Old device (pdox) %p not found on rescan.\n",
2176 PdoExtension);
2177 }
2178 else
2179 {
2180 /* Increase count of detected PDOs */
2181 PdoCount++;
2182 }
2183 }
2184
2185 /* Read the current relations and add the newly discovered relations */
2186 DeviceRelations = *pDeviceRelations;
2187 Size = FIELD_OFFSET(DEVICE_RELATIONS, Objects) +
2188 PdoCount * sizeof(PDEVICE_OBJECT);
2189 if (DeviceRelations) Size += sizeof(PDEVICE_OBJECT) * DeviceRelations->Count;
2190
2191 /* Allocate the device relations */
2192 NewRelations = (PDEVICE_RELATIONS)ExAllocatePoolWithTag(0, Size, 'BicP');
2193 if (!NewRelations)
2194 {
2195 /* Out of space, cancel the operation */
2196 PciCancelStateTransition(DeviceExtension, PciSynchronizedOperation);
2197 return STATUS_INSUFFICIENT_RESOURCES;
2198 }
2199
2200 /* Check if there were any older relations */
2201 NewRelations->Count = 0;
2202 if (DeviceRelations)
2203 {
2204 /* Copy the old relations into the new buffer, then free the old one */
2205 RtlCopyMemory(NewRelations,
2206 DeviceRelations,
2207 FIELD_OFFSET(DEVICE_RELATIONS, Objects) +
2208 DeviceRelations->Count * sizeof(PDEVICE_OBJECT));
2209 ExFreePoolWithTag(DeviceRelations, 0);
2210 }
2211
2212 /* Print out that we're ready to dump relations */
2213 DPRINT1("PCI QueryDeviceRelations/BusRelations FDOx %p (bus 0x%02x)\n",
2214 DeviceExtension,
2215 DeviceExtension->BaseBus);
2216
2217 /* Loop the current PDO children and the device relation object array */
2218 PdoExtension = DeviceExtension->ChildPdoList;
2219 ObjectArray = &NewRelations->Objects[NewRelations->Count];
2220 while (PdoExtension)
2221 {
2222 /* Dump this relation */
2223 DPRINT1(" QDR PDO %p (x %p)%s\n",
2224 PdoExtension->PhysicalDeviceObject,
2225 PdoExtension,
2226 PdoExtension->NotPresent ?
2227 "<Omitted, device flaged not present>" : "");
2228
2229 /* Is this PDO present? */
2230 if (!PdoExtension->NotPresent)
2231 {
2232 /* Reference it and add it to the array */
2233 DeviceObject = PdoExtension->PhysicalDeviceObject;
2234 ObReferenceObject(DeviceObject);
2235 *ObjectArray++ = DeviceObject;
2236 }
2237
2238 /* Go to the next PDO */
2239 PdoExtension = PdoExtension->Next;
2240 }
2241
2242 /* Terminate dumping the relations */
2243 DPRINT1(" QDR Total PDO count = %u (%u already in list)\n",
2244 NewRelations->Count + PdoCount,
2245 NewRelations->Count);
2246
2247 /* Return the final count and the new buffer */
2248 NewRelations->Count += PdoCount;
2249 *pDeviceRelations = NewRelations;
2250 return STATUS_SUCCESS;
2251}
2252
2253NTSTATUS
2254NTAPI
2255PciSetResources(IN PPCI_PDO_EXTENSION PdoExtension,
2256 IN BOOLEAN DoReset,
2257 IN BOOLEAN SomethingSomethingDarkSide)
2258{
2259 PPCI_FDO_EXTENSION FdoExtension;
2260 UCHAR NewCacheLineSize, NewLatencyTimer;
2261 PCI_COMMON_HEADER PciData;
2262 BOOLEAN Native;
2263 PPCI_CONFIGURATOR Configurator;
2264
2265 UNREFERENCED_PARAMETER(SomethingSomethingDarkSide);
2266
2267 /* Get the FDO and read the configuration data */
2268 FdoExtension = PdoExtension->ParentFdoExtension;
2269 PciReadDeviceConfig(PdoExtension, &PciData, 0, PCI_COMMON_HDR_LENGTH);
2270
2271 /* Make sure this is still the same device */
2272 if (!PcipIsSameDevice(PdoExtension, &PciData))
2273 {
2274 /* Fail */
2275 ASSERTMSG("PCI Set resources - not same device.\n", FALSE);
2276 return STATUS_DEVICE_DOES_NOT_EXIST;
2277 }
2278
2279 /* Nothing to set for a host bridge */
2280 if ((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
2281 (PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST))
2282 {
2283 /* Fake success */
2284 return STATUS_SUCCESS;
2285 }
2286
2287 /* Check if an IDE controller is being reset */
2288 if ((DoReset) &&
2289 (PdoExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
2290 (PdoExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
2291 {
2292 /* Turn off native mode */
2293 Native = PciConfigureIdeController(PdoExtension, &PciData, FALSE);
2294 ASSERT(Native == PdoExtension->IDEInNativeMode);
2295 }
2296
2297 /* Check for update of a hotplug device, or first configuration of one */
2298 if ((PdoExtension->NeedsHotPlugConfiguration) &&
2299 (FdoExtension->HotPlugParameters.Acquired))
2300 {
2301 /* Don't have hotplug devices to test with yet, QEMU 0.14 should */
2302 UNIMPLEMENTED_DBGBREAK();
2303 }
2304
2305 /* Locate the correct resource configurator for this type of device */
2306 Configurator = &PciConfigurators[PdoExtension->HeaderType];
2307
2308 /* Apply the settings change */
2309 Configurator->ChangeResourceSettings(PdoExtension, &PciData);
2310
2311 /* Assume no update needed */
2312 PdoExtension->UpdateHardware = FALSE;
2313
2314 /* Check if a reset is needed */
2315 if (DoReset)
2316 {
2317 /* Reset resources */
2318 Configurator->ResetDevice(PdoExtension, &PciData);
2319 PciData.u.type0.InterruptLine = PdoExtension->RawInterruptLine;
2320 }
2321
2322 /* Check if the latency timer changed */
2323 NewLatencyTimer = PdoExtension->SavedLatencyTimer;
2324 if (PciData.LatencyTimer != NewLatencyTimer)
2325 {
2326 /* Debug notification */
2327 DPRINT1("PCI (pdox %p) changing latency from %02x to %02x.\n",
2328 PdoExtension,
2329 PciData.LatencyTimer,
2330 NewLatencyTimer);
2331 }
2332
2333 /* Check if the cache line changed */
2334 NewCacheLineSize = PdoExtension->SavedCacheLineSize;
2335 if (PciData.CacheLineSize != NewCacheLineSize)
2336 {
2337 /* Debug notification */
2338 DPRINT1("PCI (pdox %p) changing cache line size from %02x to %02x.\n",
2339 PdoExtension,
2340 PciData.CacheLineSize,
2341 NewCacheLineSize);
2342 }
2343
2344 /* Inherit data from PDO extension */
2345 PciData.LatencyTimer = PdoExtension->SavedLatencyTimer;
2346 PciData.CacheLineSize = PdoExtension->SavedCacheLineSize;
2347 PciData.u.type0.InterruptLine = PdoExtension->RawInterruptLine;
2348
2349 /* Apply any resource hacks required */
2350 PciApplyHacks(FdoExtension,
2351 &PciData,
2352 PdoExtension->Slot,
2353 PCI_HACK_FIXUP_BEFORE_UPDATE,
2354 PdoExtension);
2355
2356 /* Check if I/O space was disabled by administrator or driver */
2357 if (PdoExtension->IoSpaceNotRequired)
2358 {
2359 /* Don't turn on the decode */
2360 PdoExtension->CommandEnables &= ~PCI_ENABLE_IO_SPACE;
2361 }
2362
2363 /* Update the device with the new settings */
2364 PciUpdateHardware(PdoExtension, &PciData);
2365
2366 /* Update complete */
2367 PdoExtension->RawInterruptLine = PciData.u.type0.InterruptLine;
2368 PdoExtension->NeedsHotPlugConfiguration = FALSE;
2369 return STATUS_SUCCESS;
2370}
2371
2372/* EOF */
PAGED_CODE
#define PAGED_CODE()
Definition: Bus_PDO_EvalMethod.c:89
RTL_NUMBER_OF
#define RTL_NUMBER_OF(x)
Definition: RtlRegistry.c:12
Type
Type
Definition: Type.h:7
BOOLEAN
unsigned char BOOLEAN
Definition: actypes.h:127
ario_ApplyBrokenVideoHack
VOID NTAPI ario_ApplyBrokenVideoHack(IN PPCI_FDO_EXTENSION FdoExtension)
Definition: ar_memio.c:181
RtlCmDecodeMemIoResource
ULONGLONG NTAPI RtlCmDecodeMemIoResource(_In_ PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor, _Out_opt_ PULONGLONG Start)
Definition: memres.c:58
NTSTATUS
LONG NTSTATUS
Definition: precomp.h:26
DPRINT1
#define DPRINT1
Definition: precomp.h:8
UNIMPLEMENTED
#define UNIMPLEMENTED
Definition: ntoskrnl.c:15
PhysicalDeviceObject
PDEVICE_OBJECT PhysicalDeviceObject
Definition: btrfs_drv.h:1157
Cardbus_SaveCurrentSettings
VOID NTAPI Cardbus_SaveCurrentSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: cardbus.c:35
Cardbus_MassageHeaderForLimitsDetermination
VOID NTAPI Cardbus_MassageHeaderForLimitsDetermination(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: cardbus.c:51
Cardbus_RestoreCurrent
VOID NTAPI Cardbus_RestoreCurrent(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: cardbus.c:59
Cardbus_ChangeResourceSettings
VOID NTAPI Cardbus_ChangeResourceSettings(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: cardbus.c:89
Cardbus_SaveLimits
VOID NTAPI Cardbus_SaveLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: cardbus.c:43
Cardbus_ResetDevice
VOID NTAPI Cardbus_ResetDevice(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: cardbus.c:79
Cardbus_GetAdditionalResourceDescriptors
VOID NTAPI Cardbus_GetAdditionalResourceDescriptors(IN PPCI_CONFIGURATOR_CONTEXT Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)
Definition: cardbus.c:67
Resource
_Acquires_exclusive_lock_ Resource _Acquires_shared_lock_ Resource _Inout_ PERESOURCE Resource
Definition: cdprocs.h:843
HackFlags
_In_ ULONG_PTR HackFlags
Definition: cdrom.h:983
Buffer
Definition: bufpool.h:45
CmiGetNextPartialDescriptor
FORCEINLINE PCM_PARTIAL_RESOURCE_DESCRIPTOR CmiGetNextPartialDescriptor(_In_ const CM_PARTIAL_RESOURCE_DESCRIPTOR *PartialDescriptor)
Definition: cmreslist.h:31
STATUS_NOT_IMPLEMENTED
#define STATUS_NOT_IMPLEMENTED
Definition: d3dkmdt.h:42
Name
LPWSTR Name
Definition: desk.c:124
NULL
#define NULL
Definition: types.h:112
TRUE
#define TRUE
Definition: types.h:120
FALSE
#define FALSE
Definition: types.h:117
NT_SUCCESS
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:33
L
#define L(x)
Definition: resources.c:13
PciDebugPrintPartialResource
VOID NTAPI PciDebugPrintPartialResource(IN PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialResource)
Definition: debug.c:349
PciDebugDumpCommonConfig
VOID NTAPI PciDebugDumpCommonConfig(IN PPCI_COMMON_HEADER PciData)
Definition: debug.c:207
PciDebugPrintIoResReqList
VOID NTAPI PciDebugPrintIoResReqList(IN PIO_RESOURCE_REQUIREMENTS_LIST Requirements)
Definition: debug.c:303
PciDebugPrintCmResList
VOID NTAPI PciDebugPrintCmResList(IN PCM_RESOURCE_LIST PartialList)
Definition: debug.c:365
Device_GetAdditionalResourceDescriptors
VOID NTAPI Device_GetAdditionalResourceDescriptors(IN PPCI_CONFIGURATOR_CONTEXT Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)
Definition: device.c:260
Device_ChangeResourceSettings
VOID NTAPI Device_ChangeResourceSettings(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: device.c:284
Device_SaveLimits
VOID NTAPI Device_SaveLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: device.c:119
Device_MassageHeaderForLimitsDetermination
VOID NTAPI Device_MassageHeaderForLimitsDetermination(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: device.c:219
Device_SaveCurrentSettings
VOID NTAPI Device_SaveCurrentSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: device.c:20
Device_ResetDevice
VOID NTAPI Device_ResetDevice(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: device.c:273
Device_RestoreCurrent
VOID NTAPI Device_RestoreCurrent(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: device.c:251
PciWriteLimitsAndRestoreCurrent
VOID NTAPI PciWriteLimitsAndRestoreCurrent(IN PVOID Reserved, IN PVOID Context2)
Definition: enum.c:1394
PciGetEnhancedCapabilities
VOID NTAPI PciGetEnhancedCapabilities(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: enum.c:1263
PciSetResources
NTSTATUS NTAPI PciSetResources(IN PPCI_PDO_EXTENSION PdoExtension, IN BOOLEAN DoReset, IN BOOLEAN SomethingSomethingDarkSide)
Definition: enum.c:2255
PciSkipThisFunction
BOOLEAN NTAPI PciSkipThisFunction(IN PPCI_COMMON_HEADER PciData, IN PCI_SLOT_NUMBER Slot, IN UCHAR OperationType, IN ULONGLONG HackFlags)
Definition: enum.c:1189
PciBuildRequirementsList
NTSTATUS NTAPI PciBuildRequirementsList(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData, OUT PIO_RESOURCE_REQUIREMENTS_LIST *Buffer)
Definition: enum.c:572
PciAllocateCmResourceList
PCM_RESOURCE_LIST NTAPI PciAllocateCmResourceList(IN ULONG Count, IN ULONG BusNumber)
Definition: enum.c:341
PciProcessBus
VOID NTAPI PciProcessBus(IN PPCI_FDO_EXTENSION DeviceExtension)
Definition: enum.c:1614
PcipIsSameDevice
BOOLEAN NTAPI PcipIsSameDevice(IN PPCI_PDO_EXTENSION DeviceExtension, IN PPCI_COMMON_HEADER PciData)
Definition: enum.c:1155
PciScanBus
NTSTATUS NTAPI PciScanBus(IN PPCI_FDO_EXTENSION DeviceExtension)
Definition: enum.c:1666
PciQueryEjectionRelations
NTSTATUS NTAPI PciQueryEjectionRelations(IN PPCI_PDO_EXTENSION PdoExtension, IN OUT PDEVICE_RELATIONS *pDeviceRelations)
Definition: enum.c:559
PciQueryRequirements
NTSTATUS NTAPI PciQueryRequirements(IN PPCI_PDO_EXTENSION PdoExtension, IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *RequirementsList)
Definition: enum.c:675
PciQueryTargetDeviceRelations
NTSTATUS NTAPI PciQueryTargetDeviceRelations(IN PPCI_PDO_EXTENSION PdoExtension, IN OUT PDEVICE_RELATIONS *pDeviceRelations)
Definition: enum.c:532
PciConfigureIdeController
BOOLEAN NTAPI PciConfigureIdeController(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData, IN BOOLEAN Initial)
Definition: enum.c:746
PciQueryDeviceRelations
NTSTATUS NTAPI PciQueryDeviceRelations(IN PPCI_FDO_EXTENSION DeviceExtension, IN OUT PDEVICE_RELATIONS *pDeviceRelations)
Definition: enum.c:2134
PcipGetFunctionLimits
NTSTATUS NTAPI PcipGetFunctionLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: enum.c:1437
PcipUpdateHardware
VOID NTAPI PcipUpdateHardware(IN PVOID Context, IN PVOID Context2)
Definition: enum.c:255
PciZeroIoResourceRequirements
PIO_RESOURCE_REQUIREMENTS_LIST PciZeroIoResourceRequirements
Definition: enum.c:18
PciUpdateHardware
VOID NTAPI PciUpdateHardware(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: enum.c:282
PciAllocateIoRequirementsList
PIO_RESOURCE_REQUIREMENTS_LIST NTAPI PciAllocateIoRequirementsList(IN ULONG Count, IN ULONG BusNumber, IN ULONG SlotNumber)
Definition: enum.c:308
PciConfigurators
PCI_CONFIGURATOR PciConfigurators[]
Definition: enum.c:20
PciApplyHacks
VOID NTAPI PciApplyHacks(IN PPCI_FDO_EXTENSION DeviceExtension, IN PPCI_COMMON_HEADER PciData, IN PCI_SLOT_NUMBER SlotNumber, IN ULONG OperationType, PPCI_PDO_EXTENSION PdoExtension)
Definition: enum.c:886
PciComputeNewCurrentSettings
BOOLEAN NTAPI PciComputeNewCurrentSettings(IN PPCI_PDO_EXTENSION PdoExtension, IN PCM_RESOURCE_LIST ResourceList)
Definition: enum.c:55
PciGetFunctionLimits
NTSTATUS NTAPI PciGetFunctionLimits(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER Current, IN ULONGLONG HackFlags)
Definition: enum.c:1578
PciQueryResources
NTSTATUS NTAPI PciQueryResources(IN PPCI_PDO_EXTENSION PdoExtension, OUT PCM_RESOURCE_LIST *Buffer)
Definition: enum.c:371
PciEnableNativeModeATA
BOOLEAN PciEnableNativeModeATA
Definition: init.c:24
WdTable
PWATCHDOG_TABLE WdTable
Definition: init.c:27
PciReadSlotConfig
VOID NTAPI PciReadSlotConfig(IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_SLOT_NUMBER Slot, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: config.c:165
InitSafeBootMode
NTSYSAPI BOOLEAN InitSafeBootMode
Definition: init.c:71
PPBridge_SaveCurrentSettings
VOID NTAPI PPBridge_SaveCurrentSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: ppbridge.c:225
PciPdoCreate
NTSTATUS NTAPI PciPdoCreate(IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_SLOT_NUMBER Slot, OUT PDEVICE_OBJECT *PdoDeviceObject)
Definition: pdo.c:542
PciWriteDeviceConfig
VOID NTAPI PciWriteDeviceConfig(IN PPCI_PDO_EXTENSION DeviceExtension, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: config.c:133
PPBridge_GetAdditionalResourceDescriptors
VOID NTAPI PPBridge_GetAdditionalResourceDescriptors(IN PPCI_CONFIGURATOR_CONTEXT Context, IN PPCI_COMMON_HEADER PciData, IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)
Definition: ppbridge.c:629
PciStarted
@ PciStarted
Definition: pci.h:140
PciSynchronizedOperation
@ PciSynchronizedOperation
Definition: pci.h:144
PciGetDeviceDescriptionMessage
PWCHAR NTAPI PciGetDeviceDescriptionMessage(IN UCHAR BaseClass, IN UCHAR SubClass)
Definition: id.c:88
PciIsSlotPresentInParentMethod
BOOLEAN NTAPI PciIsSlotPresentInParentMethod(IN PPCI_PDO_EXTENSION PdoExtension, IN ULONG Method)
Definition: utils.c:1096
PciAssignBusNumbers
BOOLEAN PciAssignBusNumbers
Definition: config.c:18
PPCI_PDO_EXTENSION
struct _PCI_PDO_EXTENSION * PPCI_PDO_EXTENSION
PciCancelStateTransition
NTSTATUS NTAPI PciCancelStateTransition(IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_STATE NewState)
Definition: state.c:145
PciClassifyDeviceType
PCI_DEVICE_TYPES NTAPI PciClassifyDeviceType(IN PPCI_PDO_EXTENSION PdoExtension)
Definition: utils.c:1053
PciGetExpressCapabilities
VOID NTAPI PciGetExpressCapabilities(_Inout_ PPCI_PDO_EXTENSION PdoExtension)
Records the Express capability of a new function and whether its extended configuration space can be ...
Definition: express.c:99
PciBeginStateTransition
NTSTATUS NTAPI PciBeginStateTransition(IN PPCI_FDO_EXTENSION DeviceExtension, IN PCI_STATE NewState)
Definition: state.c:97
PciGetBiosConfig
NTSTATUS NTAPI PciGetBiosConfig(IN PPCI_PDO_EXTENSION DeviceExtension, OUT PPCI_COMMON_HEADER PciData)
Definition: utils.c:767
PPBridge_RestoreCurrent
VOID NTAPI PPBridge_RestoreCurrent(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: ppbridge.c:621
PCI_SKIP_RESOURCE_ENUMERATION
#define PCI_SKIP_RESOURCE_ENUMERATION
Definition: pci.h:65
PCI_HACK_FIXUP_BEFORE_UPDATE
#define PCI_HACK_FIXUP_BEFORE_UPDATE
Definition: pci.h:72
PciFindPdoByFunction
PPCI_PDO_EXTENSION NTAPI PciFindPdoByFunction(IN PPCI_FDO_EXTENSION DeviceExtension, IN ULONG FunctionNumber, IN PPCI_COMMON_HEADER PciData)
Definition: utils.c:694
PPBridge_MassageHeaderForLimitsDetermination
VOID NTAPI PPBridge_MassageHeaderForLimitsDetermination(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: ppbridge.c:583
PciIsDeviceOnDebugPath
BOOLEAN NTAPI PciIsDeviceOnDebugPath(IN PPCI_PDO_EXTENSION DeviceExtension)
Definition: utils.c:750
PCI_IS_ROOT_FDO
#define PCI_IS_ROOT_FDO(x)
Definition: pci.h:32
PciDecodeEnable
VOID NTAPI PciDecodeEnable(IN PPCI_PDO_EXTENSION PdoExtension, IN BOOLEAN Enable, OUT PUSHORT Command)
Definition: utils.c:1286
PciIsCriticalDeviceClass
BOOLEAN NTAPI PciIsCriticalDeviceClass(IN UCHAR BaseClass, IN UCHAR SubClass)
Definition: utils.c:671
PciReadDeviceCapability
UCHAR NTAPI PciReadDeviceCapability(IN PPCI_PDO_EXTENSION DeviceExtension, IN UCHAR Offset, IN ULONG CapabilityId, OUT PPCI_CAPABILITIES_HEADER Buffer, IN ULONG Length)
Definition: utils.c:885
PciSetPowerManagedDevicePowerState
NTSTATUS NTAPI PciSetPowerManagedDevicePowerState(IN PPCI_PDO_EXTENSION DeviceExtension, IN DEVICE_POWER_STATE DeviceState, IN BOOLEAN IrpSet)
Definition: power.c:121
PciGetHackFlags
ULONGLONG NTAPI PciGetHackFlags(IN USHORT VendorId, IN USHORT DeviceId, IN USHORT SubVendorId, IN USHORT SubSystemId, IN UCHAR RevisionId)
Definition: utils.c:603
PPBridge_ChangeResourceSettings
VOID NTAPI PPBridge_ChangeResourceSettings(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: ppbridge.c:684
PciSaveBiosConfig
NTSTATUS NTAPI PciSaveBiosConfig(IN PPCI_PDO_EXTENSION DeviceExtension, OUT PPCI_COMMON_HEADER PciData)
PciGetAdjustedInterruptLine
UCHAR NTAPI PciGetAdjustedInterruptLine(IN PPCI_PDO_EXTENSION PdoExtension)
Definition: config.c:24
PPBridge_SaveLimits
VOID NTAPI PPBridge_SaveLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
Definition: ppbridge.c:466
PCI_HACK_FIXUP_AFTER_CONFIGURATION
#define PCI_HACK_FIXUP_AFTER_CONFIGURATION
Definition: pci.h:71
PciTypePciBridge
@ PciTypePciBridge
Definition: pci.h:129
PCI_SKIP_DEVICE_ENUMERATION
#define PCI_SKIP_DEVICE_ENUMERATION
Definition: pci.h:64
PciExecuteCriticalSystemRoutine
KIPI_BROADCAST_WORKER PciExecuteCriticalSystemRoutine
Definition: pci.h:1146
ASSERT_PDO
#define ASSERT_PDO(x)
Definition: pci.h:38
PCI_HACK_FIXUP_BEFORE_CONFIGURATION
#define PCI_HACK_FIXUP_BEFORE_CONFIGURATION
Definition: pci.h:70
PPBridge_ResetDevice
VOID NTAPI PPBridge_ResetDevice(IN PPCI_PDO_EXTENSION PdoExtension, IN PPCI_COMMON_HEADER PciData)
Definition: ppbridge.c:674
PciReadDeviceConfig
VOID NTAPI PciReadDeviceConfig(IN PPCI_PDO_EXTENSION DeviceExtension, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: config.c:149
UNIMPLEMENTED_DBGBREAK
#define UNIMPLEMENTED_DBGBREAK(...)
Definition: debug.h:57
PdoExtension
@ PdoExtension
Definition: precomp.h:49
FdoExtension
@ FdoExtension
Definition: precomp.h:48
ExAllocatePoolWithTag
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
KeWaitForSingleObject
#define KeWaitForSingleObject(pEvt, foo, a, b, c)
Definition: env_spec_w32.h:478
RtlCompareMemory
#define RtlCompareMemory(s1, s2, l)
Definition: env_spec_w32.h:465
PDEVICE_OBJECT
struct _DEVICE_OBJECT * PDEVICE_OBJECT
KeSetEvent
#define KeSetEvent(pEvt, foo, foo2)
Definition: env_spec_w32.h:476
NonPagedPool
#define NonPagedPool
Definition: env_spec_w32.h:307
PagedPool
#define PagedPool
Definition: env_spec_w32.h:308
Native
unsigned int Native
Definition: fpcontrol.c:84
Status
Status
Definition: gdiplustypes.h:24
i
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
u
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble * u
Definition: glfuncs.h:240
j
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint GLint GLint j
Definition: glfuncs.h:250
DbgPrint
#define DbgPrint
Definition: hal.h:12
KdDisableDebugger
NTSTATUS NTAPI KdDisableDebugger(VOID)
Definition: kdapi.c:2169
KdEnableDebugger
NTSTATUS NTAPI KdEnableDebugger(VOID)
Definition: kdapi.c:2158
KeLeaveCriticalRegion
#define KeLeaveCriticalRegion()
Definition: ke_x.h:119
KeEnterCriticalRegion
#define KeEnterCriticalRegion()
Definition: ke_x.h:88
if
if(dx< 0)
Definition: linetemp.h:194
ASSERT
#define ASSERT(a)
Definition: mode.c:44
ExFreePoolWithTag
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1109
k
int k
Definition: mpi.c:3369
CM_RESOURCE_PORT_POSITIVE_DECODE
#define CM_RESOURCE_PORT_POSITIVE_DECODE
Definition: cmtypes.h:113
CM_RESOURCE_MEMORY_READ_WRITE
#define CM_RESOURCE_MEMORY_READ_WRITE
Definition: cmtypes.h:121
CM_RESOURCE_PORT_10_BIT_DECODE
#define CM_RESOURCE_PORT_10_BIT_DECODE
Definition: cmtypes.h:110
KernelMode
#define KernelMode
Definition: asm.h:38
Count
int Count
Definition: noreturn.cpp:7
ASSERTMSG
#define ASSERTMSG(msg, exp)
Definition: nt_native.h:431
UNREFERENCED_PARAMETER
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:329
Offset
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
ExIsProcessorFeaturePresent
BOOLEAN NTAPI ExIsProcessorFeaturePresent(IN ULONG ProcessorFeature)
Definition: sysinfo.c:363
KeIpiGenericCall
ULONG_PTR NTAPI KeIpiGenericCall(_In_ PKIPI_BROADCAST_WORKER Function, _In_ ULONG_PTR Argument)
Definition: ipi.c:44
PowerDeviceD1
@ PowerDeviceD1
Definition: ntpoapi.h:50
PowerDeviceUnspecified
@ PowerDeviceUnspecified
Definition: ntpoapi.h:48
PowerDeviceD0
@ PowerDeviceD0
Definition: ntpoapi.h:49
PowerDeviceD2
@ PowerDeviceD2
Definition: ntpoapi.h:51
PowerDeviceD3
@ PowerDeviceD3
Definition: ntpoapi.h:52
DEVICE_POWER_STATE
enum _DEVICE_POWER_STATE DEVICE_POWER_STATE
STATUS_DEVICE_DOES_NOT_EXIST
#define STATUS_DEVICE_DOES_NOT_EXIST
Definition: ntstatus.h:522
PciSlot
_In_ ULONG _In_ PCI_SLOT_NUMBER PciSlot
Definition: pciidex.h:66
BusNumber
_In_ ULONG BusNumber
Definition: pciidex.h:65
USHORT
unsigned short USHORT
Definition: pedump.c:61
CmResourceTypeNull
#define CmResourceTypeNull
Definition: restypes.h:103
CM_RESOURCE_LIST
struct _CM_RESOURCE_LIST CM_RESOURCE_LIST
CmResourceTypeMemory
#define CmResourceTypeMemory
Definition: restypes.h:106
CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
#define CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
Definition: restypes.h:116
CmResourceTypeDevicePrivate
#define CmResourceTypeDevicePrivate
Definition: restypes.h:112
PCIBus
@ PCIBus
Definition: restypes.h:127
CM_PARTIAL_RESOURCE_DESCRIPTOR
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR CM_PARTIAL_RESOURCE_DESCRIPTOR
CmResourceTypePort
#define CmResourceTypePort
Definition: restypes.h:104
CmResourceTypeInterrupt
#define CmResourceTypeInterrupt
Definition: restypes.h:105
IO_RESOURCE_DESCRIPTOR
struct _IO_RESOURCE_DESCRIPTOR IO_RESOURCE_DESCRIPTOR
PCI_HACK_PRESERVE_COMMAND
#define PCI_HACK_PRESERVE_COMMAND
Definition: pci.h:25
PCI_HACK_CRITICAL_DEVICE
#define PCI_HACK_CRITICAL_DEVICE
Definition: pci.h:48
PCI_ENABLE_BRIDGE_VGA
#define PCI_ENABLE_BRIDGE_VGA
Definition: pci.h:63
PCI_HACK_ENUM_NO_RESOURCE
#define PCI_HACK_ENUM_NO_RESOURCE
Definition: pci.h:15
PCI_HACK_NO_REVISION_AFTER_D3
#define PCI_HACK_NO_REVISION_AFTER_D3
Definition: pci.h:51
PCI_HACK_NOT_CRITICAL_DEVICE
#define PCI_HACK_NOT_CRITICAL_DEVICE
Definition: pci.h:49
PCI_HACK_ONE_CHILD
#define PCI_HACK_ONE_CHILD
Definition: pci.h:24
PCI_HACK_NO_SUBSYSTEM_AFTER_D3
#define PCI_HACK_NO_SUBSYSTEM_AFTER_D3
Definition: pci.h:42
PCI_HACK_NO_SUBSYSTEM
#define PCI_HACK_NO_SUBSYSTEM
Definition: pci.h:33
PCI_HACK_FAKE_CLASS_CODE
#define PCI_HACK_FAKE_CLASS_CODE
Definition: pci.h:44
PCI_HACK_VIDEO_LEGACY_DECODE
#define PCI_HACK_VIDEO_LEGACY_DECODE
Definition: pci.h:43
PCI_HACK_NO_ENUM_AT_ALL
#define PCI_HACK_NO_ENUM_AT_ALL
Definition: pci.h:14
PCI_HACK_DISABLE_IDE_NATIVE_MODE
#define PCI_HACK_DISABLE_IDE_NATIVE_MODE
Definition: pci.h:46
PCI_HACK_NEVER_POWER_DOWN
#define PCI_HACK_NEVER_POWER_DOWN
Definition: pci.h:41
PCI_HACK_DOUBLE_DECKER
#define PCI_HACK_DOUBLE_DECKER
Definition: pci.h:23
PCI_HACK_BROKEN_SUBTRACTIVE_DECODE
#define PCI_HACK_BROKEN_SUBTRACTIVE_DECODE
Definition: pci.h:50
PCI_HACK_NO_PM_CAPS
#define PCI_HACK_NO_PM_CAPS
Definition: pci.h:40
PCI_HACK_KEEP_DECODES_ON_STOP
#define PCI_HACK_KEEP_DECODES_ON_STOP
Definition: pci.h:12
STATUS_SUCCESS
#define STATUS_SUCCESS
Definition: shellext.h:65
Context
_In_ PVOID Context
Definition: storport.h:2269
Command
Definition: shell.h:41
_CM_FULL_RESOURCE_DESCRIPTOR
Definition: restypes.h:142
_CM_FULL_RESOURCE_DESCRIPTOR::PartialResourceList
CM_PARTIAL_RESOURCE_LIST PartialResourceList
Definition: restypes.h:145
_CM_PARTIAL_RESOURCE_DESCRIPTOR
Definition: restypes.h:8
_CM_PARTIAL_RESOURCE_DESCRIPTOR::ShareDisposition
UCHAR ShareDisposition
Definition: restypes.h:10
_CM_PARTIAL_RESOURCE_DESCRIPTOR::Generic
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR::@486::@487 Generic
_CM_PARTIAL_RESOURCE_DESCRIPTOR::Type
UCHAR Type
Definition: restypes.h:9
_CM_PARTIAL_RESOURCE_DESCRIPTOR::Interrupt
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR::@486::@489 Interrupt
_CM_PARTIAL_RESOURCE_DESCRIPTOR::Flags
USHORT Flags
Definition: restypes.h:11
_CM_PARTIAL_RESOURCE_DESCRIPTOR::DevicePrivate
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR::@486::@493 DevicePrivate
_CM_PARTIAL_RESOURCE_DESCRIPTOR::u
union _CM_PARTIAL_RESOURCE_DESCRIPTOR::@486 u
_CM_PARTIAL_RESOURCE_LIST::PartialDescriptors
CM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptors[1]
Definition: restypes.h:100
_CM_PARTIAL_RESOURCE_LIST::Count
ULONG Count
Definition: restypes.h:99
_CM_RESOURCE_LIST
Definition: restypes.h:148
_DEVICE_OBJECT
Definition: env_spec_w32.h:413
_DEVICE_OBJECT::DeviceExtension
PVOID DeviceExtension
Definition: env_spec_w32.h:418
_DEVICE_RELATIONS
Definition: iotypes.h:2163
_DEVICE_RELATIONS::Count
ULONG Count
Definition: iotypes.h:2164
_DEVICE_RELATIONS::Objects
PDEVICE_OBJECT Objects[1]
Definition: iotypes.h:2165
_IO_RESOURCE_DESCRIPTOR
Definition: miniport.h:144
_IO_RESOURCE_DESCRIPTOR::Type
UCHAR Type
Definition: miniport.h:146
_IO_RESOURCE_REQUIREMENTS_LIST
Definition: iotypes.h:2742
_PCI_CAPABILITIES_HEADER
Definition: iotypes.h:3667
_PCI_CAPABILITIES_HEADER::CapabilityID
UCHAR CapabilityID
Definition: iotypes.h:3668
_PCI_CAPABILITIES_HEADER::Next
UCHAR Next
Definition: iotypes.h:3669
_PCI_COMMON_HEADER
Definition: iotypes.h:3580
_PCI_CONFIGURATOR_CONTEXT
Definition: pci.h:503
_PCI_CONFIGURATOR
Definition: pci.h:489
_PCI_CONFIGURATOR::ChangeResourceSettings
PCI_CONFIGURATOR_CHANGE_RESOURCE_SETTINGS ChangeResourceSettings
Definition: pci.h:494
_PCI_CONFIGURATOR::SaveLimits
PCI_CONFIGURATOR_SAVE_LIMITS SaveLimits
Definition: pci.h:492
_PCI_CONFIGURATOR::ResetDevice
PCI_CONFIGURATOR_RESET_DEVICE ResetDevice
Definition: pci.h:496
_PCI_CONFIGURATOR::Initialize
PCI_CONFIGURATOR_INITIALIZE Initialize
Definition: pci.h:490
_PCI_CONFIGURATOR::SaveCurrentSettings
PCI_CONFIGURATOR_SAVE_CURRENT_SETTINGS SaveCurrentSettings
Definition: pci.h:493
_PCI_FDO_EXTENSION
Definition: pci.h:203
_PCI_FUNCTION_RESOURCES
Definition: pci.h:246
_PCI_FUNCTION_RESOURCES::Limit
IO_RESOURCE_DESCRIPTOR Limit[7]
Definition: pci.h:247
_PCI_FUNCTION_RESOURCES::Current
CM_PARTIAL_RESOURCE_DESCRIPTOR Current[7]
Definition: pci.h:248
_PCI_IPI_CONTEXT
Definition: pci.h:525
_PCI_IPI_CONTEXT::RunCount
LONG RunCount
Definition: pci.h:526
_PCI_IPI_CONTEXT::Barrier
ULONG Barrier
Definition: pci.h:527
_PCI_IPI_CONTEXT::Context
PVOID Context
Definition: pci.h:530
_PCI_IPI_CONTEXT::Function
PCI_IPI_FUNCTION Function
Definition: pci.h:529
_PCI_IPI_CONTEXT::DeviceExtension
PVOID DeviceExtension
Definition: pci.h:528
_PCI_PDO_EXTENSION
Definition: pci.h:275
_PCI_PDO_EXTENSION::ProgIf
BOOLEAN ProgIf
Definition: pci.h:294
_PCI_PDO_EXTENSION::BaseClass
BOOLEAN BaseClass
Definition: pci.h:296
_PCI_PDO_EXTENSION::HackFlags
ULONGLONG HackFlags
Definition: pci.h:321
_PCI_PDO_EXTENSION::AdjustedInterruptLine
BOOLEAN AdjustedInterruptLine
Definition: pci.h:298
_PCI_PDO_EXTENSION::InterruptPin
BOOLEAN InterruptPin
Definition: pci.h:299
_PCI_PDO_EXTENSION::RawInterruptLine
BOOLEAN RawInterruptLine
Definition: pci.h:300
_PCI_PDO_EXTENSION::SubsystemVendorId
USHORT SubsystemVendorId
Definition: pci.h:291
_PCI_PDO_EXTENSION::SubsystemId
USHORT SubsystemId
Definition: pci.h:292
_PCI_PDO_EXTENSION::CommandEnables
USHORT CommandEnables
Definition: pci.h:329
_PCI_PDO_EXTENSION::SavedCacheLineSize
BOOLEAN SavedCacheLineSize
Definition: pci.h:303
_PCI_PDO_EXTENSION::SavedLatencyTimer
BOOLEAN SavedLatencyTimer
Definition: pci.h:302
_PCI_PDO_EXTENSION::DeviceId
USHORT DeviceId
Definition: pci.h:290
_PCI_PDO_EXTENSION::NextBridge
struct _PCI_PDO_EXTENSION * NextBridge
Definition: pci.h:324
_PCI_PDO_EXTENSION::HeaderType
BOOLEAN HeaderType
Definition: pci.h:304
_PCI_PDO_EXTENSION::InitialCommand
USHORT InitialCommand
Definition: pci.h:330
_PCI_PDO_EXTENSION::NeedsHotPlugConfiguration
BOOLEAN NeedsHotPlugConfiguration
Definition: pci.h:313
_PCI_PDO_EXTENSION::SubClass
BOOLEAN SubClass
Definition: pci.h:295
_PCI_PDO_EXTENSION::CapabilitiesPtr
BOOLEAN CapabilitiesPtr
Definition: pci.h:301
_PCI_PDO_EXTENSION::VendorId
USHORT VendorId
Definition: pci.h:289
_PCI_PDO_EXTENSION::OnDebugPath
BOOLEAN OnDebugPath
Definition: pci.h:317
_PCI_PDO_EXTENSION::DisablePowerDown
BOOLEAN DisablePowerDown
Definition: pci.h:312
_PCI_PDO_EXTENSION::ExpectedWritebackFailure
BOOLEAN ExpectedWritebackFailure
Definition: pci.h:307
_PCI_PDO_EXTENSION::RevisionId
BOOLEAN RevisionId
Definition: pci.h:293
_PCI_PM_CAPABILITY
Definition: iotypes.h:3705
_PCI_SLOT_NUMBER
Definition: iotypes.h:3491
_PCI_SLOT_NUMBER::AsULONG
ULONG AsULONG
Definition: iotypes.h:3498
_PCI_SLOT_NUMBER::u
union _PCI_SLOT_NUMBER::@4969 u
_PCI_SLOT_NUMBER::bits
struct _PCI_SLOT_NUMBER::@4969::@4970 bits
BiosData
PBIOS_DATA BiosData
Definition: bios.c:42
Context2
_In_ PNET_PNP_EVENT _In_ PTDI_PNP_CONTEXT _In_ PTDI_PNP_CONTEXT Context2
Definition: tdikrnl.h:1096
MAXULONG
#define MAXULONG
Definition: typedefs.h:251
UCHAR
unsigned char UCHAR
Definition: typedefs.h:53
FIELD_OFFSET
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
LONGLONG
int64_t LONGLONG
Definition: typedefs.h:68
NTAPI
#define NTAPI
Definition: typedefs.h:36
PVOID
void * PVOID
Definition: typedefs.h:50
SIZE_T
ULONG_PTR SIZE_T
Definition: typedefs.h:80
ULONGLONG
uint64_t ULONGLONG
Definition: typedefs.h:67
PUSHORT
uint16_t * PUSHORT
Definition: typedefs.h:56
RtlCopyMemory
#define RtlCopyMemory(Destination, Source, Length)
Definition: typedefs.h:263
RtlZeroMemory
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
ULONG_PTR
uint32_t ULONG_PTR
Definition: typedefs.h:65
IN
#define IN
Definition: typedefs.h:39
PWCHAR
uint16_t * PWCHAR
Definition: typedefs.h:56
ULONG
uint32_t ULONG
Definition: typedefs.h:59
OUT
#define OUT
Definition: typedefs.h:40
PCHAR
char * PCHAR
Definition: typedefs.h:51
STATUS_UNSUCCESSFUL
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
STATUS_INSUFFICIENT_RESOURCES
#define STATUS_INSUFFICIENT_RESOURCES
Definition: udferr_usr.h:158
DeviceObject
_In_ PDEVICE_OBJECT DeviceObject
Definition: wdfdevice.h:2061
Size
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_DEVICE_PROPERTY_DATA _In_ DEVPROPTYPE _In_ ULONG Size
Definition: wdfdevice.h:4539
PowerCapabilities
_In_ WDFDEVICE _In_ PWDF_DEVICE_POWER_CAPABILITIES PowerCapabilities
Definition: wdfdevice.h:3892
ResourceList
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
Definition: wdfresource.h:309
RequirementsList
_In_ WDFIORESREQLIST RequirementsList
Definition: wdfresource.h:65
Descriptor
_Must_inspect_result_ _In_ WDFIORESLIST _In_ PIO_RESOURCE_DESCRIPTOR Descriptor
Definition: wdfresource.h:342
SlotNumber
_In_ WDFIORESREQLIST _In_ ULONG SlotNumber
Definition: wdfresource.h:68
Reserved
_Reserved_ PVOID Reserved
Definition: winddi.h:3974
CmResourceShareDeviceExclusive
@ CmResourceShareDeviceExclusive
Definition: cmtypes.h:241
CmResourceShareShared
@ CmResourceShareShared
Definition: cmtypes.h:243
CmResourceShareDriverExclusive
@ CmResourceShareDriverExclusive
Definition: cmtypes.h:242
CmResourceTypeMemoryLarge
#define CmResourceTypeMemoryLarge
Definition: cmtypes.h:231
PCI_INVALID_VENDORID
#define PCI_INVALID_VENDORID
Definition: iotypes.h:3603
PCI_CAPABILITY_ID_AGP
#define PCI_CAPABILITY_ID_AGP
Definition: iotypes.h:3650
PCI_CAPABILITY_ID_PCIX
#define PCI_CAPABILITY_ID_PCIX
Definition: iotypes.h:3655
PCI_ENABLE_BUS_MASTER
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3620
IO_NO_INCREMENT
#define IO_NO_INCREMENT
Definition: iotypes.h:598
PCI_ENABLE_WRITE_AND_INVALIDATE
#define PCI_ENABLE_WRITE_AND_INVALIDATE
Definition: iotypes.h:3622
PCI_SUBCLASS_BR_EISA
#define PCI_SUBCLASS_BR_EISA
Definition: iotypes.h:4166
PCI_SUBCLASS_BR_HOST
#define PCI_SUBCLASS_BR_HOST
Definition: iotypes.h:4164
PCI_TYPE0_ADDRESSES
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3502
PCI_ENABLE_IO_SPACE
#define PCI_ENABLE_IO_SPACE
Definition: iotypes.h:3618
PCI_SUBCLASS_BR_PCI_TO_PCI
#define PCI_SUBCLASS_BR_PCI_TO_PCI
Definition: iotypes.h:4168
PCI_CLASS_MASS_STORAGE_CTLR
#define PCI_CLASS_MASS_STORAGE_CTLR
Definition: iotypes.h:4106
PCI_AGP_CAPABILITY
struct _PCI_AGP_CAPABILITY PCI_AGP_CAPABILITY
PCI_SUBCLASS_SYS_OTHER
#define PCI_SUBCLASS_SYS_OTHER
Definition: iotypes.h:4187
PCI_CONFIGURATION_TYPE
#define PCI_CONFIGURATION_TYPE(PciData)
Definition: iotypes.h:3611
PCI_SUBCLASS_MSC_IDE_CTLR
#define PCI_SUBCLASS_MSC_IDE_CTLR
Definition: iotypes.h:4131
PCI_ENABLE_MEMORY_SPACE
#define PCI_ENABLE_MEMORY_SPACE
Definition: iotypes.h:3619
PCI_SUBCLASS_BR_MCA
#define PCI_SUBCLASS_BR_MCA
Definition: iotypes.h:4167
PCI_MAX_FUNCTION
#define PCI_MAX_FUNCTION
Definition: iotypes.h:3601
PCI_PM_CAPABILITY
struct _PCI_PM_CAPABILITY PCI_PM_CAPABILITY
PCI_BRIDGE_TYPE
#define PCI_BRIDGE_TYPE
Definition: iotypes.h:3608
PCI_COMMON_HDR_LENGTH
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3596
PCI_SUBCLASS_BR_ISA
#define PCI_SUBCLASS_BR_ISA
Definition: iotypes.h:4165
PCI_CLASS_BRIDGE_DEV
#define PCI_CLASS_BRIDGE_DEV
Definition: iotypes.h:4111
PCI_SUBCLASS_BR_CARDBUS
#define PCI_SUBCLASS_BR_CARDBUS
Definition: iotypes.h:4171
PCI_STATUS_CAPABILITIES_LIST
#define PCI_STATUS_CAPABILITIES_LIST
Definition: iotypes.h:3632
PCI_CAPABILITY_ID_POWER_MANAGEMENT
#define PCI_CAPABILITY_ID_POWER_MANAGEMENT
Definition: iotypes.h:3649
PCI_CLASS_NOT_DEFINED
#define PCI_CLASS_NOT_DEFINED
Definition: iotypes.h:4123
PCI_CLASS_BASE_SYSTEM_DEV
#define PCI_CLASS_BASE_SYSTEM_DEV
Definition: iotypes.h:4113
PCI_CAPABILITY_ID_AGP_TARGET
#define PCI_CAPABILITY_ID_AGP_TARGET
Definition: iotypes.h:3662
PCI_MAX_DEVICES
#define PCI_MAX_DEVICES
Definition: iotypes.h:3600
PCI_MULTIFUNCTION_DEVICE
#define PCI_MULTIFUNCTION_DEVICE(PciData)
Definition: iotypes.h:3614
PCI_CLASS_DISPLAY_CTLR
#define PCI_CLASS_DISPLAY_CTLR
Definition: iotypes.h:4108
PCI_CARDBUS_BRIDGE_TYPE
#define PCI_CARDBUS_BRIDGE_TYPE
Definition: iotypes.h:3609
IO_RESOURCE_REQUIREMENTS_LIST
struct _IO_RESOURCE_REQUIREMENTS_LIST IO_RESOURCE_REQUIREMENTS_LIST
Limit
_In_ LONG _In_ LONG Limit
Definition: kefuncs.h:304
PF_PAE_ENABLED
#define PF_PAE_ENABLED
Definition: ketypes.h:185
Executive
@ Executive
Definition: ketypes.h:467
ObReferenceObject
#define ObReferenceObject
Definition: obfuncs.h:204