ReactOS  0.4.13-dev-241-g63286c6
pdo.c
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1 /*
2  * PROJECT: ReactOS PCI bus driver
3  * FILE: pdo.c
4  * PURPOSE: Child device object dispatch routines
5  * PROGRAMMERS: Casper S. Hornstrup (chorns@users.sourceforge.net)
6  * UPDATE HISTORY:
7  * 10-09-2001 CSH Created
8  */
9 
10 #include "pci.h"
11 
12 #include <initguid.h>
13 #include <wdmguid.h>
14 
15 #define NDEBUG
16 #include <debug.h>
17 
18 #if 0
19 #define DBGPRINT(...) DbgPrint(__VA_ARGS__)
20 #else
21 #define DBGPRINT(...)
22 #endif
23 
24 #define PCI_ADDRESS_MEMORY_ADDRESS_MASK_64 0xfffffffffffffff0ull
25 #define PCI_ADDRESS_IO_ADDRESS_MASK_64 0xfffffffffffffffcull
26 
27 /*** PRIVATE *****************************************************************/
28 
29 static NTSTATUS
32  IN PIRP Irp,
34 {
35  PPDO_DEVICE_EXTENSION DeviceExtension;
38 
39  DPRINT("Called\n");
40 
42 
43  switch (IrpSp->Parameters.QueryDeviceText.DeviceTextType)
44  {
47  &DeviceExtension->DeviceDescription,
48  &String);
49 
50  DPRINT("DeviceTextDescription\n");
51  Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
52  break;
53 
56  &DeviceExtension->DeviceLocation,
57  &String);
58 
59  DPRINT("DeviceTextLocationInformation\n");
60  Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
61  break;
62 
63  default:
64  Irp->IoStatus.Information = 0;
66  break;
67  }
68 
69  return Status;
70 }
71 
72 
73 static NTSTATUS
76  IN PIRP Irp,
78 {
79  PPDO_DEVICE_EXTENSION DeviceExtension;
82 
83  DPRINT("Called\n");
84 
86 
87 // Irp->IoStatus.Information = 0;
88 
90 
92 
93  switch (IrpSp->Parameters.QueryId.IdType)
94  {
95  case BusQueryDeviceID:
97  &DeviceExtension->DeviceID,
98  &String);
99 
100  DPRINT("DeviceID: %S\n", String.Buffer);
101 
102  Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
103  break;
104 
105  case BusQueryHardwareIDs:
107  &DeviceExtension->HardwareIDs,
108  &String);
109 
110  Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
111  break;
112 
115  &DeviceExtension->CompatibleIDs,
116  &String);
117 
118  Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
119  break;
120 
121  case BusQueryInstanceID:
123  &DeviceExtension->InstanceID,
124  &String);
125 
126  DPRINT("InstanceID: %S\n", String.Buffer);
127 
128  Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
129  break;
130 
132  default:
134  }
135 
136  return Status;
137 }
138 
139 
140 static NTSTATUS
143  IN PIRP Irp,
145 {
146  PPDO_DEVICE_EXTENSION DeviceExtension;
147  PPNP_BUS_INFORMATION BusInformation;
148 
150  DPRINT("Called\n");
151 
153  BusInformation = ExAllocatePoolWithTag(PagedPool, sizeof(PNP_BUS_INFORMATION), TAG_PCI);
154  Irp->IoStatus.Information = (ULONG_PTR)BusInformation;
155  if (BusInformation != NULL)
156  {
157  BusInformation->BusTypeGuid = GUID_BUS_TYPE_PCI;
158  BusInformation->LegacyBusType = PCIBus;
159  BusInformation->BusNumber = DeviceExtension->PciDevice->BusNumber;
160 
161  return STATUS_SUCCESS;
162  }
163 
165 }
166 
167 
168 static NTSTATUS
171  IN PIRP Irp,
173 {
174  PPDO_DEVICE_EXTENSION DeviceExtension;
176  ULONG DeviceNumber, FunctionNumber;
177 
179  DPRINT("Called\n");
180 
182  DeviceCapabilities = IrpSp->Parameters.DeviceCapabilities.Capabilities;
183 
184  if (DeviceCapabilities->Version != 1)
185  return STATUS_UNSUCCESSFUL;
186 
187  DeviceNumber = DeviceExtension->PciDevice->SlotNumber.u.bits.DeviceNumber;
188  FunctionNumber = DeviceExtension->PciDevice->SlotNumber.u.bits.FunctionNumber;
189 
190  DeviceCapabilities->UniqueID = FALSE;
191  DeviceCapabilities->Address = ((DeviceNumber << 16) & 0xFFFF0000) + (FunctionNumber & 0xFFFF);
192  DeviceCapabilities->UINumber = MAXULONG; /* FIXME */
193 
194  return STATUS_SUCCESS;
195 }
196 
197 static BOOLEAN
199  ULONG Offset,
200  PULONG OriginalValue,
201  PULONG NewValue)
202 {
203  ULONG Size;
204  ULONG AllOnes;
205 
206  /* Read the original value */
208  DeviceExtension->PciDevice->BusNumber,
209  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
210  OriginalValue,
211  Offset,
212  sizeof(ULONG));
213  if (Size != sizeof(ULONG))
214  {
215  DPRINT1("Wrong size %lu\n", Size);
216  return FALSE;
217  }
218 
219  /* Write all ones to determine which bits are held to zero */
220  AllOnes = MAXULONG;
222  DeviceExtension->PciDevice->BusNumber,
223  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
224  &AllOnes,
225  Offset,
226  sizeof(ULONG));
227  if (Size != sizeof(ULONG))
228  {
229  DPRINT1("Wrong size %lu\n", Size);
230  return FALSE;
231  }
232 
233  /* Get the range length */
235  DeviceExtension->PciDevice->BusNumber,
236  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
237  NewValue,
238  Offset,
239  sizeof(ULONG));
240  if (Size != sizeof(ULONG))
241  {
242  DPRINT1("Wrong size %lu\n", Size);
243  return FALSE;
244  }
245 
246  /* Restore original value */
248  DeviceExtension->PciDevice->BusNumber,
249  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
250  OriginalValue,
251  Offset,
252  sizeof(ULONG));
253  if (Size != sizeof(ULONG))
254  {
255  DPRINT1("Wrong size %lu\n", Size);
256  return FALSE;
257  }
258 
259  return TRUE;
260 }
261 
262 static BOOLEAN
264  UCHAR Bar,
267  PULONG Flags,
268  PUCHAR NextBar,
269  PULONGLONG MaximumAddress)
270 {
271  union {
272  struct {
273  ULONG Bar0;
274  ULONG Bar1;
275  } Bars;
276  ULONGLONG Bar;
277  } OriginalValue;
278  union {
279  struct {
280  ULONG Bar0;
281  ULONG Bar1;
282  } Bars;
283  ULONGLONG Bar;
284  } NewValue;
285  ULONG Offset;
286 
287  /* Compute the offset of this BAR in PCI config space */
288  Offset = 0x10 + Bar * 4;
289 
290  /* Assume this is a 32-bit BAR until we find wrong */
291  *NextBar = Bar + 1;
292 
293  /* Initialize BAR values to zero */
294  OriginalValue.Bar = 0ULL;
295  NewValue.Bar = 0ULL;
296 
297  /* Read the first BAR */
298  if (!PdoReadPciBar(DeviceExtension, Offset,
299  &OriginalValue.Bars.Bar0,
300  &NewValue.Bars.Bar0))
301  {
302  return FALSE;
303  }
304 
305  /* Check if this is a memory BAR */
306  if (!(OriginalValue.Bars.Bar0 & PCI_ADDRESS_IO_SPACE))
307  {
308  /* Write the maximum address if the caller asked for it */
309  if (MaximumAddress != NULL)
310  {
311  if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_32BIT)
312  {
313  *MaximumAddress = 0x00000000FFFFFFFFULL;
314  }
315  else if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
316  {
317  *MaximumAddress = 0x00000000000FFFFFULL;
318  }
319  else if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
320  {
321  *MaximumAddress = 0xFFFFFFFFFFFFFFFFULL;
322  }
323  }
324 
325  /* Check if this is a 64-bit BAR */
326  if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
327  {
328  /* We've now consumed the next BAR too */
329  *NextBar = Bar + 2;
330 
331  /* Read the next BAR */
332  if (!PdoReadPciBar(DeviceExtension, Offset + 4,
333  &OriginalValue.Bars.Bar1,
334  &NewValue.Bars.Bar1))
335  {
336  return FALSE;
337  }
338  }
339  }
340  else
341  {
342  /* Write the maximum I/O port address */
343  if (MaximumAddress != NULL)
344  {
345  *MaximumAddress = 0x00000000FFFFFFFFULL;
346  }
347  }
348 
349  if (NewValue.Bar == 0)
350  {
351  DPRINT("Unused address register\n");
352  *Base = 0;
353  *Length = 0;
354  *Flags = 0;
355  return TRUE;
356  }
357 
358  *Base = ((OriginalValue.Bar & PCI_ADDRESS_IO_SPACE)
359  ? (OriginalValue.Bar & PCI_ADDRESS_IO_ADDRESS_MASK_64)
360  : (OriginalValue.Bar & PCI_ADDRESS_MEMORY_ADDRESS_MASK_64));
361 
362  *Length = ~((NewValue.Bar & PCI_ADDRESS_IO_SPACE)
363  ? (NewValue.Bar & PCI_ADDRESS_IO_ADDRESS_MASK_64)
364  : (NewValue.Bar & PCI_ADDRESS_MEMORY_ADDRESS_MASK_64)) + 1;
365 
366  *Flags = (NewValue.Bar & PCI_ADDRESS_IO_SPACE)
367  ? (NewValue.Bar & ~PCI_ADDRESS_IO_ADDRESS_MASK_64)
368  : (NewValue.Bar & ~PCI_ADDRESS_MEMORY_ADDRESS_MASK_64);
369 
370  return TRUE;
371 }
372 
373 
374 static NTSTATUS
377  IN PIRP Irp,
379 {
380  PPDO_DEVICE_EXTENSION DeviceExtension;
381  PCI_COMMON_CONFIG PciConfig;
384  ULONG Size;
385  ULONG ResCount = 0;
386  ULONG ListSize;
387  UCHAR Bar;
388  ULONGLONG Base;
390  ULONG Flags;
391  ULONGLONG MaximumAddress;
392 
394  DPRINT("PdoQueryResourceRequirements() called\n");
395 
397 
398  /* Get PCI configuration space */
400  DeviceExtension->PciDevice->BusNumber,
401  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
402  &PciConfig,
404  DPRINT("Size %lu\n", Size);
406  {
407  Irp->IoStatus.Information = 0;
408  return STATUS_UNSUCCESSFUL;
409  }
410 
411  DPRINT("Command register: 0x%04hx\n", PciConfig.Command);
412 
413  /* Count required resource descriptors */
414  ResCount = 0;
415  if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
416  {
417  for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
418  {
419  if (!PdoGetRangeLength(DeviceExtension,
420  Bar,
421  &Base,
422  &Length,
423  &Flags,
424  &Bar,
425  NULL))
426  break;
427 
428  if (Length != 0)
429  ResCount += 2;
430  }
431 
432  /* FIXME: Check ROM address */
433 
434  if (PciConfig.u.type0.InterruptPin != 0)
435  ResCount++;
436  }
437  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
438  {
439  for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
440  {
441  if (!PdoGetRangeLength(DeviceExtension,
442  Bar,
443  &Base,
444  &Length,
445  &Flags,
446  &Bar,
447  NULL))
448  break;
449 
450  if (Length != 0)
451  ResCount += 2;
452  }
453 
454  if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
455  ResCount++;
456  }
457  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
458  {
459  /* FIXME: Count Cardbus bridge resources */
460  }
461  else
462  {
463  DPRINT1("Unsupported header type %d\n", PCI_CONFIGURATION_TYPE(&PciConfig));
464  }
465 
466  if (ResCount == 0)
467  {
468  Irp->IoStatus.Information = 0;
469  return STATUS_SUCCESS;
470  }
471 
472  /* Calculate the resource list size */
473  ListSize = FIELD_OFFSET(IO_RESOURCE_REQUIREMENTS_LIST, List[0].Descriptors) +
474  ResCount * sizeof(IO_RESOURCE_DESCRIPTOR);
475 
476  DPRINT("ListSize %lu (0x%lx)\n", ListSize, ListSize);
477 
478  /* Allocate the resource requirements list */
480  ListSize,
481  TAG_PCI);
482  if (ResourceList == NULL)
483  {
484  Irp->IoStatus.Information = 0;
486  }
487 
488  RtlZeroMemory(ResourceList, ListSize);
489  ResourceList->ListSize = ListSize;
490  ResourceList->InterfaceType = PCIBus;
491  ResourceList->BusNumber = DeviceExtension->PciDevice->BusNumber;
492  ResourceList->SlotNumber = DeviceExtension->PciDevice->SlotNumber.u.AsULONG;
493  ResourceList->AlternativeLists = 1;
494 
495  ResourceList->List[0].Version = 1;
496  ResourceList->List[0].Revision = 1;
497  ResourceList->List[0].Count = ResCount;
498 
499  Descriptor = &ResourceList->List[0].Descriptors[0];
500  if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
501  {
502  for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
503  {
504  if (!PdoGetRangeLength(DeviceExtension,
505  Bar,
506  &Base,
507  &Length,
508  &Flags,
509  &Bar,
510  &MaximumAddress))
511  {
512  DPRINT1("PdoGetRangeLength() failed\n");
513  break;
514  }
515 
516  if (Length == 0)
517  {
518  DPRINT("Unused address register\n");
519  continue;
520  }
521 
522  /* Set preferred descriptor */
525  {
527  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
531 
532  Descriptor->u.Port.Length = Length;
533  Descriptor->u.Port.Alignment = 1;
534  Descriptor->u.Port.MinimumAddress.QuadPart = Base;
535  Descriptor->u.Port.MaximumAddress.QuadPart = Base + Length - 1;
536  }
537  else
538  {
540  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
543 
544  Descriptor->u.Memory.Length = Length;
545  Descriptor->u.Memory.Alignment = 1;
546  Descriptor->u.Memory.MinimumAddress.QuadPart = Base;
547  Descriptor->u.Memory.MaximumAddress.QuadPart = Base + Length - 1;
548  }
549  Descriptor++;
550 
551  /* Set alternative descriptor */
554  {
556  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
560 
561  Descriptor->u.Port.Length = Length;
562  Descriptor->u.Port.Alignment = Length;
563  Descriptor->u.Port.MinimumAddress.QuadPart = 0;
564  Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
565  }
566  else
567  {
569  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
572 
573  Descriptor->u.Memory.Length = Length;
574  Descriptor->u.Memory.Alignment = Length;
575  Descriptor->u.Port.MinimumAddress.QuadPart = 0;
576  Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
577  }
578  Descriptor++;
579  }
580 
581  /* FIXME: Check ROM address */
582 
583  if (PciConfig.u.type0.InterruptPin != 0)
584  {
585  Descriptor->Option = 0; /* Required */
587  Descriptor->ShareDisposition = CmResourceShareShared;
589 
590  Descriptor->u.Interrupt.MinimumVector = 0;
591  Descriptor->u.Interrupt.MaximumVector = 0xFF;
592  }
593  }
594  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
595  {
596  for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
597  {
598  if (!PdoGetRangeLength(DeviceExtension,
599  Bar,
600  &Base,
601  &Length,
602  &Flags,
603  &Bar,
604  &MaximumAddress))
605  {
606  DPRINT1("PdoGetRangeLength() failed\n");
607  break;
608  }
609 
610  if (Length == 0)
611  {
612  DPRINT("Unused address register\n");
613  continue;
614  }
615 
616  /* Set preferred descriptor */
619  {
621  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
625 
626  Descriptor->u.Port.Length = Length;
627  Descriptor->u.Port.Alignment = 1;
628  Descriptor->u.Port.MinimumAddress.QuadPart = Base;
629  Descriptor->u.Port.MaximumAddress.QuadPart = Base + Length - 1;
630  }
631  else
632  {
634  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
637 
638  Descriptor->u.Memory.Length = Length;
639  Descriptor->u.Memory.Alignment = 1;
640  Descriptor->u.Memory.MinimumAddress.QuadPart = Base;
641  Descriptor->u.Memory.MaximumAddress.QuadPart = Base + Length - 1;
642  }
643  Descriptor++;
644 
645  /* Set alternative descriptor */
648  {
650  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
654 
655  Descriptor->u.Port.Length = Length;
656  Descriptor->u.Port.Alignment = Length;
657  Descriptor->u.Port.MinimumAddress.QuadPart = 0;
658  Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
659  }
660  else
661  {
663  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
666 
667  Descriptor->u.Memory.Length = Length;
668  Descriptor->u.Memory.Alignment = Length;
669  Descriptor->u.Port.MinimumAddress.QuadPart = 0;
670  Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
671  }
672  Descriptor++;
673  }
674 
675  if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
676  {
677  Descriptor->Option = 0; /* Required */
679  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
680 
681  ResourceList->BusNumber =
682  Descriptor->u.BusNumber.MinBusNumber =
683  Descriptor->u.BusNumber.MaxBusNumber = DeviceExtension->PciDevice->PciConfig.u.type1.SecondaryBus;
684  Descriptor->u.BusNumber.Length = 1;
685  Descriptor->u.BusNumber.Reserved = 0;
686  }
687  }
688  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
689  {
690  /* FIXME: Add Cardbus bridge resources */
691  }
692 
693  Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
694 
695  return STATUS_SUCCESS;
696 }
697 
698 
699 static NTSTATUS
702  IN PIRP Irp,
704 {
705  PPDO_DEVICE_EXTENSION DeviceExtension;
706  PCI_COMMON_CONFIG PciConfig;
708  PCM_PARTIAL_RESOURCE_LIST PartialList;
710  ULONG Size;
711  ULONG ResCount = 0;
712  ULONG ListSize;
713  UCHAR Bar;
714  ULONGLONG Base;
716  ULONG Flags;
717 
718  DPRINT("PdoQueryResources() called\n");
719 
722 
723  /* Get PCI configuration space */
725  DeviceExtension->PciDevice->BusNumber,
726  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
727  &PciConfig,
729  DPRINT("Size %lu\n", Size);
731  {
732  Irp->IoStatus.Information = 0;
733  return STATUS_UNSUCCESSFUL;
734  }
735 
736  DPRINT("Command register: 0x%04hx\n", PciConfig.Command);
737 
738  /* Count required resource descriptors */
739  ResCount = 0;
740  if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
741  {
742  for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
743  {
744  if (!PdoGetRangeLength(DeviceExtension,
745  Bar,
746  &Base,
747  &Length,
748  &Flags,
749  &Bar,
750  NULL))
751  break;
752 
753  if (Length)
754  ResCount++;
755  }
756 
757  if ((PciConfig.u.type0.InterruptPin != 0) &&
758  (PciConfig.u.type0.InterruptLine != 0) &&
759  (PciConfig.u.type0.InterruptLine != 0xFF))
760  ResCount++;
761  }
762  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
763  {
764  for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
765  {
766  if (!PdoGetRangeLength(DeviceExtension,
767  Bar,
768  &Base,
769  &Length,
770  &Flags,
771  &Bar,
772  NULL))
773  break;
774 
775  if (Length != 0)
776  ResCount++;
777  }
778 
779  if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
780  ResCount++;
781  }
782  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
783  {
784  /* FIXME: Count Cardbus bridge resources */
785  }
786  else
787  {
788  DPRINT1("Unsupported header type %d\n", PCI_CONFIGURATION_TYPE(&PciConfig));
789  }
790 
791  if (ResCount == 0)
792  {
793  Irp->IoStatus.Information = 0;
794  return STATUS_SUCCESS;
795  }
796 
797  /* Calculate the resource list size */
798  ListSize = FIELD_OFFSET(CM_RESOURCE_LIST, List[0].PartialResourceList.PartialDescriptors) +
799  ResCount * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR);
800 
801  /* Allocate the resource list */
803  ListSize,
804  TAG_PCI);
805  if (ResourceList == NULL)
807 
808  RtlZeroMemory(ResourceList, ListSize);
809  ResourceList->Count = 1;
810  ResourceList->List[0].InterfaceType = PCIBus;
811  ResourceList->List[0].BusNumber = DeviceExtension->PciDevice->BusNumber;
812 
813  PartialList = &ResourceList->List[0].PartialResourceList;
814  PartialList->Version = 1;
815  PartialList->Revision = 1;
816  PartialList->Count = ResCount;
817 
818  Descriptor = &PartialList->PartialDescriptors[0];
819  if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
820  {
821  for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
822  {
823  if (!PdoGetRangeLength(DeviceExtension,
824  Bar,
825  &Base,
826  &Length,
827  &Flags,
828  &Bar,
829  NULL))
830  break;
831 
832  if (Length == 0)
833  {
834  DPRINT("Unused address register\n");
835  continue;
836  }
837 
839  {
841  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
845  Descriptor->u.Port.Start.QuadPart = (ULONGLONG)Base;
846  Descriptor->u.Port.Length = Length;
847 
848  /* Enable IO space access */
849  DeviceExtension->PciDevice->EnableIoSpace = TRUE;
850  }
851  else
852  {
854  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
857  Descriptor->u.Memory.Start.QuadPart = (ULONGLONG)Base;
858  Descriptor->u.Memory.Length = Length;
859 
860  /* Enable memory space access */
861  DeviceExtension->PciDevice->EnableMemorySpace = TRUE;
862  }
863 
864  Descriptor++;
865  }
866 
867  /* Add interrupt resource */
868  if ((PciConfig.u.type0.InterruptPin != 0) &&
869  (PciConfig.u.type0.InterruptLine != 0) &&
870  (PciConfig.u.type0.InterruptLine != 0xFF))
871  {
873  Descriptor->ShareDisposition = CmResourceShareShared;
875  Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
876  Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
877  Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
878  }
879 
880  /* Allow bus master mode */
881  DeviceExtension->PciDevice->EnableBusMaster = TRUE;
882  }
883  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
884  {
885  for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
886  {
887  if (!PdoGetRangeLength(DeviceExtension,
888  Bar,
889  &Base,
890  &Length,
891  &Flags,
892  &Bar,
893  NULL))
894  break;
895 
896  if (Length == 0)
897  {
898  DPRINT("Unused address register\n");
899  continue;
900  }
901 
903  {
905  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
909  Descriptor->u.Port.Start.QuadPart = (ULONGLONG)Base;
910  Descriptor->u.Port.Length = Length;
911 
912  /* Enable IO space access */
913  DeviceExtension->PciDevice->EnableIoSpace = TRUE;
914  }
915  else
916  {
918  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
921  Descriptor->u.Memory.Start.QuadPart = (ULONGLONG)Base;
922  Descriptor->u.Memory.Length = Length;
923 
924  /* Enable memory space access */
925  DeviceExtension->PciDevice->EnableMemorySpace = TRUE;
926  }
927 
928  Descriptor++;
929  }
930 
931  if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
932  {
934  Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
935 
936  ResourceList->List[0].BusNumber =
937  Descriptor->u.BusNumber.Start = DeviceExtension->PciDevice->PciConfig.u.type1.SecondaryBus;
938  Descriptor->u.BusNumber.Length = 1;
939  Descriptor->u.BusNumber.Reserved = 0;
940  }
941  }
942  else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
943  {
944  /* FIXME: Add Cardbus bridge resources */
945  }
946 
947  Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
948 
949  return STATUS_SUCCESS;
950 }
951 
952 
953 static VOID NTAPI
955  IN PVOID Context)
956 {
957  PPDO_DEVICE_EXTENSION DeviceExtension;
958 
959  DPRINT("InterfaceReference(%p)\n", Context);
960 
961  DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
962  InterlockedIncrement(&DeviceExtension->References);
963 }
964 
965 
966 static VOID NTAPI
968  IN PVOID Context)
969 {
970  PPDO_DEVICE_EXTENSION DeviceExtension;
971 
972  DPRINT("InterfaceDereference(%p)\n", Context);
973 
974  DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
975  InterlockedDecrement(&DeviceExtension->References);
976 }
977 
978 static TRANSLATE_BUS_ADDRESS InterfaceBusTranslateBusAddress;
979 
980 static
981 BOOLEAN
982 NTAPI
984  IN PVOID Context,
986  IN ULONG Length,
989 {
990  PPDO_DEVICE_EXTENSION DeviceExtension;
991 
992  DPRINT("InterfaceBusTranslateBusAddress(%p %p 0x%lx %p %p)\n",
994 
995  DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
996 
998  DeviceExtension->PciDevice->BusNumber,
999  BusAddress,
1000  AddressSpace,
1002 }
1003 
1004 static GET_DMA_ADAPTER InterfaceBusGetDmaAdapter;
1005 
1006 static
1008 NTAPI
1010  IN PVOID Context,
1013 {
1014  DPRINT("InterfaceBusGetDmaAdapter(%p %p %p)\n",
1017 }
1018 
1019 static GET_SET_DEVICE_DATA InterfaceBusSetBusData;
1020 
1021 static
1022 ULONG
1023 NTAPI
1025  IN PVOID Context,
1026  IN ULONG DataType,
1027  IN PVOID Buffer,
1028  IN ULONG Offset,
1029  IN ULONG Length)
1030 {
1031  PPDO_DEVICE_EXTENSION DeviceExtension;
1032  ULONG Size;
1033 
1034  DPRINT("InterfaceBusSetBusData(%p 0x%lx %p 0x%lx 0x%lx)\n",
1036 
1038  {
1039  DPRINT("Unknown DataType %lu\n", DataType);
1040  return 0;
1041  }
1042 
1043  DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
1044 
1045  /* Get PCI configuration space */
1047  DeviceExtension->PciDevice->BusNumber,
1048  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1049  Buffer,
1050  Offset,
1051  Length);
1052  return Size;
1053 }
1054 
1055 static GET_SET_DEVICE_DATA InterfaceBusGetBusData;
1056 
1057 static
1058 ULONG
1059 NTAPI
1061  IN PVOID Context,
1062  IN ULONG DataType,
1063  IN PVOID Buffer,
1064  IN ULONG Offset,
1065  IN ULONG Length)
1066 {
1067  PPDO_DEVICE_EXTENSION DeviceExtension;
1068  ULONG Size;
1069 
1070  DPRINT("InterfaceBusGetBusData(%p 0x%lx %p 0x%lx 0x%lx) called\n",
1072 
1074  {
1075  DPRINT("Unknown DataType %lu\n", DataType);
1076  return 0;
1077  }
1078 
1079  DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
1080 
1081  /* Get PCI configuration space */
1083  DeviceExtension->PciDevice->BusNumber,
1084  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1085  Buffer,
1086  Offset,
1087  Length);
1088  return Size;
1089 }
1090 
1091 
1092 static BOOLEAN NTAPI
1094  IN USHORT VendorID,
1095  IN USHORT DeviceID,
1099  IN ULONG Flags)
1100 {
1101  PFDO_DEVICE_EXTENSION FdoDeviceExtension;
1102  PPCI_DEVICE PciDevice;
1103  PLIST_ENTRY CurrentBus, CurrentEntry;
1104  KIRQL OldIrql;
1105  BOOLEAN Found = FALSE;
1106 
1108  CurrentBus = DriverExtension->BusListHead.Flink;
1109  while (!Found && CurrentBus != &DriverExtension->BusListHead)
1110  {
1111  FdoDeviceExtension = CONTAINING_RECORD(CurrentBus, FDO_DEVICE_EXTENSION, ListEntry);
1112 
1113  KeAcquireSpinLockAtDpcLevel(&FdoDeviceExtension->DeviceListLock);
1114  CurrentEntry = FdoDeviceExtension->DeviceListHead.Flink;
1115  while (!Found && CurrentEntry != &FdoDeviceExtension->DeviceListHead)
1116  {
1117  PciDevice = CONTAINING_RECORD(CurrentEntry, PCI_DEVICE, ListEntry);
1118  if (PciDevice->PciConfig.VendorID == VendorID &&
1119  PciDevice->PciConfig.DeviceID == DeviceID)
1120  {
1121  if (!(Flags & PCI_USE_SUBSYSTEM_IDS) ||
1122  (PciDevice->PciConfig.u.type0.SubVendorID == SubVendorID &&
1123  PciDevice->PciConfig.u.type0.SubSystemID == SubSystemID))
1124  {
1125  if (!(Flags & PCI_USE_REVISION) ||
1126  PciDevice->PciConfig.RevisionID == RevisionID)
1127  {
1128  DPRINT("Found the PCI device\n");
1129  Found = TRUE;
1130  }
1131  }
1132  }
1133 
1134  CurrentEntry = CurrentEntry->Flink;
1135  }
1136 
1137  KeReleaseSpinLockFromDpcLevel(&FdoDeviceExtension->DeviceListLock);
1138  CurrentBus = CurrentBus->Flink;
1139  }
1141 
1142  return Found;
1143 }
1144 
1145 
1146 static BOOLEAN
1148  IN PPCI_COMMON_CONFIG PciConfig,
1150 {
1151  if ((Parameters->Flags & PCI_USE_VENDEV_IDS) &&
1152  (PciConfig->VendorID != Parameters->VendorID ||
1153  PciConfig->DeviceID != Parameters->DeviceID))
1154  {
1155  return FALSE;
1156  }
1157 
1159  (PciConfig->BaseClass != Parameters->BaseClass ||
1160  PciConfig->SubClass != Parameters->SubClass))
1161  {
1162  return FALSE;
1163  }
1164 
1165  if ((Parameters->Flags & PCI_USE_PROGIF) &&
1166  PciConfig->ProgIf != Parameters->ProgIf)
1167  {
1168  return FALSE;
1169  }
1170 
1172  (PciConfig->u.type0.SubVendorID != Parameters->SubVendorID ||
1173  PciConfig->u.type0.SubSystemID != Parameters->SubSystemID))
1174  {
1175  return FALSE;
1176  }
1177 
1178  if ((Parameters->Flags & PCI_USE_REVISION) &&
1179  PciConfig->RevisionID != Parameters->RevisionID)
1180  {
1181  return FALSE;
1182  }
1183 
1184  return TRUE;
1185 }
1186 
1187 
1188 static BOOLEAN NTAPI
1190  IN PVOID Context,
1192 {
1193  PPDO_DEVICE_EXTENSION DeviceExtension;
1194  PFDO_DEVICE_EXTENSION MyFdoDeviceExtension;
1195  PFDO_DEVICE_EXTENSION FdoDeviceExtension;
1196  PPCI_DEVICE PciDevice;
1197  PLIST_ENTRY CurrentBus, CurrentEntry;
1198  KIRQL OldIrql;
1199  BOOLEAN Found = FALSE;
1200 
1201  DPRINT("InterfacePciDevicePresentEx(%p %p) called\n",
1202  Context, Parameters);
1203 
1205  return FALSE;
1206 
1207  DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
1208  MyFdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->Fdo->DeviceExtension;
1209 
1211  {
1212  return CheckPciDevice(&DeviceExtension->PciDevice->PciConfig, Parameters);
1213  }
1214 
1216  CurrentBus = DriverExtension->BusListHead.Flink;
1217  while (!Found && CurrentBus != &DriverExtension->BusListHead)
1218  {
1219  FdoDeviceExtension = CONTAINING_RECORD(CurrentBus, FDO_DEVICE_EXTENSION, ListEntry);
1220  if (!(Parameters->Flags & PCI_USE_LOCAL_BUS) || FdoDeviceExtension == MyFdoDeviceExtension)
1221  {
1222  KeAcquireSpinLockAtDpcLevel(&FdoDeviceExtension->DeviceListLock);
1223  CurrentEntry = FdoDeviceExtension->DeviceListHead.Flink;
1224  while (!Found && CurrentEntry != &FdoDeviceExtension->DeviceListHead)
1225  {
1226  PciDevice = CONTAINING_RECORD(CurrentEntry, PCI_DEVICE, ListEntry);
1227 
1228  if (CheckPciDevice(&PciDevice->PciConfig, Parameters))
1229  {
1230  DPRINT("Found the PCI device\n");
1231  Found = TRUE;
1232  }
1233 
1234  CurrentEntry = CurrentEntry->Flink;
1235  }
1236 
1237  KeReleaseSpinLockFromDpcLevel(&FdoDeviceExtension->DeviceListLock);
1238  }
1239  CurrentBus = CurrentBus->Flink;
1240  }
1242 
1243  return Found;
1244 }
1245 
1246 
1247 static NTSTATUS
1250  IN PIRP Irp,
1252 {
1253  NTSTATUS Status;
1254 
1256 
1257  if (RtlCompareMemory(IrpSp->Parameters.QueryInterface.InterfaceType,
1258  &GUID_BUS_INTERFACE_STANDARD, sizeof(GUID)) == sizeof(GUID))
1259  {
1260  /* BUS_INTERFACE_STANDARD */
1261  if (IrpSp->Parameters.QueryInterface.Version < 1)
1263  else if (IrpSp->Parameters.QueryInterface.Size < sizeof(BUS_INTERFACE_STANDARD))
1265  else
1266  {
1267  PBUS_INTERFACE_STANDARD BusInterface;
1268  BusInterface = (PBUS_INTERFACE_STANDARD)IrpSp->Parameters.QueryInterface.Interface;
1269  BusInterface->Size = sizeof(BUS_INTERFACE_STANDARD);
1270  BusInterface->Version = 1;
1272  BusInterface->GetDmaAdapter = InterfaceBusGetDmaAdapter;
1273  BusInterface->SetBusData = InterfaceBusSetBusData;
1274  BusInterface->GetBusData = InterfaceBusGetBusData;
1276  }
1277  }
1278  else if (RtlCompareMemory(IrpSp->Parameters.QueryInterface.InterfaceType,
1279  &GUID_PCI_DEVICE_PRESENT_INTERFACE, sizeof(GUID)) == sizeof(GUID))
1280  {
1281  /* PCI_DEVICE_PRESENT_INTERFACE */
1282  if (IrpSp->Parameters.QueryInterface.Version < 1)
1286  else
1287  {
1291  PciDevicePresentInterface->Version = 1;
1295  }
1296  }
1297  else
1298  {
1299  /* Not a supported interface */
1300  return STATUS_NOT_SUPPORTED;
1301  }
1302 
1303  if (NT_SUCCESS(Status))
1304  {
1305  /* Add a reference for the returned interface */
1308  Interface->Context = DeviceObject;
1309  Interface->InterfaceReference = InterfaceReference;
1310  Interface->InterfaceDereference = InterfaceDereference;
1311  Interface->InterfaceReference(Interface->Context);
1312  }
1313 
1314  return Status;
1315 }
1316 
1317 static NTSTATUS
1320  IN PIRP Irp,
1322 {
1323  PCM_RESOURCE_LIST RawResList = IrpSp->Parameters.StartDevice.AllocatedResources;
1324  PCM_FULL_RESOURCE_DESCRIPTOR RawFullDesc;
1325  PCM_PARTIAL_RESOURCE_DESCRIPTOR RawPartialDesc;
1326  ULONG i, ii;
1328  UCHAR Irq;
1329  USHORT Command;
1330 
1332 
1333  if (!RawResList)
1334  return STATUS_SUCCESS;
1335 
1336  /* TODO: Assign the other resources we get to the card */
1337 
1338  for (i = 0; i < RawResList->Count; i++)
1339  {
1340  RawFullDesc = &RawResList->List[i];
1341 
1342  for (ii = 0; ii < RawFullDesc->PartialResourceList.Count; ii++)
1343  {
1344  RawPartialDesc = &RawFullDesc->PartialResourceList.PartialDescriptors[ii];
1345 
1346  if (RawPartialDesc->Type == CmResourceTypeInterrupt)
1347  {
1348  DPRINT("Assigning IRQ %u to PCI device 0x%x on bus 0x%x\n",
1349  RawPartialDesc->u.Interrupt.Vector,
1350  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1351  DeviceExtension->PciDevice->BusNumber);
1352 
1353  Irq = (UCHAR)RawPartialDesc->u.Interrupt.Vector;
1355  DeviceExtension->PciDevice->BusNumber,
1356  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1357  &Irq,
1358  0x3c /* PCI_INTERRUPT_LINE */,
1359  sizeof(UCHAR));
1360  }
1361  }
1362  }
1363 
1364  Command = 0;
1365 
1366  DBGPRINT("pci!PdoStartDevice: Enabling command flags for PCI device 0x%x on bus 0x%x: ",
1367  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1368  DeviceExtension->PciDevice->BusNumber);
1369  if (DeviceExtension->PciDevice->EnableBusMaster)
1370  {
1372  DBGPRINT("[Bus master] ");
1373  }
1374 
1375  if (DeviceExtension->PciDevice->EnableMemorySpace)
1376  {
1378  DBGPRINT("[Memory space enable] ");
1379  }
1380 
1381  if (DeviceExtension->PciDevice->EnableIoSpace)
1382  {
1384  DBGPRINT("[I/O space enable] ");
1385  }
1386 
1387  if (Command != 0)
1388  {
1389  DBGPRINT("\n");
1390 
1391  /* OR with the previous value */
1392  Command |= DeviceExtension->PciDevice->PciConfig.Command;
1393 
1395  DeviceExtension->PciDevice->BusNumber,
1396  DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1397  &Command,
1399  sizeof(USHORT));
1400  }
1401  else
1402  {
1403  DBGPRINT("None\n");
1404  }
1405 
1406  return STATUS_SUCCESS;
1407 }
1408 
1409 static NTSTATUS
1412  IN PIRP Irp,
1414 {
1415  ULONG Size;
1416 
1417  DPRINT("PdoReadConfig() called\n");
1418 
1420  IrpSp->Parameters.ReadWriteConfig.WhichSpace,
1421  IrpSp->Parameters.ReadWriteConfig.Buffer,
1422  IrpSp->Parameters.ReadWriteConfig.Offset,
1423  IrpSp->Parameters.ReadWriteConfig.Length);
1424 
1425  if (Size != IrpSp->Parameters.ReadWriteConfig.Length)
1426  {
1427  DPRINT1("Size %lu Length %lu\n", Size, IrpSp->Parameters.ReadWriteConfig.Length);
1428  Irp->IoStatus.Information = 0;
1429  return STATUS_UNSUCCESSFUL;
1430  }
1431 
1432  Irp->IoStatus.Information = Size;
1433 
1434  return STATUS_SUCCESS;
1435 }
1436 
1437 
1438 static NTSTATUS
1441  IN PIRP Irp,
1443 {
1444  ULONG Size;
1445 
1446  DPRINT1("PdoWriteConfig() called\n");
1447 
1448  /* Get PCI configuration space */
1450  IrpSp->Parameters.ReadWriteConfig.WhichSpace,
1451  IrpSp->Parameters.ReadWriteConfig.Buffer,
1452  IrpSp->Parameters.ReadWriteConfig.Offset,
1453  IrpSp->Parameters.ReadWriteConfig.Length);
1454 
1455  if (Size != IrpSp->Parameters.ReadWriteConfig.Length)
1456  {
1457  DPRINT1("Size %lu Length %lu\n", Size, IrpSp->Parameters.ReadWriteConfig.Length);
1458  Irp->IoStatus.Information = 0;
1459  return STATUS_UNSUCCESSFUL;
1460  }
1461 
1462  Irp->IoStatus.Information = Size;
1463 
1464  return STATUS_SUCCESS;
1465 }
1466 
1467 static NTSTATUS
1470  IN PIRP Irp,
1472 {
1473  PDEVICE_RELATIONS DeviceRelations;
1474 
1475  /* We only support TargetDeviceRelation for child PDOs */
1476  if (IrpSp->Parameters.QueryDeviceRelations.Type != TargetDeviceRelation)
1477  return Irp->IoStatus.Status;
1478 
1479  /* We can do this because we only return 1 PDO for TargetDeviceRelation */
1480  DeviceRelations = ExAllocatePoolWithTag(PagedPool, sizeof(*DeviceRelations), TAG_PCI);
1481  if (!DeviceRelations)
1483 
1484  DeviceRelations->Count = 1;
1485  DeviceRelations->Objects[0] = DeviceObject;
1486 
1487  /* The PnP manager will remove this when it is done with the PDO */
1489 
1490  Irp->IoStatus.Information = (ULONG_PTR)DeviceRelations;
1491 
1492  return STATUS_SUCCESS;
1493 }
1494 
1495 
1496 /*** PUBLIC ******************************************************************/
1497 
1498 NTSTATUS
1501  PIRP Irp)
1502 /*
1503  * FUNCTION: Handle Plug and Play IRPs for the child device
1504  * ARGUMENTS:
1505  * DeviceObject = Pointer to physical device object of the child device
1506  * Irp = Pointer to IRP that should be handled
1507  * RETURNS:
1508  * Status
1509  */
1510 {
1512  NTSTATUS Status;
1513 
1514  DPRINT("Called\n");
1515 
1516  Status = Irp->IoStatus.Status;
1517 
1519 
1520  switch (IrpSp->MinorFunction)
1521  {
1523  DPRINT("Unimplemented IRP_MN_DEVICE_USAGE_NOTIFICATION received\n");
1524  break;
1525 
1526  case IRP_MN_EJECT:
1527  DPRINT("Unimplemented IRP_MN_EJECT received\n");
1528  break;
1529 
1532  break;
1533 
1536  break;
1537 
1540  break;
1541 
1543  DPRINT("IRP_MN_QUERY_DEVICE_TEXT received\n");
1545  break;
1546 
1547  case IRP_MN_QUERY_ID:
1548  DPRINT("IRP_MN_QUERY_ID received\n");
1550  break;
1551 
1553  DPRINT("Unimplemented IRP_MN_QUERY_ID received\n");
1554  break;
1555 
1557  DPRINT("IRP_MN_QUERY_RESOURCE_REQUIREMENTS received\n");
1559  break;
1560 
1562  DPRINT("IRP_MN_QUERY_RESOURCES received\n");
1564  break;
1565 
1566  case IRP_MN_SET_LOCK:
1567  DPRINT("Unimplemented IRP_MN_SET_LOCK received\n");
1568  break;
1569 
1570  case IRP_MN_START_DEVICE:
1572  break;
1573 
1576  case IRP_MN_STOP_DEVICE:
1581  break;
1582 
1583  case IRP_MN_REMOVE_DEVICE:
1584  {
1586  PFDO_DEVICE_EXTENSION FdoDeviceExtension = DeviceExtension->Fdo->DeviceExtension;
1587  KIRQL OldIrql;
1588 
1589  /* Remove it from the device list */
1590  KeAcquireSpinLock(&FdoDeviceExtension->DeviceListLock, &OldIrql);
1591  RemoveEntryList(&DeviceExtension->PciDevice->ListEntry);
1592  FdoDeviceExtension->DeviceListCount--;
1593  KeReleaseSpinLock(&FdoDeviceExtension->DeviceListLock, OldIrql);
1594 
1595  /* Free the device */
1596  ExFreePoolWithTag(DeviceExtension->PciDevice, TAG_PCI);
1597 
1598  /* Complete the IRP */
1599  Irp->IoStatus.Status = STATUS_SUCCESS;
1601 
1602  /* Delete the DO */
1604  return STATUS_SUCCESS;
1605  }
1606 
1608  DPRINT("IRP_MN_QUERY_INTERFACE received\n");
1610  break;
1611 
1612  case IRP_MN_READ_CONFIG:
1613  DPRINT("IRP_MN_READ_CONFIG received\n");
1615  break;
1616 
1617  case IRP_MN_WRITE_CONFIG:
1618  DPRINT("IRP_MN_WRITE_CONFIG received\n");
1620  break;
1621 
1623  DPRINT("IRP_MN_FILTER_RESOURCE_REQUIREMENTS received\n");
1624  /* Nothing to do */
1625  Irp->IoStatus.Status = Status;
1626  break;
1627 
1628  default:
1629  DPRINT1("Unknown IOCTL 0x%lx\n", IrpSp->MinorFunction);
1630  break;
1631  }
1632 
1633  if (Status != STATUS_PENDING)
1634  {
1635  Irp->IoStatus.Status = Status;
1637  }
1638 
1639  DPRINT("Leaving. Status 0x%X\n", Status);
1640 
1641  return Status;
1642 }
1643 
1644 NTSTATUS
1647  PIRP Irp)
1648 /*
1649  * FUNCTION: Handle power management IRPs for the child device
1650  * ARGUMENTS:
1651  * DeviceObject = Pointer to physical device object of the child device
1652  * Irp = Pointer to IRP that should be handled
1653  * RETURNS:
1654  * Status
1655  */
1656 {
1658  NTSTATUS Status = Irp->IoStatus.Status;
1659 
1660  DPRINT("Called\n");
1661 
1663 
1664  switch (IrpSp->MinorFunction)
1665  {
1666  case IRP_MN_QUERY_POWER:
1667  case IRP_MN_SET_POWER:
1669  break;
1670  }
1671 
1673  Irp->IoStatus.Status = Status;
1675 
1676  DPRINT("Leaving. Status 0x%X\n", Status);
1677 
1678  return Status;
1679 }
1680 
1681 /* EOF */
#define IRP_MN_CANCEL_REMOVE_DEVICE
static NTSTATUS PdoQueryResources(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:700
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3143
#define IN
Definition: typedefs.h:38
BOOLEAN EnableMemorySpace
Definition: pci.h:21
#define DBGPRINT(...)
Definition: pdo.c:21
#define CM_RESOURCE_MEMORY_PREFETCHABLE
Definition: cmtypes.h:123
#define TRUE
Definition: types.h:120
_In_ ULONG _In_ PHYSICAL_ADDRESS BusAddress
Definition: iofuncs.h:2268
ULONG DeviceListCount
Definition: pci.h:90
#define IRP_MN_QUERY_RESOURCES
#define IRP_MN_REMOVE_DEVICE
#define STATUS_INSUFFICIENT_RESOURCES
Definition: udferr_usr.h:158
#define IRP_MN_QUERY_ID
PGET_DMA_ADAPTER GetDmaAdapter
Definition: iotypes.h:881
_Out_ PULONG NumberOfMapRegisters
Definition: halfuncs.h:209
#define PCI_TYPE_20BIT
Definition: iotypes.h:3881
static NTSTATUS PdoQueryDeviceRelations(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1468
#define IRP_MN_QUERY_POWER
#define STATUS_NOT_IMPLEMENTED
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#define PCI_ENABLE_IO_SPACE
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CM_FULL_RESOURCE_DESCRIPTOR List[1]
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_In_ PIRP Irp
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#define UNREFERENCED_PARAMETER(P)
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#define STATUS_INVALID_PARAMETER
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static NTSTATUS PdoQueryId(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:74
#define IRP_MN_FILTER_RESOURCE_REQUIREMENTS
#define IRP_MN_QUERY_RESOURCE_REQUIREMENTS
static NTSTATUS PdoQueryInterface(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
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_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG AddressSpace
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unsigned char * PUCHAR
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#define PCI_ADDRESS_MEMORY_ADDRESS_MASK_64
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struct _BUS_INTERFACE_STANDARD * PBUS_INTERFACE_STANDARD
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Definition: spinlock.c:192
_In_ USHORT DeviceID
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LONG NTSTATUS
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static BOOLEAN CheckPciDevice(IN PPCI_COMMON_CONFIG PciConfig, IN PPCI_DEVICE_PRESENCE_PARAMETERS Parameters)
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_In_opt_ ULONG Base
Definition: rtlfuncs.h:2327
static BOOLEAN NTAPI InterfacePciDevicePresentEx(IN PVOID Context, IN PPCI_DEVICE_PRESENCE_PARAMETERS Parameters)
Definition: pdo.c:1189
#define PCI_ADDRESS_MEMORY_TYPE_MASK
Definition: iotypes.h:3874
struct _PDO_DEVICE_EXTENSION * PPDO_DEVICE_EXTENSION
PDEVICE_OBJECT Fdo
Definition: pci.h:57
union _CM_PARTIAL_RESOURCE_DESCRIPTOR::@369 u
static NTSTATUS PdoQueryDeviceText(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:30
PPCI_DEVICE PciDevice
Definition: pci.h:59
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR::@369::@372 Interrupt
static WCHAR String[]
Definition: stringtable.c:55
#define IRP_MN_EJECT
Definition: shell.h:41
#define PCI_USE_PROGIF
Definition: iotypes.h:837
static NTSTATUS PdoQueryBusInformation(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:141
Definition: pci.h:8
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG _Out_ PPHYSICAL_ADDRESS TranslatedAddress
Definition: iofuncs.h:2268
const MUI_LANGUAGE_RESOURCE ResourceList[]
Definition: muilanguages.h:414
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR CM_PARTIAL_RESOURCE_DESCRIPTOR
#define PCI_TYPE_32BIT
Definition: iotypes.h:3880
#define CM_RESOURCE_MEMORY_READ_WRITE
Definition: cmtypes.h:120
KSPIN_LOCK DeviceListLock
Definition: pci.h:92
#define CmResourceTypePort
Definition: hwresource.cpp:123
struct _FDO_DEVICE_EXTENSION * PFDO_DEVICE_EXTENSION
#define PCI_USE_REVISION
Definition: iotypes.h:834
#define STATUS_BUFFER_TOO_SMALL
Definition: shellext.h:64
FORCEINLINE BOOLEAN RemoveEntryList(_In_ PLIST_ENTRY Entry)
Definition: rtlfuncs.h:105
static GET_SET_DEVICE_DATA InterfaceBusSetBusData
Definition: pdo.c:1019
_In_ USHORT _In_ UCHAR RevisionID
Definition: iotypes.h:859
UCHAR KIRQL
Definition: env_spec_w32.h:591
CM_PARTIAL_RESOURCE_LIST PartialResourceList
Definition: hwresource.cpp:160
static TRANSLATE_BUS_ADDRESS InterfaceBusTranslateBusAddress
Definition: pdo.c:978
_Must_inspect_result_ _In_ ULONG Flags
Definition: wsk.h:170
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
static BOOLEAN NTAPI InterfacePciDevicePresent(IN USHORT VendorID, IN USHORT DeviceID, IN UCHAR RevisionID, IN USHORT SubVendorID, IN USHORT SubSystemID, IN ULONG Flags)
Definition: pdo.c:1093
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
#define IRP_MN_QUERY_REMOVE_DEVICE
ULONG BusNumber
Definition: pci.h:15
static NTSTATUS PdoQueryCapabilities(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:169
LIST_ENTRY ListEntry
Definition: pci.h:11
PVOID DeviceExtension
Definition: env_spec_w32.h:418
unsigned char BOOLEAN
PTRANSLATE_BUS_ADDRESS TranslateBusAddress
Definition: iotypes.h:880
smooth NULL
Definition: ftsmooth.c:416
#define CM_RESOURCE_PORT_16_BIT_DECODE
Definition: cmtypes.h:112
BOOLEAN EnableBusMaster
Definition: pci.h:25
#define IO_RESOURCE_ALTERNATIVE
#define IoCompleteRequest
Definition: irp.c:1240
#define PCI_ADDRESS_IO_ADDRESS_MASK_64
Definition: pdo.c:25
#define DeviceCapabilities
Definition: wingdi.h:4427
void DPRINT(...)
Definition: polytest.cpp:61
Definition: bufpool.h:45
switch(r->id)
Definition: btrfs.c:2711
return Found
Definition: dirsup.c:1270
struct _INTERFACE * PINTERFACE
static NTSTATUS PdoWriteConfig(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1439
PFLT_MESSAGE_WAITER_QUEUE CONTAINING_RECORD(Csq, DEVICE_EXTENSION, IrpQueue)) -> WaiterQ.mLock) _IRQL_raises_(DISPATCH_LEVEL) VOID NTAPI FltpAcquireMessageWaiterLock(_In_ PIO_CSQ Csq, _Out_ PKIRQL Irql)
Definition: Messaging.c:560
#define ULL(a, b)
Definition: format_msg.c:27
#define IRP_MN_READ_CONFIG
union _PCI_SLOT_NUMBER::@3627 u
#define IRP_MN_QUERY_STOP_DEVICE
_Must_inspect_result_ _In_ PDEVICE_DESCRIPTION DeviceDescription
Definition: iofuncs.h:1015
struct _LIST_ENTRY * Flink
Definition: typedefs.h:119
IN PVOID IN PVOID IN USHORT IN USHORT IN PINTERFACE Interface
Definition: pci.h:359
#define IRP_MN_SURPRISE_REMOVAL
Definition: ntifs_ex.h:408
#define PCI_USE_VENDEV_IDS
Definition: iotypes.h:835
static BOOLEAN PdoGetRangeLength(PPDO_DEVICE_EXTENSION DeviceExtension, UCHAR Bar, PULONGLONG Base, PULONGLONG Length, PULONG Flags, PUCHAR NextBar, PULONGLONG MaximumAddress)
Definition: pdo.c:263
UNICODE_STRING DeviceLocation
Definition: pci.h:71
#define IRP_MN_STOP_DEVICE
NTSTATUS PdoPnpControl(PDEVICE_OBJECT DeviceObject, PIRP Irp)
Definition: pdo.c:1499
LIST_ENTRY List
Definition: psmgr.c:57
if(!(yy_init))
Definition: macro.lex.yy.c:714
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:32
#define PCI_USE_LOCAL_DEVICE
Definition: iotypes.h:839
#define STATUS_PENDING
Definition: ntstatus.h:82
struct Command Command
#define CM_RESOURCE_PORT_POSITIVE_DECODE
Definition: cmtypes.h:113
uint64_t ULONGLONG
Definition: typedefs.h:65
UNICODE_STRING HardwareIDs
Definition: pci.h:65
VOID NTAPI KeReleaseSpinLockFromDpcLevel(IN PKSPIN_LOCK SpinLock)
Definition: spinlock.c:215
struct _PCI_SLOT_NUMBER::@3627::@3628 bits
_In_ USHORT _In_ UCHAR _In_ USHORT SubVendorID
Definition: iotypes.h:859
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3261
#define KeAcquireSpinLock(sl, irql)
Definition: env_spec_w32.h:609
#define IRP_MN_START_DEVICE
KSPIN_LOCK BusListLock
Definition: pci.h:104
NTHALAPI ULONG NTAPI HalGetBusData(BUS_DATA_TYPE, ULONG, ULONG, PVOID, ULONG)
#define PCI_DEVICE_TYPE
Definition: iotypes.h:3248
#define IRP_MN_QUERY_DEVICE_TEXT
#define IRP_MN_QUERY_INTERFACE
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:101
#define RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE
Definition: green.h:15
PGET_SET_DEVICE_DATA GetBusData
Definition: iotypes.h:883
#define PCI_WHICHSPACE_CONFIG
Definition: iotypes.h:3287
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
UNICODE_STRING DeviceDescription
Definition: pci.h:69
#define IRP_MN_QUERY_BUS_INFORMATION
unsigned char UCHAR
Definition: xmlstorage.h:181
CM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptors[1]
Definition: hwresource.cpp:119
ULONG NTAPI HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:73
_In_ PPCI_DEVICE_PRESENCE_PARAMETERS Parameters
Definition: iotypes.h:871
#define InterlockedDecrement
Definition: armddk.h:52
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:803
static NTSTATUS PdoReadConfig(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1410
static GET_SET_DEVICE_DATA InterfaceBusGetBusData
Definition: pdo.c:1055
LIST_ENTRY BusListHead
Definition: pci.h:102
#define TAG_PCI
Definition: pci.h:6
#define IRP_MN_SET_POWER
Definition: typedefs.h:117
_In_ USHORT _In_ UCHAR _In_ USHORT _In_ USHORT SubSystemID
Definition: iotypes.h:859
IN PVOID IN PVOID IN USHORT IN USHORT Size
Definition: pci.h:359
PPCI_DRIVER_EXTENSION DriverExtension
Definition: pci.c:41
PGET_SET_DEVICE_DATA SetBusData
Definition: iotypes.h:882
LIST_ENTRY DeviceListHead
Definition: pci.h:88
* PDEVICE_CAPABILITIES
Definition: iotypes.h:927
BOOLEAN NTAPI HalTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bus.c:140
Status
Definition: gdiplustypes.h:24
struct _IO_RESOURCE_DESCRIPTOR IO_RESOURCE_DESCRIPTOR
BOOLEAN EnableIoSpace
Definition: pci.h:23
#define MAXULONG
Definition: typedefs.h:250
IN PDEVICE_OBJECT DeviceObject
Definition: fatprocs.h:1560
__drv_aliasesMem FORCEINLINE PIO_STACK_LOCATION IoGetCurrentIrpStackLocation(_In_ PIRP Irp)
Definition: iofuncs.h:2745
VOID NTAPI IoDeleteDevice(IN PDEVICE_OBJECT DeviceObject)
Definition: device.c:1250
struct _GUID GUID
#define InterlockedIncrement
Definition: armddk.h:53
PCI_SLOT_NUMBER SlotNumber
Definition: pci.h:17
VOID NTAPI PoStartNextPowerIrp(IN PIRP Irp)
Definition: power.c:626
#define PCI_TYPE_64BIT
Definition: iotypes.h:3882
#define CM_RESOURCE_PORT_IO
Definition: cmtypes.h:109
unsigned short USHORT
Definition: pedump.c:61
#define PCI_USE_LOCAL_BUS
Definition: iotypes.h:838
_In_ PIO_STACK_LOCATION IrpSp
Definition: create.c:4157
UNICODE_STRING InstanceID
Definition: pci.h:63
struct _PCI_DEVICE_PRESENT_INTERFACE * PPCI_DEVICE_PRESENT_INTERFACE
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:254
unsigned int * PULONG
Definition: retypes.h:1
static GET_DMA_ADAPTER InterfaceBusGetDmaAdapter
Definition: pdo.c:1004
#define KeReleaseSpinLock(sl, irql)
Definition: env_spec_w32.h:627
#define IRP_MN_QUERY_DEVICE_RELATIONS
#define CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
Definition: cmtypes.h:143
#define CmResourceTypeInterrupt
Definition: hwresource.cpp:124
#define DPRINT1
Definition: precomp.h:8
#define PCI_ENABLE_MEMORY_SPACE
Definition: iotypes.h:3260
NTSTATUS PdoPowerControl(PDEVICE_OBJECT DeviceObject, PIRP Irp)
Definition: pdo.c:1645
HRESULT QueryInterface([in] REFIID riid, [out, iid_is(riid)] void **ppvObject)
#define OUT
Definition: typedefs.h:39
#define ObReferenceObject
Definition: obfuncs.h:204
__GNU_EXTENSION typedef unsigned __int64 * PULONGLONG
Definition: ntbasedef.h:390
#define PCI_ADDRESS_MEMORY_PREFETCHABLE
Definition: iotypes.h:3875
#define IRP_MN_SET_LOCK
struct tagContext Context
Definition: acpixf.h:1012
#define PCI_CONFIGURATION_TYPE(PciData)
Definition: iotypes.h:3252
#define STATUS_NOT_SUPPORTED
Definition: ntstatus.h:409
unsigned int ULONG
Definition: retypes.h:1
static VOID NTAPI InterfaceDereference(IN PVOID Context)
Definition: pdo.c:967
#define IO_NO_INCREMENT
Definition: iotypes.h:565
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:261
#define ULONG_PTR
Definition: config.h:101
static BOOLEAN PdoReadPciBar(PPDO_DEVICE_EXTENSION DeviceExtension, ULONG Offset, PULONG OriginalValue, PULONG NewValue)
Definition: pdo.c:198
#define CmResourceTypeBusNumber
Definition: hwresource.cpp:128
static NTSTATUS PdoStartDevice(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1318
PCI_INTERFACE PciDevicePresentInterface
Definition: devhere.c:18
#define IO_RESOURCE_PREFERRED
#define PCI_CLASS_BRIDGE_DEV
Definition: iotypes.h:3752
UNICODE_STRING DeviceID
Definition: pci.h:61
#define IRP_MN_CANCEL_STOP_DEVICE
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1099
static VOID NTAPI InterfaceReference(IN PVOID Context)
Definition: pdo.c:954
#define IRP_MN_DEVICE_USAGE_NOTIFICATION
_In_ PCHAR _In_ ULONG DeviceNumber
Definition: classpnp.h:1036
struct _NAMED_PIPE_CREATE_PARAMETERS * Parameters
Definition: iotypes.h:2771
static NTSTATUS PdoQueryResourceRequirements(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:375
#define CmResourceTypeMemory
Definition: hwresource.cpp:125
_In_ ULONG DataType
Definition: iotypes.h:787
ULONG NTAPI HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:123
return STATUS_SUCCESS
Definition: btrfs.c:2745
#define PCI_TYPE1_ADDRESSES
Definition: iotypes.h:3144
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:3873
UNICODE_STRING CompatibleIDs
Definition: pci.h:67
#define PCI_USE_CLASS_SUBCLASS
Definition: iotypes.h:836
INTERFACE_TYPE LegacyBusType
Definition: cmtypes.h:363
#define IRP_MN_QUERY_PNP_DEVICE_STATE
PCI_COMMON_CONFIG PciConfig
Definition: pci.h:19
#define RtlCompareMemory(s1, s2, l)
Definition: env_spec_w32.h:465
#define PCI_CARDBUS_BRIDGE_TYPE
Definition: iotypes.h:3250
#define PCI_USE_SUBSYSTEM_IDS
Definition: iotypes.h:833
#define IRP_MN_QUERY_CAPABILITIES
PADAPTER_OBJECT NTAPI HalGetAdapter(IN PDEVICE_DESCRIPTION DeviceDescription, OUT PULONG NumberOfMapRegisters)
Definition: dma.c:22
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3237
_In_ PSTORAGE_PROPERTY_ID _Outptr_ PSTORAGE_DESCRIPTOR_HEADER * Descriptor
Definition: classpnp.h:966
#define PCI_BRIDGE_TYPE
Definition: iotypes.h:3249