ReactOS 0.4.15-dev-7897-g78dc504
pdo.c
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1/*
2 * PROJECT: ReactOS PCI bus driver
3 * FILE: pdo.c
4 * PURPOSE: Child device object dispatch routines
5 * PROGRAMMERS: Casper S. Hornstrup (chorns@users.sourceforge.net)
6 * UPDATE HISTORY:
7 * 10-09-2001 CSH Created
8 */
9
10#include "pci.h"
11
12#include <initguid.h>
13#include <wdmguid.h>
14
15#define NDEBUG
16#include <debug.h>
17
18#if 0
19#define DBGPRINT(...) DbgPrint(__VA_ARGS__)
20#else
21#define DBGPRINT(...)
22#endif
23
24#define PCI_ADDRESS_MEMORY_ADDRESS_MASK_64 0xfffffffffffffff0ull
25#define PCI_ADDRESS_IO_ADDRESS_MASK_64 0xfffffffffffffffcull
26
27/*** PRIVATE *****************************************************************/
28
29static NTSTATUS
32 IN PIRP Irp,
34{
35 PPDO_DEVICE_EXTENSION DeviceExtension;
38
39 DPRINT("Called\n");
40
41 DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
42
43 switch (IrpSp->Parameters.QueryDeviceText.DeviceTextType)
44 {
47 &DeviceExtension->DeviceDescription,
48 &String);
49
50 DPRINT("DeviceTextDescription\n");
51 Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
52 break;
53
56 &DeviceExtension->DeviceLocation,
57 &String);
58
59 DPRINT("DeviceTextLocationInformation\n");
60 Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
61 break;
62
63 default:
64 Irp->IoStatus.Information = 0;
66 break;
67 }
68
69 return Status;
70}
71
72
73static NTSTATUS
76 IN PIRP Irp,
78{
79 PPDO_DEVICE_EXTENSION DeviceExtension;
82
83 DPRINT("Called\n");
84
85 DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
86
87// Irp->IoStatus.Information = 0;
88
90
92
93 switch (IrpSp->Parameters.QueryId.IdType)
94 {
97 &DeviceExtension->DeviceID,
98 &String);
99
100 DPRINT("DeviceID: %S\n", String.Buffer);
101
102 Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
103 break;
104
107 &DeviceExtension->HardwareIDs,
108 &String);
109
110 Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
111 break;
112
115 &DeviceExtension->CompatibleIDs,
116 &String);
117
118 Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
119 break;
120
123 &DeviceExtension->InstanceID,
124 &String);
125
126 DPRINT("InstanceID: %S\n", String.Buffer);
127
128 Irp->IoStatus.Information = (ULONG_PTR)String.Buffer;
129 break;
130
132 default:
134 }
135
136 return Status;
137}
138
139
140static NTSTATUS
143 IN PIRP Irp,
145{
146 PPDO_DEVICE_EXTENSION DeviceExtension;
148
150 DPRINT("Called\n");
151
152 DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
154 Irp->IoStatus.Information = (ULONG_PTR)BusInformation;
155 if (BusInformation != NULL)
156 {
157 BusInformation->BusTypeGuid = GUID_BUS_TYPE_PCI;
158 BusInformation->LegacyBusType = PCIBus;
159 BusInformation->BusNumber = DeviceExtension->PciDevice->BusNumber;
160
161 return STATUS_SUCCESS;
162 }
163
165}
166
167
168static NTSTATUS
171 IN PIRP Irp,
173{
174 PPDO_DEVICE_EXTENSION DeviceExtension;
176 ULONG DeviceNumber, FunctionNumber;
177
179 DPRINT("Called\n");
180
181 DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
183
184 if (DeviceCapabilities->Version != 1)
185 return STATUS_UNSUCCESSFUL;
186
187 DeviceNumber = DeviceExtension->PciDevice->SlotNumber.u.bits.DeviceNumber;
188 FunctionNumber = DeviceExtension->PciDevice->SlotNumber.u.bits.FunctionNumber;
189
190 DeviceCapabilities->UniqueID = FALSE;
191 DeviceCapabilities->Address = ((DeviceNumber << 16) & 0xFFFF0000) + (FunctionNumber & 0xFFFF);
192 DeviceCapabilities->UINumber = MAXULONG; /* FIXME */
193
194 return STATUS_SUCCESS;
195}
196
197static BOOLEAN
200 PULONG OriginalValue,
201 PULONG NewValue)
202{
203 ULONG Size;
204 ULONG AllOnes;
205
206 /* Read the original value */
208 DeviceExtension->PciDevice->BusNumber,
209 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
210 OriginalValue,
211 Offset,
212 sizeof(ULONG));
213 if (Size != sizeof(ULONG))
214 {
215 DPRINT1("Wrong size %lu\n", Size);
216 return FALSE;
217 }
218
219 /* Write all ones to determine which bits are held to zero */
220 AllOnes = MAXULONG;
222 DeviceExtension->PciDevice->BusNumber,
223 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
224 &AllOnes,
225 Offset,
226 sizeof(ULONG));
227 if (Size != sizeof(ULONG))
228 {
229 DPRINT1("Wrong size %lu\n", Size);
230 return FALSE;
231 }
232
233 /* Get the range length */
235 DeviceExtension->PciDevice->BusNumber,
236 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
237 NewValue,
238 Offset,
239 sizeof(ULONG));
240 if (Size != sizeof(ULONG))
241 {
242 DPRINT1("Wrong size %lu\n", Size);
243 return FALSE;
244 }
245
246 /* Restore original value */
248 DeviceExtension->PciDevice->BusNumber,
249 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
250 OriginalValue,
251 Offset,
252 sizeof(ULONG));
253 if (Size != sizeof(ULONG))
254 {
255 DPRINT1("Wrong size %lu\n", Size);
256 return FALSE;
257 }
258
259 return TRUE;
260}
261
262static BOOLEAN
264 UCHAR Bar,
268 PUCHAR NextBar,
269 PULONGLONG MaximumAddress)
270{
271 union {
272 struct {
273 ULONG Bar0;
274 ULONG Bar1;
275 } Bars;
277 } OriginalValue;
278 union {
279 struct {
280 ULONG Bar0;
281 ULONG Bar1;
282 } Bars;
284 } NewValue;
287
288 /* Compute the offset of this BAR in PCI config space */
289 Offset = 0x10 + Bar * 4;
290
291 /* Assume this is a 32-bit BAR until we find wrong */
292 *NextBar = Bar + 1;
293
294 /* Initialize BAR values to zero */
295 OriginalValue.Bar = 0ULL;
296 NewValue.Bar = 0ULL;
297
298 /* Read the first BAR */
299 if (!PdoReadPciBar(DeviceExtension, Offset,
300 &OriginalValue.Bars.Bar0,
301 &NewValue.Bars.Bar0))
302 {
303 return FALSE;
304 }
305
306 /* Check if this is a memory BAR */
307 if (!(OriginalValue.Bars.Bar0 & PCI_ADDRESS_IO_SPACE))
308 {
309 /* Write the maximum address if the caller asked for it */
310 if (MaximumAddress != NULL)
311 {
312 if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_32BIT)
313 {
314 *MaximumAddress = 0x00000000FFFFFFFFULL;
315 }
316 else if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
317 {
318 *MaximumAddress = 0x00000000000FFFFFULL;
319 }
320 else if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
321 {
322 *MaximumAddress = 0xFFFFFFFFFFFFFFFFULL;
323 }
324 }
325
326 /* Check if this is a 64-bit BAR */
327 if ((OriginalValue.Bars.Bar0 & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
328 {
329 /* We've now consumed the next BAR too */
330 *NextBar = Bar + 2;
331
332 /* Read the next BAR */
333 if (!PdoReadPciBar(DeviceExtension, Offset + 4,
334 &OriginalValue.Bars.Bar1,
335 &NewValue.Bars.Bar1))
336 {
337 return FALSE;
338 }
339 }
340 }
341 else
342 {
343 /* Write the maximum I/O port address */
344 if (MaximumAddress != NULL)
345 {
346 *MaximumAddress = 0x00000000FFFFFFFFULL;
347 }
348 }
349
350 if (NewValue.Bar == 0)
351 {
352 DPRINT("Unused address register\n");
353 *Base = 0;
354 *Length = 0;
355 *Flags = 0;
356 return TRUE;
357 }
358
359 *Base = ((OriginalValue.Bar & PCI_ADDRESS_IO_SPACE)
360 ? (OriginalValue.Bar & PCI_ADDRESS_IO_ADDRESS_MASK_64)
361 : (OriginalValue.Bar & PCI_ADDRESS_MEMORY_ADDRESS_MASK_64));
362
363 Size = (NewValue.Bar & PCI_ADDRESS_IO_SPACE)
364 ? (NewValue.Bar & PCI_ADDRESS_IO_ADDRESS_MASK_64)
365 : (NewValue.Bar & PCI_ADDRESS_MEMORY_ADDRESS_MASK_64);
366 *Length = Size & ~(Size - 1);
367
368 *Flags = (NewValue.Bar & PCI_ADDRESS_IO_SPACE)
369 ? (NewValue.Bar & ~PCI_ADDRESS_IO_ADDRESS_MASK_64)
370 : (NewValue.Bar & ~PCI_ADDRESS_MEMORY_ADDRESS_MASK_64);
371
372 return TRUE;
373}
374
375
376static NTSTATUS
379 IN PIRP Irp,
381{
382 PPDO_DEVICE_EXTENSION DeviceExtension;
383 PCI_COMMON_CONFIG PciConfig;
386 ULONG Size;
387 ULONG ResCount = 0;
388 ULONG ListSize;
389 UCHAR Bar;
392 ULONG Flags;
393 ULONGLONG MaximumAddress;
394
396 DPRINT("PdoQueryResourceRequirements() called\n");
397
398 DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
399
400 /* Get PCI configuration space */
402 DeviceExtension->PciDevice->BusNumber,
403 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
404 &PciConfig,
406 DPRINT("Size %lu\n", Size);
408 {
409 Irp->IoStatus.Information = 0;
410 return STATUS_UNSUCCESSFUL;
411 }
412
413 DPRINT("Command register: 0x%04hx\n", PciConfig.Command);
414
415 /* Count required resource descriptors */
416 ResCount = 0;
417 if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
418 {
419 for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
420 {
421 if (!PdoGetRangeLength(DeviceExtension,
422 Bar,
423 &Base,
424 &Length,
425 &Flags,
426 &Bar,
427 NULL))
428 break;
429
430 if (Length != 0)
431 ResCount += 2;
432 }
433
434 /* FIXME: Check ROM address */
435
436 if (PciConfig.u.type0.InterruptPin != 0)
437 ResCount++;
438 }
439 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
440 {
441 for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
442 {
443 if (!PdoGetRangeLength(DeviceExtension,
444 Bar,
445 &Base,
446 &Length,
447 &Flags,
448 &Bar,
449 NULL))
450 break;
451
452 if (Length != 0)
453 ResCount += 2;
454 }
455
456 if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
457 ResCount++;
458 }
459 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
460 {
461 /* FIXME: Count Cardbus bridge resources */
462 }
463 else
464 {
465 DPRINT1("Unsupported header type %d\n", PCI_CONFIGURATION_TYPE(&PciConfig));
466 }
467
468 if (ResCount == 0)
469 {
470 Irp->IoStatus.Information = 0;
471 return STATUS_SUCCESS;
472 }
473
474 /* Calculate the resource list size */
475 ListSize = FIELD_OFFSET(IO_RESOURCE_REQUIREMENTS_LIST, List[0].Descriptors) +
476 ResCount * sizeof(IO_RESOURCE_DESCRIPTOR);
477
478 DPRINT("ListSize %lu (0x%lx)\n", ListSize, ListSize);
479
480 /* Allocate the resource requirements list */
482 ListSize,
483 TAG_PCI);
484 if (ResourceList == NULL)
485 {
486 Irp->IoStatus.Information = 0;
488 }
489
490 RtlZeroMemory(ResourceList, ListSize);
491 ResourceList->ListSize = ListSize;
492 ResourceList->InterfaceType = PCIBus;
493 ResourceList->BusNumber = DeviceExtension->PciDevice->BusNumber;
494 ResourceList->SlotNumber = DeviceExtension->PciDevice->SlotNumber.u.AsULONG;
495 ResourceList->AlternativeLists = 1;
496
497 ResourceList->List[0].Version = 1;
498 ResourceList->List[0].Revision = 1;
499 ResourceList->List[0].Count = ResCount;
500
501 Descriptor = &ResourceList->List[0].Descriptors[0];
502 if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
503 {
504 for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
505 {
506 if (!PdoGetRangeLength(DeviceExtension,
507 Bar,
508 &Base,
509 &Length,
510 &Flags,
511 &Bar,
512 &MaximumAddress))
513 {
514 DPRINT1("PdoGetRangeLength() failed\n");
515 break;
516 }
517
518 if (Length == 0)
519 {
520 DPRINT("Unused address register\n");
521 continue;
522 }
523
524 /* Set preferred descriptor */
527 {
529 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
533
534 Descriptor->u.Port.Length = Length;
535 Descriptor->u.Port.Alignment = 1;
536 Descriptor->u.Port.MinimumAddress.QuadPart = Base;
537 Descriptor->u.Port.MaximumAddress.QuadPart = Base + Length - 1;
538 }
539 else
540 {
542 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
545
546 Descriptor->u.Memory.Length = Length;
547 Descriptor->u.Memory.Alignment = 1;
548 Descriptor->u.Memory.MinimumAddress.QuadPart = Base;
549 Descriptor->u.Memory.MaximumAddress.QuadPart = Base + Length - 1;
550 }
551 Descriptor++;
552
553 /* Set alternative descriptor */
556 {
558 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
562
563 Descriptor->u.Port.Length = Length;
564 Descriptor->u.Port.Alignment = Length;
565 Descriptor->u.Port.MinimumAddress.QuadPart = 0;
566 Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
567 }
568 else
569 {
571 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
574
575 Descriptor->u.Memory.Length = Length;
576 Descriptor->u.Memory.Alignment = Length;
577 Descriptor->u.Port.MinimumAddress.QuadPart = 0;
578 Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
579 }
580 Descriptor++;
581 }
582
583 /* FIXME: Check ROM address */
584
585 if (PciConfig.u.type0.InterruptPin != 0)
586 {
587 Descriptor->Option = 0; /* Required */
589 Descriptor->ShareDisposition = CmResourceShareShared;
591
592 Descriptor->u.Interrupt.MinimumVector = 0;
593 Descriptor->u.Interrupt.MaximumVector = 0xFF;
594 }
595 }
596 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
597 {
598 for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
599 {
600 if (!PdoGetRangeLength(DeviceExtension,
601 Bar,
602 &Base,
603 &Length,
604 &Flags,
605 &Bar,
606 &MaximumAddress))
607 {
608 DPRINT1("PdoGetRangeLength() failed\n");
609 break;
610 }
611
612 if (Length == 0)
613 {
614 DPRINT("Unused address register\n");
615 continue;
616 }
617
618 /* Set preferred descriptor */
621 {
623 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
627
628 Descriptor->u.Port.Length = Length;
629 Descriptor->u.Port.Alignment = 1;
630 Descriptor->u.Port.MinimumAddress.QuadPart = Base;
631 Descriptor->u.Port.MaximumAddress.QuadPart = Base + Length - 1;
632 }
633 else
634 {
636 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
639
640 Descriptor->u.Memory.Length = Length;
641 Descriptor->u.Memory.Alignment = 1;
642 Descriptor->u.Memory.MinimumAddress.QuadPart = Base;
643 Descriptor->u.Memory.MaximumAddress.QuadPart = Base + Length - 1;
644 }
645 Descriptor++;
646
647 /* Set alternative descriptor */
650 {
652 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
656
657 Descriptor->u.Port.Length = Length;
658 Descriptor->u.Port.Alignment = Length;
659 Descriptor->u.Port.MinimumAddress.QuadPart = 0;
660 Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
661 }
662 else
663 {
665 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
668
669 Descriptor->u.Memory.Length = Length;
670 Descriptor->u.Memory.Alignment = Length;
671 Descriptor->u.Port.MinimumAddress.QuadPart = 0;
672 Descriptor->u.Port.MaximumAddress.QuadPart = MaximumAddress;
673 }
674 Descriptor++;
675 }
676
677 if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
678 {
679 Descriptor->Option = 0; /* Required */
681 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
682
683 ResourceList->BusNumber =
684 Descriptor->u.BusNumber.MinBusNumber =
685 Descriptor->u.BusNumber.MaxBusNumber = DeviceExtension->PciDevice->PciConfig.u.type1.SecondaryBus;
686 Descriptor->u.BusNumber.Length = 1;
687 Descriptor->u.BusNumber.Reserved = 0;
688 }
689 }
690 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
691 {
692 /* FIXME: Add Cardbus bridge resources */
693 }
694
695 Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
696
697 return STATUS_SUCCESS;
698}
699
700
701static NTSTATUS
704 IN PIRP Irp,
706{
707 PPDO_DEVICE_EXTENSION DeviceExtension;
708 PCI_COMMON_CONFIG PciConfig;
710 PCM_PARTIAL_RESOURCE_LIST PartialList;
712 ULONG Size;
713 ULONG ResCount = 0;
714 ULONG ListSize;
715 UCHAR Bar;
718 ULONG Flags;
719
720 DPRINT("PdoQueryResources() called\n");
721
723 DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
724
725 /* Get PCI configuration space */
727 DeviceExtension->PciDevice->BusNumber,
728 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
729 &PciConfig,
731 DPRINT("Size %lu\n", Size);
733 {
734 Irp->IoStatus.Information = 0;
735 return STATUS_UNSUCCESSFUL;
736 }
737
738 DPRINT("Command register: 0x%04hx\n", PciConfig.Command);
739
740 /* Count required resource descriptors */
741 ResCount = 0;
742 if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
743 {
744 for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
745 {
746 if (!PdoGetRangeLength(DeviceExtension,
747 Bar,
748 &Base,
749 &Length,
750 &Flags,
751 &Bar,
752 NULL))
753 break;
754
755 if (Length)
756 ResCount++;
757 }
758
759 if ((PciConfig.u.type0.InterruptPin != 0) &&
760 (PciConfig.u.type0.InterruptLine != 0) &&
761 (PciConfig.u.type0.InterruptLine != 0xFF))
762 ResCount++;
763 }
764 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
765 {
766 for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
767 {
768 if (!PdoGetRangeLength(DeviceExtension,
769 Bar,
770 &Base,
771 &Length,
772 &Flags,
773 &Bar,
774 NULL))
775 break;
776
777 if (Length != 0)
778 ResCount++;
779 }
780
781 if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
782 ResCount++;
783 }
784 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
785 {
786 /* FIXME: Count Cardbus bridge resources */
787 }
788 else
789 {
790 DPRINT1("Unsupported header type %d\n", PCI_CONFIGURATION_TYPE(&PciConfig));
791 }
792
793 if (ResCount == 0)
794 {
795 Irp->IoStatus.Information = 0;
796 return STATUS_SUCCESS;
797 }
798
799 /* Calculate the resource list size */
800 ListSize = FIELD_OFFSET(CM_RESOURCE_LIST, List[0].PartialResourceList.PartialDescriptors) +
801 ResCount * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR);
802
803 /* Allocate the resource list */
805 ListSize,
806 TAG_PCI);
807 if (ResourceList == NULL)
809
810 RtlZeroMemory(ResourceList, ListSize);
811 ResourceList->Count = 1;
812 ResourceList->List[0].InterfaceType = PCIBus;
813 ResourceList->List[0].BusNumber = DeviceExtension->PciDevice->BusNumber;
814
815 PartialList = &ResourceList->List[0].PartialResourceList;
816 PartialList->Version = 1;
817 PartialList->Revision = 1;
818 PartialList->Count = ResCount;
819
820 Descriptor = &PartialList->PartialDescriptors[0];
821 if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_DEVICE_TYPE)
822 {
823 for (Bar = 0; Bar < PCI_TYPE0_ADDRESSES;)
824 {
825 if (!PdoGetRangeLength(DeviceExtension,
826 Bar,
827 &Base,
828 &Length,
829 &Flags,
830 &Bar,
831 NULL))
832 break;
833
834 if (Length == 0)
835 {
836 DPRINT("Unused address register\n");
837 continue;
838 }
839
841 {
843 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
847 Descriptor->u.Port.Start.QuadPart = (ULONGLONG)Base;
848 Descriptor->u.Port.Length = Length;
849
850 /* Enable IO space access */
851 DeviceExtension->PciDevice->EnableIoSpace = TRUE;
852 }
853 else
854 {
856 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
859 Descriptor->u.Memory.Start.QuadPart = (ULONGLONG)Base;
860 Descriptor->u.Memory.Length = Length;
861
862 /* Enable memory space access */
863 DeviceExtension->PciDevice->EnableMemorySpace = TRUE;
864 }
865
866 Descriptor++;
867 }
868
869 /* Add interrupt resource */
870 if ((PciConfig.u.type0.InterruptPin != 0) &&
871 (PciConfig.u.type0.InterruptLine != 0) &&
872 (PciConfig.u.type0.InterruptLine != 0xFF))
873 {
875 Descriptor->ShareDisposition = CmResourceShareShared;
877 Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
878 Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
879 Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
880 }
881
882 /* Allow bus master mode */
883 DeviceExtension->PciDevice->EnableBusMaster = TRUE;
884 }
885 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_BRIDGE_TYPE)
886 {
887 for (Bar = 0; Bar < PCI_TYPE1_ADDRESSES;)
888 {
889 if (!PdoGetRangeLength(DeviceExtension,
890 Bar,
891 &Base,
892 &Length,
893 &Flags,
894 &Bar,
895 NULL))
896 break;
897
898 if (Length == 0)
899 {
900 DPRINT("Unused address register\n");
901 continue;
902 }
903
905 {
907 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
911 Descriptor->u.Port.Start.QuadPart = (ULONGLONG)Base;
912 Descriptor->u.Port.Length = Length;
913
914 /* Enable IO space access */
915 DeviceExtension->PciDevice->EnableIoSpace = TRUE;
916 }
917 else
918 {
920 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
923 Descriptor->u.Memory.Start.QuadPart = (ULONGLONG)Base;
924 Descriptor->u.Memory.Length = Length;
925
926 /* Enable memory space access */
927 DeviceExtension->PciDevice->EnableMemorySpace = TRUE;
928 }
929
930 Descriptor++;
931 }
932
933 if (DeviceExtension->PciDevice->PciConfig.BaseClass == PCI_CLASS_BRIDGE_DEV)
934 {
936 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
937
938 ResourceList->List[0].BusNumber =
939 Descriptor->u.BusNumber.Start = DeviceExtension->PciDevice->PciConfig.u.type1.SecondaryBus;
940 Descriptor->u.BusNumber.Length = 1;
941 Descriptor->u.BusNumber.Reserved = 0;
942 }
943 }
944 else if (PCI_CONFIGURATION_TYPE(&PciConfig) == PCI_CARDBUS_BRIDGE_TYPE)
945 {
946 /* FIXME: Add Cardbus bridge resources */
947 }
948
949 Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
950
951 return STATUS_SUCCESS;
952}
953
954
955static VOID NTAPI
958{
959 PPDO_DEVICE_EXTENSION DeviceExtension;
960
961 DPRINT("InterfaceReference(%p)\n", Context);
962
963 DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
964 InterlockedIncrement(&DeviceExtension->References);
965}
966
967
968static VOID NTAPI
971{
972 PPDO_DEVICE_EXTENSION DeviceExtension;
973
974 DPRINT("InterfaceDereference(%p)\n", Context);
975
976 DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
977 InterlockedDecrement(&DeviceExtension->References);
978}
979
980static TRANSLATE_BUS_ADDRESS InterfaceBusTranslateBusAddress;
981
982static
984NTAPI
991{
992 PPDO_DEVICE_EXTENSION DeviceExtension;
993
994 DPRINT("InterfaceBusTranslateBusAddress(%p %p 0x%lx %p %p)\n",
996
997 DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
998
1000 DeviceExtension->PciDevice->BusNumber,
1001 BusAddress,
1004}
1005
1006static GET_DMA_ADAPTER InterfaceBusGetDmaAdapter;
1007
1008static
1010NTAPI
1015{
1016 DPRINT("InterfaceBusGetDmaAdapter(%p %p %p)\n",
1019}
1020
1021static GET_SET_DEVICE_DATA InterfaceBusSetBusData;
1022
1023static
1024ULONG
1025NTAPI
1029 IN PVOID Buffer,
1030 IN ULONG Offset,
1031 IN ULONG Length)
1032{
1033 PPDO_DEVICE_EXTENSION DeviceExtension;
1034 ULONG Size;
1035
1036 DPRINT("InterfaceBusSetBusData(%p 0x%lx %p 0x%lx 0x%lx)\n",
1038
1040 {
1041 DPRINT("Unknown DataType %lu\n", DataType);
1042 return 0;
1043 }
1044
1045 DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
1046
1047 /* Get PCI configuration space */
1049 DeviceExtension->PciDevice->BusNumber,
1050 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1051 Buffer,
1052 Offset,
1053 Length);
1054 return Size;
1055}
1056
1057static GET_SET_DEVICE_DATA InterfaceBusGetBusData;
1058
1059static
1060ULONG
1061NTAPI
1065 IN PVOID Buffer,
1066 IN ULONG Offset,
1067 IN ULONG Length)
1068{
1069 PPDO_DEVICE_EXTENSION DeviceExtension;
1070 ULONG Size;
1071
1072 DPRINT("InterfaceBusGetBusData(%p 0x%lx %p 0x%lx 0x%lx) called\n",
1074
1076 {
1077 DPRINT("Unknown DataType %lu\n", DataType);
1078 return 0;
1079 }
1080
1081 DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
1082
1083 /* Get PCI configuration space */
1085 DeviceExtension->PciDevice->BusNumber,
1086 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1087 Buffer,
1088 Offset,
1089 Length);
1090 return Size;
1091}
1092
1093
1094static BOOLEAN NTAPI
1096 IN USHORT VendorID,
1101 IN ULONG Flags)
1102{
1103 PFDO_DEVICE_EXTENSION FdoDeviceExtension;
1104 PPCI_DEVICE PciDevice;
1105 PLIST_ENTRY CurrentBus, CurrentEntry;
1106 KIRQL OldIrql;
1108
1110 CurrentBus = DriverExtension->BusListHead.Flink;
1111 while (!Found && CurrentBus != &DriverExtension->BusListHead)
1112 {
1113 FdoDeviceExtension = CONTAINING_RECORD(CurrentBus, FDO_DEVICE_EXTENSION, ListEntry);
1114
1115 KeAcquireSpinLockAtDpcLevel(&FdoDeviceExtension->DeviceListLock);
1116 CurrentEntry = FdoDeviceExtension->DeviceListHead.Flink;
1117 while (!Found && CurrentEntry != &FdoDeviceExtension->DeviceListHead)
1118 {
1119 PciDevice = CONTAINING_RECORD(CurrentEntry, PCI_DEVICE, ListEntry);
1120 if (PciDevice->PciConfig.VendorID == VendorID &&
1121 PciDevice->PciConfig.DeviceID == DeviceID)
1122 {
1123 if (!(Flags & PCI_USE_SUBSYSTEM_IDS) ||
1124 (PciDevice->PciConfig.u.type0.SubVendorID == SubVendorID &&
1125 PciDevice->PciConfig.u.type0.SubSystemID == SubSystemID))
1126 {
1127 if (!(Flags & PCI_USE_REVISION) ||
1128 PciDevice->PciConfig.RevisionID == RevisionID)
1129 {
1130 DPRINT("Found the PCI device\n");
1131 Found = TRUE;
1132 }
1133 }
1134 }
1135
1136 CurrentEntry = CurrentEntry->Flink;
1137 }
1138
1139 KeReleaseSpinLockFromDpcLevel(&FdoDeviceExtension->DeviceListLock);
1140 CurrentBus = CurrentBus->Flink;
1141 }
1143
1144 return Found;
1145}
1146
1147
1148static BOOLEAN
1150 IN PPCI_COMMON_CONFIG PciConfig,
1152{
1153 if ((Parameters->Flags & PCI_USE_VENDEV_IDS) &&
1154 (PciConfig->VendorID != Parameters->VendorID ||
1155 PciConfig->DeviceID != Parameters->DeviceID))
1156 {
1157 return FALSE;
1158 }
1159
1160 if ((Parameters->Flags & PCI_USE_CLASS_SUBCLASS) &&
1161 (PciConfig->BaseClass != Parameters->BaseClass ||
1162 PciConfig->SubClass != Parameters->SubClass))
1163 {
1164 return FALSE;
1165 }
1166
1167 if ((Parameters->Flags & PCI_USE_PROGIF) &&
1168 PciConfig->ProgIf != Parameters->ProgIf)
1169 {
1170 return FALSE;
1171 }
1172
1173 if ((Parameters->Flags & PCI_USE_SUBSYSTEM_IDS) &&
1174 (PciConfig->u.type0.SubVendorID != Parameters->SubVendorID ||
1175 PciConfig->u.type0.SubSystemID != Parameters->SubSystemID))
1176 {
1177 return FALSE;
1178 }
1179
1180 if ((Parameters->Flags & PCI_USE_REVISION) &&
1181 PciConfig->RevisionID != Parameters->RevisionID)
1182 {
1183 return FALSE;
1184 }
1185
1186 return TRUE;
1187}
1188
1189
1190static BOOLEAN NTAPI
1194{
1195 PPDO_DEVICE_EXTENSION DeviceExtension;
1196 PFDO_DEVICE_EXTENSION MyFdoDeviceExtension;
1197 PFDO_DEVICE_EXTENSION FdoDeviceExtension;
1198 PPCI_DEVICE PciDevice;
1199 PLIST_ENTRY CurrentBus, CurrentEntry;
1200 KIRQL OldIrql;
1202
1203 DPRINT("InterfacePciDevicePresentEx(%p %p) called\n",
1205
1206 if (!Parameters || Parameters->Size != sizeof(PCI_DEVICE_PRESENCE_PARAMETERS))
1207 return FALSE;
1208
1209 DeviceExtension = (PPDO_DEVICE_EXTENSION)((PDEVICE_OBJECT)Context)->DeviceExtension;
1210 MyFdoDeviceExtension = (PFDO_DEVICE_EXTENSION)DeviceExtension->Fdo->DeviceExtension;
1211
1213 {
1214 return CheckPciDevice(&DeviceExtension->PciDevice->PciConfig, Parameters);
1215 }
1216
1218 CurrentBus = DriverExtension->BusListHead.Flink;
1219 while (!Found && CurrentBus != &DriverExtension->BusListHead)
1220 {
1221 FdoDeviceExtension = CONTAINING_RECORD(CurrentBus, FDO_DEVICE_EXTENSION, ListEntry);
1222 if (!(Parameters->Flags & PCI_USE_LOCAL_BUS) || FdoDeviceExtension == MyFdoDeviceExtension)
1223 {
1224 KeAcquireSpinLockAtDpcLevel(&FdoDeviceExtension->DeviceListLock);
1225 CurrentEntry = FdoDeviceExtension->DeviceListHead.Flink;
1226 while (!Found && CurrentEntry != &FdoDeviceExtension->DeviceListHead)
1227 {
1228 PciDevice = CONTAINING_RECORD(CurrentEntry, PCI_DEVICE, ListEntry);
1229
1230 if (CheckPciDevice(&PciDevice->PciConfig, Parameters))
1231 {
1232 DPRINT("Found the PCI device\n");
1233 Found = TRUE;
1234 }
1235
1236 CurrentEntry = CurrentEntry->Flink;
1237 }
1238
1239 KeReleaseSpinLockFromDpcLevel(&FdoDeviceExtension->DeviceListLock);
1240 }
1241 CurrentBus = CurrentBus->Flink;
1242 }
1244
1245 return Found;
1246}
1247
1248
1249static NTSTATUS
1252 IN PIRP Irp,
1254{
1256
1258
1260 &GUID_BUS_INTERFACE_STANDARD, sizeof(GUID)) == sizeof(GUID))
1261 {
1262 /* BUS_INTERFACE_STANDARD */
1263 if (IrpSp->Parameters.QueryInterface.Version < 1)
1265 else if (IrpSp->Parameters.QueryInterface.Size < sizeof(BUS_INTERFACE_STANDARD))
1267 else
1268 {
1269 PBUS_INTERFACE_STANDARD BusInterface;
1270 BusInterface = (PBUS_INTERFACE_STANDARD)IrpSp->Parameters.QueryInterface.Interface;
1271 BusInterface->Size = sizeof(BUS_INTERFACE_STANDARD);
1272 BusInterface->Version = 1;
1275 BusInterface->SetBusData = InterfaceBusSetBusData;
1276 BusInterface->GetBusData = InterfaceBusGetBusData;
1278 }
1279 }
1280 else if (RtlCompareMemory(IrpSp->Parameters.QueryInterface.InterfaceType,
1281 &GUID_PCI_DEVICE_PRESENT_INTERFACE, sizeof(GUID)) == sizeof(GUID))
1282 {
1283 /* PCI_DEVICE_PRESENT_INTERFACE */
1284 if (IrpSp->Parameters.QueryInterface.Version < 1)
1288 else
1289 {
1293 PciDevicePresentInterface->Version = 1;
1297 }
1298 }
1299 else
1300 {
1301 /* Not a supported interface */
1302 return STATUS_NOT_SUPPORTED;
1303 }
1304
1305 if (NT_SUCCESS(Status))
1306 {
1307 /* Add a reference for the returned interface */
1310 Interface->Context = DeviceObject;
1311 Interface->InterfaceReference = InterfaceReference;
1312 Interface->InterfaceDereference = InterfaceDereference;
1313 Interface->InterfaceReference(Interface->Context);
1314 }
1315
1316 return Status;
1317}
1318
1319static NTSTATUS
1322 IN PIRP Irp,
1324{
1325 PCM_RESOURCE_LIST RawResList = IrpSp->Parameters.StartDevice.AllocatedResources;
1326 PCM_FULL_RESOURCE_DESCRIPTOR RawFullDesc;
1327 PCM_PARTIAL_RESOURCE_DESCRIPTOR RawPartialDesc;
1328 ULONG i, ii;
1329 PPDO_DEVICE_EXTENSION DeviceExtension = DeviceObject->DeviceExtension;
1330 UCHAR Irq;
1332
1334
1335 if (!RawResList)
1336 return STATUS_SUCCESS;
1337
1338 /* TODO: Assign the other resources we get to the card */
1339
1340 RawFullDesc = &RawResList->List[0];
1341 for (i = 0; i < RawResList->Count; i++, RawFullDesc = CmiGetNextResourceDescriptor(RawFullDesc))
1342 {
1343 for (ii = 0; ii < RawFullDesc->PartialResourceList.Count; ii++)
1344 {
1345 /* Partial resource descriptors can be of variable size (CmResourceTypeDeviceSpecific),
1346 but only one is allowed and it must be the last one in the list! */
1347 RawPartialDesc = &RawFullDesc->PartialResourceList.PartialDescriptors[ii];
1348
1349 if (RawPartialDesc->Type == CmResourceTypeInterrupt)
1350 {
1351 DPRINT("Assigning IRQ %u to PCI device 0x%x on bus 0x%x\n",
1352 RawPartialDesc->u.Interrupt.Vector,
1353 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1354 DeviceExtension->PciDevice->BusNumber);
1355
1356 Irq = (UCHAR)RawPartialDesc->u.Interrupt.Vector;
1358 DeviceExtension->PciDevice->BusNumber,
1359 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1360 &Irq,
1361 0x3c /* PCI_INTERRUPT_LINE */,
1362 sizeof(UCHAR));
1363 }
1364 }
1365 }
1366
1367 Command = 0;
1368
1369 DBGPRINT("pci!PdoStartDevice: Enabling command flags for PCI device 0x%x on bus 0x%x: ",
1370 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1371 DeviceExtension->PciDevice->BusNumber);
1372 if (DeviceExtension->PciDevice->EnableBusMaster)
1373 {
1375 DBGPRINT("[Bus master] ");
1376 }
1377
1378 if (DeviceExtension->PciDevice->EnableMemorySpace)
1379 {
1381 DBGPRINT("[Memory space enable] ");
1382 }
1383
1384 if (DeviceExtension->PciDevice->EnableIoSpace)
1385 {
1387 DBGPRINT("[I/O space enable] ");
1388 }
1389
1390 if (Command != 0)
1391 {
1392 DBGPRINT("\n");
1393
1394 /* OR with the previous value */
1395 Command |= DeviceExtension->PciDevice->PciConfig.Command;
1396
1398 DeviceExtension->PciDevice->BusNumber,
1399 DeviceExtension->PciDevice->SlotNumber.u.AsULONG,
1400 &Command,
1402 sizeof(USHORT));
1403 }
1404 else
1405 {
1406 DBGPRINT("None\n");
1407 }
1408
1409 return STATUS_SUCCESS;
1410}
1411
1412static NTSTATUS
1415 IN PIRP Irp,
1417{
1418 ULONG Size;
1419
1420 DPRINT("PdoReadConfig() called\n");
1421
1423 IrpSp->Parameters.ReadWriteConfig.WhichSpace,
1427
1428 if (Size != IrpSp->Parameters.ReadWriteConfig.Length)
1429 {
1430 DPRINT1("Size %lu Length %lu\n", Size, IrpSp->Parameters.ReadWriteConfig.Length);
1431 Irp->IoStatus.Information = 0;
1432 return STATUS_UNSUCCESSFUL;
1433 }
1434
1435 Irp->IoStatus.Information = Size;
1436
1437 return STATUS_SUCCESS;
1438}
1439
1440
1441static NTSTATUS
1444 IN PIRP Irp,
1446{
1447 ULONG Size;
1448
1449 DPRINT1("PdoWriteConfig() called\n");
1450
1451 /* Get PCI configuration space */
1453 IrpSp->Parameters.ReadWriteConfig.WhichSpace,
1457
1458 if (Size != IrpSp->Parameters.ReadWriteConfig.Length)
1459 {
1460 DPRINT1("Size %lu Length %lu\n", Size, IrpSp->Parameters.ReadWriteConfig.Length);
1461 Irp->IoStatus.Information = 0;
1462 return STATUS_UNSUCCESSFUL;
1463 }
1464
1465 Irp->IoStatus.Information = Size;
1466
1467 return STATUS_SUCCESS;
1468}
1469
1470static NTSTATUS
1473 IN PIRP Irp,
1475{
1476 PDEVICE_RELATIONS DeviceRelations;
1477
1478 /* We only support TargetDeviceRelation for child PDOs */
1480 return Irp->IoStatus.Status;
1481
1482 /* We can do this because we only return 1 PDO for TargetDeviceRelation */
1483 DeviceRelations = ExAllocatePoolWithTag(PagedPool, sizeof(*DeviceRelations), TAG_PCI);
1484 if (!DeviceRelations)
1486
1487 DeviceRelations->Count = 1;
1488 DeviceRelations->Objects[0] = DeviceObject;
1489
1490 /* The PnP manager will remove this when it is done with the PDO */
1492
1493 Irp->IoStatus.Information = (ULONG_PTR)DeviceRelations;
1494
1495 return STATUS_SUCCESS;
1496}
1497
1498
1499/*** PUBLIC ******************************************************************/
1500
1504 PIRP Irp)
1505/*
1506 * FUNCTION: Handle Plug and Play IRPs for the child device
1507 * ARGUMENTS:
1508 * DeviceObject = Pointer to physical device object of the child device
1509 * Irp = Pointer to IRP that should be handled
1510 * RETURNS:
1511 * Status
1512 */
1513{
1516
1517 DPRINT("Called\n");
1518
1519 Status = Irp->IoStatus.Status;
1520
1522
1523 switch (IrpSp->MinorFunction)
1524 {
1526 DPRINT("Unimplemented IRP_MN_DEVICE_USAGE_NOTIFICATION received\n");
1527 break;
1528
1529 case IRP_MN_EJECT:
1530 DPRINT("Unimplemented IRP_MN_EJECT received\n");
1531 break;
1532
1535 break;
1536
1539 break;
1540
1543 break;
1544
1546 DPRINT("IRP_MN_QUERY_DEVICE_TEXT received\n");
1548 break;
1549
1550 case IRP_MN_QUERY_ID:
1551 DPRINT("IRP_MN_QUERY_ID received\n");
1553 break;
1554
1556 DPRINT("Unimplemented IRP_MN_QUERY_ID received\n");
1557 break;
1558
1560 DPRINT("IRP_MN_QUERY_RESOURCE_REQUIREMENTS received\n");
1562 break;
1563
1565 DPRINT("IRP_MN_QUERY_RESOURCES received\n");
1567 break;
1568
1569 case IRP_MN_SET_LOCK:
1570 DPRINT("Unimplemented IRP_MN_SET_LOCK received\n");
1571 break;
1572
1575 break;
1576
1579 case IRP_MN_STOP_DEVICE:
1585 break;
1586
1588 DPRINT("IRP_MN_QUERY_INTERFACE received\n");
1590 break;
1591
1592 case IRP_MN_READ_CONFIG:
1593 DPRINT("IRP_MN_READ_CONFIG received\n");
1595 break;
1596
1598 DPRINT("IRP_MN_WRITE_CONFIG received\n");
1600 break;
1601
1603 DPRINT("IRP_MN_FILTER_RESOURCE_REQUIREMENTS received\n");
1604 /* Nothing to do */
1605 Irp->IoStatus.Status = Status;
1606 break;
1607
1608 default:
1609 DPRINT1("Unknown IOCTL 0x%lx\n", IrpSp->MinorFunction);
1610 break;
1611 }
1612
1613 if (Status != STATUS_PENDING)
1614 {
1615 Irp->IoStatus.Status = Status;
1617 }
1618
1619 DPRINT("Leaving. Status 0x%X\n", Status);
1620
1621 return Status;
1622}
1623
1627 PIRP Irp)
1628/*
1629 * FUNCTION: Handle power management IRPs for the child device
1630 * ARGUMENTS:
1631 * DeviceObject = Pointer to physical device object of the child device
1632 * Irp = Pointer to IRP that should be handled
1633 * RETURNS:
1634 * Status
1635 */
1636{
1638 NTSTATUS Status = Irp->IoStatus.Status;
1639
1640 DPRINT("Called\n");
1641
1643
1644 switch (IrpSp->MinorFunction)
1645 {
1646 case IRP_MN_QUERY_POWER:
1647 case IRP_MN_SET_POWER:
1649 break;
1650 }
1651
1653 Irp->IoStatus.Status = Status;
1655
1656 DPRINT("Leaving. Status 0x%X\n", Status);
1657
1658 return Status;
1659}
1660
1661/* EOF */
static PIO_STACK_LOCATION IoGetCurrentIrpStackLocation(PIRP Irp)
unsigned char BOOLEAN
#define InterlockedIncrement
Definition: armddk.h:53
#define InterlockedDecrement
Definition: armddk.h:52
LONG NTSTATUS
Definition: precomp.h:26
#define DPRINT1
Definition: precomp.h:8
#define IO_RESOURCE_ALTERNATIVE
Definition: edit.c:119
#define IO_RESOURCE_PREFERRED
Definition: edit.c:117
struct _IO_RESOURCE_DESCRIPTOR IO_RESOURCE_DESCRIPTOR
static VOID NTAPI InterfaceReference(IN PVOID Context)
Definition: pdo.c:956
static NTSTATUS PdoReadConfig(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1413
NTSTATUS PdoPnpControl(PDEVICE_OBJECT DeviceObject, PIRP Irp)
Definition: pdo.c:1502
static GET_SET_DEVICE_DATA InterfaceBusGetBusData
Definition: pdo.c:1057
static NTSTATUS PdoWriteConfig(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1442
static NTSTATUS PdoQueryResources(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:702
static NTSTATUS PdoQueryCapabilities(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:169
static BOOLEAN PdoReadPciBar(PPDO_DEVICE_EXTENSION DeviceExtension, ULONG Offset, PULONG OriginalValue, PULONG NewValue)
Definition: pdo.c:198
static NTSTATUS PdoQueryBusInformation(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:141
NTSTATUS PdoPowerControl(PDEVICE_OBJECT DeviceObject, PIRP Irp)
Definition: pdo.c:1625
static BOOLEAN NTAPI InterfacePciDevicePresent(IN USHORT VendorID, IN USHORT DeviceID, IN UCHAR RevisionID, IN USHORT SubVendorID, IN USHORT SubSystemID, IN ULONG Flags)
Definition: pdo.c:1095
static BOOLEAN CheckPciDevice(IN PPCI_COMMON_CONFIG PciConfig, IN PPCI_DEVICE_PRESENCE_PARAMETERS Parameters)
Definition: pdo.c:1149
#define PCI_ADDRESS_MEMORY_ADDRESS_MASK_64
Definition: pdo.c:24
static NTSTATUS PdoQueryResourceRequirements(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:377
static GET_SET_DEVICE_DATA InterfaceBusSetBusData
Definition: pdo.c:1021
#define PCI_ADDRESS_IO_ADDRESS_MASK_64
Definition: pdo.c:25
static NTSTATUS PdoQueryDeviceText(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:30
static NTSTATUS PdoStartDevice(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1320
static NTSTATUS PdoQueryDeviceRelations(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1471
static TRANSLATE_BUS_ADDRESS InterfaceBusTranslateBusAddress
Definition: pdo.c:980
static VOID NTAPI InterfaceDereference(IN PVOID Context)
Definition: pdo.c:969
static NTSTATUS PdoQueryInterface(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:1250
static GET_DMA_ADAPTER InterfaceBusGetDmaAdapter
Definition: pdo.c:1006
#define DBGPRINT(...)
Definition: pdo.c:21
static NTSTATUS PdoQueryId(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp, PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:74
static BOOLEAN PdoGetRangeLength(PPDO_DEVICE_EXTENSION DeviceExtension, UCHAR Bar, PULONGLONG Base, PULONGLONG Length, PULONG Flags, PUCHAR NextBar, PULONGLONG MaximumAddress)
Definition: pdo.c:263
static BOOLEAN NTAPI InterfacePciDevicePresentEx(IN PVOID Context, IN PPCI_DEVICE_PRESENCE_PARAMETERS Parameters)
Definition: pdo.c:1191
return Found
Definition: dirsup.c:1270
Definition: bufpool.h:45
_In_ PCHAR _In_ ULONG DeviceNumber
Definition: classpnp.h:1230
FORCEINLINE PCM_FULL_RESOURCE_DESCRIPTOR CmiGetNextResourceDescriptor(_In_ const CM_FULL_RESOURCE_DESCRIPTOR *ResourceDescriptor)
Definition: cmreslist.h:54
_In_ PIRP Irp
Definition: csq.h:116
#define NULL
Definition: types.h:112
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:32
struct _FDO_DEVICE_EXTENSION * PFDO_DEVICE_EXTENSION
struct _PDO_DEVICE_EXTENSION * PPDO_DEVICE_EXTENSION
#define TAG_PCI
Definition: pci.h:8
switch(r->id)
Definition: btrfs.c:3046
_In_ PIO_STACK_LOCATION IrpSp
Definition: create.c:4137
#define ULONG_PTR
Definition: config.h:101
NTHALAPI ULONG NTAPI HalGetBusData(BUS_DATA_TYPE, ULONG, ULONG, PVOID, ULONG)
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
UCHAR KIRQL
Definition: env_spec_w32.h:591
#define RtlCompareMemory(s1, s2, l)
Definition: env_spec_w32.h:465
#define KeReleaseSpinLock(sl, irql)
Definition: env_spec_w32.h:627
#define KeAcquireSpinLock(sl, irql)
Definition: env_spec_w32.h:609
#define PagedPool
Definition: env_spec_w32.h:308
Status
Definition: gdiplustypes.h:25
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
#define RTL_DUPLICATE_UNICODE_STRING_NULL_TERMINATE
Definition: green.h:15
ULONG NTAPI HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:123
BOOLEAN NTAPI HalTranslateBusAddress(IN INTERFACE_TYPE InterfaceType, IN ULONG BusNumber, IN PHYSICAL_ADDRESS BusAddress, IN OUT PULONG AddressSpace, OUT PPHYSICAL_ADDRESS TranslatedAddress)
Definition: bus.c:140
ULONG NTAPI HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:73
PADAPTER_OBJECT NTAPI HalGetAdapter(IN PDEVICE_DESCRIPTION DeviceDescription, OUT PULONG NumberOfMapRegisters)
Definition: dma.c:22
#define CmResourceTypeMemory
Definition: hwresource.cpp:125
@ PCIBus
Definition: hwresource.cpp:142
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR CM_PARTIAL_RESOURCE_DESCRIPTOR
#define CmResourceTypePort
Definition: hwresource.cpp:123
#define CmResourceTypeBusNumber
Definition: hwresource.cpp:128
#define CmResourceTypeInterrupt
Definition: hwresource.cpp:124
PCI_INTERFACE PciDevicePresentInterface
Definition: devhere.c:18
if(dx< 0)
Definition: linetemp.h:194
void Bar(void)
Definition: terminate.cpp:70
#define ULL(a, b)
Definition: format_msg.c:27
#define CM_RESOURCE_PORT_POSITIVE_DECODE
Definition: cmtypes.h:113
#define CM_RESOURCE_MEMORY_PREFETCHABLE
Definition: cmtypes.h:123
#define CM_RESOURCE_PORT_IO
Definition: cmtypes.h:109
#define CM_RESOURCE_PORT_16_BIT_DECODE
Definition: cmtypes.h:112
#define CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
Definition: cmtypes.h:143
#define CM_RESOURCE_MEMORY_READ_WRITE
Definition: cmtypes.h:120
_In_opt_ ULONG Base
Definition: rtlfuncs.h:2439
NTSYSAPI VOID NTAPI RtlInitUnicodeString(PUNICODE_STRING DestinationString, PCWSTR SourceString)
__GNU_EXTENSION typedef unsigned __int64 * PULONGLONG
Definition: ntbasedef.h:383
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
_In_ ULONG _In_ ULONG _In_ ULONG Length
Definition: ntddpcm.h:102
#define IRP_MN_SURPRISE_REMOVAL
Definition: ntifs_ex.h:408
#define IoCompleteRequest
Definition: irp.c:1240
VOID NTAPI PoStartNextPowerIrp(IN PIRP Irp)
Definition: power.c:758
#define STATUS_PENDING
Definition: ntstatus.h:82
#define STATUS_NOT_SUPPORTED
Definition: ntstatus.h:423
#define STATUS_NOT_IMPLEMENTED
Definition: ntstatus.h:239
PPCI_DRIVER_EXTENSION DriverExtension
Definition: pci.c:31
NTSTATUS PciDuplicateUnicodeString(IN ULONG Flags, IN PCUNICODE_STRING SourceString, OUT PUNICODE_STRING DestinationString)
Definition: pci.c:713
unsigned short USHORT
Definition: pedump.c:61
@ PCIConfiguration
Definition: miniport.h:93
struct _INTERFACE * PINTERFACE
#define KeAcquireSpinLockAtDpcLevel(SpinLock)
Definition: ke.h:125
#define KeReleaseSpinLockFromDpcLevel(SpinLock)
Definition: ke.h:135
#define STATUS_SUCCESS
Definition: shellext.h:65
#define STATUS_BUFFER_TOO_SMALL
Definition: shellext.h:69
DataType
Definition: simd.h:252
#define DPRINT
Definition: sndvol32.h:71
Definition: shell.h:41
PGET_SET_DEVICE_DATA SetBusData
Definition: iotypes.h:915
PTRANSLATE_BUS_ADDRESS TranslateBusAddress
Definition: iotypes.h:913
PGET_SET_DEVICE_DATA GetBusData
Definition: iotypes.h:916
PGET_DMA_ADAPTER GetDmaAdapter
Definition: iotypes.h:914
CM_PARTIAL_RESOURCE_LIST PartialResourceList
Definition: hwresource.cpp:160
union _CM_PARTIAL_RESOURCE_DESCRIPTOR::@393 u
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR::@393::@396 Interrupt
CM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptors[1]
Definition: hwresource.cpp:119
CM_FULL_RESOURCE_DESCRIPTOR List[1]
Definition: hwresource.cpp:165
PVOID DeviceExtension
Definition: env_spec_w32.h:418
PDEVICE_OBJECT Objects[1]
Definition: iotypes.h:2163
LIST_ENTRY DeviceListHead
Definition: pci.h:92
KSPIN_LOCK DeviceListLock
Definition: pci.h:96
struct _IO_STACK_LOCATION::@3978::@4007 ReadWriteConfig
struct _IO_STACK_LOCATION::@3978::@4015 StartDevice
union _IO_STACK_LOCATION::@1564 Parameters
struct _IO_STACK_LOCATION::@3978::@4003 QueryDeviceRelations
struct _IO_STACK_LOCATION::@3978::@4004 QueryInterface
struct _IO_STACK_LOCATION::@3978::@4010 QueryDeviceText
struct _IO_STACK_LOCATION::@3978::@4005 DeviceCapabilities
struct _IO_STACK_LOCATION::@3978::@4009 QueryId
Definition: typedefs.h:120
struct _LIST_ENTRY * Flink
Definition: typedefs.h:121
PCI_SLOT_NUMBER SlotNumber
Definition: pci.h:19
BOOLEAN EnableIoSpace
Definition: pci.h:25
BOOLEAN EnableMemorySpace
Definition: pci.h:23
PCI_COMMON_CONFIG PciConfig
Definition: pci.h:21
BOOLEAN EnableBusMaster
Definition: pci.h:27
ULONG BusNumber
Definition: pci.h:17
KSPIN_LOCK BusListLock
Definition: pci.h:108
LIST_ENTRY BusListHead
Definition: pci.h:106
union _PCI_SLOT_NUMBER::@4022 u
struct _PCI_SLOT_NUMBER::@4022::@4023 bits
PDEVICE_OBJECT Fdo
Definition: pci.h:61
UNICODE_STRING DeviceDescription
Definition: pci.h:73
UNICODE_STRING CompatibleIDs
Definition: pci.h:71
PPCI_DEVICE PciDevice
Definition: pci.h:63
UNICODE_STRING InstanceID
Definition: pci.h:67
UNICODE_STRING HardwareIDs
Definition: pci.h:69
UNICODE_STRING DeviceLocation
Definition: pci.h:75
UNICODE_STRING DeviceID
Definition: pci.h:65
#define MAXULONG
Definition: typedefs.h:251
uint32_t * PULONG
Definition: typedefs.h:59
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
#define NTAPI
Definition: typedefs.h:36
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
#define IN
Definition: typedefs.h:39
#define CONTAINING_RECORD(address, type, field)
Definition: typedefs.h:260
unsigned char * PUCHAR
Definition: typedefs.h:53
uint32_t ULONG
Definition: typedefs.h:59
uint64_t ULONGLONG
Definition: typedefs.h:67
#define OUT
Definition: typedefs.h:40
#define STATUS_INVALID_PARAMETER
Definition: udferr_usr.h:135
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
#define STATUS_INSUFFICIENT_RESOURCES
Definition: udferr_usr.h:158
_In_ PDEVICE_OBJECT DeviceObject
Definition: wdfdevice.h:2055
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_DEVICE_PROPERTY_DATA _In_ DEVPROPTYPE _In_ ULONG Size
Definition: wdfdevice.h:4533
_Must_inspect_result_ _In_ WDFDEVICE _In_ WDFSTRING String
Definition: wdfdevice.h:2433
_In_ WDFDEVICE _In_ PPNP_BUS_INFORMATION BusInformation
Definition: wdfdevice.h:3915
_Must_inspect_result_ _In_ WDFDEVICE _In_ LPCGUID _Out_ PINTERFACE Interface
Definition: wdffdo.h:465
_Must_inspect_result_ _In_ WDFQUEUE _In_opt_ WDFREQUEST _In_opt_ WDFFILEOBJECT _Inout_opt_ PWDF_REQUEST_PARAMETERS Parameters
Definition: wdfio.h:869
_Must_inspect_result_ _In_ PWDFDEVICE_INIT _In_ PCUNICODE_STRING DeviceDescription
Definition: wdfpdo.h:432
_Must_inspect_result_ _In_ PWDFDEVICE_INIT _In_ PCUNICODE_STRING DeviceID
Definition: wdfpdo.h:278
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
Definition: wdfresource.h:309
_Must_inspect_result_ _In_ WDFIORESLIST _In_ PIO_RESOURCE_DESCRIPTOR Descriptor
Definition: wdfresource.h:342
_Must_inspect_result_ _In_ WDFCMRESLIST List
Definition: wdfresource.h:550
#define DeviceCapabilities
Definition: wingdi.h:4449
_Must_inspect_result_ _In_ ULONG Flags
Definition: wsk.h:170
@ CmResourceShareDeviceExclusive
Definition: cmtypes.h:241
@ CmResourceShareShared
Definition: cmtypes.h:243
_Out_ PULONG NumberOfMapRegisters
Definition: halfuncs.h:209
_In_ ULONG _In_ PHYSICAL_ADDRESS BusAddress
Definition: iofuncs.h:2273
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG _Out_ PPHYSICAL_ADDRESS TranslatedAddress
Definition: iofuncs.h:2275
_In_ ULONG _In_ PHYSICAL_ADDRESS _Inout_ PULONG AddressSpace
Definition: iofuncs.h:2274
#define PCI_TYPE_64BIT
Definition: iotypes.h:4239
#define IRP_MN_CANCEL_STOP_DEVICE
@ TargetDeviceRelation
Definition: iotypes.h:2156
#define IRP_MN_QUERY_PNP_DEVICE_STATE
#define PCI_TYPE_32BIT
Definition: iotypes.h:4237
#define IRP_MN_EJECT
#define PCI_USE_PROGIF
Definition: iotypes.h:870
#define PCI_WHICHSPACE_CONFIG
Definition: iotypes.h:3644
#define PCI_ENABLE_BUS_MASTER
Definition: iotypes.h:3618
#define IO_NO_INCREMENT
Definition: iotypes.h:598
#define IRP_MN_QUERY_INTERFACE
#define PCI_TYPE0_ADDRESSES
Definition: iotypes.h:3500
#define IRP_MN_START_DEVICE
#define PCI_USE_VENDEV_IDS
Definition: iotypes.h:868
#define IRP_MN_DEVICE_USAGE_NOTIFICATION
#define IRP_MN_READ_CONFIG
#define PCI_ENABLE_IO_SPACE
Definition: iotypes.h:3616
#define IRP_MN_WRITE_CONFIG
#define IRP_MN_QUERY_RESOURCE_REQUIREMENTS
#define IRP_MN_QUERY_ID
#define PCI_ADDRESS_IO_SPACE
Definition: iotypes.h:4230
#define PCI_CONFIGURATION_TYPE(PciData)
Definition: iotypes.h:3609
#define IRP_MN_REMOVE_DEVICE
#define PCI_USE_CLASS_SUBCLASS
Definition: iotypes.h:869
#define PCI_ENABLE_MEMORY_SPACE
Definition: iotypes.h:3617
#define PCI_TYPE1_ADDRESSES
Definition: iotypes.h:3501
#define IRP_MN_FILTER_RESOURCE_REQUIREMENTS
struct _PCI_DEVICE_PRESENT_INTERFACE * PPCI_DEVICE_PRESENT_INTERFACE
#define PCI_BRIDGE_TYPE
Definition: iotypes.h:3606
#define PCI_TYPE_20BIT
Definition: iotypes.h:4238
#define IRP_MN_QUERY_DEVICE_RELATIONS
struct _BUS_INTERFACE_STANDARD * PBUS_INTERFACE_STANDARD
#define PCI_COMMON_HDR_LENGTH
Definition: iotypes.h:3594
#define IRP_MN_QUERY_STOP_DEVICE
#define PCI_CLASS_BRIDGE_DEV
Definition: iotypes.h:4109
#define IRP_MN_QUERY_DEVICE_TEXT
#define IRP_MN_QUERY_CAPABILITIES
#define IRP_MN_QUERY_RESOURCES
#define IRP_MN_SET_POWER
#define PCI_USE_REVISION
Definition: iotypes.h:867
* PDEVICE_CAPABILITIES
Definition: iotypes.h:965
_In_ USHORT _In_ UCHAR _In_ USHORT _In_ USHORT SubSystemID
Definition: iotypes.h:895
#define IRP_MN_CANCEL_REMOVE_DEVICE
#define PCI_USE_LOCAL_DEVICE
Definition: iotypes.h:872
#define PCI_ADDRESS_MEMORY_PREFETCHABLE
Definition: iotypes.h:4232
#define IRP_MN_STOP_DEVICE
#define IRP_MN_SET_LOCK
@ DeviceTextLocationInformation
Definition: iotypes.h:2946
@ DeviceTextDescription
Definition: iotypes.h:2945
_In_ USHORT _In_ UCHAR RevisionID
Definition: iotypes.h:893
#define PCI_ADDRESS_MEMORY_TYPE_MASK
Definition: iotypes.h:4231
@ BusQueryCompatibleIDs
Definition: iotypes.h:2938
@ BusQueryDeviceSerialNumber
Definition: iotypes.h:2940
@ BusQueryInstanceID
Definition: iotypes.h:2939
@ BusQueryDeviceID
Definition: iotypes.h:2936
@ BusQueryHardwareIDs
Definition: iotypes.h:2937
#define PCI_USE_LOCAL_BUS
Definition: iotypes.h:871
#define PCI_USE_SUBSYSTEM_IDS
Definition: iotypes.h:866
#define PCI_DEVICE_TYPE
Definition: iotypes.h:3605
_In_ USHORT _In_ UCHAR _In_ USHORT SubVendorID
Definition: iotypes.h:894
#define IRP_MN_QUERY_POWER
#define PCI_CARDBUS_BRIDGE_TYPE
Definition: iotypes.h:3607
#define IRP_MN_QUERY_BUS_INFORMATION
#define IRP_MN_QUERY_REMOVE_DEVICE
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:778
#define ObReferenceObject
Definition: obfuncs.h:204
unsigned char UCHAR
Definition: xmlstorage.h:181