pic.c File Reference

#include <hal.h>
#include <debug.h>

Include dependency graph for pic.c:

Go to the source code of this file.

Macros
#define	NDEBUG

Functions
VOID NTAPI	HalpEndSoftwareInterrupt (IN KIRQL OldIrql, IN PKTRAP_FRAME TrapFrame)
	HalpDelayedHardwareInterrupt (0)
	HalpDelayedHardwareInterrupt (1)
	HalpDelayedHardwareInterrupt (2)
	HalpDelayedHardwareInterrupt (3)
	HalpDelayedHardwareInterrupt (4)
	HalpDelayedHardwareInterrupt (5)
	HalpDelayedHardwareInterrupt (6)
	HalpDelayedHardwareInterrupt (7)
	HalpDelayedHardwareInterrupt (8)
	HalpDelayedHardwareInterrupt (9)
	HalpDelayedHardwareInterrupt (10)
	HalpDelayedHardwareInterrupt (11)
	HalpDelayedHardwareInterrupt (12)
	HalpDelayedHardwareInterrupt (13)
	HalpDelayedHardwareInterrupt (14)
	HalpDelayedHardwareInterrupt (15)
VOID NTAPI	HalpInitializePICs (IN BOOLEAN EnableInterrupts)
UCHAR FASTCALL	HalpIrqToVector (UCHAR Irq)
UCHAR FASTCALL	HalpVectorToIrq (UCHAR Vector)
KIRQL FASTCALL	HalpVectorToIrql (UCHAR Vector)
KIRQL NTAPI	KeGetCurrentIrql (VOID)
KIRQL NTAPI	KeRaiseIrqlToDpcLevel (VOID)
KIRQL NTAPI	KeRaiseIrqlToSynchLevel (VOID)
KIRQL FASTCALL	KfRaiseIrql (IN KIRQL NewIrql)
VOID FASTCALL	KfLowerIrql (IN KIRQL OldIrql)
VOID FASTCALL	HalRequestSoftwareInterrupt (IN KIRQL Irql)
VOID FASTCALL	HalClearSoftwareInterrupt (IN KIRQL Irql)
PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY FASTCALL	HalpEndSoftwareInterrupt2 (IN KIRQL OldIrql, IN PKTRAP_FRAME TrapFrame)
FORCEINLINE BOOLEAN	_HalpDismissIrqGeneric (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrqGeneric (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrq15 (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrq13 (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrq07 (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
FORCEINLINE BOOLEAN	_HalpDismissIrqLevel (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrqLevel (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrq15Level (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrq13Level (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
BOOLEAN NTAPI	HalpDismissIrq07Level (IN KIRQL Irql, IN ULONG Irq, OUT PKIRQL OldIrql)
PHAL_SW_INTERRUPT_HANDLER __cdecl	HalpHardwareInterruptLevel2 (VOID)
BOOLEAN NTAPI	HalEnableSystemInterrupt (IN ULONG Vector, IN KIRQL Irql, IN KINTERRUPT_MODE InterruptMode)
VOID NTAPI	HalDisableSystemInterrupt (IN ULONG Vector, IN KIRQL Irql)
BOOLEAN NTAPI	HalBeginSystemInterrupt (IN KIRQL Irql, IN ULONG Vector, OUT PKIRQL OldIrql)
PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY FASTCALL	HalEndSystemInterrupt2 (IN KIRQL OldIrql, IN PKTRAP_FRAME TrapFrame)
FORCEINLINE DECLSPEC_NORETURN VOID	_HalpApcInterruptHandler (IN PKTRAP_FRAME TrapFrame)
DECLSPEC_NORETURN VOID FASTCALL	HalpApcInterrupt2ndEntry (IN PKTRAP_FRAME TrapFrame)
DECLSPEC_NORETURN VOID FASTCALL	HalpApcInterruptHandler (IN PKTRAP_FRAME TrapFrame)
FORCEINLINE KIRQL	_HalpDispatchInterruptHandler (VOID)
DECLSPEC_NORETURN VOID FASTCALL	HalpDispatchInterrupt2ndEntry (IN PKTRAP_FRAME TrapFrame)
PHAL_SW_INTERRUPT_HANDLER __cdecl	HalpDispatchInterrupt2 (VOID)
ULONG NTAPI	HalpGetRootInterruptVector (IN ULONG BusInterruptLevel, IN ULONG BusInterruptVector, OUT PKIRQL Irql, OUT PKAFFINITY Affinity)

Variables
PHAL_DISMISS_INTERRUPT	HalpSpecialDismissTable [16]
PHAL_DISMISS_INTERRUPT	HalpSpecialDismissLevelTable [16]
ULONG	KiI8259MaskTable [32]
ULONG	FindHigherIrqlMask [32]
KIRQL	SWInterruptLookUpTable [8]
PHAL_SW_INTERRUPT_HANDLER	SWInterruptHandlerTable [20]
PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY	SWInterruptHandlerTable2 [3]
LONG	HalpEisaELCR

Macro Definition Documentation

NDEBUG

#define NDEBUG

Definition at line 12 of file pic.c.

Function Documentation

_HalpApcInterruptHandler()

FORCEINLINE DECLSPEC_NORETURN VOID _HalpApcInterruptHandler

(

IN PKTRAP_FRAME

TrapFrame

)

Definition at line 1104 of file pic.c.

{
    KIRQL CurrentIrql;
    PKPCR Pcr = KeGetPcr();

    /* Save the current IRQL and update it */
    CurrentIrql = Pcr->Irql;
    Pcr->Irql = APC_LEVEL;

    /* Remove DPC from IRR */
    Pcr->IRR &= ~(1 << APC_LEVEL);

    /* Enable interrupts and call the kernel's APC interrupt handler */
    _enable();
    KiDeliverApc(((KiUserTrap(TrapFrame)) || (TrapFrame->EFlags & EFLAGS_V86_MASK)) ?
                UserMode : KernelMode,
                NULL,
                TrapFrame);

    /* Disable interrupts and end the interrupt */
    _disable();
    HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame);

    /* Exit the interrupt */
    KiEoiHelper(TrapFrame);
}

Referenced by HalpApcInterrupt2ndEntry(), and HalpApcInterruptHandler().

_HalpDismissIrqGeneric()

FORCEINLINE BOOLEAN _HalpDismissIrqGeneric	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 553 of file pic.c.

{
    PIC_MASK Mask;
    KIRQL CurrentIrql;
    I8259_OCW2 Ocw2;
    PKPCR Pcr = KeGetPcr();

    /* First save current IRQL and compare it to the requested one */
    CurrentIrql = Pcr->Irql;

    /* Check if this interrupt is really allowed to happen */
    if (Irql > CurrentIrql)
    {
        /* Set the new IRQL and return the current one */
        Pcr->Irql = Irql;
        *OldIrql = CurrentIrql;

        /* Prepare OCW2 for EOI */
        Ocw2.Bits = 0;
        Ocw2.EoiMode = SpecificEoi;

        /* Check which PIC needs the EOI */
        if (Irq >= 8)
        {
#if defined(SARCH_PC98)
            I8259_OCW3 Ocw3;
            I8259_ISR Isr;

            /* Send the EOI for the IRQ */
            __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));

            /* Request the ISR */
            Ocw3.Bits = 0;
            Ocw3.Sbo = 1;
            Ocw3.ReadRequest = ReadIsr;
            __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);

            /* Read the ISR */
            Isr.Bits = __inbyte(PIC2_CONTROL_PORT);

            /* Check if the interrupt serviced was the only one from the slave PIC */
            if (Isr.Bits == 0)
            {
                /* If ISR is empty, send the EOI for cascade IRQ on the master PIC */
                __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
            }
#else
            /* Send the EOI for the IRQ */
            __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));

            /* Send the EOI for cascade IRQ on the master PIC */
            __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
#endif
        }
        else
        {
            /* Send the EOI for the IRQ */
            __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | (Irq & 0xFF));
        }

        /* Enable interrupts and return success */
        _enable();
        return TRUE;
    }

    /* Update the IRR so that we deliver this interrupt when the IRQL is proper */
    Pcr->IRR |= (1 << (Irq + 4));

    /* Set new PIC mask to real IRQL level, since the optimization is lost now */
    Mask.Both = (KiI8259MaskTable[CurrentIrql] | Pcr->IDR) & 0xFFFF;
    __outbyte(PIC1_DATA_PORT, Mask.Master);
    __outbyte(PIC2_DATA_PORT, Mask.Slave);

    /* Now lie and say this was spurious */
    return FALSE;
}

Referenced by HalpDismissIrq07(), HalpDismissIrq13(), HalpDismissIrq15(), and HalpDismissIrqGeneric().

_HalpDismissIrqLevel()

FORCEINLINE BOOLEAN _HalpDismissIrqLevel	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 735 of file pic.c.

{
    PIC_MASK Mask;
    KIRQL CurrentIrql;
    I8259_OCW2 Ocw2;
    PKPCR Pcr = KeGetPcr();

    /* Update the PIC */
    Mask.Both = (KiI8259MaskTable[Irql] | Pcr->IDR) & 0xFFFF;
    __outbyte(PIC1_DATA_PORT, Mask.Master);
    __outbyte(PIC2_DATA_PORT, Mask.Slave);

    /* Update the IRR so that we clear this interrupt when the IRQL is proper */
    Pcr->IRR |= (1 << (Irq + 4));

    /* Save current IRQL */
    CurrentIrql = Pcr->Irql;

    /* Prepare OCW2 for EOI */
    Ocw2.Bits = 0;
    Ocw2.EoiMode = SpecificEoi;

    /* Check which PIC needs the EOI */
    if (Irq >= 8)
    {
#if defined(SARCH_PC98)
        I8259_OCW3 Ocw3;
        I8259_ISR Isr;

        /* Send the EOI for the IRQ */
        __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));

        /* Request the ISR */
        Ocw3.Bits = 0;
        Ocw3.Sbo = 1;
        Ocw3.ReadRequest = ReadIsr;
        __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);

        /* Read the ISR */
        Isr.Bits = __inbyte(PIC2_CONTROL_PORT);

        /* Check if the interrupt serviced was the only one from the slave PIC */
        if (Isr.Bits == 0)
        {
            /* If ISR is empty, send the EOI for cascade IRQ on the master PIC */
            __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
        }
#else
        /* Send the EOI for the IRQ */
        __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));

        /* Send the EOI for cascade IRQ on the master PIC */
        __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);
#endif
    }
    else
    {
        /* Send the EOI for the IRQ */
        __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | (Irq & 0xFF));
    }

    /* Check if this interrupt should be allowed to happen */
    if (Irql > CurrentIrql)
    {
        /* Set the new IRQL and return the current one */
        Pcr->Irql = Irql;
        *OldIrql = CurrentIrql;

        /* Enable interrupts and return success */
        _enable();
        return TRUE;
    }

    /* Now lie and say this was spurious */
    return FALSE;
}

Referenced by HalpDismissIrq07Level(), HalpDismissIrq13Level(), HalpDismissIrq15Level(), and HalpDismissIrqLevel().

_HalpDispatchInterruptHandler()

FORCEINLINE KIRQL _HalpDispatchInterruptHandler

(

VOID

)

Definition at line 1159 of file pic.c.

{
    KIRQL CurrentIrql;
    PKPCR Pcr = KeGetPcr();

    /* Save the current IRQL and update it */
    CurrentIrql = Pcr->Irql;
    Pcr->Irql = DISPATCH_LEVEL;

    /* Remove DPC from IRR */
    Pcr->IRR &= ~(1 << DISPATCH_LEVEL);

    /* Enable interrupts and call the kernel's DPC interrupt handler */
    _enable();
    KiDispatchInterrupt();
    _disable();

    /* Return IRQL */
    return CurrentIrql;
}

Referenced by HalpDispatchInterrupt2(), and HalpDispatchInterrupt2ndEntry().

HalBeginSystemInterrupt()

BOOLEAN NTAPI HalBeginSystemInterrupt	(	IN KIRQL	Irql,
		IN ULONG	Vector,
		OUT PKIRQL	OldIrql
	)

Definition at line 1025 of file pic.c.

{
    ULONG Irq;

    /* Get the IRQ and call the proper routine to handle it */
    Irq = Vector - PRIMARY_VECTOR_BASE;
    return HalpSpecialDismissTable[Irq](Irql, Irq, OldIrql);
}

HalClearSoftwareInterrupt()

VOID FASTCALL HalClearSoftwareInterrupt

(

IN KIRQL

Irql

)

Definition at line 489 of file pic.c.

{
    /* Mask out the requested bit */
    KeGetPcr()->IRR &= ~(1 << Irql);
}

HalDisableSystemInterrupt()

VOID NTAPI HalDisableSystemInterrupt	(	IN ULONG	Vector,
		IN KIRQL	Irql
	)

Definition at line 990 of file pic.c.

{
    ULONG IrqMask;
    PIC_MASK PicMask;

    /* Compute new combined IRQ mask */
    IrqMask = 1 << (Vector - PRIMARY_VECTOR_BASE);

    /* Disable interrupts */
    _disable();

    /* Update software IDR */
    KeGetPcr()->IDR |= IrqMask;

    /* Read current interrupt mask */
    PicMask.Master = __inbyte(PIC1_DATA_PORT);
    PicMask.Slave = __inbyte(PIC2_DATA_PORT);

    /* Add the new disabled interrupt */
    PicMask.Both |= IrqMask;

    /* Write new interrupt mask */
    __outbyte(PIC1_DATA_PORT, PicMask.Master);
    __outbyte(PIC2_DATA_PORT, PicMask.Slave);

    /* Bring interrupts back */
    _enable();
}

HalEnableSystemInterrupt()

BOOLEAN NTAPI HalEnableSystemInterrupt	(	IN ULONG	Vector,
		IN KIRQL	Irql,
		IN KINTERRUPT_MODE	InterruptMode
	)

Definition at line 947 of file pic.c.

{
    ULONG Irq;
    PKPCR Pcr = KeGetPcr();
    PIC_MASK PicMask;

    /* Validate the IRQ */
    Irq = Vector - PRIMARY_VECTOR_BASE;
    if (Irq >= CLOCK2_LEVEL) return FALSE;

    /* Check for level interrupt */
    if (InterruptMode == LevelSensitive)
    {
        /* Switch handler to level */
        SWInterruptHandlerTable[Irq + 4] = HalpHardwareInterruptLevel;

        /* Switch dismiss to level */
        HalpSpecialDismissTable[Irq] = HalpSpecialDismissLevelTable[Irq];
    }

    /* Disable interrupts */
    _disable();

    /* Update software IDR */
    Pcr->IDR &= ~(1 << Irq);

    /* Set new PIC mask */
    PicMask.Both = (KiI8259MaskTable[Pcr->Irql] | Pcr->IDR) & 0xFFFF;
    __outbyte(PIC1_DATA_PORT, PicMask.Master);
    __outbyte(PIC2_DATA_PORT, PicMask.Slave);

    /* Enable interrupts and exit */
    _enable();
    return TRUE;
}

HalEndSystemInterrupt2()

PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY FASTCALL HalEndSystemInterrupt2	(	IN KIRQL	OldIrql,
		IN PKTRAP_FRAME	TrapFrame
	)

Definition at line 1041 of file pic.c.

{
    ULONG PendingIrql, PendingIrqlMask, PendingIrqMask;
    PKPCR Pcr = KeGetPcr();
    PIC_MASK Mask;

    /* Set old IRQL */
    Pcr->Irql = OldIrql;

    /* Check for pending software interrupts and compare with current IRQL */
    PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
    if (PendingIrqlMask)
    {
        /* Check for in-service delayed interrupt */
        if (Pcr->IrrActive & 0xFFFFFFF0) return NULL;

        /* Loop checking for pending interrupts */
        while (TRUE)
        {
            /* Check if pending IRQL affects hardware state */
            BitScanReverse(&PendingIrql, PendingIrqlMask);
            if (PendingIrql > DISPATCH_LEVEL)
            {
                /* Set new PIC mask */
                Mask.Both = Pcr->IDR & 0xFFFF;
                __outbyte(PIC1_DATA_PORT, Mask.Master);
                __outbyte(PIC2_DATA_PORT, Mask.Slave);

                /* Now check if this specific interrupt is already in-service */
                PendingIrqMask = (1 << PendingIrql);
                if (Pcr->IrrActive & PendingIrqMask) return NULL;

                /* Set active bit otherwise, and clear it from IRR */
                Pcr->IrrActive |= PendingIrqMask;
                Pcr->IRR ^= PendingIrqMask;

                /* Handle delayed hardware interrupt */
                SWInterruptHandlerTable[PendingIrql]();

                /* Handling complete */
                Pcr->IrrActive ^= PendingIrqMask;

                /* Check if there's still interrupts pending */
                PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
                if (!PendingIrqlMask) break;
            }
            else
            {
                /* Now handle pending software interrupt */
                return SWInterruptHandlerTable2[PendingIrql];
            }
        }
    }

    return NULL;
}

HalpApcInterrupt2ndEntry()

DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry

(

IN PKTRAP_FRAME

TrapFrame

)

Definition at line 1134 of file pic.c.

{
    /* Do the work */
    _HalpApcInterruptHandler(TrapFrame);
}

HalpApcInterruptHandler()

DECLSPEC_NORETURN VOID FASTCALL HalpApcInterruptHandler

(

IN PKTRAP_FRAME

TrapFrame

)

Definition at line 1143 of file pic.c.

{
    /* Set up a fake INT Stack */
    TrapFrame->EFlags = __readeflags();
    TrapFrame->SegCs = KGDT_R0_CODE;
    TrapFrame->Eip = TrapFrame->Eax;

    /* Build the trap frame */
    KiEnterInterruptTrap(TrapFrame);

    /* Do the work */
    _HalpApcInterruptHandler(TrapFrame);
}

HalpDelayedHardwareInterrupt() [1/16]

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HalpDismissIrq07()

BOOLEAN NTAPI HalpDismissIrq07	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 708 of file pic.c.

{
    I8259_OCW3 Ocw3;
    I8259_ISR Isr;

    /* Request the ISR */
    Ocw3.Bits = 0;
    Ocw3.Sbo = 1;
    Ocw3.ReadRequest = ReadIsr;
    __outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);

    /* Read the ISR */
    Isr.Bits = __inbyte(PIC1_CONTROL_PORT);

    /* Is IRQ 7 really active? If it isn't, this is spurious so fail */
    if (Isr.Irq7 == FALSE) return FALSE;

    /* Do normal interrupt dismiss */
    return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
}

HalpDismissIrq07Level()

BOOLEAN NTAPI HalpDismissIrq07Level	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 890 of file pic.c.

{
    I8259_OCW3 Ocw3;
    I8259_ISR Isr;

    /* Request the ISR */
    Ocw3.Bits = 0;
    Ocw3.Sbo = 1;
    Ocw3.ReadRequest = ReadIsr;
    __outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);

    /* Read the ISR */
    Isr.Bits = __inbyte(PIC1_CONTROL_PORT);

    /* Is IRQ 7 really active? If it isn't, this is spurious so fail */
    if (Isr.Irq7 == FALSE) return FALSE;

    /* Do normal interrupt dismiss */
    return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
}

HalpDismissIrq13()

BOOLEAN NTAPI HalpDismissIrq13	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 679 of file pic.c.

{
    /* Clear the FPU busy latch */
    __outbyte(0xF0, 0);

    /* Do normal interrupt dismiss */
    return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
}

HalpDismissIrq13Level()

BOOLEAN NTAPI HalpDismissIrq13Level	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 861 of file pic.c.

{
    /* Clear the FPU busy latch */
    __outbyte(0xF0, 0);

    /* Do normal interrupt dismiss */
    return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
}

HalpDismissIrq15()

BOOLEAN NTAPI HalpDismissIrq15	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 644 of file pic.c.

{
    I8259_OCW3 Ocw3;
    I8259_OCW2 Ocw2;
    I8259_ISR Isr;

    /* Request the ISR */
    Ocw3.Bits = 0;
    Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
    Ocw3.ReadRequest = ReadIsr;
    __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);

    /* Read the ISR */
    Isr.Bits = __inbyte(PIC2_CONTROL_PORT);

    /* Is IRQ15 really active (this is IR7) */
    if (Isr.Irq7 == FALSE)
    {
        /* It isn't, so we have to EOI cascade IRQ */
        Ocw2.Bits = 0;
        Ocw2.EoiMode = SpecificEoi;
        __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);

        /* And now fail since this was spurious */
        return FALSE;
    }

    /* Do normal interrupt dismiss */
    return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
}

HalpDismissIrq15Level()

BOOLEAN NTAPI HalpDismissIrq15Level	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 826 of file pic.c.

{
    I8259_OCW3 Ocw3;
    I8259_OCW2 Ocw2;
    I8259_ISR Isr;

    /* Request the ISR */
    Ocw3.Bits = 0;
    Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
    Ocw3.ReadRequest = ReadIsr;
    __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);

    /* Read the ISR */
    Isr.Bits = __inbyte(PIC2_CONTROL_PORT);

    /* Is IRQ15 really active (this is IR7) */
    if (Isr.Irq7 == FALSE)
    {
        /* It isn't, so we have to EOI cascade IRQ */
        Ocw2.Bits = 0;
        Ocw2.EoiMode = SpecificEoi;
        __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | PIC_CASCADE_IRQ);

        /* And now fail since this was spurious */
        return FALSE;
    }

    /* Do normal interrupt dismiss */
    return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
}

HalpDismissIrqGeneric()

BOOLEAN NTAPI HalpDismissIrqGeneric	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 634 of file pic.c.

{
    /* Run the inline code */
    return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
}

HalpDismissIrqLevel()

BOOLEAN NTAPI HalpDismissIrqLevel	(	IN KIRQL	Irql,
		IN ULONG	Irq,
		OUT PKIRQL	OldIrql
	)

Definition at line 816 of file pic.c.

{
    /* Run the inline code */
    return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
}

HalpDispatchInterrupt2()

PHAL_SW_INTERRUPT_HANDLER __cdecl HalpDispatchInterrupt2

(

VOID

)

Definition at line 1199 of file pic.c.

{
    ULONG PendingIrqlMask, PendingIrql;
    KIRQL OldIrql;
    PIC_MASK Mask;
    PKPCR Pcr = KeGetPcr();

    /* Do the work */
    OldIrql = _HalpDispatchInterruptHandler();

    /* Restore IRQL */
    Pcr->Irql = OldIrql;

    /* Check for pending software interrupts and compare with current IRQL */
    PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
    if (PendingIrqlMask)
    {
        /* Check if pending IRQL affects hardware state */
        BitScanReverse(&PendingIrql, PendingIrqlMask);
        if (PendingIrql > DISPATCH_LEVEL)
        {
            /* Set new PIC mask */
            Mask.Both = Pcr->IDR & 0xFFFF;
            __outbyte(PIC1_DATA_PORT, Mask.Master);
            __outbyte(PIC2_DATA_PORT, Mask.Slave);

            /* Clear IRR bit */
            Pcr->IRR ^= (1 << PendingIrql);
        }

        /* Now handle pending interrupt */
        return SWInterruptHandlerTable[PendingIrql];
    }

    return NULL;
}

HalpDispatchInterrupt2ndEntry()

DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry

(

IN PKTRAP_FRAME

TrapFrame

)

Definition at line 1183 of file pic.c.

{
    KIRQL CurrentIrql;

    /* Do the work */
    CurrentIrql = _HalpDispatchInterruptHandler();

    /* End the interrupt */
    HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame);

    /* Exit the interrupt */
    KiEoiHelper(TrapFrame);
}

HalpEndSoftwareInterrupt()

VOID NTAPI HalpEndSoftwareInterrupt	(	IN KIRQL	OldIrql,
		IN PKTRAP_FRAME	TrapFrame
	)

Referenced by _HalpApcInterruptHandler(), and HalpDispatchInterrupt2ndEntry().

HalpEndSoftwareInterrupt2()

PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY FASTCALL HalpEndSoftwareInterrupt2	(	IN KIRQL	OldIrql,
		IN PKTRAP_FRAME	TrapFrame
	)

Definition at line 497 of file pic.c.

{
    ULONG PendingIrql, PendingIrqlMask, PendingIrqMask;
    PKPCR Pcr = KeGetPcr();
    PIC_MASK Mask;

    UNREFERENCED_PARAMETER(TrapFrame);

    /* Set old IRQL */
    Pcr->Irql = OldIrql;

    /* Loop checking for pending interrupts */
    while (TRUE)
    {
        /* Check for pending software interrupts and compare with current IRQL */
        PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
        if (!PendingIrqlMask) return NULL;

        /* Check for in-service delayed interrupt */
        if (Pcr->IrrActive & 0xFFFFFFF0) return NULL;

        /* Check if pending IRQL affects hardware state */
        BitScanReverse(&PendingIrql, PendingIrqlMask);
        if (PendingIrql > DISPATCH_LEVEL)
        {
            /* Set new PIC mask */
            Mask.Both = Pcr->IDR & 0xFFFF;
            __outbyte(PIC1_DATA_PORT, Mask.Master);
            __outbyte(PIC2_DATA_PORT, Mask.Slave);

            /* Set active bit otherwise, and clear it from IRR */
            PendingIrqMask = (1 << PendingIrql);
            Pcr->IrrActive |= PendingIrqMask;
            Pcr->IRR ^= PendingIrqMask;

            /* Handle delayed hardware interrupt */
            SWInterruptHandlerTable[PendingIrql]();

            /* Handling complete */
            Pcr->IrrActive ^= PendingIrqMask;
        }
        else
        {
            /* No need to loop checking for hardware interrupts */
            return SWInterruptHandlerTable2[PendingIrql];
        }
    }

    return NULL;
}

HalpGetRootInterruptVector()

ULONG NTAPI HalpGetRootInterruptVector	(	IN ULONG	BusInterruptLevel,
		IN ULONG	BusInterruptVector,
		OUT PKIRQL	Irql,
		OUT PKAFFINITY	Affinity
	)

Definition at line 1238 of file pic.c.

{
    UCHAR SystemVector;

    /* Validate the IRQ */
    if (BusInterruptLevel > 23)
    {
        /* Invalid vector */
        DPRINT1("IRQ %lx is too high!\n", BusInterruptLevel);
        return 0;
    }

    /* Get the system vector */
    SystemVector = HalpIrqToVector((UCHAR)BusInterruptLevel);

    /* Return the IRQL and affinity */
    *Irql = HalpVectorToIrql(SystemVector);
    *Affinity = HalpDefaultInterruptAffinity;
    ASSERT(HalpDefaultInterruptAffinity);

    /* Return the vector */
    return SystemVector;
}

HalpHardwareInterruptLevel2()

PHAL_SW_INTERRUPT_HANDLER __cdecl HalpHardwareInterruptLevel2

(

VOID

)

Definition at line 915 of file pic.c.

{
    PKPCR Pcr = KeGetPcr();
    ULONG PendingIrqlMask, PendingIrql;

    /* Check for pending software interrupts and compare with current IRQL */
    PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
    if (PendingIrqlMask)
    {
        /* Check for in-service delayed interrupt */
        if (Pcr->IrrActive & 0xFFFFFFF0) return NULL;

        /* Check if pending IRQL affects hardware state */
        BitScanReverse(&PendingIrql, PendingIrqlMask);

        /* Clear IRR bit */
        Pcr->IRR ^= (1 << PendingIrql);

        /* Now handle pending interrupt */
        return SWInterruptHandlerTable[PendingIrql];
    }

    return NULL;
}

HalpInitializePICs()

VOID NTAPI HalpInitializePICs

(

IN BOOLEAN

EnableInterrupts

)

Definition at line 220 of file pic.c.

{
    ULONG EFlags;
    EISA_ELCR Elcr;
    ULONG i, j;
    BOOLEAN ElcrFound;

    /* Save EFlags and disable interrupts */
    EFlags = __readeflags();
    _disable();

    /* Initialize and mask the PIC */
    HalpInitializeLegacyPICs();

    /* Read EISA Edge/Level Register for master and slave */
    Elcr.Bits = (__inbyte(EISA_ELCR_SLAVE) << 8) | __inbyte(EISA_ELCR_MASTER);

#if defined(SARCH_PC98)
    /* Force defaults when ELCR is not supported */
    if (Elcr.Bits == 0xFFFF)
    {
        Elcr.Master.Irq0Level = 0;
        Elcr.Master.Irq1Level = 0;
        Elcr.Master.Irq7Level = 0;
        Elcr.Slave.Irq8Level = 0;
    }
    ElcrFound = TRUE;
#else
    /* IRQs 0, 1, 2, 8, and 13 are system-reserved and must be edge */
    ElcrFound = (!(Elcr.Master.Irq0Level) && !(Elcr.Master.Irq1Level) && !(Elcr.Master.Irq2Level) &&
                 !(Elcr.Slave.Irq8Level) && !(Elcr.Slave.Irq13Level));
#endif

    if (ElcrFound)
    {
        /* ELCR is as it's supposed to be, save it */
        HalpEisaELCR = Elcr.Bits;

        /* Scan for level interrupts */
        for (i = 1, j = 0; j < 16; i <<= 1, j++)
        {
            if (HalpEisaELCR & i)
            {
                /* Switch handler to level */
                SWInterruptHandlerTable[j + 4] = HalpHardwareInterruptLevel;

                /* Switch dismiss to level */
                HalpSpecialDismissTable[j] = HalpSpecialDismissLevelTable[j];
            }
        }
    }

    /* Report cascade IRQ usage */
    HalpRegisterVector(IDT_INTERNAL,
                       PRIMARY_VECTOR_BASE + PIC_CASCADE_IRQ,
                       PRIMARY_VECTOR_BASE + PIC_CASCADE_IRQ,
                       HIGH_LEVEL);

    /* Restore interrupt state */
    if (EnableInterrupts) EFlags |= EFLAGS_INTERRUPT_MASK;
    __writeeflags(EFlags);
}

HalpIrqToVector()

UCHAR FASTCALL HalpIrqToVector

(

UCHAR

Irq

)

Definition at line 285 of file pic.c.

{
    return (PRIMARY_VECTOR_BASE + Irq);
}

Referenced by HalpGetRootInterruptVector().

HalpVectorToIrq()

UCHAR FASTCALL HalpVectorToIrq

(

UCHAR

Vector

)

Definition at line 292 of file pic.c.

{
    return (Vector - PRIMARY_VECTOR_BASE);
}

HalpVectorToIrql()

KIRQL FASTCALL HalpVectorToIrql

(

UCHAR

Vector

)

Definition at line 299 of file pic.c.

{
    return (PROFILE_LEVEL - (Vector - PRIMARY_VECTOR_BASE));
}

Referenced by HalpGetRootInterruptVector().

HalRequestSoftwareInterrupt()

VOID FASTCALL HalRequestSoftwareInterrupt

(

IN KIRQL

Irql

)

Definition at line 463 of file pic.c.

{
    ULONG EFlags;
    PKPCR Pcr = KeGetPcr();
    KIRQL PendingIrql;

    /* Save EFlags and disable interrupts */
    EFlags = __readeflags();
    _disable();

    /* Mask out the requested bit */
    Pcr->IRR |= (1 << Irql);

    /* Check for pending software interrupts and compare with current IRQL */
    PendingIrql = SWInterruptLookUpTable[Pcr->IRR & 3];
    if (PendingIrql > Pcr->Irql) SWInterruptHandlerTable[PendingIrql]();

    /* Restore interrupt state */
    __writeeflags(EFlags);
}

KeGetCurrentIrql()

KIRQL NTAPI KeGetCurrentIrql

(

VOID

)

Definition at line 311 of file pic.c.

{
    /* Return the IRQL */
    return KeGetPcr()->Irql;
}

KeRaiseIrqlToDpcLevel()

KIRQL NTAPI KeRaiseIrqlToDpcLevel

(

VOID

)

Definition at line 322 of file pic.c.

{
    PKPCR Pcr = KeGetPcr();
    KIRQL CurrentIrql;

    /* Save and update IRQL */
    CurrentIrql = Pcr->Irql;
    Pcr->Irql = DISPATCH_LEVEL;

#if DBG
    /* Validate correct raise */
    if (CurrentIrql > DISPATCH_LEVEL) KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
#endif

    /* Return the previous value */
    return CurrentIrql;
}

KeRaiseIrqlToSynchLevel()

KIRQL NTAPI KeRaiseIrqlToSynchLevel

(

VOID

)

Definition at line 345 of file pic.c.

{
    PKPCR Pcr = KeGetPcr();
    KIRQL CurrentIrql;

    /* Save and update IRQL */
    CurrentIrql = Pcr->Irql;
    Pcr->Irql = SYNCH_LEVEL;

#if DBG
    /* Validate correct raise */
    if (CurrentIrql > SYNCH_LEVEL)
    {
        /* Crash system */
        KeBugCheckEx(IRQL_NOT_GREATER_OR_EQUAL,
                     CurrentIrql,
                     SYNCH_LEVEL,
                     0,
                     1);
    }
#endif

    /* Return the previous value */
    return CurrentIrql;
}

KfLowerIrql()

VOID FASTCALL KfLowerIrql

(

IN KIRQL

OldIrql

)

Definition at line 407 of file pic.c.

{
    ULONG EFlags;
    ULONG PendingIrql, PendingIrqlMask;
    PKPCR Pcr = KeGetPcr();
    PIC_MASK Mask;

#if DBG
    /* Validate correct lower */
    if (OldIrql > Pcr->Irql)
    {
        /* Crash system */
        Pcr->Irql = HIGH_LEVEL;
        KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
    }
#endif

    /* Save EFlags and disable interrupts */
    EFlags = __readeflags();
    _disable();

    /* Set old IRQL */
    Pcr->Irql = OldIrql;

    /* Check for pending software interrupts and compare with current IRQL */
    PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
    if (PendingIrqlMask)
    {
        /* Check if pending IRQL affects hardware state */
        BitScanReverse(&PendingIrql, PendingIrqlMask);
        if (PendingIrql > DISPATCH_LEVEL)
        {
            /* Set new PIC mask */
            Mask.Both = Pcr->IDR & 0xFFFF;
            __outbyte(PIC1_DATA_PORT, Mask.Master);
            __outbyte(PIC2_DATA_PORT, Mask.Slave);

            /* Clear IRR bit */
            Pcr->IRR ^= (1 << PendingIrql);
        }

        /* Now handle pending interrupt */
        SWInterruptHandlerTable[PendingIrql]();
    }

    /* Restore interrupt state */
    __writeeflags(EFlags);
}

Referenced by KiCheckForApcDelivery().

KfRaiseIrql()

KIRQL FASTCALL KfRaiseIrql

(

IN KIRQL

NewIrql

)

Definition at line 376 of file pic.c.

{
    PKPCR Pcr = KeGetPcr();
    KIRQL CurrentIrql;

    /* Read current IRQL */
    CurrentIrql = Pcr->Irql;

#if DBG
    /* Validate correct raise */
    if (CurrentIrql > NewIrql)
    {
        /* Crash system */
        Pcr->Irql = PASSIVE_LEVEL;
        KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
    }
#endif

    /* Set new IRQL */
    Pcr->Irql = NewIrql;

    /* Return old IRQL */
    return CurrentIrql;
}

Referenced by _IRQL_requires_max_(), KeRaiseIrqlToSynchLevel(), and KiCheckForApcDelivery().

Variable Documentation

FindHigherIrqlMask

ULONG FindHigherIrqlMask[32]

Definition at line 70 of file irql.c.

Referenced by HalEndSystemInterrupt2(), HalpDispatchInterrupt2(), HalpEndSoftwareInterrupt2(), HalpHardwareInterruptLevel2(), and KfLowerIrql().

HalpEisaELCR

LONG HalpEisaELCR

Definition at line 214 of file pic.c.

Referenced by HalpInitializePICs().

HalpSpecialDismissLevelTable

PHAL_DISMISS_INTERRUPT HalpSpecialDismissLevelTable[16]

Initial value:

=
{
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrq07Level,



    HalpDismissIrqLevel,

    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,
    HalpDismissIrqLevel,



    HalpDismissIrq13Level,

    HalpDismissIrqLevel,
    HalpDismissIrq15Level
}

Definition at line 87 of file pic.c.

Referenced by HalEnableSystemInterrupt(), and HalpInitializePICs().

HalpSpecialDismissTable

PHAL_DISMISS_INTERRUPT HalpSpecialDismissTable[16]

Initial value:

=
{
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrq07,



    HalpDismissIrqGeneric,

    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,
    HalpDismissIrqGeneric,



    HalpDismissIrq13,

    HalpDismissIrqGeneric,
    HalpDismissIrq15
}

Definition at line 55 of file pic.c.

Referenced by HalBeginSystemInterrupt(), HalEnableSystemInterrupt(), and HalpInitializePICs().

KiI8259MaskTable

ULONG KiI8259MaskTable[32]

Definition at line 15 of file irql.c.

Referenced by _HalpDismissIrqGeneric(), _HalpDismissIrqLevel(), and HalEnableSystemInterrupt().

SWInterruptHandlerTable

PHAL_SW_INTERRUPT_HANDLER SWInterruptHandlerTable[20]

Initial value:

=
{
    (PHAL_SW_INTERRUPT_HANDLER)KiUnexpectedInterrupt,
    HalpApcInterrupt,
    HalpDispatchInterrupt,
    (PHAL_SW_INTERRUPT_HANDLER)KiUnexpectedInterrupt,
    HalpHardwareInterrupt0,
    HalpHardwareInterrupt1,
    HalpHardwareInterrupt2,
    HalpHardwareInterrupt3,
    HalpHardwareInterrupt4,
    HalpHardwareInterrupt5,
    HalpHardwareInterrupt6,
    HalpHardwareInterrupt7,
    HalpHardwareInterrupt8,
    HalpHardwareInterrupt9,
    HalpHardwareInterrupt10,
    HalpHardwareInterrupt11,
    HalpHardwareInterrupt12,
    HalpHardwareInterrupt13,
    HalpHardwareInterrupt14,
    HalpHardwareInterrupt15
}

Definition at line 182 of file pic.c.

Referenced by HalEnableSystemInterrupt(), HalEndSystemInterrupt2(), HalpDispatchInterrupt2(), HalpEndSoftwareInterrupt2(), HalpHardwareInterruptLevel2(), HalpInitializePICs(), HalRequestSoftwareInterrupt(), and KfLowerIrql().

SWInterruptHandlerTable2

PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY SWInterruptHandlerTable2[3]

Initial value:

=
{
    (PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(PVOID)KiUnexpectedInterrupt,
    HalpApcInterrupt2ndEntry,
    HalpDispatchInterrupt2ndEntry
}

Definition at line 207 of file pic.c.

Referenced by HalEndSystemInterrupt2(), and HalpEndSoftwareInterrupt2().

SWInterruptLookUpTable

KIRQL SWInterruptLookUpTable[8]

Initial value:

=
{
    PASSIVE_LEVEL,                 
    PASSIVE_LEVEL,                 
    APC_LEVEL,                     
    APC_LEVEL,                     
    DISPATCH_LEVEL,                
    DISPATCH_LEVEL,                
    DISPATCH_LEVEL,                
    DISPATCH_LEVEL                 
}

Definition at line 122 of file pic.c.

Referenced by HalRequestSoftwareInterrupt().