ReactOS 0.4.15-dev-5664-g3bf4ef6
halhw.h
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1/*
2 * PROJECT: ReactOS Hardware Abstraction Layer
3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4 * PURPOSE: PC/AT hardware header file
5 * COPYRIGHT: ...
6 */
7
8#pragma once
9
10/* CMOS Registers and Ports */
11#define CMOS_CONTROL_PORT (PUCHAR)0x70
12#define CMOS_DATA_PORT (PUCHAR)0x71
13#define RTC_REGISTER_A 0x0A
14#define RTC_REG_A_UIP 0x80
15#define RTC_REGISTER_B 0x0B
16#define RTC_REG_B_PI 0x40
17#define RTC_REGISTER_C 0x0C
18#define RTC_REG_C_IRQ 0x80
19#define RTC_REGISTER_D 0x0D
20#define RTC_REGISTER_CENTURY 0x32
21
22//
23// BIOS Interrupts
24//
25#define VIDEO_SERVICES 0x10
26
27//
28// Operations for INT 10h (in AH)
29//
30#define SET_VIDEO_MODE 0x00
31
32//
33// Video Modes for INT10h AH=00 (in AL)
34//
35#define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
36
37#if defined(SARCH_XBOX)
38//
39// For some unknown reason the PIT of the Xbox is fixed at 1.125000 MHz,
40// which is ~5.7% lower than on the PC.
41//
42#define PIT_FREQUENCY 1125000
43#else
44//
45// Commonly stated as being 1.19318MHz
46//
47// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
48// p. 471
49//
50// However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
51// of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
52//
53// Note that Windows uses 1.193167MHz which seems to have no basis. However, if
54// one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
55// infinite series) and divides it by three, one obtains 1.19318167.
56//
57// It may be that the original NT HAL source code introduced a typo and turned
58// 119318167 into 1193167 by ommitting the "18". This is very plausible as the
59// number is quite long.
60//
61#define PIT_FREQUENCY 1193182
62#endif
63
64//
65// These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
66//
67#define TIMER_CHANNEL0_DATA_PORT 0x40
68#define TIMER_CHANNEL1_DATA_PORT 0x41
69#define TIMER_CHANNEL2_DATA_PORT 0x42
70#define TIMER_CONTROL_PORT 0x43
71
72//
73// Mode 0 - Interrupt On Terminal Count
74// Mode 1 - Hardware Re-triggerable One-Shot
75// Mode 2 - Rate Generator
76// Mode 3 - Square Wave Generator
77// Mode 4 - Software Triggered Strobe
78// Mode 5 - Hardware Triggered Strobe
79//
81{
91
93{
99
100typedef enum _TIMER_CHANNELS
101{
107
109{
110 struct
111 {
116 };
119
120//
121// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
122// P. 400
123//
124// This port is controled by the i8255 Programmable Peripheral Interface (PPI)
125//
126#define SYSTEM_CONTROL_PORT_A 0x92
127#define SYSTEM_CONTROL_PORT_B 0x61
129{
130 struct
131 {
140 };
143
144//
145// See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
146// P. 396, 397
147//
148// These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
149//
150#define PIC1_CONTROL_PORT 0x20
151#define PIC1_DATA_PORT 0x21
152#define PIC2_CONTROL_PORT 0xA0
153#define PIC2_DATA_PORT 0xA1
154
155#define PIC_TIMER_IRQ 0
156#define PIC_CASCADE_IRQ 2
157#define PIC_RTC_IRQ 8
158
159//
160// Definitions for ICW/OCW Bits
161//
163{
165 Single
167
169{
173
175{
179
181{
185
187{
191
193{
199
201{
205 ReadIsr
207
208typedef enum _I8259_EOI_MODE
209{
219
220//
221// Definitions for ICW Registers
222//
223typedef union _I8259_ICW1
224{
225 struct
226 {
233 };
236
237typedef union _I8259_ICW2
238{
239 struct
240 {
243 };
246
247typedef union _I8259_ICW3
248{
249 union
250 {
251 struct
252 {
261 };
262 struct
263 {
266 };
267 };
270
271typedef union _I8259_ICW4
272{
273 struct
274 {
280 };
283
284typedef union _I8259_OCW2
285{
286 struct
287 {
291 };
294
295typedef union _I8259_OCW3
296{
297 struct
298 {
305 };
308
309typedef union _I8259_ISR
310{
311 struct
312 {
321 };
324
326
327//
328// See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
329// P. 34, 35
330//
331// These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
332//
333#define EISA_ELCR_MASTER 0x4D0
334#define EISA_ELCR_SLAVE 0x4D1
335
336typedef union _EISA_ELCR
337{
338 struct
339 {
340 struct
341 {
351 struct
352 {
362 };
365
366typedef union _PIC_MASK
367{
368 struct
369 {
372 };
_I8259_ICW4_BUFFERED_MODE
Definition: halhw.h:193
@ BufferedSlave
Definition: halhw.h:196
@ NonBuffered2
Definition: halhw.h:195
@ NonBuffered
Definition: halhw.h:194
@ BufferedMaster
Definition: halhw.h:197
union _SYSTEM_CONTROL_PORT_B_REGISTER * PSYSTEM_CONTROL_PORT_B_REGISTER
_I8259_ICW4_EOI_MODE
Definition: halhw.h:187
@ NormalEoi
Definition: halhw.h:188
@ AutomaticEoi
Definition: halhw.h:189
enum _TIMER_ACCESS_MODES TIMER_ACCESS_MODES
union _I8259_OCW2 I8259_OCW2
union _I8259_OCW3 * PI8259_OCW3
union _I8259_ISR * PI8259_ISR
_TIMER_CHANNELS
Definition: halhw.h:101
@ PitReadBack
Definition: halhw.h:105
@ PitChannel0
Definition: halhw.h:102
@ PitChannel2
Definition: halhw.h:104
@ PitChannel1
Definition: halhw.h:103
union _EISA_ELCR * PEISA_ELCR
union _I8259_ICW2 I8259_ICW2
enum _I8259_ICW4_EOI_MODE I8259_ICW4_EOI_MODE
_I8259_ICW1_OPERATING_MODE
Definition: halhw.h:163
@ Single
Definition: halhw.h:165
@ Cascade
Definition: halhw.h:164
_I8259_ICW4_SYSTEM_MODE
Definition: halhw.h:181
@ Mcs8085Mode
Definition: halhw.h:182
@ New8086Mode
Definition: halhw.h:183
enum _TIMER_OPERATING_MODES TIMER_OPERATING_MODES
union _SYSTEM_CONTROL_PORT_B_REGISTER SYSTEM_CONTROL_PORT_B_REGISTER
union _I8259_ICW3 I8259_ICW3
union _I8259_OCW2 * PI8259_OCW2
enum _I8259_READ_REQUEST I8259_READ_REQUEST
_TIMER_ACCESS_MODES
Definition: halhw.h:93
@ PitAccessModeLow
Definition: halhw.h:95
@ PitAccessModeCounterLatch
Definition: halhw.h:94
@ PitAccessModeHigh
Definition: halhw.h:96
@ PitAccessModeLowHigh
Definition: halhw.h:97
enum _I8259_EOI_MODE I8259_EOI_MODE
enum _TIMER_CHANNELS TIMER_CHANNELS
_I8259_ICW1_INTERRUPT_MODE
Definition: halhw.h:169
@ EdgeTriggered
Definition: halhw.h:170
@ LevelTriggered
Definition: halhw.h:171
union _I8259_ICW1 I8259_ICW1
union _EISA_ELCR EISA_ELCR
I8259_ISR I8259_IDR
Definition: halhw.h:325
union _I8259_ICW2 * PI8259_ICW2
enum _I8259_ICW4_SYSTEM_MODE I8259_ICW4_SYSTEM_MODE
I8259_ISR * PI8259_IDR
Definition: halhw.h:325
union _PIC_MASK * PPIC_MASK
union _TIMER_CONTROL_PORT_REGISTER * PTIMER_CONTROL_PORT_REGISTER
_I8259_EOI_MODE
Definition: halhw.h:209
@ NonSpecificEoi
Definition: halhw.h:211
@ RotateSpecific
Definition: halhw.h:217
@ RotateAutoEoiSet
Definition: halhw.h:214
@ RotateNonSpecific
Definition: halhw.h:215
@ InvalidEoiMode
Definition: halhw.h:212
@ SetPriority
Definition: halhw.h:216
@ SpecificEoi
Definition: halhw.h:213
@ RotateAutoEoiClear
Definition: halhw.h:210
union _I8259_ISR I8259_ISR
union _I8259_ICW3 * PI8259_ICW3
enum _I8259_ICW1_INTERRUPT_MODE I8259_ICW1_INTERRUPT_MODE
enum _I8259_ICW1_OPERATING_MODE I8259_ICW1_OPERATING_MODE
union _I8259_ICW1 * PI8259_ICW1
_TIMER_OPERATING_MODES
Definition: halhw.h:81
@ PitOperatingMode3
Definition: halhw.h:85
@ PitOperatingMode2Reserved
Definition: halhw.h:88
@ PitOperatingMode2
Definition: halhw.h:84
@ PitOperatingMode5
Definition: halhw.h:87
@ PitOperatingMode0
Definition: halhw.h:82
@ PitOperatingMode4
Definition: halhw.h:86
@ PitOperatingMode5Reserved
Definition: halhw.h:89
@ PitOperatingMode1
Definition: halhw.h:83
union _TIMER_CONTROL_PORT_REGISTER TIMER_CONTROL_PORT_REGISTER
union _I8259_ICW4 * PI8259_ICW4
union _I8259_ICW4 I8259_ICW4
_I8259_ICW1_INTERVAL
Definition: halhw.h:175
@ Interval4
Definition: halhw.h:177
@ Interval8
Definition: halhw.h:176
enum _I8259_ICW1_INTERVAL I8259_ICW1_INTERVAL
union _I8259_OCW3 I8259_OCW3
union _PIC_MASK PIC_MASK
_I8259_READ_REQUEST
Definition: halhw.h:201
@ ReadIsr
Definition: halhw.h:205
@ InvalidRequest
Definition: halhw.h:202
@ InvalidRequest2
Definition: halhw.h:203
@ ReadIdr
Definition: halhw.h:204
enum _I8259_ICW4_BUFFERED_MODE I8259_ICW4_BUFFERED_MODE
unsigned short USHORT
Definition: pedump.c:61
UCHAR Irq4Level
Definition: halhw.h:346
UCHAR Irq11Level
Definition: halhw.h:356
UCHAR Irq3Level
Definition: halhw.h:345
struct _EISA_ELCR::@1499::@1502 Slave
UCHAR Irq14Level
Definition: halhw.h:359
UCHAR Irq1Level
Definition: halhw.h:343
UCHAR Irq15Level
Definition: halhw.h:360
UCHAR Irq10Level
Definition: halhw.h:355
UCHAR Irq9Level
Definition: halhw.h:354
UCHAR Irq2Level
Definition: halhw.h:344
UCHAR Irq12Level
Definition: halhw.h:357
USHORT Bits
Definition: halhw.h:363
UCHAR Irq13Level
Definition: halhw.h:358
UCHAR Irq8Level
Definition: halhw.h:353
UCHAR Irq7Level
Definition: halhw.h:349
struct _EISA_ELCR::@1499::@1501 Master
UCHAR Irq0Level
Definition: halhw.h:342
UCHAR Irq6Level
Definition: halhw.h:348
UCHAR Irq5Level
Definition: halhw.h:347
UCHAR Init
Definition: halhw.h:231
UCHAR OperatingMode
Definition: halhw.h:228
UCHAR Bits
Definition: halhw.h:234
UCHAR NeedIcw4
Definition: halhw.h:227
UCHAR Interval
Definition: halhw.h:229
UCHAR InterruptVectorAddress
Definition: halhw.h:232
UCHAR InterruptMode
Definition: halhw.h:230
UCHAR Bits
Definition: halhw.h:244
UCHAR Sbz
Definition: halhw.h:241
UCHAR InterruptVector
Definition: halhw.h:242
UCHAR SlaveIrq5
Definition: halhw.h:258
UCHAR SlaveId
Definition: halhw.h:264
UCHAR SlaveIrq4
Definition: halhw.h:257
UCHAR SlaveIrq0
Definition: halhw.h:253
UCHAR SlaveIrq1
Definition: halhw.h:254
UCHAR SlaveIrq2
Definition: halhw.h:255
UCHAR Bits
Definition: halhw.h:268
UCHAR Reserved
Definition: halhw.h:265
UCHAR SlaveIrq6
Definition: halhw.h:259
UCHAR SlaveIrq7
Definition: halhw.h:260
UCHAR SlaveIrq3
Definition: halhw.h:256
UCHAR SystemMode
Definition: halhw.h:275
UCHAR BufferedMode
Definition: halhw.h:277
UCHAR SpecialFullyNestedMode
Definition: halhw.h:278
UCHAR Reserved
Definition: halhw.h:279
UCHAR Bits
Definition: halhw.h:281
UCHAR EoiMode
Definition: halhw.h:276
UCHAR Irq0
Definition: halhw.h:313
UCHAR Irq4
Definition: halhw.h:317
UCHAR Irq3
Definition: halhw.h:316
UCHAR Irq2
Definition: halhw.h:315
UCHAR Irq6
Definition: halhw.h:319
UCHAR Irq5
Definition: halhw.h:318
UCHAR Bits
Definition: halhw.h:322
UCHAR Irq1
Definition: halhw.h:314
UCHAR Irq7
Definition: halhw.h:320
UCHAR EoiMode
Definition: halhw.h:290
UCHAR Sbz
Definition: halhw.h:289
UCHAR Bits
Definition: halhw.h:292
UCHAR IrqNumber
Definition: halhw.h:288
UCHAR Sbo
Definition: halhw.h:301
UCHAR Sbz
Definition: halhw.h:302
UCHAR ReadRequest
Definition: halhw.h:299
UCHAR Bits
Definition: halhw.h:306
UCHAR PollCommand
Definition: halhw.h:300
UCHAR Reserved
Definition: halhw.h:304
UCHAR SpecialMaskMode
Definition: halhw.h:303
UCHAR Slave
Definition: halhw.h:371
USHORT Both
Definition: halhw.h:373
UCHAR Master
Definition: halhw.h:370
unsigned char UCHAR
Definition: xmlstorage.h:181