ReactOS  0.4.15-dev-321-g2d9b385
halhw.h
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1 /*
2  * PROJECT: ReactOS Hardware Abstraction Layer
3  * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4  * PURPOSE: PC/AT hardware header file
5  * COPYRIGHT: ...
6  */
7 
8 #pragma once
9 
10 /* CMOS Registers and Ports */
11 #define CMOS_CONTROL_PORT (PUCHAR)0x70
12 #define CMOS_DATA_PORT (PUCHAR)0x71
13 #define RTC_REGISTER_A 0x0A
14 #define RTC_REG_A_UIP 0x80
15 #define RTC_REGISTER_B 0x0B
16 #define RTC_REG_B_PI 0x40
17 #define RTC_REGISTER_C 0x0C
18 #define RTC_REG_C_IRQ 0x80
19 #define RTC_REGISTER_D 0x0D
20 #define RTC_REGISTER_CENTURY 0x32
21 
22 //
23 // BIOS Interrupts
24 //
25 #define VIDEO_SERVICES 0x10
26 
27 //
28 // Operations for INT 10h (in AH)
29 //
30 #define SET_VIDEO_MODE 0x00
31 
32 //
33 // Video Modes for INT10h AH=00 (in AL)
34 //
35 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
36 
37 #if defined(SARCH_XBOX)
38 //
39 // For some unknown reason the PIT of the Xbox is fixed at 1.125000 MHz,
40 // which is ~5.7% lower than on the PC.
41 //
42 #define PIT_FREQUENCY 1125000
43 #else
44 //
45 // Commonly stated as being 1.19318MHz
46 //
47 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
48 // p. 471
49 //
50 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
51 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
52 //
53 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
54 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
55 // infinite series) and divides it by three, one obtains 1.19318167.
56 //
57 // It may be that the original NT HAL source code introduced a typo and turned
58 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
59 // number is quite long.
60 //
61 #define PIT_FREQUENCY 1193182
62 #endif
63 
64 //
65 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
66 //
67 #define TIMER_CHANNEL0_DATA_PORT 0x40
68 #define TIMER_CHANNEL1_DATA_PORT 0x41
69 #define TIMER_CHANNEL2_DATA_PORT 0x42
70 #define TIMER_CONTROL_PORT 0x43
71 
72 //
73 // Mode 0 - Interrupt On Terminal Count
74 // Mode 1 - Hardware Re-triggerable One-Shot
75 // Mode 2 - Rate Generator
76 // Mode 3 - Square Wave Generator
77 // Mode 4 - Software Triggered Strobe
78 // Mode 5 - Hardware Triggered Strobe
79 //
81 {
91 
92 typedef enum _TIMER_ACCESS_MODES
93 {
99 
100 typedef enum _TIMER_CHANNELS
101 {
107 
109 {
110  struct
111  {
116  };
119 
120 //
121 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
122 // P. 400
123 //
124 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
125 //
126 #define SYSTEM_CONTROL_PORT_A 0x92
127 #define SYSTEM_CONTROL_PORT_B 0x61
129 {
130  struct
131  {
140  };
143 
144 //
145 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
146 // P. 396, 397
147 //
148 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
149 //
150 #define PIC1_CONTROL_PORT 0x20
151 #define PIC1_DATA_PORT 0x21
152 #define PIC2_CONTROL_PORT 0xA0
153 #define PIC2_DATA_PORT 0xA1
154 
155 //
156 // Definitions for ICW/OCW Bits
157 //
159 {
163 
165 {
169 
171 {
175 
177 {
181 
183 {
187 
189 {
195 
197 {
203 
204 typedef enum _I8259_EOI_MODE
205 {
215 
216 //
217 // Definitions for ICW Registers
218 //
219 typedef union _I8259_ICW1
220 {
221  struct
222  {
229  };
232 
233 typedef union _I8259_ICW2
234 {
235  struct
236  {
239  };
242 
243 typedef union _I8259_ICW3
244 {
245  union
246  {
247  struct
248  {
257  };
258  struct
259  {
262  };
263  };
266 
267 typedef union _I8259_ICW4
268 {
269  struct
270  {
276  };
279 
280 typedef union _I8259_OCW2
281 {
282  struct
283  {
287  };
290 
291 typedef union _I8259_OCW3
292 {
293  struct
294  {
301  };
304 
305 typedef union _I8259_ISR
306 {
307  union
308  {
309  struct
310  {
319  };
320  };
323 
325 
326 //
327 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
328 // P. 34, 35
329 //
330 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
331 //
332 #define EISA_ELCR_MASTER 0x4D0
333 #define EISA_ELCR_SLAVE 0x4D1
334 
335 typedef union _EISA_ELCR
336 {
337  struct
338  {
339  struct
340  {
349  } Master;
350  struct
351  {
360  } Slave;
361  };
364 
365 typedef struct _PIC_MASK
366 {
367  union
368  {
369  struct
370  {
373  };
375  };
376 } PIC_MASK, *PPIC_MASK;
UCHAR InterruptVector
Definition: halhw.h:238
UCHAR IrqNumber
Definition: halhw.h:284
UCHAR Irq8Level
Definition: halhw.h:352
UCHAR SpecialMaskMode
Definition: halhw.h:299
UCHAR Irq11Level
Definition: halhw.h:355
union _SYSTEM_CONTROL_PORT_B_REGISTER SYSTEM_CONTROL_PORT_B_REGISTER
UCHAR Interval
Definition: halhw.h:225
UCHAR Irq5
Definition: halhw.h:316
Definition: halhw.h:161
_I8259_READ_REQUEST
Definition: halhw.h:196
UCHAR InterruptMode
Definition: halhw.h:226
union _I8259_OCW2 * PI8259_OCW2
USHORT Bits
Definition: halhw.h:362
UCHAR Irq0
Definition: halhw.h:311
enum _I8259_ICW4_SYSTEM_MODE I8259_ICW4_SYSTEM_MODE
UCHAR EoiMode
Definition: halhw.h:286
UCHAR SlaveIrq5
Definition: halhw.h:254
UCHAR Sbz
Definition: halhw.h:285
USHORT Both
Definition: halhw.h:374
union _I8259_ICW4 * PI8259_ICW4
union _I8259_ICW4 I8259_ICW4
UCHAR Irq2Level
Definition: halhw.h:343
UCHAR Irq9Level
Definition: halhw.h:353
_I8259_ICW1_OPERATING_MODE
Definition: halhw.h:158
enum _I8259_ICW4_BUFFERED_MODE I8259_ICW4_BUFFERED_MODE
UCHAR SlaveIrq3
Definition: halhw.h:252
UCHAR SlaveIrq2
Definition: halhw.h:251
union _I8259_ICW2 I8259_ICW2
UCHAR Bits
Definition: halhw.h:240
UCHAR Bits
Definition: halhw.h:264
UCHAR SlaveIrq7
Definition: halhw.h:256
union _EISA_ELCR EISA_ELCR
UCHAR ReadRequest
Definition: halhw.h:295
_TIMER_OPERATING_MODES
Definition: halhw.h:80
UCHAR Irq2
Definition: halhw.h:313
UCHAR Bits
Definition: halhw.h:321
enum _I8259_EOI_MODE I8259_EOI_MODE
UCHAR Slave
Definition: halhw.h:372
UCHAR Irq4Level
Definition: halhw.h:345
UCHAR SpecialFullyNestedMode
Definition: halhw.h:274
union _I8259_ISR * PI8259_ISR
UCHAR Reserved
Definition: halhw.h:275
union _I8259_ICW3 I8259_ICW3
UCHAR Irq6Level
Definition: halhw.h:347
union _I8259_ICW3 * PI8259_ICW3
enum _I8259_ICW1_INTERRUPT_MODE I8259_ICW1_INTERRUPT_MODE
_TIMER_ACCESS_MODES
Definition: halhw.h:92
_I8259_ICW1_INTERRUPT_MODE
Definition: halhw.h:164
UCHAR Sbz
Definition: halhw.h:237
UCHAR Bits
Definition: halhw.h:230
UCHAR Sbo
Definition: halhw.h:297
UCHAR Irq4
Definition: halhw.h:315
UCHAR SlaveIrq6
Definition: halhw.h:255
UCHAR SystemMode
Definition: halhw.h:271
union _SYSTEM_CONTROL_PORT_B_REGISTER * PSYSTEM_CONTROL_PORT_B_REGISTER
I8259_ISR * PI8259_IDR
Definition: halhw.h:324
_I8259_ICW4_BUFFERED_MODE
Definition: halhw.h:188
union _I8259_OCW2 I8259_OCW2
enum _TIMER_CHANNELS TIMER_CHANNELS
UCHAR OperatingMode
Definition: halhw.h:224
UCHAR BufferedMode
Definition: halhw.h:273
struct _EISA_ELCR::@1505::@1507 Master
UCHAR NeedIcw4
Definition: halhw.h:223
UCHAR Irq5Level
Definition: halhw.h:346
union _TIMER_CONTROL_PORT_REGISTER TIMER_CONTROL_PORT_REGISTER
UCHAR Irq15Level
Definition: halhw.h:359
UCHAR Irq7
Definition: halhw.h:318
struct _PIC_MASK * PPIC_MASK
UCHAR EoiMode
Definition: halhw.h:272
UCHAR Irq1Level
Definition: halhw.h:342
_I8259_ICW1_INTERVAL
Definition: halhw.h:170
unsigned char UCHAR
Definition: xmlstorage.h:181
union _I8259_ICW2 * PI8259_ICW2
UCHAR Irq10Level
Definition: halhw.h:354
UCHAR Irq3Level
Definition: halhw.h:344
UCHAR Bits
Definition: halhw.h:277
UCHAR Bits
Definition: halhw.h:288
Definition: halhw.h:201
UCHAR Irq7Level
Definition: halhw.h:348
UCHAR SlaveIrq4
Definition: halhw.h:253
UCHAR Irq14Level
Definition: halhw.h:358
struct _EISA_ELCR::@1505::@1508 Slave
UCHAR Reserved
Definition: halhw.h:300
_I8259_ICW4_SYSTEM_MODE
Definition: halhw.h:176
UCHAR InterruptVectorAddress
Definition: halhw.h:228
UCHAR Irq6
Definition: halhw.h:317
UCHAR PollCommand
Definition: halhw.h:296
UCHAR Irq0Level
Definition: halhw.h:341
UCHAR Bits
Definition: halhw.h:302
enum _I8259_ICW1_OPERATING_MODE I8259_ICW1_OPERATING_MODE
unsigned short USHORT
Definition: pedump.c:61
struct _PIC_MASK PIC_MASK
union _EISA_ELCR * PEISA_ELCR
union _I8259_ICW1 I8259_ICW1
Definition: halhw.h:200
UCHAR SlaveIrq0
Definition: halhw.h:249
union _I8259_ISR I8259_ISR
UCHAR Init
Definition: halhw.h:227
union _I8259_ICW1 * PI8259_ICW1
enum _I8259_READ_REQUEST I8259_READ_REQUEST
_I8259_ICW4_EOI_MODE
Definition: halhw.h:182
enum _TIMER_ACCESS_MODES TIMER_ACCESS_MODES
UCHAR Irq3
Definition: halhw.h:314
union _TIMER_CONTROL_PORT_REGISTER * PTIMER_CONTROL_PORT_REGISTER
_I8259_EOI_MODE
Definition: halhw.h:204
I8259_ISR I8259_IDR
Definition: halhw.h:324
union _I8259_OCW3 * PI8259_OCW3
union _I8259_OCW3 I8259_OCW3
Definition: halhw.h:160
UCHAR Irq13Level
Definition: halhw.h:357
_TIMER_CHANNELS
Definition: halhw.h:100
UCHAR Master
Definition: halhw.h:371
UCHAR Sbz
Definition: halhw.h:298
enum _TIMER_OPERATING_MODES TIMER_OPERATING_MODES
UCHAR SlaveId
Definition: halhw.h:260
UCHAR Reserved
Definition: halhw.h:261
enum _I8259_ICW1_INTERVAL I8259_ICW1_INTERVAL
UCHAR SlaveIrq1
Definition: halhw.h:250
UCHAR Irq1
Definition: halhw.h:312
enum _I8259_ICW4_EOI_MODE I8259_ICW4_EOI_MODE
UCHAR Irq12Level
Definition: halhw.h:356