11#define CMOS_CONTROL_PORT (PUCHAR)0x70
12#define CMOS_DATA_PORT (PUCHAR)0x71
13#define RTC_REGISTER_A 0x0A
14#define RTC_REG_A_UIP 0x80
15#define RTC_REGISTER_B 0x0B
16#define RTC_REG_B_PI 0x40
17#define RTC_REGISTER_C 0x0C
18#define RTC_REG_C_IRQ 0x80
19#define RTC_REGISTER_D 0x0D
20#define RTC_REGISTER_CENTURY 0x32
25#define VIDEO_SERVICES 0x10
30#define SET_VIDEO_MODE 0x00
35#define GRAPHICS_MODE_12 0x12
37#if defined(SARCH_XBOX)
42#define PIT_FREQUENCY 1125000
61#define PIT_FREQUENCY 1193182
67#define TIMER_CHANNEL0_DATA_PORT 0x40
68#define TIMER_CHANNEL1_DATA_PORT 0x41
69#define TIMER_CHANNEL2_DATA_PORT 0x42
70#define TIMER_CONTROL_PORT 0x43
126#define SYSTEM_CONTROL_PORT_A 0x92
127#define SYSTEM_CONTROL_PORT_B 0x61
150#define PIC1_CONTROL_PORT 0x20
151#define PIC1_DATA_PORT 0x21
152#define PIC2_CONTROL_PORT 0xA0
153#define PIC2_DATA_PORT 0xA1
155#define PIC_TIMER_IRQ 0
156#define PIC_CASCADE_IRQ 2
333#define EISA_ELCR_MASTER 0x4D0
334#define EISA_ELCR_SLAVE 0x4D1
_I8259_ICW4_BUFFERED_MODE
union _SYSTEM_CONTROL_PORT_B_REGISTER * PSYSTEM_CONTROL_PORT_B_REGISTER
enum _TIMER_ACCESS_MODES TIMER_ACCESS_MODES
union _I8259_OCW2 I8259_OCW2
union _I8259_OCW3 * PI8259_OCW3
union _I8259_ISR * PI8259_ISR
union _EISA_ELCR * PEISA_ELCR
union _I8259_ICW2 I8259_ICW2
enum _I8259_ICW4_EOI_MODE I8259_ICW4_EOI_MODE
_I8259_ICW1_OPERATING_MODE
enum _TIMER_OPERATING_MODES TIMER_OPERATING_MODES
union _SYSTEM_CONTROL_PORT_B_REGISTER SYSTEM_CONTROL_PORT_B_REGISTER
union _I8259_ICW3 I8259_ICW3
union _I8259_OCW2 * PI8259_OCW2
enum _I8259_READ_REQUEST I8259_READ_REQUEST
@ PitAccessModeCounterLatch
enum _I8259_EOI_MODE I8259_EOI_MODE
enum _TIMER_CHANNELS TIMER_CHANNELS
_I8259_ICW1_INTERRUPT_MODE
union _I8259_ICW1 I8259_ICW1
union _EISA_ELCR EISA_ELCR
union _I8259_ICW2 * PI8259_ICW2
enum _I8259_ICW4_SYSTEM_MODE I8259_ICW4_SYSTEM_MODE
union _PIC_MASK * PPIC_MASK
union _TIMER_CONTROL_PORT_REGISTER * PTIMER_CONTROL_PORT_REGISTER
union _I8259_ISR I8259_ISR
union _I8259_ICW3 * PI8259_ICW3
enum _I8259_ICW1_INTERRUPT_MODE I8259_ICW1_INTERRUPT_MODE
enum _I8259_ICW1_OPERATING_MODE I8259_ICW1_OPERATING_MODE
union _I8259_ICW1 * PI8259_ICW1
@ PitOperatingMode2Reserved
@ PitOperatingMode5Reserved
union _TIMER_CONTROL_PORT_REGISTER TIMER_CONTROL_PORT_REGISTER
union _I8259_ICW4 * PI8259_ICW4
union _I8259_ICW4 I8259_ICW4
enum _I8259_ICW1_INTERVAL I8259_ICW1_INTERVAL
union _I8259_OCW3 I8259_OCW3
enum _I8259_ICW4_BUFFERED_MODE I8259_ICW4_BUFFERED_MODE
struct _EISA_ELCR::@1533::@1536 Slave
struct _EISA_ELCR::@1533::@1535 Master
UCHAR InterruptVectorAddress
UCHAR SpecialFullyNestedMode
UCHAR Timer2GateToSpeaker