ReactOS 0.4.15-dev-5666-gc548b97
pic.c
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1/*
2 * PROJECT: ReactOS HAL
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * PURPOSE: Generic HAL PIC Management Code shared between APIC and PIC HAL
5 * PROGRAMMERS: ReactOS Portable Systems Group
6 */
7
8 /* INCLUDES *******************************************************************/
9
10#include <hal.h>
11#define NDEBUG
12#include <debug.h>
13
14 /* FUNCTIONS ******************************************************************/
15
16VOID
19{
20 I8259_ICW1 Icw1;
21 I8259_ICW2 Icw2;
22 I8259_ICW3 Icw3;
23 I8259_ICW4 Icw4;
24
26
27 /* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */
28 Icw1.NeedIcw4 = TRUE;
30 Icw1.Interval = Interval8;
32 Icw1.Init = TRUE;
35
36 /* ICW2 - interrupt vector offset */
39
40 /* Connect slave to IRQ 2 */
41 Icw3.Bits = 0;
42 Icw3.SlaveIrq2 = TRUE;
44
45 /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
47 Icw4.EoiMode = NormalEoi;
50 Icw4.Reserved = 0;
52
53 /* Mask all interrupts */
55
56 /* Initialize ICW1 for slave, interval 8, edge-triggered mode with ICW4 */
57 Icw1.NeedIcw4 = TRUE;
60 Icw1.Interval = Interval8;
61 Icw1.Init = TRUE;
62 Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */
64
65 /* Set interrupt vector base */
66 Icw2.Bits = PRIMARY_VECTOR_BASE + 8;
68
69 /* Slave ID */
70 Icw3.Bits = 0;
71 Icw3.SlaveId = 2;
73
74 /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
76 Icw4.EoiMode = NormalEoi;
79 Icw4.Reserved = 0;
81
82 /* Mask all interrupts */
84}
#define TRUE
Definition: types.h:120
#define FALSE
Definition: types.h:117
VOID NTAPI HalpInitializeLegacyPICs(VOID)
Definition: pic.c:18
#define PRIMARY_VECTOR_BASE
Definition: halp.h:16
@ NonBuffered
Definition: halhw.h:194
#define PIC1_DATA_PORT
Definition: halhw.h:151
@ NormalEoi
Definition: halhw.h:188
@ Cascade
Definition: halhw.h:164
@ New8086Mode
Definition: halhw.h:183
#define PIC2_DATA_PORT
Definition: halhw.h:153
@ EdgeTriggered
Definition: halhw.h:170
#define PIC2_CONTROL_PORT
Definition: halhw.h:152
#define PIC1_CONTROL_PORT
Definition: halhw.h:150
@ Interval8
Definition: halhw.h:176
PPC_QUAL void __outbyte(unsigned long const Port, const unsigned char Data)
Definition: intrin_ppc.h:605
__INTRIN_INLINE uintptr_t __readeflags(void)
Definition: intrin_x86.h:1674
#define ASSERT(a)
Definition: mode.c:44
#define EFLAGS_INTERRUPT_MASK
Definition: ketypes.h:126
#define NTAPI
Definition: typedefs.h:36
UCHAR Init
Definition: halhw.h:231
UCHAR OperatingMode
Definition: halhw.h:228
UCHAR Bits
Definition: halhw.h:234
UCHAR NeedIcw4
Definition: halhw.h:227
UCHAR Interval
Definition: halhw.h:229
UCHAR InterruptVectorAddress
Definition: halhw.h:232
UCHAR InterruptMode
Definition: halhw.h:230
UCHAR Bits
Definition: halhw.h:244
UCHAR SlaveId
Definition: halhw.h:264
UCHAR SlaveIrq2
Definition: halhw.h:255
UCHAR Bits
Definition: halhw.h:268
UCHAR SystemMode
Definition: halhw.h:275
UCHAR BufferedMode
Definition: halhw.h:277
UCHAR SpecialFullyNestedMode
Definition: halhw.h:278
UCHAR Reserved
Definition: halhw.h:279
UCHAR Bits
Definition: halhw.h:281
UCHAR EoiMode
Definition: halhw.h:276