26{
36
37
38
39
42
43
44
45
50
51
52
53
58 CacheAttribute,
59 0);
61
62
63
64
67 if (PageCount != MdlPageCount)
68 {
69
70
71
72 ASSERT(PageCount > MdlPageCount);
76 }
77
78
79
80
81
83 if (!PointerPte)
84 {
85
86
87
91 }
92
93
94
95
97
98
99
100
102
103
104
105
107
108
109
110
112
113
114
115
116 switch (CacheAttribute)
117 {
119
120
121
122
125 break;
126
128
129
130
131
134 break;
135
136 default:
137
138
139
140 break;
141 }
142
143
144
145
146 do
147 {
148
149
150
151 PageFrameIndex = *MdlPages++;
152
153
154
155
158 } while (--PageCount);
159
160
161
162
164
165}
HARDWARE_PTE_ARMV6 TempPte
MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType]
PMDL NTAPI MiAllocatePagesForMdl(IN PHYSICAL_ADDRESS LowAddress, IN PHYSICAL_ADDRESS HighAddress, IN PHYSICAL_ADDRESS SkipBytes, IN SIZE_T TotalBytes, IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute, IN ULONG Flags)
enum _MI_PFN_CACHE_ATTRIBUTE MI_PFN_CACHE_ATTRIBUTE
PMMPTE NTAPI MiReserveSystemPtes(IN ULONG NumberOfPtes, IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType)
FORCEINLINE VOID MI_WRITE_VALID_PTE(IN PMMPTE PointerPte, IN MMPTE TempPte)
VOID NTAPI MmFreePagesFromMdl(IN PMDL Mdl)
#define ExFreePoolWithTag(_P, _T)
_In_ HANDLE _Outptr_result_bytebuffer_ ViewSize PVOID * BaseAddress
#define MI_PAGE_WRITE_COMBINED(x)
#define MI_PAGE_DISABLE_CACHE(x)
#define MI_PAGE_WRITE_THROUGH(x)
#define MiPteToAddress(_Pte)
_In_ WDFDEVICE _In_ PVOID _In_opt_ PMDL Mdl
_Must_inspect_result_ typedef _In_ PHYSICAL_ADDRESS _Inout_ PLARGE_INTEGER NumberOfBytes
_Must_inspect_result_ _In_ PHYSICAL_ADDRESS HighAddress
#define BYTES_TO_PAGES(Size)
#define ADDRESS_AND_SIZE_TO_SPAN_PAGES(_Va, _Size)
_Must_inspect_result_ _In_ PHYSICAL_ADDRESS _In_ PHYSICAL_ADDRESS SkipBytes