#include <hal.h>
#include <halfuncs.h>
#include <rtlfuncs.h>
#include <debug.h>

Include dependency graph for apic.c:

Macros
#define	NDEBUG

#define	BIOS_AREA 0x0

#define	COMMON_AREA 0x2000

#define	HZ (100)

#define	APIC_DIVISOR (16)

#define	CMOS_READ(address)

#define	CMOS_WRITE(address, value)

Functions
ULONG	Read8254Timer (VOID)

VOID	WaitFor8254Wraparound (VOID)

VOID	MpsTimerInterrupt (VOID)

VOID	MpsErrorInterrupt (VOID)

VOID	MpsSpuriousInterrupt (VOID)

VOID	MpsIpiInterrupt (VOID)

ULONG	APICGetMaxLVT (VOID)

VOID	APICClear (VOID)

VOID	EnableApicMode (VOID)

__inline VOID	DisableSMPMode (VOID)

VOID	DumpESR (VOID)

VOID	APICDisable (VOID)

static VOID	APICDumpBit (ULONG base)

VOID	APICDump (VOID)

BOOLEAN	VerifyLocalAPIC (VOID)

VOID	APICSetup (VOID)

VOID	MpsErrorHandler (VOID)

VOID	MpsSpuriousHandler (VOID)

VOID	MpsIRQTrapFrameToTrapFrame (PKIRQ_TRAPFRAME IrqTrapFrame, PKTRAP_FRAME TrapFrame)

VOID	MpsTimerHandler (ULONG Vector, PKIRQ_TRAPFRAME Trapframe)

VOID	APICSetupLVTT (ULONG ClockTicks)

VOID	APICCalibrateTimer (ULONG CPU)

VOID	SetInterruptGate (ULONG index, ULONG_PTR address)

VOID	HaliInitBSP (VOID)

VOID FASTCALL DECLSPEC_NORETURN	HalpApcInterruptHandler (IN PKTRAP_FRAME TrapFrame)

Variables
ULONG	CPUCount

ULONG	BootCPU

ULONG	OnlineCPUs

CPU_INFO	CPUMap [MAX_CPU]

PULONG	APICBase = (PULONG)APIC_DEFAULT_BASE

ULONG	APICMode

ULONG	lastregr [MAX_CPU]

ULONG	lastvalr [MAX_CPU]

ULONG	lastregw [MAX_CPU]

ULONG	lastvalw [MAX_CPU]

CHAR *	APstart

CHAR *	APend

ULONG_PTR	KernelBase

Macro Definition Documentation

◆ APIC_DIVISOR

#define APIC_DIVISOR (16)

Definition at line 76 of file apic.c.

◆ BIOS_AREA

#define BIOS_AREA 0x0

Definition at line 72 of file apic.c.

◆ CMOS_READ

#define CMOS_READ ( address )

Value:

   { \
   WRITE_PORT_UCHAR((PUCHAR)0x70, address)); \
   READ_PORT_UCHAR((PUCHAR)0x71)); \
}

Definition at line 78 of file apic.c.

◆ CMOS_WRITE

#define CMOS_WRITE	(	address,
		value
	)

Value:

   { \
   WRITE_PORT_UCHAR((PUCHAR)0x70, address); \
   WRITE_PORT_UCHAR((PUCHAR)0x71, value); \
}

Definition at line 83 of file apic.c.

◆ COMMON_AREA

#define COMMON_AREA 0x2000

Definition at line 73 of file apic.c.

◆ HZ

#define HZ (100)

Definition at line 75 of file apic.c.

◆ NDEBUG

#define NDEBUG

Definition at line 32 of file apic.c.

Function Documentation

◆ APICCalibrateTimer()

VOID APICCalibrateTimer ( ULONG CPU )

Definition at line 794 of file apic.c.

{
   ULARGE_INTEGER t1, t2;
   LONG tt1, tt2;
   BOOLEAN TSCPresent;
 
   DPRINT("Calibrating APIC timer for CPU %d\n", CPU);
 
   APICSetupLVTT(1000000000);
 
   TSCPresent = KeGetCurrentPrcb()->FeatureBits & KF_RDTSC ? TRUE : FALSE;
 
   /*
    * The timer chip counts down to zero. Let's wait
    * for a wraparound to start exact measurement:
    * (the current tick might have been already half done)
    */
   //WaitFor8254Wraparound();
 
   /*
    * We wrapped around just now. Let's start
    */
   if (TSCPresent)
   {
      t1.QuadPart = (LONGLONG)__rdtsc();
   }
   tt1 = APICRead(APIC_CCRT);
 
   //WaitFor8254Wraparound();
 
 
   tt2 = APICRead(APIC_CCRT);
   if (TSCPresent)
   {
      t2.QuadPart = (LONGLONG)__rdtsc();
      CPUMap[CPU].CoreSpeed = (HZ * (ULONG)(t2.QuadPart - t1.QuadPart));
      DPRINT("CPU clock speed is %ld.%04ld MHz.\n",
         CPUMap[CPU].CoreSpeed/1000000,
         CPUMap[CPU].CoreSpeed%1000000);
      KeGetCurrentPrcb()->MHz = CPUMap[CPU].CoreSpeed/1000000;
   }
 
   CPUMap[CPU].BusSpeed = (HZ * (long)(tt1 - tt2) * APIC_DIVISOR);
 
   /* Setup timer for normal operation */
// APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100);    // 100ns
   APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 10000);  // 10ms
// APICSetupLVTT((CPUMap[CPU].BusSpeed / 1000000) * 100000); // 100ms
 
   DPRINT("Host bus clock speed is %ld.%04ld MHz.\n",
      CPUMap[CPU].BusSpeed/1000000,
      CPUMap[CPU].BusSpeed%1000000);
}

Referenced by HaliInitBSP(), and HalInitializeProcessor().

◆ APICClear()

VOID APICClear ( VOID )

Definition at line 111 of file apic.c.

{
  ULONG tmp, maxlvt;
 
  maxlvt = APICGetMaxLVT();
 
  /*
   * Careful: we have to set masks only first to deassert
   * any level-triggered sources.
   */
 
  if (maxlvt >= 3)
  {
    tmp = ERROR_VECTOR;
    APICWrite(APIC_LVT3, tmp | APIC_LVT3_MASKED);
  }
 
  tmp = APICRead(APIC_LVTT);
  APICWrite(APIC_LVTT, tmp | APIC_LVT_MASKED);
 
  tmp = APICRead(APIC_LINT0);
  APICWrite(APIC_LINT0, tmp | APIC_LVT_MASKED);
 
  tmp = APICRead(APIC_LINT1);
  APICWrite(APIC_LINT1, tmp | APIC_LVT_MASKED);
 
  if (maxlvt >= 4)
  {
    tmp = APICRead(APIC_LVTPC);
    APICWrite(APIC_LVTPC, tmp | APIC_LVT_MASKED);
  }
#if 0
  if (maxlvt >= 5)
  {
    tmp = APICRead(APIC_LVTTHMR);
    APICWrite(APIC_LVTTHMR, tmp | APIC_LVT_MASKED);
  }
#endif
  /*
   * Clean APIC state for other OSs:
   */
  APICWrite(APIC_LVTT, APIC_LVT_MASKED);
  APICWrite(APIC_LINT0, APIC_LVT_MASKED);
  APICWrite(APIC_LINT1, APIC_LVT_MASKED);
 
  if (maxlvt >= 3)
  {
    APICWrite(APIC_LVT3, APIC_LVT3_MASKED);
  }
 
  if (maxlvt >= 4)
  {
    APICWrite(APIC_LVTPC, APIC_LVT_MASKED);
  }
#if 0
  if (maxlvt >= 5)
  {
    APICWrite(APIC_LVTTHMR, APIC_LVT_MASKED);
  }
#endif
}

Referenced by APICDisable(), and EnableApicMode().

◆ APICDisable()

VOID APICDisable ( VOID )

Definition at line 211 of file apic.c.

{
  ULONG tmp;
 
  APICClear();
 
  /*
   * Disable APIC (implies clearing of registers for 82489DX!).
   */
  tmp = APICRead(APIC_SIVR);
  tmp &= ~APIC_SIVR_ENABLE;
  APICWrite(APIC_SIVR, tmp);
}

◆ APICDump()

VOID APICDump ( VOID )

Definition at line 245 of file apic.c.

{
  ULONG v, ver, maxlvt;
  ULONG r1, r2, w1, w2;
  ULONG CPU = ThisCPU();
 
 
  r1 = lastregr[CPU];
  r2 = lastvalr[CPU];
  w1 = lastregw[CPU];
  w2 = lastvalw[CPU];
 
  DbgPrint("\nPrinting local APIC contents on CPU(%d):\n", ThisCPU());
  v = APICRead(APIC_ID);
  DbgPrint("... ID     : %08x (%01x) ", v, GET_APIC_ID(v));
  v = APICRead(APIC_VER);
  DbgPrint("... VERSION: %08x\n", v);
  ver = GET_APIC_VERSION(v);
  maxlvt = APICGetMaxLVT();
 
  v = APICRead(APIC_TPR);
  DbgPrint("... TPR    : %08x (%02x)", v, v & ~0);
 
  if (APIC_INTEGRATED(ver))
  {
     /* !82489DX */
     v = APICRead(APIC_APR);
     DbgPrint("... APR    : %08x (%02x)\n", v, v & ~0);
     v = APICRead(APIC_PPR);
     DbgPrint("... PPR    : %08x\n", v);
  }
 
  v = APICRead(APIC_EOI);
  DbgPrint("... EOI    : %08x  !  ", v);
  v = APICRead(APIC_LDR);
  DbgPrint("... LDR    : %08x\n", v);
  v = APICRead(APIC_DFR);
  DbgPrint("... DFR    : %08x  !  ", v);
  v = APICRead(APIC_SIVR);
  DbgPrint("... SIVR   : %08x\n", v);
 
  if (0)
  {
    DbgPrint("... ISR field:\n");
    APICDumpBit(APIC_ISR);
    DbgPrint("... TMR field:\n");
    APICDumpBit(APIC_TMR);
    DbgPrint("... IRR field:\n");
    APICDumpBit(APIC_IRR);
  }
 
  if (APIC_INTEGRATED(ver))
  {
     /* !82489DX */
     if (maxlvt > 3)
     {
    /* Due to the Pentium erratum 3AP. */
    APICWrite(APIC_ESR, 0);
     }
     v = APICRead(APIC_ESR);
     DbgPrint("... ESR    : %08x\n", v);
  }
 
  v = APICRead(APIC_ICR0);
  DbgPrint("... ICR0   : %08x  !  ", v);
  v = APICRead(APIC_ICR1);
  DbgPrint("... ICR1   : %08x  !  ", v);
 
  v = APICRead(APIC_LVTT);
  DbgPrint("... LVTT   : %08x\n", v);
 
  if (maxlvt > 3)
  {
     /* PC is LVT#4. */
     v = APICRead(APIC_LVTPC);
     DbgPrint("... LVTPC  : %08x  !  ", v);
  }
  v = APICRead(APIC_LINT0);
  DbgPrint("... LINT0  : %08x  !  ", v);
  v = APICRead(APIC_LINT1);
  DbgPrint("... LINT1  : %08x\n", v);
 
  if (maxlvt > 2)
  {
     v = APICRead(APIC_LVT3);
     DbgPrint("... LVT3   : %08x\n", v);
  }
 
  v = APICRead(APIC_ICRT);
  DbgPrint("... ICRT   : %08x  !  ", v);
  v = APICRead(APIC_CCRT);
  DbgPrint("... CCCT   : %08x  !  ", v);
  v = APICRead(APIC_TDCR);
  DbgPrint("... TDCR   : %08x\n", v);
  DbgPrint("\n");
  DbgPrint("Last register read (offset): 0x%08X\n", r1);
  DbgPrint("Last register read (value): 0x%08X\n", r2);
  DbgPrint("Last register written (offset): 0x%08X\n", w1);
  DbgPrint("Last register written (value): 0x%08X\n", w2);
  DbgPrint("\n");
}

Referenced by MpsErrorHandler(), and MpsSpuriousHandler().

◆ APICDumpBit()

static VOID APICDumpBit ( ULONG base )

static

Definition at line 225 of file apic.c.

{
    ULONG v, i, j;
 
    DbgPrint("0123456789abcdef0123456789abcdef\n");
    for (i = 0; i < 8; i++)
    {
        v = APICRead(base + i*0x10);
        for (j = 0; j < 32; j++)
        {
            if (v & (1<<j))
                DbgPrint("1");
            else
                DbgPrint("0");
        }
        DbgPrint("\n");
    }
}

Referenced by APICDump().

◆ APICGetMaxLVT()

ULONG APICGetMaxLVT ( VOID )

Definition at line 99 of file apic.c.

{
  ULONG tmp, ver, maxlvt;
 
  tmp = APICRead(APIC_VER);
  ver = GET_APIC_VERSION(tmp);
  /* 82489DXs do not report # of LVT entries. */
  maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(tmp) : 2;
 
  return maxlvt;
}

Referenced by APICClear(), APICDump(), APICSetup(), DumpESR(), and VerifyLocalAPIC().

◆ APICSetup()

VOID APICSetup ( VOID )

Definition at line 482 of file apic.c.

{
   ULONG CPU, tmp;
 
   CPU = ThisCPU();
 
//   APICDump();
 
   DPRINT1("CPU%d:\n", CPU);
   DPRINT1("  Physical APIC id: %d\n", GET_APIC_ID(APICRead(APIC_ID)));
   DPRINT1("  Logical APIC id:  %d\n", GET_APIC_LOGICAL_ID(APICRead(APIC_LDR)));
   DPRINT1("%08x %08x %08x\n", APICRead(APIC_ID), APICRead(APIC_LDR), APICRead(APIC_DFR));
 
   /*
    * Intel recommends to set DFR, LDR and TPR before enabling
    * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
    * document number 292116).  So here it goes...
    */
 
   /*
    * Put the APIC into flat delivery mode.
    * Must be "all ones" explicitly for 82489DX.
    */
   APICWrite(APIC_DFR, 0xFFFFFFFF);
 
   /*
    * Set up the logical destination ID.
    */
   tmp = APICRead(APIC_LDR);
   tmp &= ~APIC_LDR_MASK;
   /*
    * FIXME:
    *   This works only up to 8 CPU's
    */
   tmp |= (1 << (KeGetCurrentProcessorNumber() + 24));
   APICWrite(APIC_LDR, tmp);
 
 
   DPRINT1("CPU%d:\n", CPU);
   DPRINT1("  Physical APIC id: %d\n", GET_APIC_ID(APICRead(APIC_ID)));
   DPRINT1("  Logical APIC id:  %d\n", GET_APIC_LOGICAL_ID(APICRead(APIC_LDR)));
   DPRINT1("%08x %08x %08x\n", APICRead(APIC_ID), APICRead(APIC_LDR), APICRead(APIC_DFR));
   DPRINT1("%d\n", CPUMap[CPU].APICId);
 
   /* Accept only higher interrupts */
   APICWrite(APIC_TPR, 0xef);
 
   /* Enable local APIC */
   tmp = APICRead(APIC_SIVR);
   tmp &= ~0xff;
   tmp |= APIC_SIVR_ENABLE;
 
#if 0
   tmp &= ~APIC_SIVR_FOCUS;
#else
   tmp |= APIC_SIVR_FOCUS;
#endif
 
  /* Set spurious interrupt vector */
  tmp |= SPURIOUS_VECTOR;
  APICWrite(APIC_SIVR, tmp);
 
  /*
   * Set up LVT0, LVT1:
   *
   * set up through-local-APIC on the BP's LINT0. This is not
   * strictly necessery in pure symmetric-IO mode, but sometimes
   * we delegate interrupts to the 8259A.
   */
  tmp = APICRead(APIC_LINT0) & APIC_LVT_MASKED;
  if (CPU == BootCPU && (APICMode == amPIC || !tmp))
  {
     tmp = APIC_DM_EXTINT;
     DPRINT1("enabled ExtINT on CPU#%d\n", CPU);
  }
  else
  {
     tmp = APIC_DM_EXTINT | APIC_LVT_MASKED;
     DPRINT1("masked ExtINT on CPU#%d\n", CPU);
  }
  APICWrite(APIC_LINT0, tmp);
 
  /*
   * Only the BSP should see the LINT1 NMI signal, obviously.
   */
  if (CPU == BootCPU)
  {
     tmp = APIC_DM_NMI;
  }
  else
  {
     tmp = APIC_DM_NMI | APIC_LVT_MASKED;
  }
  if (!APIC_INTEGRATED(CPUMap[CPU].APICVersion))
  {
     /* 82489DX */
     tmp |= APIC_LVT_LEVEL_TRIGGER;
  }
  APICWrite(APIC_LINT1, tmp);
 
  if (APIC_INTEGRATED(CPUMap[CPU].APICVersion))
  {
     /* !82489DX */
     if (APICGetMaxLVT() > 3)
     {
    /* Due to the Pentium erratum 3AP */
    APICWrite(APIC_ESR, 0);
     }
 
     tmp = APICRead(APIC_ESR);
     DPRINT("ESR value before enabling vector: 0x%X\n", tmp);
 
     /* Enable sending errors */
     tmp = ERROR_VECTOR;
     APICWrite(APIC_LVT3, tmp);
 
     /*
      * Spec says clear errors after enabling vector
      */
     if (APICGetMaxLVT() > 3)
     {
        APICWrite(APIC_ESR, 0);
     }
     tmp = APICRead(APIC_ESR);
     DPRINT("ESR value after enabling vector: 0x%X\n", tmp);
  }
}

Referenced by HaliInitBSP(), and HalInitializeProcessor().

◆ APICSetupLVTT()

VOID APICSetupLVTT ( ULONG ClockTicks )

Definition at line 770 of file apic.c.

{
   ULONG tmp;
 
   tmp = GET_APIC_VERSION(APICRead(APIC_VER));
   if (!APIC_INTEGRATED(tmp))
   {
      tmp = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) | APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;
   }
   else
   {
      /* Periodic timer */
      tmp = APIC_LVT_PERIODIC | LOCAL_TIMER_VECTOR;
   }
   APICWrite(APIC_LVTT, tmp);
 
   tmp = APICRead(APIC_TDCR);
   tmp &= ~(APIC_TDCR_1 | APIC_TIMER_BASE_DIV);
   tmp |= APIC_TDCR_16;
   APICWrite(APIC_TDCR, tmp);
   APICWrite(APIC_ICRT, ClockTicks / APIC_DIVISOR);
}

Referenced by APICCalibrateTimer().

◆ DisableSMPMode()

__inline VOID DisableSMPMode ( VOID )

Definition at line 186 of file apic.c.

{
   /*
    * Put the board back into PIC mode (has an effect
    * only on certain older boards).  Note that APIC
    * interrupts, including IPIs, won't work beyond
    * this point!  The only exception are INIT IPIs.
    */
   WRITE_PORT_UCHAR((PUCHAR)0x22, 0x70);
   WRITE_PORT_UCHAR((PUCHAR)0x23, 0x00);
}

◆ DumpESR()

VOID DumpESR ( VOID )

Definition at line 198 of file apic.c.

{
  ULONG tmp;
 
  if (APICGetMaxLVT() > 3)
  {
    APICWrite(APIC_ESR, 0);
  }
  tmp = APICRead(APIC_ESR);
  DbgPrint("ESR %08x\n", tmp);
}

◆ EnableApicMode()

VOID EnableApicMode ( VOID )

Definition at line 174 of file apic.c.

{
   /*
    * Do not trust the local APIC being empty at bootup.
    */
   APICClear();
 
   WRITE_PORT_UCHAR((PUCHAR)0x22, 0x70);
   WRITE_PORT_UCHAR((PUCHAR)0x23, 0x01);
}

Referenced by HaliInitBSP().

◆ HaliInitBSP()

VOID HaliInitBSP ( VOID )

Definition at line 886 of file apic.c.

{
#ifdef CONFIG_SMP
   PUSHORT ps;
#endif
 
   static BOOLEAN BSPInitialized = FALSE;
 
   /* Only initialize the BSP once */
   if (BSPInitialized)
   {
      ASSERT(FALSE);
      return;
   }
 
   BSPInitialized = TRUE;
 
   /* Setup interrupt handlers */
   SetInterruptGate(LOCAL_TIMER_VECTOR, (ULONG_PTR)MpsTimerInterrupt);
   SetInterruptGate(ERROR_VECTOR, (ULONG_PTR)MpsErrorInterrupt);
   SetInterruptGate(SPURIOUS_VECTOR, (ULONG_PTR)MpsSpuriousInterrupt);
#ifdef CONFIG_SMP
   SetInterruptGate(IPI_VECTOR, (ULONG_PTR)MpsIpiInterrupt);
#endif
   DPRINT("APIC is mapped at 0x%X\n", APICBase);
 
   if (VerifyLocalAPIC())
   {
      DPRINT("APIC found\n");
   }
   else
   {
      DPRINT("No APIC found\n");
      ASSERT(FALSE);
   }
 
   if (APICMode == amPIC)
   {
      EnableApicMode();
   }
 
   APICSetup();
 
#ifdef CONFIG_SMP
   /* BIOS data segment */
   BIOSBase = (PULONG)BIOS_AREA;
 
   /* Area for communicating with the APs */
   CommonBase = (PULONG)COMMON_AREA;
 
   /* Copy bootstrap code to common area */
   memcpy((PVOID)((ULONG_PTR)CommonBase + PAGE_SIZE),
      &APstart,
      (ULONG_PTR)&APend - (ULONG_PTR)&APstart + 1);
 
   /* Set shutdown code */
   CMOS_WRITE(0xF, 0xA);
 
   /* Set warm reset vector */
   ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x467);
   *ps = (COMMON_AREA + PAGE_SIZE) & 0xF;
 
   ps = (PUSHORT)((ULONG_PTR)BIOSBase + 0x469);
   *ps = (COMMON_AREA + PAGE_SIZE) >> 4;
#endif
 
   /* Calibrate APIC timer */
   APICCalibrateTimer(BootCPU);
}

Referenced by HalInitializeProcessor().

◆ HalpApcInterruptHandler()

VOID FASTCALL DECLSPEC_NORETURN HalpApcInterruptHandler ( IN PKTRAP_FRAME TrapFrame )

Definition at line 1115 of file apic.c.

{
    /* Set up a fake INT Stack */
    TrapFrame->EFlags = __readeflags();
    TrapFrame->SegCs = KGDT_R0_CODE;
    TrapFrame->Eip = TrapFrame->Eax;
 
    /* Build the trap frame */
    KiEnterInterruptTrap(TrapFrame);
 
    /* unimplemented */
    UNIMPLEMENTED;
 
    /* Exit the interrupt */
    KiEoiHelper(TrapFrame);
 
}

◆ MpsErrorHandler()

VOID MpsErrorHandler ( VOID )

Definition at line 634 of file apic.c.

{
  ULONG tmp1, tmp2;
 
  APICDump();
 
  tmp1 = APICRead(APIC_ESR);
  APICWrite(APIC_ESR, 0);
  tmp2 = APICRead(APIC_ESR);
  DPRINT1("APIC error on CPU(%d) ESR(%x)(%x)\n", ThisCPU(), tmp1, tmp2);
 
  /*
   * Acknowledge the interrupt
   */
  APICSendEOI();
 
  /* Here is what the APIC error bits mean:
   *   0: Send CS error
   *   1: Receive CS error
   *   2: Send accept error
   *   3: Receive accept error
   *   4: Reserved
   *   5: Send illegal vector
   *   6: Received illegal vector
   *   7: Illegal register address
   */
  DPRINT1("APIC error on CPU(%d) ESR(%x)(%x)\n", ThisCPU(), tmp1, tmp2);
  for (;;);
}

◆ MpsErrorInterrupt()

VOID MpsErrorInterrupt ( VOID )

Referenced by HaliInitBSP().

◆ MpsIpiInterrupt()

VOID MpsIpiInterrupt ( VOID )

Referenced by HaliInitBSP().

◆ MpsIRQTrapFrameToTrapFrame()

VOID MpsIRQTrapFrameToTrapFrame	(	PKIRQ_TRAPFRAME	IrqTrapFrame,
		PKTRAP_FRAME	TrapFrame
	)

Definition at line 708 of file apic.c.

{
#ifdef _M_AMD64
    UNIMPLEMENTED;
#else
   TrapFrame->SegGs     = (USHORT)IrqTrapFrame->Gs;
   TrapFrame->SegFs     = (USHORT)IrqTrapFrame->Fs;
   TrapFrame->SegEs     = (USHORT)IrqTrapFrame->Es;
   TrapFrame->SegDs     = (USHORT)IrqTrapFrame->Ds;
   TrapFrame->Eax    = IrqTrapFrame->Eax;
   TrapFrame->Ecx    = IrqTrapFrame->Ecx;
   TrapFrame->Edx    = IrqTrapFrame->Edx;
   TrapFrame->Ebx    = IrqTrapFrame->Ebx;
   TrapFrame->HardwareEsp    = IrqTrapFrame->Esp;
   TrapFrame->Ebp    = IrqTrapFrame->Ebp;
   TrapFrame->Esi    = IrqTrapFrame->Esi;
   TrapFrame->Edi    = IrqTrapFrame->Edi;
   TrapFrame->Eip    = IrqTrapFrame->Eip;
   TrapFrame->SegCs     = IrqTrapFrame->Cs;
   TrapFrame->EFlags = IrqTrapFrame->Eflags;
#endif
}

Referenced by MpsTimerHandler().

◆ MpsSpuriousHandler()

VOID MpsSpuriousHandler ( VOID )

Definition at line 664 of file apic.c.

{
  ULONG tmp;
 
  DPRINT("Spurious interrupt on CPU(%d)\n", ThisCPU());
 
  tmp = APICRead(APIC_ISR + ((SPURIOUS_VECTOR & ~0x1f) >> 1));
  if (tmp & (1 << (SPURIOUS_VECTOR & 0x1f)))
  {
      APICSendEOI();
      return;
  }
#if 0
  /* No need to send EOI here */
  APICDump();
#endif
}

◆ MpsSpuriousInterrupt()

VOID MpsSpuriousInterrupt ( VOID )

Referenced by HaliInitBSP().

◆ MpsTimerHandler()

VOID MpsTimerHandler	(	ULONG	Vector,
		PKIRQ_TRAPFRAME	Trapframe
	)

Definition at line 733 of file apic.c.

{
   KIRQL oldIrql;
   KTRAP_FRAME KernelTrapFrame;
#if 0
   ULONG CPU;
   static ULONG Count[MAX_CPU] = {0,};
#endif
   HalBeginSystemInterrupt(LOCAL_TIMER_VECTOR,
                           PROFILE_LEVEL,
               &oldIrql);
   _enable();
 
#if 0
   CPU = ThisCPU();
   if ((Count[CPU] % 100) == 0)
   {
     DbgPrint("(%s:%d) MpsTimerHandler on CPU%d, irql = %d, epi = %x, KPCR = %x\n", __FILE__, __LINE__, CPU, oldIrql,Trapframe->Eip, KeGetPcr());
   }
   Count[CPU]++;
#endif
 
   /* FIXME: SMP is totally broken */
   MpsIRQTrapFrameToTrapFrame(Trapframe, &KernelTrapFrame);
   if (KeGetCurrentProcessorNumber() == 0)
   {
      //KeUpdateSystemTime(&KernelTrapFrame, oldIrql);
   }
   else
   {
      //KeUpdateRunTime(&KernelTrapFrame, oldIrql);
   }
 
   _disable();
   HalEndSystemInterrupt (oldIrql, 0);
}

◆ MpsTimerInterrupt()

VOID MpsTimerInterrupt ( VOID )

Referenced by HaliInitBSP().

◆ Read8254Timer()

ULONG Read8254Timer ( VOID )

◆ SetInterruptGate()

VOID SetInterruptGate	(	ULONG	index,
		ULONG_PTR	address
	)

Definition at line 849 of file apic.c.

{
#ifdef _M_AMD64
  KIDTENTRY64 *idt;
 
  idt = &KeGetPcr()->IdtBase[index];
 
  idt->OffsetLow = address & 0xffff;
  idt->Selector = KGDT_64_R0_CODE;
  idt->IstIndex = 0;
  idt->Reserved0 = 0;
  idt->Type = 0x0e;
  idt->Dpl = 0;
  idt->Present = 1;
  idt->OffsetMiddle = (address >> 16) & 0xffff;
  idt->OffsetHigh = address >> 32;
  idt->Reserved1 = 0;
  idt->Alignment = 0;
#else
  KIDTENTRY *idt;
  KIDT_ACCESS Access;
 
  /* Set the IDT Access Bits */
  Access.Reserved = 0;
  Access.Present = 1;
  Access.Dpl = 0; /* Kernel-Mode */
  Access.SystemSegmentFlag = 0;
  Access.SegmentType = I386_INTERRUPT_GATE;
 
  idt = (KIDTENTRY*)((ULONG)KeGetPcr()->IDT + index * sizeof(KIDTENTRY));
  idt->Offset = (USHORT)(address & 0xffff);
  idt->Selector = KGDT_R0_CODE;
  idt->Access = Access.Value;
  idt->ExtendedOffset = (USHORT)(address >> 16);
#endif
}

Referenced by HaliInitBSP().

◆ VerifyLocalAPIC()

BOOLEAN VerifyLocalAPIC ( VOID )

Definition at line 350 of file apic.c.

{
   SIZE_T reg0, reg1;
   LARGE_INTEGER MsrValue;
 
   /* The version register is read-only in a real APIC */
   reg0 = APICRead(APIC_VER);
   DPRINT1("Getting VERSION: %x\n", reg0);
   APICWrite(APIC_VER, reg0 ^ APIC_VER_MASK);
   reg1 = APICRead(APIC_VER);
   DPRINT1("Getting VERSION: %x\n", reg1);
 
   /*
    * The two version reads above should print the same
    * numbers.  If the second one is different, then we
    * poke at a non-APIC.
    */
 
   if (reg1 != reg0)
   {
      return FALSE;
   }
 
   /*
    * Check if the version looks reasonably.
    */
   reg1 = GET_APIC_VERSION(reg0);
   if (reg1 == 0x00 || reg1 == 0xff)
   {
      return FALSE;
   }
   reg1 = APICGetMaxLVT();
   if (reg1 < 0x02 || reg1 == 0xff)
   {
      return FALSE;
   }
 
   /*
    * The ID register is read/write in a real APIC.
    */
   reg0 = APICRead(APIC_ID);
   DPRINT1("Getting ID: %x\n", reg0);
   APICWrite(APIC_ID, reg0 ^ APIC_ID_MASK);
   reg1 = APICRead(APIC_ID);
   DPRINT1("Getting ID: %x\n", reg1);
   APICWrite(APIC_ID, reg0);
   if (reg1 != (reg0 ^ APIC_ID_MASK))
   {
      return FALSE;
   }
 
   MsrValue.QuadPart = __readmsr(0x1B /*MSR_IA32_APICBASE*/);
 
   if (!(MsrValue.LowPart & /*MSR_IA32_APICBASE_ENABLE*/(1<<11)))
   {
      DPRINT1("Local APIC disabled by BIOS -- reenabling.\n");
      MsrValue.LowPart &= ~/*MSR_IA32_APICBASE_BASE*/(1<<11);
      MsrValue.LowPart |= /*MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE*/(1<<11)|0xfee00000;
      __writemsr(0x1B /*MSR_IA32_APICBASE*/, MsrValue.HighPart);
   }
 
 
 
   return TRUE;
}

Referenced by HaliInitBSP().

◆ WaitFor8254Wraparound()

VOID WaitFor8254Wraparound ( VOID )

Variable Documentation

◆ APend

CHAR * APend

Definition at line 70 of file apic.c.

Referenced by HaliInitBSP().

◆ APICBase

PULONG APICBase = (PULONG)APIC_DEFAULT_BASE

Definition at line 47 of file apic.c.

Referenced by HaliInitBSP().

◆ APICMode

ULONG APICMode

Definition at line 49 of file apic.c.

Referenced by APICSetup(), HaliGetSmpConfig(), and HaliInitBSP().

◆ APstart

CHAR* APstart

extern

Referenced by HaliInitBSP().

◆ BootCPU

ULONG BootCPU

Definition at line 38 of file apic.c.

Referenced by APICSetup(), HaliInitBSP(), and HaliMPProcessorInfo().

◆ CPUCount

ULONG CPUCount

Definition at line 37 of file apic.c.

Referenced by HalAllProcessorsStarted(), HaliMPProcessorInfo(), and HalStartNextProcessor().

◆ CPUMap

CPU_INFO CPUMap[MAX_CPU]

Definition at line 40 of file apic.c.

Referenced by APICCalibrateTimer(), APICSetup(), HaliMPProcessorInfo(), and HalInitializeProcessor().

◆ KernelBase

ULONG_PTR KernelBase

extern

Definition at line 20 of file halinit_mp.c.

Referenced by HalpInitPhase0(), and LoadWindowsCore().

◆ lastregr

ULONG lastregr[MAX_CPU]

Definition at line 52 of file apic.c.

Referenced by APICDump().

◆ lastregw

ULONG lastregw[MAX_CPU]

Definition at line 54 of file apic.c.

Referenced by APICDump().

◆ lastvalr

ULONG lastvalr[MAX_CPU]

Definition at line 53 of file apic.c.

Referenced by APICDump().

◆ lastvalw

ULONG lastvalw[MAX_CPU]

Definition at line 55 of file apic.c.

Referenced by APICDump().

◆ OnlineCPUs

ULONG OnlineCPUs

Definition at line 39 of file apic.c.

Referenced by HalAllProcessorsStarted(), HalInitializeProcessor(), and HalStartNextProcessor().

Macros

Functions

Variables

Macro Definition Documentation

◆ APIC_DIVISOR

◆ BIOS_AREA

◆ CMOS_READ

◆ CMOS_WRITE

◆ COMMON_AREA

◆ HZ

◆ NDEBUG

Function Documentation

◆ APICCalibrateTimer()

◆ APICClear()

◆ APICDisable()

◆ APICDump()

◆ APICDumpBit()

◆ APICGetMaxLVT()

◆ APICSetup()

◆ APICSetupLVTT()

◆ DisableSMPMode()

◆ DumpESR()

◆ EnableApicMode()

◆ HaliInitBSP()

◆ HalpApcInterruptHandler()

◆ MpsErrorHandler()

◆ MpsErrorInterrupt()

◆ MpsIpiInterrupt()

◆ MpsIRQTrapFrameToTrapFrame()

◆ MpsSpuriousHandler()

◆ MpsSpuriousInterrupt()

◆ MpsTimerHandler()

◆ MpsTimerInterrupt()

◆ Read8254Timer()

◆ SetInterruptGate()

◆ VerifyLocalAPIC()

◆ WaitFor8254Wraparound()

Variable Documentation

◆ APend

◆ APICBase

◆ APICMode

◆ APstart

◆ BootCPU

◆ CPUCount

◆ CPUMap

◆ KernelBase

◆ lastregr

◆ lastregw

◆ lastvalr

◆ lastvalw

◆ OnlineCPUs