ReactOS 0.4.16-dev-334-g4d9f67c
Classes | Macros | Typedefs | Functions
8390.h File Reference
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Classes

struct  _PACKET_HEADER
 
struct  _ETH_HEADER
 
struct  _DISCARD_HEADER
 

Macros

#define PG0_CR   0x00 /* Command Register (R/W) */
 
#define PG0_CLDA0   0x01 /* Current Local DMA Address 0 (R) */
 
#define PG0_PSTART   0x01 /* Page Start Register (W) */
 
#define PG0_CLDA1   0x02 /* Current Local DMA Address 1 (R) */
 
#define PG0_PSTOP   0x02 /* Page Stop Register (W) */
 
#define PG0_BNRY   0x03 /* Boundary Pointer (R/W) */
 
#define PG0_TSR   0x04 /* Transmit Status Register (R) */
 
#define PG0_TPSR   0x04 /* Transmit Page Start Register (W) */
 
#define PG0_NCR   0x05 /* Number of Collisions Register (R) */
 
#define PG0_TBCR0   0x05 /* Transmit Byte Count Register 0 (W) */
 
#define PG0_FIFO   0x06 /* FIFO (R) */
 
#define PG0_TBCR1   0x06 /* Transmit Byte Count Register 1 (W) */
 
#define PG0_ISR   0x07 /* Interrupt Status Register (R/W) */
 
#define PG0_CRDA0   0x08 /* Current Remote DMA Address 0 (R) */
 
#define PG0_RSAR0   0x08 /* Remote Start Address Register 0 (W) */
 
#define PG0_CRDA1   0x09 /* Current Remote DMA Address 1 (R) */
 
#define PG0_RSAR1   0x09 /* Remote Start Address Register 1 (W) */
 
#define PG0_RBCR0   0x0A /* Remote Byte Count Register 0 (W) */
 
#define PG0_RBCR1   0x0B /* Remote Byte Count Register 1 (W) */
 
#define PG0_RSR   0x0C /* Receive Status Register (R) */
 
#define PG0_RCR   0x0C /* Receive Configuration Register (W) */
 
#define PG0_CNTR0   0x0D /* Tally Counter 0 (Frame Alignment Errors) (R) */
 
#define PG0_TCR   0x0D /* Transmit Configuration Register (W) */
 
#define PG0_CNTR1   0x0E /* Tally Counter 1 (CRC Errors) (R) */
 
#define PG0_DCR   0x0E /* Data Configuration Register (W) */
 
#define PG0_CNTR2   0x0F /* Tally Counter 2 (Missed Packet Errors) (R) */
 
#define PG0_IMR   0x0F /* Interrupt Mask Register (W) */
 
#define PG1_CR   0x00 /* Command Register (R/W) */
 
#define PG1_PAR   0x01 /* Physical Address Registers (6 registers) (R/W) */
 
#define PG1_CURR   0x07 /* Current Page Register (R/W) */
 
#define PG1_MAR   0x08 /* Multicast Address Registers (8 registers) (R/W) */
 
#define PG2_CR   0x00 /* Command Register (R/W) */
 
#define PG2_PSTART   0x01 /* Page Start Register (R) */
 
#define PG2_CLDA0   0x01 /* Current Local DMA Address 0 (W) */
 
#define PG2_PSTOP   0x02 /* Page Stop Register (R) */
 
#define PG2_CLDA1   0x02 /* Current Local DMA Address 1 (W) */
 
#define PG2_RNPP   0x03 /* Remote Next Packet Pointer (R/W) */
 
#define PG2_TPSR   0x04 /* Transmit Page Start Address (R) */
 
#define PG2_LNPP   0x05 /* Local Next Packet Pointer (R/W) */
 
#define PG2_AC1   0x06 /* Address Counter (Upper) (R/W) */
 
#define PG2_AC0   0x07 /* Address Counter (Lower) (R/W) */
 
#define PG2_RCR   0x0C /* Receive Configuration Register (R) */
 
#define PG2_TCR   0x0D /* Transmit Configuration Register (R) */
 
#define PG2_DCR   0x0E /* Data Configuration Register (R) */
 
#define PG2_IMR   0x0F /* Interrupt Mask Register (R) */
 
#define CR_STP   0x01 /* Stop chip */
 
#define CR_STA   0x02 /* Start chip */
 
#define CR_TXP   0x04 /* Transmit a frame */
 
#define CR_RD0   0x08 /* Remote read */
 
#define CR_RD1   0x10 /* Remote write */
 
#define CR_RD2   0x20 /* Abort/complete remote DMA */
 
#define CR_PAGE0   0x00 /* Select page 0 of chip registers */
 
#define CR_PAGE1   0x40 /* Select page 1 of chip registers */
 
#define CR_PAGE2   0x80 /* Select page 2 of chip registers */
 
#define ISR_PRX   0x01 /* Packet received, no errors */
 
#define ISR_PTX   0x02 /* Packet transmitted, no errors */
 
#define ISR_RXE   0x04 /* Receive error */
 
#define ISR_TXE   0x08 /* Transmit error */
 
#define ISR_OVW   0x10 /* Overwrite warning */
 
#define ISR_CNT   0x20 /* Counter overflow */
 
#define ISR_RDC   0x40 /* Remote DMA complete */
 
#define ISR_RST   0x80 /* Reset status */
 
#define TSR_PTX   0x01h /* Packet transmitted without error */
 
#define TSR_COL   0x04h /* Collided at least once */
 
#define TSR_ABT   0x08h /* Collided 16 times and was dropped */
 
#define TSR_CRS   0x10h /* Carrier sense lost */
 
#define TSR_FU   0x20h /* Transmit FIFO Underrun */
 
#define TSR_CDH   0x40h /* Collision detect heartbeat */
 
#define TSR_OWC   0x80h /* Out of window collision */
 
#define RCR_SEP   0x01 /* Save error packets */
 
#define RCR_AR   0x02 /* Accept runt packets */
 
#define RCR_AB   0x04 /* Accept broadcasts */
 
#define RCR_AM   0x08 /* Accept multicast */
 
#define RCR_PRO   0x10 /* Promiscuous physical addresses */
 
#define RCR_MON   0x20 /* Monitor mode */
 
#define RSR_PRX   0x01 /* Received packet intact */
 
#define RSR_CRC   0x02 /* CRC error */
 
#define RSR_FAE   0x04 /* Frame alignment error */
 
#define RSR_FO   0x08 /* FIFO overrun */
 
#define RSR_MPA   0x10 /* Missed packet */
 
#define RSR_PHY   0x20 /* Physical/multicast address */
 
#define RSR_DIS   0x40 /* Receiver disabled (monitor mode) */
 
#define RSR_DFR   0x80 /* Deferring */
 
#define TCR_CRC   0x01 /* Inhibit CRC, do not append CRC */
 
#define TCR_LOOP   0x02 /* Set loopback mode */
 
#define TCR_LB01   0x06 /* Encoded loopback control */
 
#define TCR_ATD   0x08 /* Auto transmit disable */
 
#define TCR_OFST   0x10 /* Collision offset enable */
 
#define DCR_WTS   0x01 /* Word transfer mode selection */
 
#define DCR_BOS   0x02 /* Byte order selection */
 
#define DCR_LAS   0x04 /* Long address selection */
 
#define DCR_LS   0x08 /* Loopback select (when 0) */
 
#define DCR_ARM   0x10 /* Autoinitialize remote */
 
#define DCR_FT00   0x00 /* Burst length selection (1 word/2 bytes) */
 
#define DCR_FT01   0x20 /* burst length selection (2 words/4 bytes) */
 
#define DCR_FT10   0x40 /* Burst length selection (4 words/8 bytes) */
 
#define DCR_FT11   0x60 /* Burst length selection (6 words/12 bytes) */
 
#define IMR_PRXE   0x01 /* Packet received interrupt enable */
 
#define IMR_PTXE   0x02 /* Packet transmitted interrupt enable */
 
#define IMR_RXEE   0x04 /* Receive error interrupt enable */
 
#define IMR_TXEE   0x08 /* Transmit error interrupt enable */
 
#define IMR_OVWE   0x10 /* Overwrite warning interrupt enable */
 
#define IMR_CNTE   0x20 /* Counter overflow interrupt enable */
 
#define IMR_RDCE   0x40 /* Remote DMA complete interrupt enable */
 
#define IMR_ALLE   0x7F /* All interrupts enable */
 
#define IEEE_802_ADDR_LENGTH   6
 
#define NICDisableInterrupts(Adapter)
 
#define NICEnableInterrupts(Adapter)
 

Typedefs

typedef struct _PACKET_HEADER PACKET_HEADER
 
typedef struct _PACKET_HEADER * PPACKET_HEADER
 
typedef struct _ETH_HEADER ETH_HEADER
 
typedef struct _ETH_HEADER * PETH_HEADER
 
typedef struct _DISCARD_HEADER DISCARD_HEADER
 
typedef struct _DISCARD_HEADER * PDISCARD_HEADER
 

Functions

VOID NTAPI MiniportHandleInterrupt (IN NDIS_HANDLE MiniportAdapterContext)
 

Macro Definition Documentation

◆ CR_PAGE0

#define CR_PAGE0   0x00 /* Select page 0 of chip registers */

Definition at line 68 of file 8390.h.

◆ CR_PAGE1

#define CR_PAGE1   0x40 /* Select page 1 of chip registers */

Definition at line 69 of file 8390.h.

◆ CR_PAGE2

#define CR_PAGE2   0x80 /* Select page 2 of chip registers */

Definition at line 70 of file 8390.h.

◆ CR_RD0

#define CR_RD0   0x08 /* Remote read */

Definition at line 65 of file 8390.h.

◆ CR_RD1

#define CR_RD1   0x10 /* Remote write */

Definition at line 66 of file 8390.h.

◆ CR_RD2

#define CR_RD2   0x20 /* Abort/complete remote DMA */

Definition at line 67 of file 8390.h.

◆ CR_STA

#define CR_STA   0x02 /* Start chip */

Definition at line 63 of file 8390.h.

◆ CR_STP

#define CR_STP   0x01 /* Stop chip */

Definition at line 62 of file 8390.h.

◆ CR_TXP

#define CR_TXP   0x04 /* Transmit a frame */

Definition at line 64 of file 8390.h.

◆ DCR_ARM

#define DCR_ARM   0x10 /* Autoinitialize remote */

Definition at line 121 of file 8390.h.

◆ DCR_BOS

#define DCR_BOS   0x02 /* Byte order selection */

Definition at line 118 of file 8390.h.

◆ DCR_FT00

#define DCR_FT00   0x00 /* Burst length selection (1 word/2 bytes) */

Definition at line 122 of file 8390.h.

◆ DCR_FT01

#define DCR_FT01   0x20 /* burst length selection (2 words/4 bytes) */

Definition at line 123 of file 8390.h.

◆ DCR_FT10

#define DCR_FT10   0x40 /* Burst length selection (4 words/8 bytes) */

Definition at line 124 of file 8390.h.

◆ DCR_FT11

#define DCR_FT11   0x60 /* Burst length selection (6 words/12 bytes) */

Definition at line 125 of file 8390.h.

◆ DCR_LAS

#define DCR_LAS   0x04 /* Long address selection */

Definition at line 119 of file 8390.h.

◆ DCR_LS

#define DCR_LS   0x08 /* Loopback select (when 0) */

Definition at line 120 of file 8390.h.

◆ DCR_WTS

#define DCR_WTS   0x01 /* Word transfer mode selection */

Definition at line 117 of file 8390.h.

◆ IEEE_802_ADDR_LENGTH

#define IEEE_802_ADDR_LENGTH   6

Definition at line 145 of file 8390.h.

◆ IMR_ALLE

#define IMR_ALLE   0x7F /* All interrupts enable */

Definition at line 135 of file 8390.h.

◆ IMR_CNTE

#define IMR_CNTE   0x20 /* Counter overflow interrupt enable */

Definition at line 133 of file 8390.h.

◆ IMR_OVWE

#define IMR_OVWE   0x10 /* Overwrite warning interrupt enable */

Definition at line 132 of file 8390.h.

◆ IMR_PRXE

#define IMR_PRXE   0x01 /* Packet received interrupt enable */

Definition at line 128 of file 8390.h.

◆ IMR_PTXE

#define IMR_PTXE   0x02 /* Packet transmitted interrupt enable */

Definition at line 129 of file 8390.h.

◆ IMR_RDCE

#define IMR_RDCE   0x40 /* Remote DMA complete interrupt enable */

Definition at line 134 of file 8390.h.

◆ IMR_RXEE

#define IMR_RXEE   0x04 /* Receive error interrupt enable */

Definition at line 130 of file 8390.h.

◆ IMR_TXEE

#define IMR_TXEE   0x08 /* Transmit error interrupt enable */

Definition at line 131 of file 8390.h.

◆ ISR_CNT

#define ISR_CNT   0x20 /* Counter overflow */

Definition at line 78 of file 8390.h.

◆ ISR_OVW

#define ISR_OVW   0x10 /* Overwrite warning */

Definition at line 77 of file 8390.h.

◆ ISR_PRX

#define ISR_PRX   0x01 /* Packet received, no errors */

Definition at line 73 of file 8390.h.

◆ ISR_PTX

#define ISR_PTX   0x02 /* Packet transmitted, no errors */

Definition at line 74 of file 8390.h.

◆ ISR_RDC

#define ISR_RDC   0x40 /* Remote DMA complete */

Definition at line 79 of file 8390.h.

◆ ISR_RST

#define ISR_RST   0x80 /* Reset status */

Definition at line 80 of file 8390.h.

◆ ISR_RXE

#define ISR_RXE   0x04 /* Receive error */

Definition at line 75 of file 8390.h.

◆ ISR_TXE

#define ISR_TXE   0x08 /* Transmit error */

Definition at line 76 of file 8390.h.

◆ NICDisableInterrupts

#define NICDisableInterrupts (   Adapter)
Value:
{ \
NDIS_DbgPrint(MAX_TRACE, ("NICDisableInterrupts()\n")); \
NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, 0x00); \
}
PG0_IMR
#define PG0_IMR
Definition: 8390.h:37
MAX_TRACE
#define MAX_TRACE
Definition: debug.h:16

Definition at line 159 of file 8390.h.

◆ NICEnableInterrupts

#define NICEnableInterrupts (   Adapter)
Value:
{ \
NDIS_DbgPrint(MAX_TRACE, ("NICEnableInterrupts() Mask (0x%X)\n", (Adapter)->InterruptMask)); \
NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, (Adapter)->InterruptMask); \
}

Definition at line 164 of file 8390.h.

◆ PG0_BNRY

#define PG0_BNRY   0x03 /* Boundary Pointer (R/W) */

Definition at line 16 of file 8390.h.

◆ PG0_CLDA0

#define PG0_CLDA0   0x01 /* Current Local DMA Address 0 (R) */

Definition at line 12 of file 8390.h.

◆ PG0_CLDA1

#define PG0_CLDA1   0x02 /* Current Local DMA Address 1 (R) */

Definition at line 14 of file 8390.h.

◆ PG0_CNTR0

#define PG0_CNTR0   0x0D /* Tally Counter 0 (Frame Alignment Errors) (R) */

Definition at line 32 of file 8390.h.

◆ PG0_CNTR1

#define PG0_CNTR1   0x0E /* Tally Counter 1 (CRC Errors) (R) */

Definition at line 34 of file 8390.h.

◆ PG0_CNTR2

#define PG0_CNTR2   0x0F /* Tally Counter 2 (Missed Packet Errors) (R) */

Definition at line 36 of file 8390.h.

◆ PG0_CR

#define PG0_CR   0x00 /* Command Register (R/W) */

Definition at line 11 of file 8390.h.

◆ PG0_CRDA0

#define PG0_CRDA0   0x08 /* Current Remote DMA Address 0 (R) */

Definition at line 24 of file 8390.h.

◆ PG0_CRDA1

#define PG0_CRDA1   0x09 /* Current Remote DMA Address 1 (R) */

Definition at line 26 of file 8390.h.

◆ PG0_DCR

#define PG0_DCR   0x0E /* Data Configuration Register (W) */

Definition at line 35 of file 8390.h.

◆ PG0_FIFO

#define PG0_FIFO   0x06 /* FIFO (R) */

Definition at line 21 of file 8390.h.

◆ PG0_IMR

#define PG0_IMR   0x0F /* Interrupt Mask Register (W) */

Definition at line 37 of file 8390.h.

◆ PG0_ISR

#define PG0_ISR   0x07 /* Interrupt Status Register (R/W) */

Definition at line 23 of file 8390.h.

◆ PG0_NCR

#define PG0_NCR   0x05 /* Number of Collisions Register (R) */

Definition at line 19 of file 8390.h.

◆ PG0_PSTART

#define PG0_PSTART   0x01 /* Page Start Register (W) */

Definition at line 13 of file 8390.h.

◆ PG0_PSTOP

#define PG0_PSTOP   0x02 /* Page Stop Register (W) */

Definition at line 15 of file 8390.h.

◆ PG0_RBCR0

#define PG0_RBCR0   0x0A /* Remote Byte Count Register 0 (W) */

Definition at line 28 of file 8390.h.

◆ PG0_RBCR1

#define PG0_RBCR1   0x0B /* Remote Byte Count Register 1 (W) */

Definition at line 29 of file 8390.h.

◆ PG0_RCR

#define PG0_RCR   0x0C /* Receive Configuration Register (W) */

Definition at line 31 of file 8390.h.

◆ PG0_RSAR0

#define PG0_RSAR0   0x08 /* Remote Start Address Register 0 (W) */

Definition at line 25 of file 8390.h.

◆ PG0_RSAR1

#define PG0_RSAR1   0x09 /* Remote Start Address Register 1 (W) */

Definition at line 27 of file 8390.h.

◆ PG0_RSR

#define PG0_RSR   0x0C /* Receive Status Register (R) */

Definition at line 30 of file 8390.h.

◆ PG0_TBCR0

#define PG0_TBCR0   0x05 /* Transmit Byte Count Register 0 (W) */

Definition at line 20 of file 8390.h.

◆ PG0_TBCR1

#define PG0_TBCR1   0x06 /* Transmit Byte Count Register 1 (W) */

Definition at line 22 of file 8390.h.

◆ PG0_TCR

#define PG0_TCR   0x0D /* Transmit Configuration Register (W) */

Definition at line 33 of file 8390.h.

◆ PG0_TPSR

#define PG0_TPSR   0x04 /* Transmit Page Start Register (W) */

Definition at line 18 of file 8390.h.

◆ PG0_TSR

#define PG0_TSR   0x04 /* Transmit Status Register (R) */

Definition at line 17 of file 8390.h.

◆ PG1_CR

#define PG1_CR   0x00 /* Command Register (R/W) */

Definition at line 40 of file 8390.h.

◆ PG1_CURR

#define PG1_CURR   0x07 /* Current Page Register (R/W) */

Definition at line 42 of file 8390.h.

◆ PG1_MAR

#define PG1_MAR   0x08 /* Multicast Address Registers (8 registers) (R/W) */

Definition at line 43 of file 8390.h.

◆ PG1_PAR

#define PG1_PAR   0x01 /* Physical Address Registers (6 registers) (R/W) */

Definition at line 41 of file 8390.h.

◆ PG2_AC0

#define PG2_AC0   0x07 /* Address Counter (Lower) (R/W) */

Definition at line 55 of file 8390.h.

◆ PG2_AC1

#define PG2_AC1   0x06 /* Address Counter (Upper) (R/W) */

Definition at line 54 of file 8390.h.

◆ PG2_CLDA0

#define PG2_CLDA0   0x01 /* Current Local DMA Address 0 (W) */

Definition at line 48 of file 8390.h.

◆ PG2_CLDA1

#define PG2_CLDA1   0x02 /* Current Local DMA Address 1 (W) */

Definition at line 50 of file 8390.h.

◆ PG2_CR

#define PG2_CR   0x00 /* Command Register (R/W) */

Definition at line 46 of file 8390.h.

◆ PG2_DCR

#define PG2_DCR   0x0E /* Data Configuration Register (R) */

Definition at line 58 of file 8390.h.

◆ PG2_IMR

#define PG2_IMR   0x0F /* Interrupt Mask Register (R) */

Definition at line 59 of file 8390.h.

◆ PG2_LNPP

#define PG2_LNPP   0x05 /* Local Next Packet Pointer (R/W) */

Definition at line 53 of file 8390.h.

◆ PG2_PSTART

#define PG2_PSTART   0x01 /* Page Start Register (R) */

Definition at line 47 of file 8390.h.

◆ PG2_PSTOP

#define PG2_PSTOP   0x02 /* Page Stop Register (R) */

Definition at line 49 of file 8390.h.

◆ PG2_RCR

#define PG2_RCR   0x0C /* Receive Configuration Register (R) */

Definition at line 56 of file 8390.h.

◆ PG2_RNPP

#define PG2_RNPP   0x03 /* Remote Next Packet Pointer (R/W) */

Definition at line 51 of file 8390.h.

◆ PG2_TCR

#define PG2_TCR   0x0D /* Transmit Configuration Register (R) */

Definition at line 57 of file 8390.h.

◆ PG2_TPSR

#define PG2_TPSR   0x04 /* Transmit Page Start Address (R) */

Definition at line 52 of file 8390.h.

◆ RCR_AB

#define RCR_AB   0x04 /* Accept broadcasts */

Definition at line 94 of file 8390.h.

◆ RCR_AM

#define RCR_AM   0x08 /* Accept multicast */

Definition at line 95 of file 8390.h.

◆ RCR_AR

#define RCR_AR   0x02 /* Accept runt packets */

Definition at line 93 of file 8390.h.

◆ RCR_MON

#define RCR_MON   0x20 /* Monitor mode */

Definition at line 97 of file 8390.h.

◆ RCR_PRO

#define RCR_PRO   0x10 /* Promiscuous physical addresses */

Definition at line 96 of file 8390.h.

◆ RCR_SEP

#define RCR_SEP   0x01 /* Save error packets */

Definition at line 92 of file 8390.h.

◆ RSR_CRC

#define RSR_CRC   0x02 /* CRC error */

Definition at line 101 of file 8390.h.

◆ RSR_DFR

#define RSR_DFR   0x80 /* Deferring */

Definition at line 107 of file 8390.h.

◆ RSR_DIS

#define RSR_DIS   0x40 /* Receiver disabled (monitor mode) */

Definition at line 106 of file 8390.h.

◆ RSR_FAE

#define RSR_FAE   0x04 /* Frame alignment error */

Definition at line 102 of file 8390.h.

◆ RSR_FO

#define RSR_FO   0x08 /* FIFO overrun */

Definition at line 103 of file 8390.h.

◆ RSR_MPA

#define RSR_MPA   0x10 /* Missed packet */

Definition at line 104 of file 8390.h.

◆ RSR_PHY

#define RSR_PHY   0x20 /* Physical/multicast address */

Definition at line 105 of file 8390.h.

◆ RSR_PRX

#define RSR_PRX   0x01 /* Received packet intact */

Definition at line 100 of file 8390.h.

◆ TCR_ATD

#define TCR_ATD   0x08 /* Auto transmit disable */

Definition at line 113 of file 8390.h.

◆ TCR_CRC

#define TCR_CRC   0x01 /* Inhibit CRC, do not append CRC */

Definition at line 110 of file 8390.h.

◆ TCR_LB01

#define TCR_LB01   0x06 /* Encoded loopback control */

Definition at line 112 of file 8390.h.

◆ TCR_LOOP

#define TCR_LOOP   0x02 /* Set loopback mode */

Definition at line 111 of file 8390.h.

◆ TCR_OFST

#define TCR_OFST   0x10 /* Collision offset enable */

Definition at line 114 of file 8390.h.

◆ TSR_ABT

#define TSR_ABT   0x08h /* Collided 16 times and was dropped */

Definition at line 85 of file 8390.h.

◆ TSR_CDH

#define TSR_CDH   0x40h /* Collision detect heartbeat */

Definition at line 88 of file 8390.h.

◆ TSR_COL

#define TSR_COL   0x04h /* Collided at least once */

Definition at line 84 of file 8390.h.

◆ TSR_CRS

#define TSR_CRS   0x10h /* Carrier sense lost */

Definition at line 86 of file 8390.h.

◆ TSR_FU

#define TSR_FU   0x20h /* Transmit FIFO Underrun */

Definition at line 87 of file 8390.h.

◆ TSR_OWC

#define TSR_OWC   0x80h /* Out of window collision */

Definition at line 89 of file 8390.h.

◆ TSR_PTX

#define TSR_PTX   0x01h /* Packet transmitted without error */

Definition at line 83 of file 8390.h.

Typedef Documentation

◆ DISCARD_HEADER

typedef struct _DISCARD_HEADER DISCARD_HEADER

◆ ETH_HEADER

typedef struct _ETH_HEADER ETH_HEADER

◆ PACKET_HEADER

typedef struct _PACKET_HEADER PACKET_HEADER

◆ PDISCARD_HEADER

typedef struct _DISCARD_HEADER * PDISCARD_HEADER

◆ PETH_HEADER

typedef struct _ETH_HEADER * PETH_HEADER

◆ PPACKET_HEADER

typedef struct _PACKET_HEADER * PPACKET_HEADER

Function Documentation

◆ MiniportHandleInterrupt()

VOID NTAPI MiniportHandleInterrupt ( IN NDIS_HANDLE  MiniportAdapterContext)

Definition at line 46 of file interrupt.c.

48{
49 ULONG InterruptPending;
50 PE1000_ADAPTER Adapter = (PE1000_ADAPTER)MiniportAdapterContext;
51 volatile PE1000_TRANSMIT_DESCRIPTOR TransmitDescriptor;
52
53 NDIS_DbgPrint(MAX_TRACE, ("Called.\n"));
54
55 InterruptPending = _InterlockedExchange(&Adapter->InterruptPending, 0);
56
57
58 /* Link State Changed */
59 if (InterruptPending & E1000_IMS_LSC)
60 {
61 ULONG Status;
62
63 InterruptPending &= ~E1000_IMS_LSC;
64 NDIS_DbgPrint(MAX_TRACE, ("Link status changed!.\n"));
65
66 NICUpdateLinkStatus(Adapter);
67
68 Status = Adapter->MediaState == NdisMediaStateConnected ? NDIS_STATUS_MEDIA_CONNECT : NDIS_STATUS_MEDIA_DISCONNECT;
69
70 NdisMIndicateStatus(Adapter->AdapterHandle, Status, NULL, 0);
71 NdisMIndicateStatusComplete(Adapter->AdapterHandle);
72 }
73
74 /* Handling receive interrupts */
75 if (InterruptPending & (E1000_IMS_RXDMT0 | E1000_IMS_RXT0))
76 {
77 volatile PE1000_RECEIVE_DESCRIPTOR ReceiveDescriptor;
78 PETH_HEADER EthHeader;
79 ULONG BufferOffset;
80 BOOLEAN bGotAny = FALSE;
81 ULONG RxDescHead, RxDescTail, CurrRxDesc;
82
83 /* Clear out these interrupts */
84 InterruptPending &= ~(E1000_IMS_RXDMT0 | E1000_IMS_RXT0);
85
86 E1000ReadUlong(Adapter, E1000_REG_RDH, &RxDescHead);
87 E1000ReadUlong(Adapter, E1000_REG_RDT, &RxDescTail);
88
89 while (((RxDescTail + 1) % NUM_RECEIVE_DESCRIPTORS) != RxDescHead)
90 {
91 CurrRxDesc = (RxDescTail + 1) % NUM_RECEIVE_DESCRIPTORS;
92 BufferOffset = CurrRxDesc * Adapter->ReceiveBufferEntrySize;
93 ReceiveDescriptor = Adapter->ReceiveDescriptors + CurrRxDesc;
94
95 /* Check if the hardware have released this descriptor (DD - Descriptor Done) */
96 if (!(ReceiveDescriptor->Status & E1000_RDESC_STATUS_DD))
97 {
98 /* No need to check descriptors after the first unfinished one */
99 break;
100 }
101
102 /* Ignoring these flags for now */
103 ReceiveDescriptor->Status &= ~(E1000_RDESC_STATUS_IXSM | E1000_RDESC_STATUS_PIF);
104
105 if (ReceiveDescriptor->Status != (E1000_RDESC_STATUS_EOP | E1000_RDESC_STATUS_DD))
106 {
107 NDIS_DbgPrint(MIN_TRACE, ("Unrecognized ReceiveDescriptor status flag: %u\n", ReceiveDescriptor->Status));
108 }
109
110 /* Make sure the receive indications are enabled */
111 if (!Adapter->PacketFilter)
112 {
113 goto NextReceiveDescriptor;
114 }
115
116 if (ReceiveDescriptor->Length != 0 && ReceiveDescriptor->Address != 0)
117 {
118 EthHeader = (PETH_HEADER)(Adapter->ReceiveBuffer + BufferOffset);
119
120 NdisMEthIndicateReceive(Adapter->AdapterHandle,
121 NULL,
122 (PCHAR)EthHeader,
123 sizeof(ETH_HEADER),
124 (PCHAR)(EthHeader + 1),
125 ReceiveDescriptor->Length - sizeof(ETH_HEADER),
126 ReceiveDescriptor->Length - sizeof(ETH_HEADER));
127
128 bGotAny = TRUE;
129 }
130 else
131 {
132 NDIS_DbgPrint(MIN_TRACE, ("Got a NULL descriptor"));
133 }
134
135NextReceiveDescriptor:
136 /* Give the descriptor back */
137 ReceiveDescriptor->Status = 0;
138
139 RxDescTail = CurrRxDesc;
140 }
141
142 if (bGotAny)
143 {
144 /* Write back new tail value */
145 E1000WriteUlong(Adapter, E1000_REG_RDT, RxDescTail);
146
147 NDIS_DbgPrint(MAX_TRACE, ("Rx done (RDH: %u, RDT: %u)\n", RxDescHead, RxDescTail));
148
149 NdisMEthIndicateReceiveComplete(Adapter->AdapterHandle);
150 }
151 }
152
153 /* Handling transmit interrupts */
154 if (InterruptPending & (E1000_IMS_TXD_LOW | E1000_IMS_TXDW | E1000_IMS_TXQE))
155 {
156 PNDIS_PACKET AckPackets[40] = {0};
157 ULONG NumPackets = 0, i;
158
159 /* Clear out these interrupts */
160 InterruptPending &= ~(E1000_IMS_TXD_LOW | E1000_IMS_TXDW | E1000_IMS_TXQE);
161
162 while ((Adapter->TxFull || Adapter->LastTxDesc != Adapter->CurrentTxDesc) && NumPackets < ARRAYSIZE(AckPackets))
163 {
164 TransmitDescriptor = Adapter->TransmitDescriptors + Adapter->LastTxDesc;
165
166 if (TransmitDescriptor->Status & E1000_TDESC_STATUS_DD)
167 {
168 if (Adapter->TransmitPackets[Adapter->LastTxDesc])
169 {
170 AckPackets[NumPackets++] = Adapter->TransmitPackets[Adapter->LastTxDesc];
171 Adapter->TransmitPackets[Adapter->LastTxDesc] = NULL;
172 TransmitDescriptor->Status = 0;
173 }
174
175 Adapter->LastTxDesc = (Adapter->LastTxDesc + 1) % NUM_TRANSMIT_DESCRIPTORS;
176 Adapter->TxFull = FALSE;
177 }
178 else
179 {
180 break;
181 }
182 }
183
184 if (NumPackets)
185 {
186 NDIS_DbgPrint(MAX_TRACE, ("Tx: (TDH: %u, TDT: %u)\n", Adapter->CurrentTxDesc, Adapter->LastTxDesc));
187 NDIS_DbgPrint(MAX_TRACE, ("Tx Done: %u packets to ack\n", NumPackets));
188
189 for (i = 0; i < NumPackets; ++i)
190 {
191 NdisMSendComplete(Adapter->AdapterHandle, AckPackets[i], NDIS_STATUS_SUCCESS);
192 }
193 }
194 }
195
196 ASSERT(InterruptPending == 0);
197}
BOOLEAN
unsigned char BOOLEAN
Definition: ProcessorBind.h:185
MIN_TRACE
#define MIN_TRACE
Definition: debug.h:14
NULL
#define NULL
Definition: types.h:112
TRUE
#define TRUE
Definition: types.h:120
FALSE
#define FALSE
Definition: types.h:117
ARRAYSIZE
#define ARRAYSIZE(array)
Definition: filtermapper.c:47
PETH_HEADER
struct _ETH_HEADER * PETH_HEADER
NDIS_DbgPrint
#define NDIS_DbgPrint(_t_, _x_)
Definition: debug.h:40
NICUpdateLinkStatus
VOID NTAPI NICUpdateLinkStatus(IN PE1000_ADAPTER Adapter)
Definition: hardware.c:740
PE1000_ADAPTER
struct _E1000_ADAPTER * PE1000_ADAPTER
E1000ReadUlong
FORCEINLINE VOID E1000ReadUlong(_In_ PE1000_ADAPTER Adapter, _In_ ULONG Address, _Out_ PULONG Value)
Definition: nic.h:209
E1000WriteUlong
FORCEINLINE VOID E1000WriteUlong(_In_ PE1000_ADAPTER Adapter, _In_ ULONG Address, _In_ ULONG Value)
Definition: nic.h:219
E1000_IMS_RXDMT0
#define E1000_IMS_RXDMT0
Definition: e1000hw.h:185
E1000_RDESC_STATUS_PIF
#define E1000_RDESC_STATUS_PIF
Definition: e1000hw.h:59
E1000_RDESC_STATUS_IXSM
#define E1000_RDESC_STATUS_IXSM
Definition: e1000hw.h:60
E1000_IMS_TXQE
#define E1000_IMS_TXQE
Definition: e1000hw.h:183
E1000_IMS_LSC
#define E1000_IMS_LSC
Definition: e1000hw.h:184
E1000_RDESC_STATUS_DD
#define E1000_RDESC_STATUS_DD
Definition: e1000hw.h:62
E1000_IMS_TXD_LOW
#define E1000_IMS_TXD_LOW
Definition: e1000hw.h:187
E1000_IMS_TXDW
#define E1000_IMS_TXDW
Definition: e1000hw.h:182
E1000_REG_RDH
#define E1000_REG_RDH
Definition: e1000hw.h:132
E1000_TDESC_STATUS_DD
#define E1000_TDESC_STATUS_DD
Definition: e1000hw.h:84
NUM_RECEIVE_DESCRIPTORS
#define NUM_RECEIVE_DESCRIPTORS
Definition: e1000hw.h:109
E1000_RDESC_STATUS_EOP
#define E1000_RDESC_STATUS_EOP
Definition: e1000hw.h:61
NUM_TRANSMIT_DESCRIPTORS
#define NUM_TRANSMIT_DESCRIPTORS
Definition: e1000hw.h:108
E1000_IMS_RXT0
#define E1000_IMS_RXT0
Definition: e1000hw.h:186
E1000_REG_RDT
#define E1000_REG_RDT
Definition: e1000hw.h:133
Status
Status
Definition: gdiplustypes.h:25
i
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
_InterlockedExchange
long __cdecl _InterlockedExchange(_Interlocked_operand_ long volatile *_Target, long _Value)
ASSERT
#define ASSERT(a)
Definition: mode.c:44
NDIS_STATUS_MEDIA_CONNECT
#define NDIS_STATUS_MEDIA_CONNECT
Definition: ndis.h:361
NdisMEthIndicateReceiveComplete
#define NdisMEthIndicateReceiveComplete(MiniportAdapterHandle)
Definition: ndis.h:5482
NdisMIndicateStatusComplete
#define NdisMIndicateStatusComplete(MiniportAdapterHandle)
Definition: ndis.h:5580
NdisMEthIndicateReceive
#define NdisMEthIndicateReceive(MiniportAdapterHandle, MiniportReceiveContext, HeaderBuffer, HeaderBufferSize, LookaheadBuffer, LookaheadBufferSize, PacketSize)
Definition: ndis.h:5458
NDIS_STATUS_MEDIA_DISCONNECT
#define NDIS_STATUS_MEDIA_DISCONNECT
Definition: ndis.h:362
NDIS_STATUS_SUCCESS
#define NDIS_STATUS_SUCCESS
Definition: ndis.h:346
NdisMSendComplete
#define NdisMSendComplete(MiniportAdapterHandle, Packet, Status)
Definition: ndis.h:5689
NdisMIndicateStatus
#define NdisMIndicateStatus(MiniportAdapterHandle, GeneralStatus, StatusBuffer, StatusBufferSize)
Definition: ndis.h:5570
NdisMediaStateConnected
@ NdisMediaStateConnected
Definition: ntddndis.h:470
ETH_HEADER
Definition: lan.h:33
_E1000_ADAPTER
Definition: nic.h:28
_E1000_ADAPTER::ReceiveDescriptors
PE1000_RECEIVE_DESCRIPTOR ReceiveDescriptors
Definition: nic.h:85
_E1000_ADAPTER::LastTxDesc
ULONG LastTxDesc
Definition: nic.h:80
_E1000_ADAPTER::PacketFilter
ULONG PacketFilter
Definition: nic.h:51
_E1000_ADAPTER::TxFull
BOOLEAN TxFull
Definition: nic.h:81
_E1000_ADAPTER::ReceiveBufferEntrySize
ULONG ReceiveBufferEntrySize
Definition: nic.h:91
_E1000_ADAPTER::TransmitDescriptors
PE1000_TRANSMIT_DESCRIPTOR TransmitDescriptors
Definition: nic.h:74
_E1000_ADAPTER::MediaState
ULONG MediaState
Definition: nic.h:50
_E1000_ADAPTER::TransmitPackets
PNDIS_PACKET TransmitPackets[NUM_TRANSMIT_DESCRIPTORS]
Definition: nic.h:77
_E1000_ADAPTER::AdapterHandle
NDIS_HANDLE AdapterHandle
Definition: nic.h:36
_E1000_ADAPTER::InterruptPending
_Interlocked_ volatile LONG InterruptPending
Definition: nic.h:70
_E1000_ADAPTER::ReceiveBuffer
volatile PUCHAR ReceiveBuffer
Definition: nic.h:89
_E1000_ADAPTER::CurrentTxDesc
ULONG CurrentTxDesc
Definition: nic.h:79
_E1000_RECEIVE_DESCRIPTOR
Definition: e1000hw.h:65
_E1000_RECEIVE_DESCRIPTOR::Length
USHORT Length
Definition: e1000hw.h:68
_E1000_RECEIVE_DESCRIPTOR::Status
UCHAR Status
Definition: e1000hw.h:70
_E1000_RECEIVE_DESCRIPTOR::Address
UINT64 Address
Definition: e1000hw.h:66
_E1000_TRANSMIT_DESCRIPTOR
Definition: e1000hw.h:87
_E1000_TRANSMIT_DESCRIPTOR::Status
UCHAR Status
Definition: e1000hw.h:93
_ETH_HEADER
Definition: util.h:12
_NDIS_PACKET
Definition: ndis.h:734
ULONG
uint32_t ULONG
Definition: typedefs.h:59
PCHAR
char * PCHAR
Definition: typedefs.h:51