ReactOS 0.4.15-dev-8102-g108db8f
8390.h
Go to the documentation of this file.
1/*
2 * COPYRIGHT: See COPYING in the top level directory
3 * PROJECT: ReactOS Novell Eagle 2000 driver
4 * FILE: include/8390.h
5 * PURPOSE: National Semiconductor 8390 NIC definitions
6 */
7
8#pragma once
9
10/* Page 0 register layout (PS1 = 0, PS0 = 0) */
11#define PG0_CR 0x00 /* Command Register (R/W) */
12#define PG0_CLDA0 0x01 /* Current Local DMA Address 0 (R) */
13#define PG0_PSTART 0x01 /* Page Start Register (W) */
14#define PG0_CLDA1 0x02 /* Current Local DMA Address 1 (R) */
15#define PG0_PSTOP 0x02 /* Page Stop Register (W) */
16#define PG0_BNRY 0x03 /* Boundary Pointer (R/W) */
17#define PG0_TSR 0x04 /* Transmit Status Register (R) */
18#define PG0_TPSR 0x04 /* Transmit Page Start Register (W) */
19#define PG0_NCR 0x05 /* Number of Collisions Register (R) */
20#define PG0_TBCR0 0x05 /* Transmit Byte Count Register 0 (W) */
21#define PG0_FIFO 0x06 /* FIFO (R) */
22#define PG0_TBCR1 0x06 /* Transmit Byte Count Register 1 (W) */
23#define PG0_ISR 0x07 /* Interrupt Status Register (R/W) */
24#define PG0_CRDA0 0x08 /* Current Remote DMA Address 0 (R) */
25#define PG0_RSAR0 0x08 /* Remote Start Address Register 0 (W) */
26#define PG0_CRDA1 0x09 /* Current Remote DMA Address 1 (R) */
27#define PG0_RSAR1 0x09 /* Remote Start Address Register 1 (W) */
28#define PG0_RBCR0 0x0A /* Remote Byte Count Register 0 (W) */
29#define PG0_RBCR1 0x0B /* Remote Byte Count Register 1 (W) */
30#define PG0_RSR 0x0C /* Receive Status Register (R) */
31#define PG0_RCR 0x0C /* Receive Configuration Register (W) */
32#define PG0_CNTR0 0x0D /* Tally Counter 0 (Frame Alignment Errors) (R) */
33#define PG0_TCR 0x0D /* Transmit Configuration Register (W) */
34#define PG0_CNTR1 0x0E /* Tally Counter 1 (CRC Errors) (R) */
35#define PG0_DCR 0x0E /* Data Configuration Register (W) */
36#define PG0_CNTR2 0x0F /* Tally Counter 2 (Missed Packet Errors) (R) */
37#define PG0_IMR 0x0F /* Interrupt Mask Register (W) */
38
39/* Page 1 register layout (PS1 = 0, PS0 = 1) */
40#define PG1_CR 0x00 /* Command Register (R/W) */
41#define PG1_PAR 0x01 /* Physical Address Registers (6 registers) (R/W) */
42#define PG1_CURR 0x07 /* Current Page Register (R/W) */
43#define PG1_MAR 0x08 /* Multicast Address Registers (8 registers) (R/W) */
44
45/* Page 2 register layout (PS1 = 1, PS0 = 0) */
46#define PG2_CR 0x00 /* Command Register (R/W) */
47#define PG2_PSTART 0x01 /* Page Start Register (R) */
48#define PG2_CLDA0 0x01 /* Current Local DMA Address 0 (W) */
49#define PG2_PSTOP 0x02 /* Page Stop Register (R) */
50#define PG2_CLDA1 0x02 /* Current Local DMA Address 1 (W) */
51#define PG2_RNPP 0x03 /* Remote Next Packet Pointer (R/W) */
52#define PG2_TPSR 0x04 /* Transmit Page Start Address (R) */
53#define PG2_LNPP 0x05 /* Local Next Packet Pointer (R/W) */
54#define PG2_AC1 0x06 /* Address Counter (Upper) (R/W) */
55#define PG2_AC0 0x07 /* Address Counter (Lower) (R/W) */
56#define PG2_RCR 0x0C /* Receive Configuration Register (R) */
57#define PG2_TCR 0x0D /* Transmit Configuration Register (R) */
58#define PG2_DCR 0x0E /* Data Configuration Register (R) */
59#define PG2_IMR 0x0F /* Interrupt Mask Register (R) */
60
61/* Bits in PGX_CR - Command Register */
62#define CR_STP 0x01 /* Stop chip */
63#define CR_STA 0x02 /* Start chip */
64#define CR_TXP 0x04 /* Transmit a frame */
65#define CR_RD0 0x08 /* Remote read */
66#define CR_RD1 0x10 /* Remote write */
67#define CR_RD2 0x20 /* Abort/complete remote DMA */
68#define CR_PAGE0 0x00 /* Select page 0 of chip registers */
69#define CR_PAGE1 0x40 /* Select page 1 of chip registers */
70#define CR_PAGE2 0x80 /* Select page 2 of chip registers */
71
72/* Bits in PG0_ISR - Interrupt Status Register */
73#define ISR_PRX 0x01 /* Packet received, no errors */
74#define ISR_PTX 0x02 /* Packet transmitted, no errors */
75#define ISR_RXE 0x04 /* Receive error */
76#define ISR_TXE 0x08 /* Transmit error */
77#define ISR_OVW 0x10 /* Overwrite warning */
78#define ISR_CNT 0x20 /* Counter overflow */
79#define ISR_RDC 0x40 /* Remote DMA complete */
80#define ISR_RST 0x80 /* Reset status */
81
82/* Bits in PG0_TSR - Transmit Status Register */
83#define TSR_PTX 0x01h /* Packet transmitted without error */
84#define TSR_COL 0x04h /* Collided at least once */
85#define TSR_ABT 0x08h /* Collided 16 times and was dropped */
86#define TSR_CRS 0x10h /* Carrier sense lost */
87#define TSR_FU 0x20h /* Transmit FIFO Underrun */
88#define TSR_CDH 0x40h /* Collision detect heartbeat */
89#define TSR_OWC 0x80h /* Out of window collision */
90
91/* Bits for PG0_RCR - Receive Configuration Register */
92#define RCR_SEP 0x01 /* Save error packets */
93#define RCR_AR 0x02 /* Accept runt packets */
94#define RCR_AB 0x04 /* Accept broadcasts */
95#define RCR_AM 0x08 /* Accept multicast */
96#define RCR_PRO 0x10 /* Promiscuous physical addresses */
97#define RCR_MON 0x20 /* Monitor mode */
98
99/* Bits in PG0_RSR - Receive Status Register */
100#define RSR_PRX 0x01 /* Received packet intact */
101#define RSR_CRC 0x02 /* CRC error */
102#define RSR_FAE 0x04 /* Frame alignment error */
103#define RSR_FO 0x08 /* FIFO overrun */
104#define RSR_MPA 0x10 /* Missed packet */
105#define RSR_PHY 0x20 /* Physical/multicast address */
106#define RSR_DIS 0x40 /* Receiver disabled (monitor mode) */
107#define RSR_DFR 0x80 /* Deferring */
108
109/* Bits in PG0_TCR - Transmit Configuration Register */
110#define TCR_CRC 0x01 /* Inhibit CRC, do not append CRC */
111#define TCR_LOOP 0x02 /* Set loopback mode */
112#define TCR_LB01 0x06 /* Encoded loopback control */
113#define TCR_ATD 0x08 /* Auto transmit disable */
114#define TCR_OFST 0x10 /* Collision offset enable */
115
116/* Bits in PG0_DCR - Data Configuration Register */
117#define DCR_WTS 0x01 /* Word transfer mode selection */
118#define DCR_BOS 0x02 /* Byte order selection */
119#define DCR_LAS 0x04 /* Long address selection */
120#define DCR_LS 0x08 /* Loopback select (when 0) */
121#define DCR_ARM 0x10 /* Autoinitialize remote */
122#define DCR_FT00 0x00 /* Burst length selection (1 word/2 bytes) */
123#define DCR_FT01 0x20 /* burst length selection (2 words/4 bytes) */
124#define DCR_FT10 0x40 /* Burst length selection (4 words/8 bytes) */
125#define DCR_FT11 0x60 /* Burst length selection (6 words/12 bytes) */
126
127/* Bits in PG0_IMR - Interrupt Mask Register */
128#define IMR_PRXE 0x01 /* Packet received interrupt enable */
129#define IMR_PTXE 0x02 /* Packet transmitted interrupt enable */
130#define IMR_RXEE 0x04 /* Receive error interrupt enable */
131#define IMR_TXEE 0x08 /* Transmit error interrupt enable */
132#define IMR_OVWE 0x10 /* Overwrite warning interrupt enable */
133#define IMR_CNTE 0x20 /* Counter overflow interrupt enable */
134#define IMR_RDCE 0x40 /* Remote DMA complete interrupt enable */
135#define IMR_ALLE 0x7F /* All interrupts enable */
136
137
138/* NIC prepended structure to a received packet */
139typedef struct _PACKET_HEADER {
140 UCHAR Status; /* See RSR_* constants */
141 UCHAR NextPacket; /* Pointer to next packet in chain */
142 USHORT PacketLength; /* Length of packet including this header */
144
145#define IEEE_802_ADDR_LENGTH 6
146
147/* Ethernet frame header */
148typedef struct _ETH_HEADER {
153
154typedef struct _DISCARD_HEADER {
158
159#define NICDisableInterrupts(Adapter) { \
160 NDIS_DbgPrint(MAX_TRACE, ("NICDisableInterrupts()\n")); \
161 NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, 0x00); \
162}
163
164#define NICEnableInterrupts(Adapter) { \
165 NDIS_DbgPrint(MAX_TRACE, ("NICEnableInterrupts() Mask (0x%X)\n", (Adapter)->InterruptMask)); \
166 NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, (Adapter)->InterruptMask); \
167}
168
170 IN NDIS_HANDLE MiniportAdapterContext);
171
172/* EOF */
struct _DISCARD_HEADER DISCARD_HEADER
struct _ETH_HEADER ETH_HEADER
struct _DISCARD_HEADER * PDISCARD_HEADER
VOID NTAPI MiniportHandleInterrupt(IN NDIS_HANDLE MiniportAdapterContext)
Definition: interrupt.c:46
struct _PACKET_HEADER PACKET_HEADER
struct _PACKET_HEADER * PPACKET_HEADER
struct _ETH_HEADER * PETH_HEADER
unsigned short USHORT
Definition: pedump.c:61
#define IEEE_802_ADDR_LENGTH
Definition: rtlhw.h:160
ETH_HEADER EthernetHeader
Definition: 8390.h:156
PACKET_HEADER HWHeader
Definition: 8390.h:155
UCHAR Destination[ETH_LENGTH_OF_ADDRESS]
Definition: util.h:13
UCHAR Source[ETH_LENGTH_OF_ADDRESS]
Definition: util.h:14
USHORT PayloadType
Definition: util.h:15
USHORT PacketLength
Definition: 8390.h:142
UCHAR NextPacket
Definition: 8390.h:141
UCHAR Status
Definition: 8390.h:140
#define NTAPI
Definition: typedefs.h:36
#define IN
Definition: typedefs.h:39
unsigned char UCHAR
Definition: xmlstorage.h:181