ReactOS  0.4.15-dev-489-g75a0787
rtlhw.h
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1 /*
2  * COPYRIGHT: See COPYING in the top level directory
3  * PROJECT: ReactOS RTL8139 Driver
4  * FILE: rtlhw.h
5  * PURPOSE: 8139 NIC definitions
6  */
7 
8 #pragma once
9 
10 #define MAXIMUM_MULTICAST_ADDRESSES 8
11 #define DEFAULT_INTERRUPT_MASK (R_I_RXOK | R_I_RXERR | R_I_TXOK | \
12  R_I_TXERR | R_I_RXOVRFLW | R_I_RXUNDRUN | \
13  R_I_FIFOOVR | R_I_PCSTMOUT | R_I_PCIERR)
14 #define TX_DESC_COUNT 4
15 
16 //Register addresses
17 #define R_MAC 0x00 //MAC address uses bytes 0-5, 6 and 7 are reserved
18 #define R_MCAST0 0x08 //Multicast registers
19 #define R_MCAST1 0x09 //Multicast registers
20 #define R_MCAST2 0x0A
21 #define R_MCAST3 0x0B
22 #define R_MCAST4 0x0C
23 #define R_MCAST5 0x0D
24 #define R_MCAST6 0x0E
25 #define R_MCAST7 0x0F
26 #define R_TXSTS0 0x10 //TX status, 0x10-0x13, 4 bytes
27 #define R_TXSTS1 0x14
28 #define R_TXSTS2 0x18
29 #define R_TXSTS3 0x1C
30 #define R_TXSAD0 0x20 //TX start address of descriptor 0
31 #define R_TXSAD1 0x24
32 #define R_TXSAD2 0x28
33 #define R_TXSAD3 0x2C
34 #define R_RXSA 0x30 //RX buffer start address
35 #define R_ERXBC 0x34 //Early RX byte count register
36 #define R_ERXSTS 0x36 //Early RX status register
37 
38 #define R_TXS_HOSTOWNS 0x00002000 //Driver still owns the buffer
39 #define R_TXS_UNDERRUN 0x00004000 //TX underrun
40 #define R_TXS_STATOK 0x00008000 //Successful TX
41 #define R_TXS_OOW 0x20000000 //Out of window
42 #define R_TXS_ABORTED 0x40000000 //TX aborted
43 #define R_TXS_CARLOST 0x80000000 //Carrier lost
44 
45 #define R_CMD 0x37 //Command register
46 #define R_CMD_RXEMPTY 0x01 //Receive buffer empty
47 #define B_CMD_TXE 0x04 //Enable TX
48 #define B_CMD_RXE 0x08 //Enable RX
49 #define B_CMD_RST 0x10 //Reset bit
50 
51 #define R_CAPR 0x38 //Current address of packet read
52 #define R_CBA 0x3A //Current buffer address
53 #define R_IM 0x3C //Interrupt mask register
54 #define R_IS 0x3E //Interrupt status register
55 #define R_TC 0x40 //Transmit configuration register
56 
57 #define R_I_RXOK 0x0001 //Receive OK
58 #define R_I_RXERR 0x0002 //Receive error
59 #define R_I_TXOK 0x0004 //Transmit OK
60 #define R_I_TXERR 0x0008 //Trasmit error
61 #define R_I_RXOVRFLW 0x0010 //Receive overflow
62 #define R_I_RXUNDRUN 0x0020 //Receive underrun
63 #define R_I_FIFOOVR 0x0040 //FIFO overflow
64 #define R_I_PCSTMOUT 0x4000 //PCS timeout
65 #define R_I_PCIERR 0x8000 //PCI error
66 
67 #define R_RC 0x44 //Receive configuration register
68 #define B_RC_AAP 0x01 //Accept all packets
69 #define B_RC_APM 0x02 //Accept packets sent to device MAC
70 #define B_RC_AM 0x04 //Accept multicast packets
71 #define B_RC_AB 0x08 //Accept broadcast packets
72 #define B_RC_AR 0x10 //Accept runt (smaller than 64bytes) packets
73 
74 #define R_TCTR 0x48 //Timer counter register
75 #define R_MPC 0x4C //Missed packet counter
76 #define R_9346CR 0x50 //93C46 command register
77 #define R_CFG0 0x51 //Configuration register 0
78 #define R_CFG1 0x52
79 #define R_TINTR 0x54 //Timer interrupt register
80 #define R_MS 0x58 //Media status register
81 
82 #define R_MS_LINKDWN 0x04 //Link is down
83 #define R_MS_SPEED_10 0x08 //Media is at 10mbps
84 
85 #define R_CFG3 0x59 //Configuration register 3
86 #define R_CFG4 0x5A //Configuration register 4
87 #define R_MINTS 0x5C //Multiple interrupt select
88 #define R_PCIID 0x5E //PCI Revision ID = 0x10
89 #define R_DTSTS 0x60 //TX status of all descriptors
90 #define R_BMC 0x62 //Basic mode control register
91 #define R_BMSTS 0x64 //Basic mode status register
92 #define R_ANA 0x66 //Auto-negotiation advertisement
93 #define R_ANLP 0x68 //Auto-negotiation link partner
94 #define R_ANEX 0x6A //Auto-negotiation expansion
95 #define R_DCTR 0x6C //Disconnect counter
96 #define R_FCSCTR 0x6E //False carrier sense counter
97 #define R_NWT 0x70 //N-way test register
98 #define R_RXERRCTR 0x72 //RX error counter
99 #define R_CSCFG 0x74 //CS configuration register
100 
101 #define R_CSCR_LINKOK 0x00400 //Link up
102 #define R_CSCR_LINKCHNG 0x00800 //Link changed
103 
104 #define R_PHYP1 0x78 //PHY parameter 1
105 #define R_TWP 0x7C //Twister parameter
106 #define R_PHYP2 0x80 //PHY parameter 2
107 #define R_PCRC0 0x84 //Power management CRC for wakeup frame 0
108 #define R_PCRC1 0x85
109 #define R_PCRC2 0x86
110 #define R_PCRC3 0x87
111 #define R_PCRC4 0x88
112 #define R_PCRC5 0x89
113 #define R_PCRC6 0x8A
114 #define R_PCRC7 0x8B
115 #define R_WAKE0 0x8C //Power management wakeup frame 0
116 #define R_WAKE1 0x94
117 #define R_WAKE2 0x9C
118 #define R_WAKE3 0xA4
119 #define R_WAKE4 0xAC
120 #define R_WAKE5 0xB4
121 #define R_WAKE6 0xBC
122 #define R_WAKE7 0xC4
123 #define R_LSBCRC0 0xCC //LSB of the mask byte of wakeup frame 0 within offset 12 to 75
124 #define R_LSBCRC1 0xCD
125 #define R_LSBCRC2 0xCE
126 #define R_LSBCRC3 0xCF
127 #define R_LSBCRC4 0xD0
128 #define R_LSBCRC5 0xD1
129 #define R_LSBCRC6 0xD2
130 #define R_LSBCRC7 0xD3
131 #define R_CFG5 0xD8 //Configuration register 5
132 
133 //EEPROM Control Bytes
134 #define EE_DATA_READ 0x01 //Chip data out
135 #define EE_DATA_WRITE 0x02 //Chip data in
136 #define EE_SHIFT_CLK 0x04 //Chip shift clock
137 #define EE_CS 0x08 //Chip select
138 #define EE_ENB 0x88 //Chip enable
139 
140 
141 //EEPROM Commands
142 #define EE_READ_CMD 0x06
143 
144 #define RSR_MAR 0x8000 //Multicast receive
145 #define RSR_PAM 0x4000 //Physical address match (directed packet)
146 #define RSR_BAR 0x2000 //Broadcast receive
147 #define RSR_ISE 0x0020 //Invalid symbol
148 #define RSR_RUNT 0x0010 //Runt packet
149 #define RSR_LONG 0x0008 //Long packet
150 #define RSR_CRC 0x0004 //CRC error
151 #define RSR_FAE 0x0002 //Frame alignment error
152 #define RSR_ROK 0x0001 //Receive OK
153 
154 /* NIC prepended structure to a received packet */
155 typedef struct _PACKET_HEADER {
156  USHORT Status; /* See RSR_* constants */
157  USHORT PacketLength; /* Length of packet NOT including this header */
159 
160 #define IEEE_802_ADDR_LENGTH 6
161 
162 /* Ethernet frame header */
163 typedef struct _ETH_HEADER {
168 
169 /* EOF */
USHORT Status
Definition: rtlhw.h:156
struct _ETH_HEADER * PETH_HEADER
UCHAR Source[IEEE_802_ADDR_LENGTH]
Definition: e1000hw.h:29
#define IEEE_802_ADDR_LENGTH
Definition: rtlhw.h:160
struct _PACKET_HEADER * PPACKET_HEADER
UCHAR Destination[IEEE_802_ADDR_LENGTH]
Definition: e1000hw.h:28
USHORT PayloadType
Definition: e1000hw.h:30
unsigned char UCHAR
Definition: xmlstorage.h:181
struct _PACKET_HEADER PACKET_HEADER
unsigned short USHORT
Definition: pedump.c:61
USHORT PacketLength
Definition: 8390.h:142
struct _ETH_HEADER ETH_HEADER