11 #define IEEE_802_ADDR_LENGTH 6 13 #define HW_VENDOR_INTEL 0x8086 15 #define MAX_RESET_ATTEMPTS 10 17 #define MAX_PHY_REG_ADDRESS 0x1F 18 #define MAX_PHY_READ_ATTEMPTS 1800 20 #define MAX_EEPROM_READ_ATTEMPTS 10000 23 #define MAXIMUM_MULTICAST_ADDRESSES 16 59 #define E1000_RDESC_STATUS_PIF (1 << 7) 60 #define E1000_RDESC_STATUS_IXSM (1 << 2) 61 #define E1000_RDESC_STATUS_EOP (1 << 1) 62 #define E1000_RDESC_STATUS_DD (1 << 0) 79 #define E1000_TDESC_CMD_IDE (1 << 7) 80 #define E1000_TDESC_CMD_RS (1 << 3) 81 #define E1000_TDESC_CMD_IFCS (1 << 1) 82 #define E1000_TDESC_CMD_EOP (1 << 0) 84 #define E1000_TDESC_STATUS_DD (1 << 0) 108 #define NUM_TRANSMIT_DESCRIPTORS 128 109 #define NUM_RECEIVE_DESCRIPTORS 128 114 #define E1000_REG_CTRL 0x0000 115 #define E1000_REG_STATUS 0x0008 116 #define E1000_REG_EERD 0x0014 117 #define E1000_REG_MDIC 0x0020 118 #define E1000_REG_VET 0x0038 119 #define E1000_REG_ICR 0x00C0 120 #define E1000_REG_ITR 0x00C4 122 #define E1000_REG_IMS 0x00D0 123 #define E1000_REG_IMC 0x00D8 125 #define E1000_REG_RCTL 0x0100 126 #define E1000_REG_TCTL 0x0400 127 #define E1000_REG_TIPG 0x0410 129 #define E1000_REG_RDBAL 0x2800 130 #define E1000_REG_RDBAH 0x2804 131 #define E1000_REG_RDLEN 0x2808 132 #define E1000_REG_RDH 0x2810 133 #define E1000_REG_RDT 0x2818 134 #define E1000_REG_RDTR 0x2820 135 #define E1000_REG_RADV 0x282C 137 #define E1000_REG_TDBAL 0x3800 138 #define E1000_REG_TDBAH 0x3804 139 #define E1000_REG_TDLEN 0x3808 140 #define E1000_REG_TDH 0x3810 141 #define E1000_REG_TDT 0x3818 142 #define E1000_REG_TIDV 0x3820 143 #define E1000_REG_TADV 0x382C 146 #define E1000_REG_RAL 0x5400 147 #define E1000_REG_RAH 0x5404 151 #define E1000_CTRL_LRST (1 << 3) 152 #define E1000_CTRL_ASDE (1 << 5) 153 #define E1000_CTRL_SLU (1 << 6) 154 #define E1000_CTRL_RST (1 << 26) 155 #define E1000_CTRL_VME (1 << 30) 159 #define E1000_STATUS_FD (1 << 0) 160 #define E1000_STATUS_LU (1 << 1) 161 #define E1000_STATUS_SPEEDSHIFT 6 162 #define E1000_STATUS_SPEEDMASK (3 << E1000_STATUS_SPEEDSHIFT) 166 #define E1000_EERD_START (1 << 0) 167 #define E1000_EERD_DONE (1 << 4) 168 #define E1000_EERD_ADDR_SHIFT 8 169 #define E1000_EERD_DATA_SHIFT 16 173 #define E1000_MDIC_REGADD_SHIFT 16 174 #define E1000_MDIC_PHYADD_SHIFT 21 175 #define E1000_MDIC_PHYADD_GIGABIT 1 176 #define E1000_MDIC_OP_READ (2 << 26) 177 #define E1000_MDIC_R (1 << 28) 178 #define E1000_MDIC_E (1 << 30) 182 #define E1000_IMS_TXDW (1 << 0) 183 #define E1000_IMS_TXQE (1 << 1) 184 #define E1000_IMS_LSC (1 << 2) 185 #define E1000_IMS_RXDMT0 (1 << 4) 186 #define E1000_IMS_RXT0 (1 << 7) 187 #define E1000_IMS_TXD_LOW (1 << 15) 188 #define E1000_IMS_SRPD (1 << 16) 192 #define MAX_INTS_PER_SEC 2000 193 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 197 #define E1000_RCTL_EN (1 << 1) 198 #define E1000_RCTL_SBP (1 << 2) 199 #define E1000_RCTL_UPE (1 << 3) 200 #define E1000_RCTL_MPE (1 << 4) 201 #define E1000_RCTL_BAM (1 << 15) 202 #define E1000_RCTL_BSIZE_SHIFT 16 203 #define E1000_RCTL_PMCF (1 << 23) 204 #define E1000_RCTL_BSEX (1 << 25) 205 #define E1000_RCTL_SECRC (1 << 26) 207 #define E1000_RCTL_FILTER_BITS (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF) 211 #define E1000_TCTL_EN (1 << 1) 212 #define E1000_TCTL_PSP (1 << 3) 215 #define E1000_TIPG_IPGT_DEF (10 << 0) 216 #define E1000_TIPG_IPGR1_DEF (10 << 10) 217 #define E1000_TIPG_IPGR2_DEF (10 << 20) 221 #define E1000_RAH_AV (1 << 31) 227 #define E1000_NVM_REG_CHECKSUM 0x03f 228 #define NVM_MAGIC_SUM 0xBABA 234 #define E1000_PHY_STATUS 0x01 235 #define E1000_PHY_SPECIFIC_STATUS 0x11 239 #define E1000_PS_LINK_STATUS (1 << 2) 244 #define E1000_PSS_SPEED_AND_DUPLEX (1 << 11) 245 #define E1000_PSS_SPEEDSHIFT 14 246 #define E1000_PSS_SPEEDMASK (3 << E1000_PSS_SPEEDSHIFT)
enum _E1000_RCVBUF_SIZE E1000_RCVBUF_SIZE
struct _E1000_RECEIVE_DESCRIPTOR E1000_RECEIVE_DESCRIPTOR
C_ASSERT(sizeof(ETH_HEADER)==14)
struct _E1000_TRANSMIT_DESCRIPTOR E1000_TRANSMIT_DESCRIPTOR
struct _E1000_TRANSMIT_DESCRIPTOR * PE1000_TRANSMIT_DESCRIPTOR
struct _ETH_HEADER ETH_HEADER
#define IEEE_802_ADDR_LENGTH
struct _ETH_HEADER * PETH_HEADER
struct _E1000_RECEIVE_DESCRIPTOR * PE1000_RECEIVE_DESCRIPTOR
unsigned long long UINT64