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| #define | IEEE_802_ADDR_LENGTH 6 |
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| #define | HW_VENDOR_INTEL 0x8086 |
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| #define | MAX_RESET_ATTEMPTS 10 |
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| #define | MAX_PHY_REG_ADDRESS 0x1F |
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| #define | MAX_PHY_READ_ATTEMPTS 1800 |
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| #define | MAX_EEPROM_READ_ATTEMPTS 10000 |
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| #define | MAXIMUM_MULTICAST_ADDRESSES 16 |
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| #define | E1000_RDESC_STATUS_PIF (1 << 7) /* Passed in-exact filter */ |
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| #define | E1000_RDESC_STATUS_IXSM (1 << 2) /* Ignore Checksum Indication */ |
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| #define | E1000_RDESC_STATUS_EOP (1 << 1) /* End of Packet */ |
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| #define | E1000_RDESC_STATUS_DD (1 << 0) /* Descriptor Done */ |
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| #define | E1000_TDESC_CMD_IDE (1 << 7) /* Interrupt Delay Enable */ |
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| #define | E1000_TDESC_CMD_RS (1 << 3) /* Report Status */ |
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| #define | E1000_TDESC_CMD_IFCS (1 << 1) /* Insert FCS */ |
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| #define | E1000_TDESC_CMD_EOP (1 << 0) /* End Of Packet */ |
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| #define | E1000_TDESC_STATUS_DD (1 << 0) /* Descriptor Done */ |
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| #define | NUM_TRANSMIT_DESCRIPTORS 128 |
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| #define | NUM_RECEIVE_DESCRIPTORS 128 |
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| #define | E1000_REG_CTRL 0x0000 /* Device Control Register, R/W */ |
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| #define | E1000_REG_STATUS 0x0008 /* Device Status Register, R */ |
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| #define | E1000_REG_EERD 0x0014 /* EEPROM Read Register, R/W */ |
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| #define | E1000_REG_MDIC 0x0020 /* MDI Control Register, R/W */ |
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| #define | E1000_REG_VET 0x0038 /* VLAN Ether Type, R/W */ |
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| #define | E1000_REG_ICR 0x00C0 /* Interrupt Cause Read, R/clr */ |
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| #define | E1000_REG_ITR 0x00C4 /* Interrupt Throttling Register, R/W */ |
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| #define | E1000_REG_IMS 0x00D0 /* Interrupt Mask Set/Read Register, R/W */ |
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| #define | E1000_REG_IMC 0x00D8 /* Interrupt Mask Clear, W */ |
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| #define | E1000_REG_RCTL 0x0100 /* Receive Control Register, R/W */ |
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| #define | E1000_REG_TCTL 0x0400 /* Transmit Control Register, R/W */ |
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| #define | E1000_REG_TIPG 0x0410 /* Transmit IPG Register, R/W */ |
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| #define | E1000_REG_RDBAL 0x2800 /* Receive Descriptor Base Address Low, R/W */ |
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| #define | E1000_REG_RDBAH 0x2804 /* Receive Descriptor Base Address High, R/W */ |
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| #define | E1000_REG_RDLEN 0x2808 /* Receive Descriptor Length, R/W */ |
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| #define | E1000_REG_RDH 0x2810 /* Receive Descriptor Head, R/W */ |
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| #define | E1000_REG_RDT 0x2818 /* Receive Descriptor Tail, R/W */ |
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| #define | E1000_REG_RDTR 0x2820 /* Receive Delay Timer, R/W */ |
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| #define | E1000_REG_RADV 0x282C /* Receive Absolute Delay Timer, R/W */ |
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| #define | E1000_REG_TDBAL 0x3800 /* Transmit Descriptor Base Address Low, R/W */ |
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| #define | E1000_REG_TDBAH 0x3804 /* Transmit Descriptor Base Address High, R/W */ |
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| #define | E1000_REG_TDLEN 0x3808 /* Transmit Descriptor Length, R/W */ |
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| #define | E1000_REG_TDH 0x3810 /* Transmit Descriptor Head, R/W */ |
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| #define | E1000_REG_TDT 0x3818 /* Transmit Descriptor Tail, R/W */ |
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| #define | E1000_REG_TIDV 0x3820 /* Transmit Interrupt Delay Value, R/W */ |
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| #define | E1000_REG_TADV 0x382C /* Transmit Absolute Delay Timer, R/W */ |
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| #define | E1000_REG_RAL 0x5400 /* Receive Address Low, R/W */ |
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| #define | E1000_REG_RAH 0x5404 /* Receive Address High, R/W */ |
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| #define | E1000_CTRL_LRST (1 << 3) /* Link Reset */ |
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| #define | E1000_CTRL_ASDE (1 << 5) /* Auto-Speed Detection Enable */ |
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| #define | E1000_CTRL_SLU (1 << 6) /* Set Link Up */ |
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| #define | E1000_CTRL_RST (1 << 26) /* Device Reset, Self clearing */ |
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| #define | E1000_CTRL_VME (1 << 30) /* VLAN Mode Enable */ |
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| #define | E1000_STATUS_FD (1 << 0) /* Full Duplex Indication */ |
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| #define | E1000_STATUS_LU (1 << 1) /* Link Up Indication */ |
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| #define | E1000_STATUS_SPEEDSHIFT 6 /* Link speed setting */ |
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| #define | E1000_STATUS_SPEEDMASK (3 << E1000_STATUS_SPEEDSHIFT) |
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| #define | E1000_EERD_START (1 << 0) /* Start Read*/ |
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| #define | E1000_EERD_DONE (1 << 4) /* Read Done */ |
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| #define | E1000_EERD_ADDR_SHIFT 8 |
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| #define | E1000_EERD_DATA_SHIFT 16 |
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| #define | E1000_MDIC_REGADD_SHIFT 16 /* PHY Register Address */ |
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| #define | E1000_MDIC_PHYADD_SHIFT 21 /* PHY Address (1=Gigabit, 2=PCIe) */ |
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| #define | E1000_MDIC_PHYADD_GIGABIT 1 |
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| #define | E1000_MDIC_OP_READ (2 << 26) /* Opcode */ |
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| #define | E1000_MDIC_R (1 << 28) /* Ready Bit */ |
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| #define | E1000_MDIC_E (1 << 30) /* Error */ |
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| #define | E1000_IMS_TXDW (1 << 0) /* Transmit Descriptor Written Back */ |
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| #define | E1000_IMS_TXQE (1 << 1) /* Transmit Queue Empty */ |
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| #define | E1000_IMS_LSC (1 << 2) /* Sets mask for Link Status Change */ |
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| #define | E1000_IMS_RXDMT0 (1 << 4) /* Receive Descriptor Minimum Threshold Reached */ |
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| #define | E1000_IMS_RXT0 (1 << 7) /* Receiver Timer Interrupt */ |
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| #define | E1000_IMS_TXD_LOW (1 << 15) /* Transmit Descriptor Low Threshold hit */ |
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| #define | E1000_IMS_SRPD (1 << 16) /* Small Receive Packet Detection */ |
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| #define | MAX_INTS_PER_SEC 2000 |
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| #define | DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) |
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| #define | E1000_RCTL_EN (1 << 1) /* Receiver Enable */ |
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| #define | E1000_RCTL_SBP (1 << 2) /* Store Bad Packets */ |
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| #define | E1000_RCTL_UPE (1 << 3) /* Unicast Promiscuous Enabled */ |
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| #define | E1000_RCTL_MPE (1 << 4) /* Multicast Promiscuous Enabled */ |
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| #define | E1000_RCTL_BAM (1 << 15) /* Broadcast Accept Mode */ |
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| #define | E1000_RCTL_BSIZE_SHIFT 16 |
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| #define | E1000_RCTL_PMCF (1 << 23) /* Pass MAC Control Frames */ |
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| #define | E1000_RCTL_BSEX (1 << 25) /* Buffer Size Extension */ |
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| #define | E1000_RCTL_SECRC (1 << 26) /* Strip Ethernet CRC from incoming packet */ |
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| #define | E1000_RCTL_FILTER_BITS (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF) |
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| #define | E1000_TCTL_EN (1 << 1) /* Transmit Enable */ |
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| #define | E1000_TCTL_PSP (1 << 3) /* Pad Short Packets */ |
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| #define | E1000_TIPG_IPGT_DEF (10 << 0) /* IPG Transmit Time */ |
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| #define | E1000_TIPG_IPGR1_DEF (10 << 10) /* IPG Receive Time 1 */ |
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| #define | E1000_TIPG_IPGR2_DEF (10 << 20) /* IPG Receive Time 2 */ |
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| #define | E1000_RAH_AV (1 << 31) /* Address Valid */ |
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| #define | E1000_NVM_REG_CHECKSUM 0x03f |
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| #define | NVM_MAGIC_SUM 0xBABA |
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| #define | E1000_PHY_STATUS 0x01 |
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| #define | E1000_PHY_SPECIFIC_STATUS 0x11 |
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| #define | E1000_PS_LINK_STATUS (1 << 2) |
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| #define | E1000_PSS_SPEED_AND_DUPLEX (1 << 11) /* Speed and Duplex Resolved */ |
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| #define | E1000_PSS_SPEEDSHIFT 14 |
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| #define | E1000_PSS_SPEEDMASK (3 << E1000_PSS_SPEEDSHIFT) |
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