ReactOS  0.4.14-dev-77-gd9e7c48
e1000hw.h File Reference
#include <pshpack1.h>
#include <poppack.h>
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Classes

struct  _ETH_HEADER
 
struct  _E1000_RECEIVE_DESCRIPTOR
 
struct  _E1000_TRANSMIT_DESCRIPTOR
 

Macros

#define IEEE_802_ADDR_LENGTH   6
 
#define HW_VENDOR_INTEL   0x8086
 
#define MAX_RESET_ATTEMPTS   10
 
#define MAX_PHY_REG_ADDRESS   0x1F
 
#define MAX_PHY_READ_ATTEMPTS   1800
 
#define MAX_EEPROM_READ_ATTEMPTS   10000
 
#define MAXIMUM_MULTICAST_ADDRESSES   16
 
#define E1000_RDESC_STATUS_PIF   (1 << 7) /* Passed in-exact filter */
 
#define E1000_RDESC_STATUS_IXSM   (1 << 2) /* Ignore Checksum Indication */
 
#define E1000_RDESC_STATUS_EOP   (1 << 1) /* End of Packet */
 
#define E1000_RDESC_STATUS_DD   (1 << 0) /* Descriptor Done */
 
#define E1000_TDESC_CMD_IDE   (1 << 7) /* Interrupt Delay Enable */
 
#define E1000_TDESC_CMD_RS   (1 << 3) /* Report Status */
 
#define E1000_TDESC_CMD_IFCS   (1 << 1) /* Insert FCS */
 
#define E1000_TDESC_CMD_EOP   (1 << 0) /* End Of Packet */
 
#define E1000_TDESC_STATUS_DD   (1 << 0) /* Descriptor Done */
 
#define NUM_TRANSMIT_DESCRIPTORS   128
 
#define NUM_RECEIVE_DESCRIPTORS   128
 
#define E1000_REG_CTRL   0x0000 /* Device Control Register, R/W */
 
#define E1000_REG_STATUS   0x0008 /* Device Status Register, R */
 
#define E1000_REG_EERD   0x0014 /* EEPROM Read Register, R/W */
 
#define E1000_REG_MDIC   0x0020 /* MDI Control Register, R/W */
 
#define E1000_REG_VET   0x0038 /* VLAN Ether Type, R/W */
 
#define E1000_REG_ICR   0x00C0 /* Interrupt Cause Read, R/clr */
 
#define E1000_REG_ITR   0x00C4 /* Interrupt Throttling Register, R/W */
 
#define E1000_REG_IMS   0x00D0 /* Interrupt Mask Set/Read Register, R/W */
 
#define E1000_REG_IMC   0x00D8 /* Interrupt Mask Clear, W */
 
#define E1000_REG_RCTL   0x0100 /* Receive Control Register, R/W */
 
#define E1000_REG_TCTL   0x0400 /* Transmit Control Register, R/W */
 
#define E1000_REG_TIPG   0x0410 /* Transmit IPG Register, R/W */
 
#define E1000_REG_RDBAL   0x2800 /* Receive Descriptor Base Address Low, R/W */
 
#define E1000_REG_RDBAH   0x2804 /* Receive Descriptor Base Address High, R/W */
 
#define E1000_REG_RDLEN   0x2808 /* Receive Descriptor Length, R/W */
 
#define E1000_REG_RDH   0x2810 /* Receive Descriptor Head, R/W */
 
#define E1000_REG_RDT   0x2818 /* Receive Descriptor Tail, R/W */
 
#define E1000_REG_RDTR   0x2820 /* Receive Delay Timer, R/W */
 
#define E1000_REG_RADV   0x282C /* Receive Absolute Delay Timer, R/W */
 
#define E1000_REG_TDBAL   0x3800 /* Transmit Descriptor Base Address Low, R/W */
 
#define E1000_REG_TDBAH   0x3804 /* Transmit Descriptor Base Address High, R/W */
 
#define E1000_REG_TDLEN   0x3808 /* Transmit Descriptor Length, R/W */
 
#define E1000_REG_TDH   0x3810 /* Transmit Descriptor Head, R/W */
 
#define E1000_REG_TDT   0x3818 /* Transmit Descriptor Tail, R/W */
 
#define E1000_REG_TIDV   0x3820 /* Transmit Interrupt Delay Value, R/W */
 
#define E1000_REG_TADV   0x382C /* Transmit Absolute Delay Timer, R/W */
 
#define E1000_REG_RAL   0x5400 /* Receive Address Low, R/W */
 
#define E1000_REG_RAH   0x5404 /* Receive Address High, R/W */
 
#define E1000_CTRL_LRST   (1 << 3) /* Link Reset */
 
#define E1000_CTRL_ASDE   (1 << 5) /* Auto-Speed Detection Enable */
 
#define E1000_CTRL_SLU   (1 << 6) /* Set Link Up */
 
#define E1000_CTRL_RST   (1 << 26) /* Device Reset, Self clearing */
 
#define E1000_CTRL_VME   (1 << 30) /* VLAN Mode Enable */
 
#define E1000_STATUS_FD   (1 << 0) /* Full Duplex Indication */
 
#define E1000_STATUS_LU   (1 << 1) /* Link Up Indication */
 
#define E1000_STATUS_SPEEDSHIFT   6 /* Link speed setting */
 
#define E1000_STATUS_SPEEDMASK   (3 << E1000_STATUS_SPEEDSHIFT)
 
#define E1000_EERD_START   (1 << 0) /* Start Read*/
 
#define E1000_EERD_DONE   (1 << 4) /* Read Done */
 
#define E1000_EERD_ADDR_SHIFT   8
 
#define E1000_EERD_DATA_SHIFT   16
 
#define E1000_MDIC_REGADD_SHIFT   16 /* PHY Register Address */
 
#define E1000_MDIC_PHYADD_SHIFT   21 /* PHY Address (1=Gigabit, 2=PCIe) */
 
#define E1000_MDIC_PHYADD_GIGABIT   1
 
#define E1000_MDIC_OP_READ   (2 << 26) /* Opcode */
 
#define E1000_MDIC_R   (1 << 28) /* Ready Bit */
 
#define E1000_MDIC_E   (1 << 30) /* Error */
 
#define E1000_IMS_TXDW   (1 << 0) /* Transmit Descriptor Written Back */
 
#define E1000_IMS_TXQE   (1 << 1) /* Transmit Queue Empty */
 
#define E1000_IMS_LSC   (1 << 2) /* Sets mask for Link Status Change */
 
#define E1000_IMS_RXDMT0   (1 << 4) /* Receive Descriptor Minimum Threshold Reached */
 
#define E1000_IMS_RXT0   (1 << 7) /* Receiver Timer Interrupt */
 
#define E1000_IMS_TXD_LOW   (1 << 15) /* Transmit Descriptor Low Threshold hit */
 
#define E1000_IMS_SRPD   (1 << 16) /* Small Receive Packet Detection */
 
#define MAX_INTS_PER_SEC   2000
 
#define DEFAULT_ITR   1000000000/(MAX_INTS_PER_SEC * 256)
 
#define E1000_RCTL_EN   (1 << 1) /* Receiver Enable */
 
#define E1000_RCTL_SBP   (1 << 2) /* Store Bad Packets */
 
#define E1000_RCTL_UPE   (1 << 3) /* Unicast Promiscuous Enabled */
 
#define E1000_RCTL_MPE   (1 << 4) /* Multicast Promiscuous Enabled */
 
#define E1000_RCTL_BAM   (1 << 15) /* Broadcast Accept Mode */
 
#define E1000_RCTL_BSIZE_SHIFT   16
 
#define E1000_RCTL_PMCF   (1 << 23) /* Pass MAC Control Frames */
 
#define E1000_RCTL_BSEX   (1 << 25) /* Buffer Size Extension */
 
#define E1000_RCTL_SECRC   (1 << 26) /* Strip Ethernet CRC from incoming packet */
 
#define E1000_RCTL_FILTER_BITS   (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF)
 
#define E1000_TCTL_EN   (1 << 1) /* Transmit Enable */
 
#define E1000_TCTL_PSP   (1 << 3) /* Pad Short Packets */
 
#define E1000_TIPG_IPGT_DEF   (10 << 0) /* IPG Transmit Time */
 
#define E1000_TIPG_IPGR1_DEF   (10 << 10) /* IPG Receive Time 1 */
 
#define E1000_TIPG_IPGR2_DEF   (10 << 20) /* IPG Receive Time 2 */
 
#define E1000_RAH_AV   (1 << 31) /* Address Valid */
 
#define E1000_NVM_REG_CHECKSUM   0x03f
 
#define NVM_MAGIC_SUM   0xBABA
 
#define E1000_PHY_STATUS   0x01
 
#define E1000_PHY_SPECIFIC_STATUS   0x11
 
#define E1000_PS_LINK_STATUS   (1 << 2)
 
#define E1000_PSS_SPEED_AND_DUPLEX   (1 << 11) /* Speed and Duplex Resolved */
 
#define E1000_PSS_SPEEDSHIFT   14
 
#define E1000_PSS_SPEEDMASK   (3 << E1000_PSS_SPEEDSHIFT)
 

Typedefs

typedef struct _ETH_HEADER ETH_HEADER
 
typedef struct _ETH_HEADERPETH_HEADER
 
typedef enum _E1000_RCVBUF_SIZE E1000_RCVBUF_SIZE
 
typedef struct _E1000_RECEIVE_DESCRIPTOR E1000_RECEIVE_DESCRIPTOR
 
typedef struct _E1000_RECEIVE_DESCRIPTORPE1000_RECEIVE_DESCRIPTOR
 
typedef struct _E1000_TRANSMIT_DESCRIPTOR E1000_TRANSMIT_DESCRIPTOR
 
typedef struct _E1000_TRANSMIT_DESCRIPTORPE1000_TRANSMIT_DESCRIPTOR
 

Enumerations

enum  _E1000_RCVBUF_SIZE {
  E1000_RCVBUF_2048 = 0, E1000_RCVBUF_1024 = 1, E1000_RCVBUF_512 = 2, E1000_RCVBUF_256 = 3,
  E1000_RCVBUF_INDEXMASK = 3, E1000_RCVBUF_RESERVED = 4 | 0, E1000_RCVBUF_16384 = 4 | 1, E1000_RCVBUF_8192 = 4 | 2,
  E1000_RCVBUF_4096 = 4 | 3
}
 

Functions

 C_ASSERT (sizeof(ETH_HEADER)==14)
 
 C_ASSERT (sizeof(E1000_RECEIVE_DESCRIPTOR)==16)
 
 C_ASSERT (sizeof(E1000_TRANSMIT_DESCRIPTOR)==16)
 

Macro Definition Documentation

◆ DEFAULT_ITR

#define DEFAULT_ITR   1000000000/(MAX_INTS_PER_SEC * 256)

Definition at line 193 of file e1000hw.h.

◆ E1000_CTRL_ASDE

#define E1000_CTRL_ASDE   (1 << 5) /* Auto-Speed Detection Enable */

Definition at line 152 of file e1000hw.h.

◆ E1000_CTRL_LRST

#define E1000_CTRL_LRST   (1 << 3) /* Link Reset */

Definition at line 151 of file e1000hw.h.

◆ E1000_CTRL_RST

#define E1000_CTRL_RST   (1 << 26) /* Device Reset, Self clearing */

Definition at line 154 of file e1000hw.h.

◆ E1000_CTRL_SLU

#define E1000_CTRL_SLU   (1 << 6) /* Set Link Up */

Definition at line 153 of file e1000hw.h.

◆ E1000_CTRL_VME

#define E1000_CTRL_VME   (1 << 30) /* VLAN Mode Enable */

Definition at line 155 of file e1000hw.h.

◆ E1000_EERD_ADDR_SHIFT

#define E1000_EERD_ADDR_SHIFT   8

Definition at line 168 of file e1000hw.h.

◆ E1000_EERD_DATA_SHIFT

#define E1000_EERD_DATA_SHIFT   16

Definition at line 169 of file e1000hw.h.

◆ E1000_EERD_DONE

#define E1000_EERD_DONE   (1 << 4) /* Read Done */

Definition at line 167 of file e1000hw.h.

◆ E1000_EERD_START

#define E1000_EERD_START   (1 << 0) /* Start Read*/

Definition at line 166 of file e1000hw.h.

◆ E1000_IMS_LSC

#define E1000_IMS_LSC   (1 << 2) /* Sets mask for Link Status Change */

Definition at line 184 of file e1000hw.h.

◆ E1000_IMS_RXDMT0

#define E1000_IMS_RXDMT0   (1 << 4) /* Receive Descriptor Minimum Threshold Reached */

Definition at line 185 of file e1000hw.h.

◆ E1000_IMS_RXT0

#define E1000_IMS_RXT0   (1 << 7) /* Receiver Timer Interrupt */

Definition at line 186 of file e1000hw.h.

◆ E1000_IMS_SRPD

#define E1000_IMS_SRPD   (1 << 16) /* Small Receive Packet Detection */

Definition at line 188 of file e1000hw.h.

◆ E1000_IMS_TXD_LOW

#define E1000_IMS_TXD_LOW   (1 << 15) /* Transmit Descriptor Low Threshold hit */

Definition at line 187 of file e1000hw.h.

◆ E1000_IMS_TXDW

#define E1000_IMS_TXDW   (1 << 0) /* Transmit Descriptor Written Back */

Definition at line 182 of file e1000hw.h.

◆ E1000_IMS_TXQE

#define E1000_IMS_TXQE   (1 << 1) /* Transmit Queue Empty */

Definition at line 183 of file e1000hw.h.

◆ E1000_MDIC_E

#define E1000_MDIC_E   (1 << 30) /* Error */

Definition at line 178 of file e1000hw.h.

◆ E1000_MDIC_OP_READ

#define E1000_MDIC_OP_READ   (2 << 26) /* Opcode */

Definition at line 176 of file e1000hw.h.

◆ E1000_MDIC_PHYADD_GIGABIT

#define E1000_MDIC_PHYADD_GIGABIT   1

Definition at line 175 of file e1000hw.h.

◆ E1000_MDIC_PHYADD_SHIFT

#define E1000_MDIC_PHYADD_SHIFT   21 /* PHY Address (1=Gigabit, 2=PCIe) */

Definition at line 174 of file e1000hw.h.

◆ E1000_MDIC_R

#define E1000_MDIC_R   (1 << 28) /* Ready Bit */

Definition at line 177 of file e1000hw.h.

◆ E1000_MDIC_REGADD_SHIFT

#define E1000_MDIC_REGADD_SHIFT   16 /* PHY Register Address */

Definition at line 173 of file e1000hw.h.

◆ E1000_NVM_REG_CHECKSUM

#define E1000_NVM_REG_CHECKSUM   0x03f

Definition at line 227 of file e1000hw.h.

◆ E1000_PHY_SPECIFIC_STATUS

#define E1000_PHY_SPECIFIC_STATUS   0x11

Definition at line 235 of file e1000hw.h.

◆ E1000_PHY_STATUS

#define E1000_PHY_STATUS   0x01

Definition at line 234 of file e1000hw.h.

◆ E1000_PS_LINK_STATUS

#define E1000_PS_LINK_STATUS   (1 << 2)

Definition at line 239 of file e1000hw.h.

◆ E1000_PSS_SPEED_AND_DUPLEX

#define E1000_PSS_SPEED_AND_DUPLEX   (1 << 11) /* Speed and Duplex Resolved */

Definition at line 244 of file e1000hw.h.

◆ E1000_PSS_SPEEDMASK

#define E1000_PSS_SPEEDMASK   (3 << E1000_PSS_SPEEDSHIFT)

Definition at line 246 of file e1000hw.h.

◆ E1000_PSS_SPEEDSHIFT

#define E1000_PSS_SPEEDSHIFT   14

Definition at line 245 of file e1000hw.h.

◆ E1000_RAH_AV

#define E1000_RAH_AV   (1 << 31) /* Address Valid */

Definition at line 221 of file e1000hw.h.

◆ E1000_RCTL_BAM

#define E1000_RCTL_BAM   (1 << 15) /* Broadcast Accept Mode */

Definition at line 201 of file e1000hw.h.

◆ E1000_RCTL_BSEX

#define E1000_RCTL_BSEX   (1 << 25) /* Buffer Size Extension */

Definition at line 204 of file e1000hw.h.

◆ E1000_RCTL_BSIZE_SHIFT

#define E1000_RCTL_BSIZE_SHIFT   16

Definition at line 202 of file e1000hw.h.

◆ E1000_RCTL_EN

#define E1000_RCTL_EN   (1 << 1) /* Receiver Enable */

Definition at line 197 of file e1000hw.h.

◆ E1000_RCTL_FILTER_BITS

Definition at line 207 of file e1000hw.h.

◆ E1000_RCTL_MPE

#define E1000_RCTL_MPE   (1 << 4) /* Multicast Promiscuous Enabled */

Definition at line 200 of file e1000hw.h.

◆ E1000_RCTL_PMCF

#define E1000_RCTL_PMCF   (1 << 23) /* Pass MAC Control Frames */

Definition at line 203 of file e1000hw.h.

◆ E1000_RCTL_SBP

#define E1000_RCTL_SBP   (1 << 2) /* Store Bad Packets */

Definition at line 198 of file e1000hw.h.

◆ E1000_RCTL_SECRC

#define E1000_RCTL_SECRC   (1 << 26) /* Strip Ethernet CRC from incoming packet */

Definition at line 205 of file e1000hw.h.

◆ E1000_RCTL_UPE

#define E1000_RCTL_UPE   (1 << 3) /* Unicast Promiscuous Enabled */

Definition at line 199 of file e1000hw.h.

◆ E1000_RDESC_STATUS_DD

#define E1000_RDESC_STATUS_DD   (1 << 0) /* Descriptor Done */

Definition at line 62 of file e1000hw.h.

◆ E1000_RDESC_STATUS_EOP

#define E1000_RDESC_STATUS_EOP   (1 << 1) /* End of Packet */

Definition at line 61 of file e1000hw.h.

◆ E1000_RDESC_STATUS_IXSM

#define E1000_RDESC_STATUS_IXSM   (1 << 2) /* Ignore Checksum Indication */

Definition at line 60 of file e1000hw.h.

◆ E1000_RDESC_STATUS_PIF

#define E1000_RDESC_STATUS_PIF   (1 << 7) /* Passed in-exact filter */

Definition at line 59 of file e1000hw.h.

◆ E1000_REG_CTRL

#define E1000_REG_CTRL   0x0000 /* Device Control Register, R/W */

Definition at line 114 of file e1000hw.h.

◆ E1000_REG_EERD

#define E1000_REG_EERD   0x0014 /* EEPROM Read Register, R/W */

Definition at line 116 of file e1000hw.h.

◆ E1000_REG_ICR

#define E1000_REG_ICR   0x00C0 /* Interrupt Cause Read, R/clr */

Definition at line 119 of file e1000hw.h.

◆ E1000_REG_IMC

#define E1000_REG_IMC   0x00D8 /* Interrupt Mask Clear, W */

Definition at line 123 of file e1000hw.h.

◆ E1000_REG_IMS

#define E1000_REG_IMS   0x00D0 /* Interrupt Mask Set/Read Register, R/W */

Definition at line 122 of file e1000hw.h.

◆ E1000_REG_ITR

#define E1000_REG_ITR   0x00C4 /* Interrupt Throttling Register, R/W */

Definition at line 120 of file e1000hw.h.

◆ E1000_REG_MDIC

#define E1000_REG_MDIC   0x0020 /* MDI Control Register, R/W */

Definition at line 117 of file e1000hw.h.

◆ E1000_REG_RADV

#define E1000_REG_RADV   0x282C /* Receive Absolute Delay Timer, R/W */

Definition at line 135 of file e1000hw.h.

◆ E1000_REG_RAH

#define E1000_REG_RAH   0x5404 /* Receive Address High, R/W */

Definition at line 147 of file e1000hw.h.

◆ E1000_REG_RAL

#define E1000_REG_RAL   0x5400 /* Receive Address Low, R/W */

Definition at line 146 of file e1000hw.h.

◆ E1000_REG_RCTL

#define E1000_REG_RCTL   0x0100 /* Receive Control Register, R/W */

Definition at line 125 of file e1000hw.h.

◆ E1000_REG_RDBAH

#define E1000_REG_RDBAH   0x2804 /* Receive Descriptor Base Address High, R/W */

Definition at line 130 of file e1000hw.h.

◆ E1000_REG_RDBAL

#define E1000_REG_RDBAL   0x2800 /* Receive Descriptor Base Address Low, R/W */

Definition at line 129 of file e1000hw.h.

◆ E1000_REG_RDH

#define E1000_REG_RDH   0x2810 /* Receive Descriptor Head, R/W */

Definition at line 132 of file e1000hw.h.

◆ E1000_REG_RDLEN

#define E1000_REG_RDLEN   0x2808 /* Receive Descriptor Length, R/W */

Definition at line 131 of file e1000hw.h.

◆ E1000_REG_RDT

#define E1000_REG_RDT   0x2818 /* Receive Descriptor Tail, R/W */

Definition at line 133 of file e1000hw.h.

◆ E1000_REG_RDTR

#define E1000_REG_RDTR   0x2820 /* Receive Delay Timer, R/W */

Definition at line 134 of file e1000hw.h.

◆ E1000_REG_STATUS

#define E1000_REG_STATUS   0x0008 /* Device Status Register, R */

Definition at line 115 of file e1000hw.h.

◆ E1000_REG_TADV

#define E1000_REG_TADV   0x382C /* Transmit Absolute Delay Timer, R/W */

Definition at line 143 of file e1000hw.h.

◆ E1000_REG_TCTL

#define E1000_REG_TCTL   0x0400 /* Transmit Control Register, R/W */

Definition at line 126 of file e1000hw.h.

◆ E1000_REG_TDBAH

#define E1000_REG_TDBAH   0x3804 /* Transmit Descriptor Base Address High, R/W */

Definition at line 138 of file e1000hw.h.

◆ E1000_REG_TDBAL

#define E1000_REG_TDBAL   0x3800 /* Transmit Descriptor Base Address Low, R/W */

Definition at line 137 of file e1000hw.h.

◆ E1000_REG_TDH

#define E1000_REG_TDH   0x3810 /* Transmit Descriptor Head, R/W */

Definition at line 140 of file e1000hw.h.

◆ E1000_REG_TDLEN

#define E1000_REG_TDLEN   0x3808 /* Transmit Descriptor Length, R/W */

Definition at line 139 of file e1000hw.h.

◆ E1000_REG_TDT

#define E1000_REG_TDT   0x3818 /* Transmit Descriptor Tail, R/W */

Definition at line 141 of file e1000hw.h.

◆ E1000_REG_TIDV

#define E1000_REG_TIDV   0x3820 /* Transmit Interrupt Delay Value, R/W */

Definition at line 142 of file e1000hw.h.

◆ E1000_REG_TIPG

#define E1000_REG_TIPG   0x0410 /* Transmit IPG Register, R/W */

Definition at line 127 of file e1000hw.h.

◆ E1000_REG_VET

#define E1000_REG_VET   0x0038 /* VLAN Ether Type, R/W */

Definition at line 118 of file e1000hw.h.

◆ E1000_STATUS_FD

#define E1000_STATUS_FD   (1 << 0) /* Full Duplex Indication */

Definition at line 159 of file e1000hw.h.

◆ E1000_STATUS_LU

#define E1000_STATUS_LU   (1 << 1) /* Link Up Indication */

Definition at line 160 of file e1000hw.h.

◆ E1000_STATUS_SPEEDMASK

#define E1000_STATUS_SPEEDMASK   (3 << E1000_STATUS_SPEEDSHIFT)

Definition at line 162 of file e1000hw.h.

◆ E1000_STATUS_SPEEDSHIFT

#define E1000_STATUS_SPEEDSHIFT   6 /* Link speed setting */

Definition at line 161 of file e1000hw.h.

◆ E1000_TCTL_EN

#define E1000_TCTL_EN   (1 << 1) /* Transmit Enable */

Definition at line 211 of file e1000hw.h.

◆ E1000_TCTL_PSP

#define E1000_TCTL_PSP   (1 << 3) /* Pad Short Packets */

Definition at line 212 of file e1000hw.h.

◆ E1000_TDESC_CMD_EOP

#define E1000_TDESC_CMD_EOP   (1 << 0) /* End Of Packet */

Definition at line 82 of file e1000hw.h.

◆ E1000_TDESC_CMD_IDE

#define E1000_TDESC_CMD_IDE   (1 << 7) /* Interrupt Delay Enable */

Definition at line 79 of file e1000hw.h.

◆ E1000_TDESC_CMD_IFCS

#define E1000_TDESC_CMD_IFCS   (1 << 1) /* Insert FCS */

Definition at line 81 of file e1000hw.h.

◆ E1000_TDESC_CMD_RS

#define E1000_TDESC_CMD_RS   (1 << 3) /* Report Status */

Definition at line 80 of file e1000hw.h.

◆ E1000_TDESC_STATUS_DD

#define E1000_TDESC_STATUS_DD   (1 << 0) /* Descriptor Done */

Definition at line 84 of file e1000hw.h.

◆ E1000_TIPG_IPGR1_DEF

#define E1000_TIPG_IPGR1_DEF   (10 << 10) /* IPG Receive Time 1 */

Definition at line 216 of file e1000hw.h.

◆ E1000_TIPG_IPGR2_DEF

#define E1000_TIPG_IPGR2_DEF   (10 << 20) /* IPG Receive Time 2 */

Definition at line 217 of file e1000hw.h.

◆ E1000_TIPG_IPGT_DEF

#define E1000_TIPG_IPGT_DEF   (10 << 0) /* IPG Transmit Time */

Definition at line 215 of file e1000hw.h.

◆ HW_VENDOR_INTEL

#define HW_VENDOR_INTEL   0x8086

Definition at line 13 of file e1000hw.h.

◆ IEEE_802_ADDR_LENGTH

#define IEEE_802_ADDR_LENGTH   6

Definition at line 11 of file e1000hw.h.

◆ MAX_EEPROM_READ_ATTEMPTS

#define MAX_EEPROM_READ_ATTEMPTS   10000

Definition at line 20 of file e1000hw.h.

◆ MAX_INTS_PER_SEC

#define MAX_INTS_PER_SEC   2000

Definition at line 192 of file e1000hw.h.

◆ MAX_PHY_READ_ATTEMPTS

#define MAX_PHY_READ_ATTEMPTS   1800

Definition at line 18 of file e1000hw.h.

◆ MAX_PHY_REG_ADDRESS

#define MAX_PHY_REG_ADDRESS   0x1F

Definition at line 17 of file e1000hw.h.

◆ MAX_RESET_ATTEMPTS

#define MAX_RESET_ATTEMPTS   10

Definition at line 15 of file e1000hw.h.

◆ MAXIMUM_MULTICAST_ADDRESSES

#define MAXIMUM_MULTICAST_ADDRESSES   16

Definition at line 23 of file e1000hw.h.

◆ NUM_RECEIVE_DESCRIPTORS

#define NUM_RECEIVE_DESCRIPTORS   128

Definition at line 109 of file e1000hw.h.

◆ NUM_TRANSMIT_DESCRIPTORS

#define NUM_TRANSMIT_DESCRIPTORS   128

Definition at line 108 of file e1000hw.h.

◆ NVM_MAGIC_SUM

#define NVM_MAGIC_SUM   0xBABA

Definition at line 228 of file e1000hw.h.

Typedef Documentation

◆ E1000_RCVBUF_SIZE

◆ E1000_RECEIVE_DESCRIPTOR

◆ E1000_TRANSMIT_DESCRIPTOR

◆ ETH_HEADER

◆ PE1000_RECEIVE_DESCRIPTOR

◆ PE1000_TRANSMIT_DESCRIPTOR

◆ PETH_HEADER

Enumeration Type Documentation

◆ _E1000_RCVBUF_SIZE

Enumerator
E1000_RCVBUF_2048 
E1000_RCVBUF_1024 
E1000_RCVBUF_512 
E1000_RCVBUF_256 
E1000_RCVBUF_INDEXMASK 
E1000_RCVBUF_RESERVED 
E1000_RCVBUF_16384 
E1000_RCVBUF_8192 
E1000_RCVBUF_4096 

Definition at line 37 of file e1000hw.h.

Function Documentation

◆ C_ASSERT() [1/3]

C_ASSERT ( sizeof(ETH_HEADER = =14)

◆ C_ASSERT() [2/3]

C_ASSERT ( sizeof(E1000_RECEIVE_DESCRIPTOR = =16)

◆ C_ASSERT() [3/3]

C_ASSERT ( sizeof(E1000_TRANSMIT_DESCRIPTOR = =16)