hardware.h File Reference

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Macros
#define	FLOPPY_DEFAULT_IRQ   0x6
#define	FDC_PORT_BYTES   0x8
#define	STATUS_REGISTER_A   0x0 /* Read; PS/2 Only */
#define	STATUS_REGISTER_B   0x1 /* Read; PS/2 Only */
#define	DIGITAL_OUTPUT_REGISTER   0x2 /* Read/Write */
#define	TAPE_DRIVE_REGISTER   0x3 /* Read/Write */
#define	MAIN_STATUS_REGISTER   0x4 /* Read */
#define	DATA_RATE_SELECT_REGISTER   0x4 /* Write */
#define	FIFO   0x5 /* Read/Write */
#define	RESERVED_REGISTER   0x6 /* Reserved */
#define	DIGITAL_INPUT_REGISTER   0x7 /* Read; PS/2 Only */
#define	CONFIGURATION_CONTROL_REGISTER   0x7 /* Write; PS/2 Only */
#define	DSRA_DIRECTION   0x1
#define	DSRA_WRITE_PROTECT   0x2
#define	DSRA_INDEX   0x4
#define	DSRA_HEAD_1_SELECT   0x8
#define	DSRA_TRACK_0   0x10
#define	DSRA_STEP   0x20
#define	DSRA_SECOND_DRIVE_INSTALLED   0x40
#define	DSRA_INTERRUPT_PENDING   0x80
#define	DSRB_MOTOR_ENABLE_0   0x1
#define	DSRB_MOTOR_ENABLE_1   0x2
#define	DSRB_WRITE_ENABLE   0x4
#define	DSRB_READ_DATA   0x8
#define	DSRB_WRITE_DATA   0x10
#define	DSRB_DRIVE_SELECT   0x20
#define	DOR_FLOPPY_DRIVE_SELECT   0x3 /* Covers 2 bits, defined below */
#define	DOR_FDC_ENABLE   0x4 /* from the website */
#define	DOR_RESET   0x4 /* from the Intel guide; 0 = resetting, 1 = enabled */
#define	DOR_DMA_IO_INTERFACE_ENABLE   0x8 /* Reserved on PS/2 */
#define	DOR_FLOPPY_MOTOR_ON_A   0x10
#define	DOR_FLOPPY_MOTOR_ON_B   0x20
#define	DOR_FLOPPY_MOTOR_ON_C   0x40 /* Reserved on PS/2 */
#define	DOR_FLOPPY_MOTOR_ON_D   0x80 /* Reserved on PS/2 */
#define	DOR_FLOPPY_DRIVE_SELECT_A   0x0
#define	DOR_FLOPPY_DRIVE_SELECT_B   0x1
#define	DOR_FLOPPY_DRIVE_SELECT_C   0x2 /* Reserved on PS/2 */
#define	DOR_FLOPPY_DRIVE_SELECT_D   0x3 /* Reserved on PS/2 */
#define	MSR_FLOPPY_BUSY_0   0x1
#define	MSR_FLOPPY_BUSY_1   0x2
#define	MSR_FLOPPY_BUSY_2   0x4 /* Reserved on PS/2 */
#define	MSR_FLOPPY_BUSY_3   0x8 /* Reserved on PS/2 */
#define	MSR_READ_WRITE_IN_PROGRESS   0x10
#define	MSR_NON_DMA_MODE   0x20
#define	MSR_IO_DIRECTION   0x40 /* Determines meaning of Command Status Registers */
#define	MSR_DATA_REG_READY_FOR_IO   0x80
#define	DRSR_DSEL   0x3 /* covers two bits as defined below */
#define	DRSR_PRECOMP   0x1c /* covers three bits as defined below */
#define	DRSR_MBZ   0x20
#define	DRSR_POWER_DOWN   0x40
#define	DRSR_SW_RESET   0x80
#define	DRSR_DSEL_500KBPS   0x0
#define	DRSR_DSEL_300KBPS   0x1
#define	DRSR_DSEL_250KBPS   0x2
#define	DRSR_DSEL_1MBPS   0x3
#define	SR0_UNIT_SELECTED_AT_INTERRUPT   0x3 /* Covers two bits as defined below */
#define	SR0_HEAD_NUMBER_AT_INTERRUPT   0x4 /* Values defined below */
#define	SR0_NOT_READY_ON_READ_WRITE   0x8 /* Unused in PS/2 */
#define	SR0_SS_ACCESS_TO_HEAD_1   0x8 /* Unused in PS/2 */
#define	SR0_EQUIPMENT_CHECK   0x10
#define	SR0_SEEK_COMPLETE   0x20
#define	SR0_LAST_COMMAND_STATUS   0xC0 /* Covers two bits as defined below */
#define	SR0_UNIT_SELECTED_A   0x0
#define	SR0_UNIT_SELECTED_B   0x1
#define	SR0_UNIT_SELECTED_C   0x2
#define	SR0_UNIT_SELECTED_D   0x3
#define	SR0_PS2_UNIT_SELECTED_A   0x1 /* PS/2 uses only two drives: A = 01b B = 10b */
#define	SR0_PST_UNIT_SELECTED_B   0x2
#define	SR0_HEAD_0   0x0
#define	SR0_HEAD_1   0x1
#define	SR0_LCS_SUCCESS   0x0
#define	SR0_LCS_TERMINATED_ABNORMALLY   0x40
#define	SR0_LCS_INVALID_COMMAND_ISSUED   0x80
#define	SR0_LCS_READY_SIGNAL_CHANGED   0xc0 /* Reserved on PS/2; a/k/a abnormal termination due to polling */
#define	SR1_CANNOT_FIND_ID_ADDRESS   0x1 /* Mimics SR2_WRONG_CYLINDER_DETECTED */
#define	SR1_WRITE_PROTECT_DETECTED   0x2
#define	SR1_CANNOT_FIND_SECTOR_ID   0x4
#define	SR1_OVERRUN   0x10
#define	SR1_CRC_ERROR   0x20
#define	SR1_END_OF_CYLINDER   0x80
#define	SR2_MISSING_ADDRESS_MARK   0x1
#define	SR2_BAD_CYLINDER   0x2
#define	SR2_SCAN_COMMAND_FAILED   0x4
#define	SR2_SCAN_COMMAND_EQUAL   0x8
#define	SR2_WRONG_CYLINDER_DETECTED   0x10 /* Mimics SR1_CANNOT_FIND_ID_ADDRESS */
#define	SR2_CRC_ERROR_IN_SECTOR_DATA   0x20
#define	SR2_SECTOR_WITH_DELETED_DATA   0x40
#define	SR3_UNIT_SELECTED   0x3 /* Covers two bits; defined below */
#define	SR3_SIDE_HEAD_SELECT_STATUS   0x4 /* Values defined below */
#define	SR3_TWO_SIDED_STATUS_SIGNAL   0x8
#define	SR3_TRACK_ZERO_STATUS_SIGNAL   0x10
#define	SR3_READY_STATUS_SIGNAL   0x20
#define	SR3_WRITE_PROTECT_STATUS_SIGNAL   0x40
#define	SR3_FAULT_STATUS_SIGNAL   0x80
#define	SR3_UNIT_SELECTED_A   0x0
#define	SR3_UNIT_SELECTED_B   0x1
#define	SR3_UNIT_SELECTED_C   0x2
#define	SR3_UNIT_SELECTED_D   0x3
#define	SR3_SHSS_HEAD_0   0x0
#define	SR3_SHSS_HEAD_1   0x1
#define	DIR_HIGH_DENSITY_SELECT   0x1
#define	DIR_DISKETTE_CHANGE   0x80
#define	CCR_DRC   0x3 /* Covers two bits, defined below */
#define	CCR_DRC_0   0x1
#define	CCR_DRC_1   0x2
#define	CCR_DRC_500000   0x0
#define	CCR_DRC_250000   0x2
#define	COMMAND_READ_TRACK   0x2
#define	COMMAND_SPECIFY   0x3
#define	COMMAND_SENSE_DRIVE_STATUS   0x4
#define	COMMAND_WRITE_DATA   0x5
#define	COMMAND_READ_DATA   0x6
#define	COMMAND_RECALIBRATE   0x7
#define	COMMAND_SENSE_INTERRUPT_STATUS   0x8
#define	COMMAND_WRITE_DELETED_DATA   0x9
#define	COMMAND_READ_ID   0xA
#define	COMMAND_READ_DELETED_DATA   0xC
#define	COMMAND_FORMAT_TRACK   0xD
#define	COMMAND_SEEK   0xF
#define	COMMAND_VERSION   0x10
#define	COMMAND_SCAN_EQUAL   0x11
#define	COMMAND_CONFIGURE   0x13
#define	COMMAND_SCAN_LOW_OR_EQUAL   0x19
#define	COMMAND_SCAN_HIGH_OR_EQUAL   0x1D
#define	READ_DATA_DS0   0x1
#define	READ_DATA_DS1   0x2
#define	READ_DATA_HDS   0x4
#define	READ_DATA_SK   0x20
#define	READ_DATA_MFM   0x40
#define	READ_DATA_MT   0x80
#define	READ_ID_MFM   0x40
#define	SPECIFY_HLT_1M   0x10 /* 16ms; based on intel data sheet */
#define	SPECIFY_HLT_500K   0x8 /* 16ms; based on intel data sheet */
#define	SPECIFY_HLT_300K   0x6 /* 16ms; based on intel data sheet */
#define	SPECIFY_HLT_250K   0x4 /* 16ms; based on intel data sheet */
#define	SPECIFY_HUT_1M   0x0 /* Need to figure out these eight values; 0 is max */
#define	SPECIFY_HUT_500K   0x0
#define	SPECIFY_HUT_300K   0x0
#define	SPECIFY_HUT_250K   0x0
#define	SPECIFY_SRT_1M   0x0
#define	SPECIFY_SRT_500K   0x0
#define	SPECIFY_SRT_300K   0x0
#define	SPECIFY_SRT_250K   0x0
#define	COMMAND_UNIT_SELECT   0x3 /* Covers two bits; defined below */
#define	COMMAND_UNIT_SELECT_0   0x1
#define	COMMAND_UNIT_SELECT_1   0x2
#define	COMMAND_HEAD_NUMBER   0x4
#define	COMMAND_HEAD_NUMBER_SHIFT   0x2
#define	VERSION_ENHANCED   0x90
#define	CUS_UNIT_0   0x0
#define	CUS_UNIT_1   0x1
#define	CONFIGURE_FIFOTHR   0xf
#define	CONFIGURE_POLL   0x10
#define	CONFIGURE_EFIFO   0x20
#define	CONFIGURE_EIS   0x40
#define	CONFIGURE_PRETRK   0xff
#define	COMMAND_HEAD_0   0x0
#define	COMMAND_HEAD_1   0x1
#define	HW_128_BYTES_PER_SECTOR   0x0
#define	HW_256_BYTES_PER_SECTOR   0x1
#define	HW_512_BYTES_PER_SECTOR   0x2
#define	HW_1024_BYTES_PER_SECTOR   0x3

Functions
NTSTATUS NTAPI	HwTurnOnMotor (PDRIVE_INFO DriveInfo)
NTSTATUS NTAPI	HwSenseDriveStatus (PDRIVE_INFO DriveInfo)
NTSTATUS NTAPI	HwReadWriteData (PCONTROLLER_INFO ControllerInfo, BOOLEAN Read, UCHAR Unit, UCHAR Cylinder, UCHAR Head, UCHAR Sector, UCHAR BytesPerSector, UCHAR EndOfTrack, UCHAR Gap3Length, UCHAR DataLength)
NTSTATUS NTAPI	HwRecalibrate (PDRIVE_INFO DriveInfo)
NTSTATUS NTAPI	HwSenseInterruptStatus (PCONTROLLER_INFO ControllerInfo)
NTSTATUS NTAPI	HwReadId (PDRIVE_INFO DriveInfo, UCHAR Head)
NTSTATUS NTAPI	HwFormatTrack (PCONTROLLER_INFO ControllerInfo, UCHAR Unit, UCHAR Head, UCHAR BytesPerSector, UCHAR SectorsPerTrack, UCHAR Gap3Length, UCHAR FillerPattern)
NTSTATUS NTAPI	HwSeek (PDRIVE_INFO DriveInfo, UCHAR Cylinder)
NTSTATUS NTAPI	HwReadWriteResult (PCONTROLLER_INFO ControllerInfo)
NTSTATUS NTAPI	HwGetVersion (PCONTROLLER_INFO ControllerInfo)
NTSTATUS NTAPI	HwConfigure (PCONTROLLER_INFO ControllerInfo, BOOLEAN EIS, BOOLEAN EFIFO, BOOLEAN POLL, UCHAR FIFOTHR, UCHAR PRETRK)
NTSTATUS NTAPI	HwRecalibrateResult (PCONTROLLER_INFO ControllerInfo)
NTSTATUS NTAPI	HwDiskChanged (PDRIVE_INFO DriveInfo, PBOOLEAN DiskChanged)
NTSTATUS NTAPI	HwSenseDriveStatusResult (PCONTROLLER_INFO ControllerInfo, PUCHAR Status)
NTSTATUS NTAPI	HwSpecify (PCONTROLLER_INFO ControllerInfo, UCHAR HeadLoadTime, UCHAR HeadUnloadTime, UCHAR StepRateTime, BOOLEAN NonDma)
NTSTATUS NTAPI	HwReadIdResult (PCONTROLLER_INFO ControllerInfo, PUCHAR CurCylinder, PUCHAR CurHead)
NTSTATUS NTAPI	HwSetDataRate (PCONTROLLER_INFO ControllerInfo, UCHAR DataRate)
NTSTATUS NTAPI	HwReset (PCONTROLLER_INFO Controller)
NTSTATUS NTAPI	HwPowerOff (PCONTROLLER_INFO ControllerInfo)
VOID NTAPI	HwDumpRegisters (PCONTROLLER_INFO ControllerInfo)
NTSTATUS NTAPI	HwTurnOffMotor (PCONTROLLER_INFO ControllerInfo)

Macro Definition Documentation

CCR_DRC

#define CCR_DRC   0x3 /* Covers two bits, defined below */

Definition at line 179 of file hardware.h.

CCR_DRC_0

#define CCR_DRC_0   0x1

Definition at line 180 of file hardware.h.

CCR_DRC_1

#define CCR_DRC_1   0x2

Definition at line 181 of file hardware.h.

CCR_DRC_250000

#define CCR_DRC_250000   0x2

Definition at line 185 of file hardware.h.

CCR_DRC_500000

#define CCR_DRC_500000   0x0

Definition at line 184 of file hardware.h.

COMMAND_CONFIGURE

#define COMMAND_CONFIGURE   0x13

Definition at line 202 of file hardware.h.

COMMAND_FORMAT_TRACK

#define COMMAND_FORMAT_TRACK   0xD

Definition at line 198 of file hardware.h.

COMMAND_HEAD_0

#define COMMAND_HEAD_0   0x0

Definition at line 253 of file hardware.h.

COMMAND_HEAD_1

#define COMMAND_HEAD_1   0x1

Definition at line 254 of file hardware.h.

COMMAND_HEAD_NUMBER

#define COMMAND_HEAD_NUMBER   0x4

Definition at line 235 of file hardware.h.

COMMAND_HEAD_NUMBER_SHIFT

#define COMMAND_HEAD_NUMBER_SHIFT   0x2

Definition at line 236 of file hardware.h.

COMMAND_READ_DATA

#define COMMAND_READ_DATA   0x6

Definition at line 192 of file hardware.h.

COMMAND_READ_DELETED_DATA

#define COMMAND_READ_DELETED_DATA   0xC

Definition at line 197 of file hardware.h.

COMMAND_READ_ID

#define COMMAND_READ_ID   0xA

Definition at line 196 of file hardware.h.

COMMAND_READ_TRACK

#define COMMAND_READ_TRACK   0x2

Definition at line 188 of file hardware.h.

COMMAND_RECALIBRATE

#define COMMAND_RECALIBRATE   0x7

Definition at line 193 of file hardware.h.

COMMAND_SCAN_EQUAL

#define COMMAND_SCAN_EQUAL   0x11

Definition at line 201 of file hardware.h.

COMMAND_SCAN_HIGH_OR_EQUAL

#define COMMAND_SCAN_HIGH_OR_EQUAL   0x1D

Definition at line 204 of file hardware.h.

COMMAND_SCAN_LOW_OR_EQUAL

#define COMMAND_SCAN_LOW_OR_EQUAL   0x19

Definition at line 203 of file hardware.h.

COMMAND_SEEK

#define COMMAND_SEEK   0xF

Definition at line 199 of file hardware.h.

COMMAND_SENSE_DRIVE_STATUS

#define COMMAND_SENSE_DRIVE_STATUS   0x4

Definition at line 190 of file hardware.h.

COMMAND_SENSE_INTERRUPT_STATUS

#define COMMAND_SENSE_INTERRUPT_STATUS   0x8

Definition at line 194 of file hardware.h.

COMMAND_SPECIFY

#define COMMAND_SPECIFY   0x3

Definition at line 189 of file hardware.h.

COMMAND_UNIT_SELECT

#define COMMAND_UNIT_SELECT   0x3 /* Covers two bits; defined below */

Definition at line 232 of file hardware.h.

COMMAND_UNIT_SELECT_0

#define COMMAND_UNIT_SELECT_0   0x1

Definition at line 233 of file hardware.h.

COMMAND_UNIT_SELECT_1

#define COMMAND_UNIT_SELECT_1   0x2

Definition at line 234 of file hardware.h.

COMMAND_VERSION

#define COMMAND_VERSION   0x10

Definition at line 200 of file hardware.h.

COMMAND_WRITE_DATA

#define COMMAND_WRITE_DATA   0x5

Definition at line 191 of file hardware.h.

COMMAND_WRITE_DELETED_DATA

#define COMMAND_WRITE_DELETED_DATA   0x9

Definition at line 195 of file hardware.h.

CONFIGURATION_CONTROL_REGISTER

#define CONFIGURATION_CONTROL_REGISTER   0x7 /* Write; PS/2 Only */

Definition at line 52 of file hardware.h.

CONFIGURE_EFIFO

#define CONFIGURE_EFIFO   0x20

Definition at line 248 of file hardware.h.

CONFIGURE_EIS

#define CONFIGURE_EIS   0x40

Definition at line 249 of file hardware.h.

CONFIGURE_FIFOTHR

#define CONFIGURE_FIFOTHR   0xf

Definition at line 246 of file hardware.h.

CONFIGURE_POLL

#define CONFIGURE_POLL   0x10

Definition at line 247 of file hardware.h.

CONFIGURE_PRETRK

#define CONFIGURE_PRETRK   0xff

Definition at line 250 of file hardware.h.

CUS_UNIT_0

#define CUS_UNIT_0   0x0

Definition at line 242 of file hardware.h.

CUS_UNIT_1

#define CUS_UNIT_1   0x1

Definition at line 243 of file hardware.h.

DATA_RATE_SELECT_REGISTER

#define DATA_RATE_SELECT_REGISTER   0x4 /* Write */

Definition at line 48 of file hardware.h.

DIGITAL_INPUT_REGISTER

#define DIGITAL_INPUT_REGISTER   0x7 /* Read; PS/2 Only */

Definition at line 51 of file hardware.h.

DIGITAL_OUTPUT_REGISTER

#define DIGITAL_OUTPUT_REGISTER   0x2 /* Read/Write */

Definition at line 45 of file hardware.h.

DIR_DISKETTE_CHANGE

#define DIR_DISKETTE_CHANGE   0x80

Definition at line 176 of file hardware.h.

DIR_HIGH_DENSITY_SELECT

#define DIR_HIGH_DENSITY_SELECT   0x1

Definition at line 175 of file hardware.h.

DOR_DMA_IO_INTERFACE_ENABLE

#define DOR_DMA_IO_INTERFACE_ENABLE   0x8 /* Reserved on PS/2 */

Definition at line 76 of file hardware.h.

DOR_FDC_ENABLE

#define DOR_FDC_ENABLE   0x4 /* from the website */

Definition at line 74 of file hardware.h.

DOR_FLOPPY_DRIVE_SELECT

#define DOR_FLOPPY_DRIVE_SELECT   0x3 /* Covers 2 bits, defined below */

Definition at line 73 of file hardware.h.

DOR_FLOPPY_DRIVE_SELECT_A

#define DOR_FLOPPY_DRIVE_SELECT_A   0x0

Definition at line 83 of file hardware.h.

DOR_FLOPPY_DRIVE_SELECT_B

#define DOR_FLOPPY_DRIVE_SELECT_B   0x1

Definition at line 84 of file hardware.h.

DOR_FLOPPY_DRIVE_SELECT_C

#define DOR_FLOPPY_DRIVE_SELECT_C   0x2 /* Reserved on PS/2 */

Definition at line 85 of file hardware.h.

DOR_FLOPPY_DRIVE_SELECT_D

#define DOR_FLOPPY_DRIVE_SELECT_D   0x3 /* Reserved on PS/2 */

Definition at line 86 of file hardware.h.

DOR_FLOPPY_MOTOR_ON_A

#define DOR_FLOPPY_MOTOR_ON_A   0x10

Definition at line 77 of file hardware.h.

DOR_FLOPPY_MOTOR_ON_B

#define DOR_FLOPPY_MOTOR_ON_B   0x20

Definition at line 78 of file hardware.h.

DOR_FLOPPY_MOTOR_ON_C

#define DOR_FLOPPY_MOTOR_ON_C   0x40 /* Reserved on PS/2 */

Definition at line 79 of file hardware.h.

DOR_FLOPPY_MOTOR_ON_D

#define DOR_FLOPPY_MOTOR_ON_D   0x80 /* Reserved on PS/2 */

Definition at line 80 of file hardware.h.

DOR_RESET

#define DOR_RESET   0x4 /* from the Intel guide; 0 = resetting, 1 = enabled */

Definition at line 75 of file hardware.h.

DRSR_DSEL

#define DRSR_DSEL   0x3 /* covers two bits as defined below */

Definition at line 99 of file hardware.h.

DRSR_DSEL_1MBPS

#define DRSR_DSEL_1MBPS   0x3

Definition at line 109 of file hardware.h.

DRSR_DSEL_250KBPS

#define DRSR_DSEL_250KBPS   0x2

Definition at line 108 of file hardware.h.

DRSR_DSEL_300KBPS

#define DRSR_DSEL_300KBPS   0x1

Definition at line 107 of file hardware.h.

DRSR_DSEL_500KBPS

#define DRSR_DSEL_500KBPS   0x0

Definition at line 106 of file hardware.h.

DRSR_MBZ

#define DRSR_MBZ   0x20

Definition at line 101 of file hardware.h.

DRSR_POWER_DOWN

#define DRSR_POWER_DOWN   0x40

Definition at line 102 of file hardware.h.

DRSR_PRECOMP

#define DRSR_PRECOMP   0x1c /* covers three bits as defined below */

Definition at line 100 of file hardware.h.

DRSR_SW_RESET

#define DRSR_SW_RESET   0x80

Definition at line 103 of file hardware.h.

DSRA_DIRECTION

#define DSRA_DIRECTION   0x1

Definition at line 55 of file hardware.h.

DSRA_HEAD_1_SELECT

#define DSRA_HEAD_1_SELECT   0x8

Definition at line 58 of file hardware.h.

DSRA_INDEX

#define DSRA_INDEX   0x4

Definition at line 57 of file hardware.h.

DSRA_INTERRUPT_PENDING

#define DSRA_INTERRUPT_PENDING   0x80

Definition at line 62 of file hardware.h.

DSRA_SECOND_DRIVE_INSTALLED

#define DSRA_SECOND_DRIVE_INSTALLED   0x40

Definition at line 61 of file hardware.h.

DSRA_STEP

#define DSRA_STEP   0x20

Definition at line 60 of file hardware.h.

DSRA_TRACK_0

#define DSRA_TRACK_0   0x10

Definition at line 59 of file hardware.h.

DSRA_WRITE_PROTECT

#define DSRA_WRITE_PROTECT   0x2

Definition at line 56 of file hardware.h.

DSRB_DRIVE_SELECT

#define DSRB_DRIVE_SELECT   0x20

Definition at line 70 of file hardware.h.

DSRB_MOTOR_ENABLE_0

#define DSRB_MOTOR_ENABLE_0   0x1

Definition at line 65 of file hardware.h.

DSRB_MOTOR_ENABLE_1

#define DSRB_MOTOR_ENABLE_1   0x2

Definition at line 66 of file hardware.h.

DSRB_READ_DATA

#define DSRB_READ_DATA   0x8

Definition at line 68 of file hardware.h.

DSRB_WRITE_DATA

#define DSRB_WRITE_DATA   0x10

Definition at line 69 of file hardware.h.

DSRB_WRITE_ENABLE

#define DSRB_WRITE_ENABLE   0x4

Definition at line 67 of file hardware.h.

FDC_PORT_BYTES

#define FDC_PORT_BYTES   0x8

Definition at line 40 of file hardware.h.

FIFO

#define FIFO   0x5 /* Read/Write */

Definition at line 49 of file hardware.h.

FLOPPY_DEFAULT_IRQ

#define FLOPPY_DEFAULT_IRQ   0x6

Definition at line 39 of file hardware.h.

HW_1024_BYTES_PER_SECTOR

#define HW_1024_BYTES_PER_SECTOR   0x3

Definition at line 260 of file hardware.h.

HW_128_BYTES_PER_SECTOR

#define HW_128_BYTES_PER_SECTOR   0x0

Definition at line 257 of file hardware.h.

HW_256_BYTES_PER_SECTOR

#define HW_256_BYTES_PER_SECTOR   0x1

Definition at line 258 of file hardware.h.

HW_512_BYTES_PER_SECTOR

#define HW_512_BYTES_PER_SECTOR   0x2

Definition at line 259 of file hardware.h.

MAIN_STATUS_REGISTER

#define MAIN_STATUS_REGISTER   0x4 /* Read */

Definition at line 47 of file hardware.h.

MSR_DATA_REG_READY_FOR_IO

#define MSR_DATA_REG_READY_FOR_IO   0x80

Definition at line 96 of file hardware.h.

MSR_FLOPPY_BUSY_0

#define MSR_FLOPPY_BUSY_0   0x1

Definition at line 89 of file hardware.h.

MSR_FLOPPY_BUSY_1

#define MSR_FLOPPY_BUSY_1   0x2

Definition at line 90 of file hardware.h.

MSR_FLOPPY_BUSY_2

#define MSR_FLOPPY_BUSY_2   0x4 /* Reserved on PS/2 */

Definition at line 91 of file hardware.h.

MSR_FLOPPY_BUSY_3

#define MSR_FLOPPY_BUSY_3   0x8 /* Reserved on PS/2 */

Definition at line 92 of file hardware.h.

MSR_IO_DIRECTION

#define MSR_IO_DIRECTION   0x40 /* Determines meaning of Command Status Registers */

Definition at line 95 of file hardware.h.

MSR_NON_DMA_MODE

#define MSR_NON_DMA_MODE   0x20

Definition at line 94 of file hardware.h.

MSR_READ_WRITE_IN_PROGRESS

#define MSR_READ_WRITE_IN_PROGRESS   0x10

Definition at line 93 of file hardware.h.

READ_DATA_DS0

#define READ_DATA_DS0   0x1

Definition at line 207 of file hardware.h.

READ_DATA_DS1

#define READ_DATA_DS1   0x2

Definition at line 208 of file hardware.h.

READ_DATA_HDS

#define READ_DATA_HDS   0x4

Definition at line 209 of file hardware.h.

READ_DATA_MFM

#define READ_DATA_MFM   0x40

Definition at line 211 of file hardware.h.

READ_DATA_MT

#define READ_DATA_MT   0x80

Definition at line 212 of file hardware.h.

READ_DATA_SK

#define READ_DATA_SK   0x20

Definition at line 210 of file hardware.h.

READ_ID_MFM

#define READ_ID_MFM   0x40

Definition at line 215 of file hardware.h.

RESERVED_REGISTER

#define RESERVED_REGISTER   0x6 /* Reserved */

Definition at line 50 of file hardware.h.

SPECIFY_HLT_1M

#define SPECIFY_HLT_1M   0x10 /* 16ms; based on intel data sheet */

Definition at line 218 of file hardware.h.

SPECIFY_HLT_250K

#define SPECIFY_HLT_250K   0x4 /* 16ms; based on intel data sheet */

Definition at line 221 of file hardware.h.

SPECIFY_HLT_300K

#define SPECIFY_HLT_300K   0x6 /* 16ms; based on intel data sheet */

Definition at line 220 of file hardware.h.

SPECIFY_HLT_500K

#define SPECIFY_HLT_500K   0x8 /* 16ms; based on intel data sheet */

Definition at line 219 of file hardware.h.

SPECIFY_HUT_1M

#define SPECIFY_HUT_1M   0x0 /* Need to figure out these eight values; 0 is max */

Definition at line 222 of file hardware.h.

SPECIFY_HUT_250K

#define SPECIFY_HUT_250K   0x0

Definition at line 225 of file hardware.h.

SPECIFY_HUT_300K

#define SPECIFY_HUT_300K   0x0

Definition at line 224 of file hardware.h.

SPECIFY_HUT_500K

#define SPECIFY_HUT_500K   0x0

Definition at line 223 of file hardware.h.

SPECIFY_SRT_1M

#define SPECIFY_SRT_1M   0x0

Definition at line 226 of file hardware.h.

SPECIFY_SRT_250K

#define SPECIFY_SRT_250K   0x0

Definition at line 229 of file hardware.h.

SPECIFY_SRT_300K

#define SPECIFY_SRT_300K   0x0

Definition at line 228 of file hardware.h.

SPECIFY_SRT_500K

#define SPECIFY_SRT_500K   0x0

Definition at line 227 of file hardware.h.

SR0_EQUIPMENT_CHECK

#define SR0_EQUIPMENT_CHECK   0x10

Definition at line 116 of file hardware.h.

SR0_HEAD_0

#define SR0_HEAD_0   0x0

Definition at line 129 of file hardware.h.

SR0_HEAD_1

#define SR0_HEAD_1   0x1

Definition at line 130 of file hardware.h.

SR0_HEAD_NUMBER_AT_INTERRUPT

#define SR0_HEAD_NUMBER_AT_INTERRUPT   0x4 /* Values defined below */

Definition at line 113 of file hardware.h.

SR0_LAST_COMMAND_STATUS

#define SR0_LAST_COMMAND_STATUS   0xC0 /* Covers two bits as defined below */

Definition at line 118 of file hardware.h.

SR0_LCS_INVALID_COMMAND_ISSUED

#define SR0_LCS_INVALID_COMMAND_ISSUED   0x80

Definition at line 135 of file hardware.h.

SR0_LCS_READY_SIGNAL_CHANGED

#define SR0_LCS_READY_SIGNAL_CHANGED   0xc0 /* Reserved on PS/2; a/k/a abnormal termination due to polling */

Definition at line 136 of file hardware.h.

SR0_LCS_SUCCESS

#define SR0_LCS_SUCCESS   0x0

Definition at line 133 of file hardware.h.

SR0_LCS_TERMINATED_ABNORMALLY

#define SR0_LCS_TERMINATED_ABNORMALLY   0x40

Definition at line 134 of file hardware.h.

SR0_NOT_READY_ON_READ_WRITE

#define SR0_NOT_READY_ON_READ_WRITE   0x8 /* Unused in PS/2 */

Definition at line 114 of file hardware.h.

SR0_PS2_UNIT_SELECTED_A

#define SR0_PS2_UNIT_SELECTED_A   0x1 /* PS/2 uses only two drives: A = 01b B = 10b */

Definition at line 125 of file hardware.h.

SR0_PST_UNIT_SELECTED_B

#define SR0_PST_UNIT_SELECTED_B   0x2

Definition at line 126 of file hardware.h.

SR0_SEEK_COMPLETE

#define SR0_SEEK_COMPLETE   0x20

Definition at line 117 of file hardware.h.

SR0_SS_ACCESS_TO_HEAD_1

#define SR0_SS_ACCESS_TO_HEAD_1   0x8 /* Unused in PS/2 */

Definition at line 115 of file hardware.h.

SR0_UNIT_SELECTED_A

#define SR0_UNIT_SELECTED_A   0x0

Definition at line 121 of file hardware.h.

SR0_UNIT_SELECTED_AT_INTERRUPT

#define SR0_UNIT_SELECTED_AT_INTERRUPT   0x3 /* Covers two bits as defined below */

Definition at line 112 of file hardware.h.

SR0_UNIT_SELECTED_B

#define SR0_UNIT_SELECTED_B   0x1

Definition at line 122 of file hardware.h.

SR0_UNIT_SELECTED_C

#define SR0_UNIT_SELECTED_C   0x2

Definition at line 123 of file hardware.h.

SR0_UNIT_SELECTED_D

#define SR0_UNIT_SELECTED_D   0x3

Definition at line 124 of file hardware.h.

SR1_CANNOT_FIND_ID_ADDRESS

#define SR1_CANNOT_FIND_ID_ADDRESS   0x1 /* Mimics SR2_WRONG_CYLINDER_DETECTED */

Definition at line 139 of file hardware.h.

SR1_CANNOT_FIND_SECTOR_ID

#define SR1_CANNOT_FIND_SECTOR_ID   0x4

Definition at line 141 of file hardware.h.

SR1_CRC_ERROR

#define SR1_CRC_ERROR   0x20

Definition at line 143 of file hardware.h.

SR1_END_OF_CYLINDER

#define SR1_END_OF_CYLINDER   0x80

Definition at line 144 of file hardware.h.

SR1_OVERRUN

#define SR1_OVERRUN   0x10

Definition at line 142 of file hardware.h.

SR1_WRITE_PROTECT_DETECTED

#define SR1_WRITE_PROTECT_DETECTED   0x2

Definition at line 140 of file hardware.h.

SR2_BAD_CYLINDER

#define SR2_BAD_CYLINDER   0x2

Definition at line 148 of file hardware.h.

SR2_CRC_ERROR_IN_SECTOR_DATA

#define SR2_CRC_ERROR_IN_SECTOR_DATA   0x20

Definition at line 152 of file hardware.h.

SR2_MISSING_ADDRESS_MARK

#define SR2_MISSING_ADDRESS_MARK   0x1

Definition at line 147 of file hardware.h.

SR2_SCAN_COMMAND_EQUAL

#define SR2_SCAN_COMMAND_EQUAL   0x8

Definition at line 150 of file hardware.h.

SR2_SCAN_COMMAND_FAILED

#define SR2_SCAN_COMMAND_FAILED   0x4

Definition at line 149 of file hardware.h.

SR2_SECTOR_WITH_DELETED_DATA

#define SR2_SECTOR_WITH_DELETED_DATA   0x40

Definition at line 153 of file hardware.h.

SR2_WRONG_CYLINDER_DETECTED

#define SR2_WRONG_CYLINDER_DETECTED   0x10 /* Mimics SR1_CANNOT_FIND_ID_ADDRESS */

Definition at line 151 of file hardware.h.

SR3_FAULT_STATUS_SIGNAL

#define SR3_FAULT_STATUS_SIGNAL   0x80

Definition at line 162 of file hardware.h.

SR3_READY_STATUS_SIGNAL

#define SR3_READY_STATUS_SIGNAL   0x20

Definition at line 160 of file hardware.h.

SR3_SHSS_HEAD_0

#define SR3_SHSS_HEAD_0   0x0

Definition at line 171 of file hardware.h.

SR3_SHSS_HEAD_1

#define SR3_SHSS_HEAD_1   0x1

Definition at line 172 of file hardware.h.

SR3_SIDE_HEAD_SELECT_STATUS

#define SR3_SIDE_HEAD_SELECT_STATUS   0x4 /* Values defined below */

Definition at line 157 of file hardware.h.

SR3_TRACK_ZERO_STATUS_SIGNAL

#define SR3_TRACK_ZERO_STATUS_SIGNAL   0x10

Definition at line 159 of file hardware.h.

SR3_TWO_SIDED_STATUS_SIGNAL

#define SR3_TWO_SIDED_STATUS_SIGNAL   0x8

Definition at line 158 of file hardware.h.

SR3_UNIT_SELECTED

#define SR3_UNIT_SELECTED   0x3 /* Covers two bits; defined below */

Definition at line 156 of file hardware.h.

SR3_UNIT_SELECTED_A

#define SR3_UNIT_SELECTED_A   0x0

Definition at line 165 of file hardware.h.

SR3_UNIT_SELECTED_B

#define SR3_UNIT_SELECTED_B   0x1

Definition at line 166 of file hardware.h.

SR3_UNIT_SELECTED_C

#define SR3_UNIT_SELECTED_C   0x2

Definition at line 167 of file hardware.h.

SR3_UNIT_SELECTED_D

#define SR3_UNIT_SELECTED_D   0x3

Definition at line 168 of file hardware.h.

SR3_WRITE_PROTECT_STATUS_SIGNAL

#define SR3_WRITE_PROTECT_STATUS_SIGNAL   0x40

Definition at line 161 of file hardware.h.

STATUS_REGISTER_A

#define STATUS_REGISTER_A   0x0 /* Read; PS/2 Only */

Definition at line 43 of file hardware.h.

STATUS_REGISTER_B

#define STATUS_REGISTER_B   0x1 /* Read; PS/2 Only */

Definition at line 44 of file hardware.h.

TAPE_DRIVE_REGISTER

#define TAPE_DRIVE_REGISTER   0x3 /* Read/Write */

Definition at line 46 of file hardware.h.

VERSION_ENHANCED

#define VERSION_ENHANCED   0x90

Definition at line 239 of file hardware.h.

Function Documentation

HwConfigure()

NTSTATUS NTAPI HwConfigure	(	PCONTROLLER_INFO	ControllerInfo,
		BOOLEAN	EIS,
		BOOLEAN	EFIFO,
		BOOLEAN	POLL,
		UCHAR	FIFOTHR,
		UCHAR	PRETRK
	)

Definition at line 703 of file hardware.c.

{
    UCHAR Buffer[4];
    int i;

    TRACE_(FLOPPY, "HwConfigure called\n");

    PAGED_CODE();

    Buffer[0] = COMMAND_CONFIGURE;
    Buffer[1] = 0;
    Buffer[2] = (EIS * CONFIGURE_EIS) + (EFIFO * CONFIGURE_EFIFO) + (POLL * CONFIGURE_POLL) + (FIFOTHR);
    Buffer[3] = PRETRK;

    for(i = 0; i < 4; i++)
        if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwConfigure: failed to write the fifo\n");
            return STATUS_UNSUCCESSFUL;
        }

    return STATUS_SUCCESS;
}

Referenced by InitController().

HwDiskChanged()

NTSTATUS NTAPI HwDiskChanged	(	PDRIVE_INFO	DriveInfo,
		PBOOLEAN	DiskChanged
	)

Definition at line 785 of file hardware.c.

{
    UCHAR Buffer;
    PCONTROLLER_INFO ControllerInfo = (PCONTROLLER_INFO) DriveInfo->ControllerInfo;

    Buffer = READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_INPUT_REGISTER);

    TRACE_(FLOPPY, "HwDiskChanged: read 0x%x from DIR\n", Buffer);

    if(ControllerInfo->Model30)
    {
        if(!(Buffer & DIR_DISKETTE_CHANGE))
        {
            INFO_(FLOPPY, "HdDiskChanged - Model30 - returning TRUE\n");
            *DiskChanged = TRUE;
        }
        else
        {
            INFO_(FLOPPY, "HdDiskChanged - Model30 - returning FALSE\n");
            *DiskChanged = FALSE;
        }
    }
    else
    {
        if(Buffer & DIR_DISKETTE_CHANGE)
        {
            INFO_(FLOPPY, "HdDiskChanged - PS2 - returning TRUE\n");
            *DiskChanged = TRUE;
        }
        else
        {
            INFO_(FLOPPY, "HdDiskChanged - PS2 - returning FALSE\n");
            *DiskChanged = FALSE;
        }
    }

    return STATUS_SUCCESS;
}

Referenced by DeviceIoctlPassive(), ReadWritePassive(), and ResetChangeFlag().

HwDumpRegisters()

VOID NTAPI HwDumpRegisters

(

PCONTROLLER_INFO

ControllerInfo

)

Definition at line 1029 of file hardware.c.

{
    UNREFERENCED_PARAMETER(ControllerInfo);

    INFO_(FLOPPY, "STATUS:\n");
    INFO_(FLOPPY, "STATUS_REGISTER_A = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + STATUS_REGISTER_A));
    INFO_(FLOPPY, "STATUS_REGISTER_B = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + STATUS_REGISTER_B));
    INFO_(FLOPPY, "DIGITAL_OUTPUT_REGISTER = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER));
    INFO_(FLOPPY, "MAIN_STATUS_REGISTER =0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + MAIN_STATUS_REGISTER));
    INFO_(FLOPPY, "DIGITAL_INPUT_REGISTER = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_INPUT_REGISTER));
}

Referenced by Get_Byte(), HwReset(), ReadWritePassive(), and Send_Byte().

HwFormatTrack()

NTSTATUS NTAPI HwFormatTrack	(	PCONTROLLER_INFO	ControllerInfo,
		UCHAR	Unit,
		UCHAR	Head,
		UCHAR	BytesPerSector,
		UCHAR	SectorsPerTrack,
		UCHAR	Gap3Length,
		UCHAR	FillerPattern
	)

Definition at line 611 of file hardware.c.

{
    UCHAR Buffer[6];
    int i;

    TRACE_(FLOPPY, "HwFormatTrack called\n");

    PAGED_CODE();

    Buffer[0] = COMMAND_FORMAT_TRACK;
    Buffer[1] = (Head << COMMAND_HEAD_NUMBER_SHIFT) | Unit;
    Buffer[2] = BytesPerSector;
    Buffer[3] = SectorsPerTrack;
    Buffer[4] = Gap3Length;
    Buffer[5] = FillerPattern;

    for(i = 0; i < 6; i++)
        if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwFormatTrack: unable to send bytes to floppy\n");
            return STATUS_UNSUCCESSFUL;
        }

    return STATUS_SUCCESS;
}

HwGetVersion()

NTSTATUS NTAPI HwGetVersion

(

PCONTROLLER_INFO

ControllerInfo

)

Definition at line 749 of file hardware.c.

{
    UCHAR Buffer;

    PAGED_CODE();

    if(Send_Byte(ControllerInfo, COMMAND_VERSION) != STATUS_SUCCESS)
    {
        WARN_(FLOPPY, "HwGetVersion: unable to write fifo\n");
        return STATUS_UNSUCCESSFUL;
    }

    if(Get_Byte(ControllerInfo, &Buffer) != STATUS_SUCCESS)
    {
        WARN_(FLOPPY, "HwGetVersion: unable to write fifo\n");
        return STATUS_UNSUCCESSFUL;
    }

    INFO_(FLOPPY, "HwGetVersion returning version 0x%x\n", Buffer);

    return Buffer;
}

Referenced by InitController().

HwPowerOff()

NTSTATUS NTAPI HwPowerOff

(

PCONTROLLER_INFO

ControllerInfo

)

Definition at line 1010 of file hardware.c.

{
    TRACE_(FLOPPY, "HwPowerOff called on controller 0x%p\n", ControllerInfo);

    WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DRSR_POWER_DOWN);

    return STATUS_SUCCESS;
}

Referenced by Unload().

HwReadId()

NTSTATUS NTAPI HwReadId	(	PDRIVE_INFO	DriveInfo,
		UCHAR	Head
	)

Definition at line 576 of file hardware.c.

{
    UCHAR Buffer[2];
    int i;

    TRACE_(FLOPPY, "HwReadId called\n");

    PAGED_CODE();

    Buffer[0] = COMMAND_READ_ID | READ_ID_MFM;
    Buffer[1] = (Head << COMMAND_HEAD_NUMBER_SHIFT) | DriveInfo->UnitNumber;

    for(i = 0; i < 2; i++)
        if(Send_Byte(DriveInfo->ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwReadId: unable to send bytes to fifo\n");
            return STATUS_UNSUCCESSFUL;
        }

    return STATUS_SUCCESS;
}

Referenced by RWDetermineMediaType(), and RWSeekToCylinder().

HwReadIdResult()

NTSTATUS NTAPI HwReadIdResult	(	PCONTROLLER_INFO	ControllerInfo,
		PUCHAR	CurCylinder,
		PUCHAR	CurHead
	)

Definition at line 864 of file hardware.c.

{
    UCHAR Buffer[7] = {0,0,0,0,0,0,0};
    int i;

    PAGED_CODE();

    for(i = 0; i < 7; i++)
        if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "ReadIdResult(): can't read from the controller\n");
            return STATUS_UNSUCCESSFUL;
        }

    /* Validate  that it did what we told it to */
    INFO_(FLOPPY, "ReadId results: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", Buffer[0], Buffer[1], Buffer[2], Buffer[3],
          Buffer[4], Buffer[5], Buffer[6]);

    /* Last command successful? */
    if((Buffer[0] & SR0_LAST_COMMAND_STATUS) != SR0_LCS_SUCCESS)
    {
        WARN_(FLOPPY, "ReadId didn't return last command success\n");
        return STATUS_UNSUCCESSFUL;
    }

    /* ID mark found? */
    if(Buffer[1] & SR1_CANNOT_FIND_ID_ADDRESS)
    {
        WARN_(FLOPPY, "ReadId didn't find an address mark\n");
        return STATUS_UNSUCCESSFUL;
    }

    if(CurCylinder)
        *CurCylinder = Buffer[3];

    if(CurHead)
        *CurHead = Buffer[4];

    return STATUS_SUCCESS;
}

Referenced by RWDetermineMediaType(), and RWSeekToCylinder().

HwReadWriteData()

NTSTATUS NTAPI HwReadWriteData	(	PCONTROLLER_INFO	ControllerInfo,
		BOOLEAN	Read,
		UCHAR	Unit,
		UCHAR	Cylinder,
		UCHAR	Head,
		UCHAR	Sector,
		UCHAR	BytesPerSector,
		UCHAR	EndOfTrack,
		UCHAR	Gap3Length,
		UCHAR	DataLength
	)

Definition at line 322 of file hardware.c.

{
    UCHAR Buffer[9];
    int i;

    PAGED_CODE();

    /* Shouldn't be using DataLength in this driver */
    ASSERT(DataLength == 0xff);

    /* Build the command to send */
    if(Read)
        Buffer[0] = COMMAND_READ_DATA;
    else
        Buffer[0] = COMMAND_WRITE_DATA;

    Buffer[0] |= READ_DATA_MFM | READ_DATA_MT;

    Buffer[1] = (Head << COMMAND_HEAD_NUMBER_SHIFT) | Unit;
    Buffer[2] = Cylinder;
    Buffer[3] = Head;
    Buffer[4] = Sector;
    Buffer[5] = BytesPerSector;
    Buffer[6] = EndOfTrack;
    Buffer[7] = Gap3Length;
    Buffer[8] = DataLength;

    /* Send the command */
    for(i = 0; i < 9; i++)
    {
        INFO_(FLOPPY, "HwReadWriteData: Sending a command byte to the FIFO: 0x%x\n", Buffer[i]);

        if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwReadWriteData: Unable to write to the FIFO\n");
            return STATUS_UNSUCCESSFUL;
        }
    }

    return STATUS_SUCCESS;
}

Referenced by ReadWritePassive().

HwReadWriteResult()

NTSTATUS NTAPI HwReadWriteResult

(

PCONTROLLER_INFO

ControllerInfo

)

Definition at line 462 of file hardware.c.

{
    UCHAR Buffer[7];
    int i;

    PAGED_CODE();

    for(i = 0; i < 7; i++)
        if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwReadWriteResult: unable to read fifo\n");
            return STATUS_UNSUCCESSFUL;
        }

    /* Validate  that it did what we told it to */
    INFO_(FLOPPY, "HwReadWriteResult results: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", Buffer[0], Buffer[1], Buffer[2], Buffer[3],
          Buffer[4], Buffer[5], Buffer[6]);

    /* Last command successful? */
    if((Buffer[0] & SR0_LAST_COMMAND_STATUS) != SR0_LCS_SUCCESS)
        return STATUS_UNSUCCESSFUL;

    return STATUS_SUCCESS;
}

Referenced by ReadWritePassive().

HwRecalibrate()

NTSTATUS NTAPI HwRecalibrate

(

PDRIVE_INFO

DriveInfo

)

Definition at line 503 of file hardware.c.

{
    PCONTROLLER_INFO ControllerInfo = DriveInfo->ControllerInfo;
    UCHAR Unit = DriveInfo->UnitNumber;
    UCHAR Buffer[2];
    int i;

    TRACE_(FLOPPY, "HwRecalibrate called\n");

    PAGED_CODE();

    Buffer[0] = COMMAND_RECALIBRATE;
    Buffer[1] = Unit;

    for(i = 0; i < 2; i++)
        if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwRecalibrate: unable to write FIFO\n");
            return STATUS_UNSUCCESSFUL;
        }

    return STATUS_SUCCESS;
}

Referenced by Recalibrate(), and RWDetermineMediaType().

HwRecalibrateResult()

NTSTATUS NTAPI HwRecalibrateResult

(

PCONTROLLER_INFO

ControllerInfo

)

Definition at line 394 of file hardware.c.

{
    UCHAR Buffer[2];
    int i;

    PAGED_CODE();

    if(Send_Byte(ControllerInfo, COMMAND_SENSE_INTERRUPT_STATUS) != STATUS_SUCCESS)
    {
        WARN_(FLOPPY, "HwRecalibrateResult: Unable to write the controller\n");
        return STATUS_UNSUCCESSFUL;
    }

    for(i = 0; i < 2; i++)
        if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwRecalibrateResult: unable to read FIFO\n");
            return STATUS_UNSUCCESSFUL;
        }

    /* Validate  that it did what we told it to */
    INFO_(FLOPPY, "HwRecalibrateResult results: ST0: 0x%x PCN: 0x%x\n", Buffer[0], Buffer[1]);

    /*
     * Buffer[0] = ST0
     * Buffer[1] = PCN
     */

    /* Is the PCN 0? */
    if(Buffer[1] != 0)
    {
        WARN_(FLOPPY, "HwRecalibrateResult: PCN not 0\n");
        return STATUS_UNSUCCESSFUL;
    }

    /* test seek complete */
    if((Buffer[0] & SR0_SEEK_COMPLETE) != SR0_SEEK_COMPLETE)
    {
        WARN_(FLOPPY, "HwRecalibrateResult: Failed to complete the seek\n");
        return STATUS_UNSUCCESSFUL;
    }

    /* Is the equipment check flag set?  Could be no disk in drive... */
    if((Buffer[0] & SR0_EQUIPMENT_CHECK) == SR0_EQUIPMENT_CHECK)
    {
        WARN_(FLOPPY, "HwRecalibrateResult: Seeked to track 0 successfully, but EC is set; returning failure\n");
        return STATUS_UNSUCCESSFUL;
    }

    return STATUS_SUCCESS;
}

Referenced by Recalibrate(), and RWDetermineMediaType().

HwReset()

NTSTATUS NTAPI HwReset

(

PCONTROLLER_INFO

Controller

)

Definition at line 973 of file hardware.c.

{
    TRACE_(FLOPPY, "HwReset called\n");

    /* Write the reset bit in the DRSR */
    WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DRSR_SW_RESET);

    /* Check for the reset bit in the DOR and set it if necessary (see Intel doc) */
    if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET))
    {
        HwDumpRegisters(ControllerInfo);
        INFO_(FLOPPY, "HwReset: Setting Enable bit\n");
        WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, DOR_DMA_IO_INTERFACE_ENABLE|DOR_RESET);
        HwDumpRegisters(ControllerInfo);

        if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET))
        {
            WARN_(FLOPPY, "HwReset: failed to set the DOR enable bit!\n");
            HwDumpRegisters(ControllerInfo);
            return STATUS_UNSUCCESSFUL;
        }
    }

    return STATUS_SUCCESS;
}

Referenced by InitController().

HwSeek()

NTSTATUS NTAPI HwSeek	(	PDRIVE_INFO	DriveInfo,
		UCHAR	Cylinder
	)

Definition at line 659 of file hardware.c.

{
    LARGE_INTEGER Delay;
    UCHAR Buffer[3];
    int i;

    TRACE_(FLOPPY, "HwSeek called for cyl 0x%x\n", Cylinder);

    PAGED_CODE();

    Buffer[0] = COMMAND_SEEK;
    Buffer[1] = DriveInfo->UnitNumber;
    Buffer[2] = Cylinder;

    for(i = 0; i < 3; i++)
        if(Send_Byte(DriveInfo->ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwSeek: failed to write fifo\n");
            return STATUS_UNSUCCESSFUL;
        }

    /* Wait for the head to settle */
    Delay.QuadPart = 10 * 1000;
    Delay.QuadPart *= -1;
    Delay.QuadPart *= DriveInfo->FloppyDeviceData.HeadSettleTime;

    KeDelayExecutionThread(KernelMode, FALSE, &Delay);

    return STATUS_SUCCESS;
}

Referenced by ResetChangeFlag(), and RWSeekToCylinder().

HwSenseDriveStatus()

NTSTATUS NTAPI HwSenseDriveStatus

(

PDRIVE_INFO

DriveInfo

)

Definition at line 287 of file hardware.c.

{
    UCHAR Buffer[2];
    int i;

    PAGED_CODE();

    TRACE_(FLOPPY, "HwSenseDriveStatus called\n");

    Buffer[0] = COMMAND_SENSE_DRIVE_STATUS;
    Buffer[1] = DriveInfo->UnitNumber; /* hard-wired to head 0 for now */

    for(i = 0; i < 2; i++)
        if(Send_Byte(DriveInfo->ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwSenseDriveStatus: failed to write FIFO\n");
            return STATUS_UNSUCCESSFUL;
        }

    return STATUS_SUCCESS;
}

Referenced by DeviceIoctlPassive().

HwSenseDriveStatusResult()

NTSTATUS NTAPI HwSenseDriveStatusResult	(	PCONTROLLER_INFO	ControllerInfo,
		PUCHAR	Status
	)

Definition at line 836 of file hardware.c.

{
    PAGED_CODE();

    if(Get_Byte(ControllerInfo, Status) != STATUS_SUCCESS)
    {
        WARN_(FLOPPY, "HwSenseDriveStatus: unable to read fifo\n");
        return STATUS_UNSUCCESSFUL;
    }

    TRACE_(FLOPPY, "HwSenseDriveStatusResult: ST3: 0x%x\n", *Status);

    return STATUS_SUCCESS;
}

Referenced by DeviceIoctlPassive().

HwSenseInterruptStatus()

NTSTATUS NTAPI HwSenseInterruptStatus

(

PCONTROLLER_INFO

ControllerInfo

)

Definition at line 539 of file hardware.c.

{
    UCHAR Buffer[2];
    int i;

    PAGED_CODE();

    if(Send_Byte(ControllerInfo, COMMAND_SENSE_INTERRUPT_STATUS) != STATUS_SUCCESS)
    {
        WARN_(FLOPPY, "HwSenseInterruptStatus: failed to write controller\n");
        return STATUS_UNSUCCESSFUL;
    }

    for(i = 0; i  < 2; i++)
    {
        if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwSenseInterruptStatus: failed to read controller\n");
            return STATUS_UNSUCCESSFUL;
        }
    }

    INFO_(FLOPPY, "HwSenseInterruptStatus returned 0x%x 0x%x\n", Buffer[0], Buffer[1]);

    return STATUS_SUCCESS;
}

Referenced by InitController(), ResetChangeFlag(), and RWSeekToCylinder().

HwSetDataRate()

NTSTATUS NTAPI HwSetDataRate	(	PCONTROLLER_INFO	ControllerInfo,
		UCHAR	DataRate
	)

Definition at line 204 of file hardware.c.

{
    TRACE_(FLOPPY, "HwSetDataRate called; writing rate code 0x%x to offset 0x%x\n", DataRate, DATA_RATE_SELECT_REGISTER);

    WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DataRate);

    return STATUS_SUCCESS;
}

Referenced by InitController(), Recalibrate(), and RWDetermineMediaType().

HwSpecify()

NTSTATUS NTAPI HwSpecify	(	PCONTROLLER_INFO	ControllerInfo,
		UCHAR	HeadLoadTime,
		UCHAR	HeadUnloadTime,
		UCHAR	StepRateTime,
		BOOLEAN	NonDma
	)

Definition at line 925 of file hardware.c.

{
    UCHAR Buffer[3];
    int i;

    Buffer[0] = COMMAND_SPECIFY;
    /*
    Buffer[1] = (StepRateTime << 4) + HeadUnloadTime;
    Buffer[2] = (HeadLoadTime << 1) + (NonDma ? 1 : 0);
    */
    Buffer[1] = 0xdf;
    Buffer[2] = 0x2;

    //INFO_(FLOPPY, "HwSpecify: sending 0x%x 0x%x 0x%x to FIFO\n", Buffer[0], Buffer[1], Buffer[2]);
    WARN_(FLOPPY, "HWSPECIFY: FIXME - sending 0x3 0xd1 0x2 to FIFO\n");

    for(i = 0; i < 3; i++)
        if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
        {
            WARN_(FLOPPY, "HwSpecify: unable to write to controller\n");
            return STATUS_UNSUCCESSFUL;
        }

    return STATUS_SUCCESS;
}

Referenced by InitController(), and RWDetermineMediaType().

HwTurnOffMotor()

NTSTATUS NTAPI HwTurnOffMotor

(

PCONTROLLER_INFO

ControllerInfo

)

Definition at line 223 of file hardware.c.

{
    TRACE_(FLOPPY, "HwTurnOffMotor: writing byte 0x%x to offset 0x%x\n", DOR_FDC_ENABLE|DOR_DMA_IO_INTERFACE_ENABLE, DIGITAL_OUTPUT_REGISTER);

    WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, DOR_FDC_ENABLE|DOR_DMA_IO_INTERFACE_ENABLE);

    return STATUS_SUCCESS;
}

Referenced by MotorStopDpcFunc().

HwTurnOnMotor()

NTSTATUS NTAPI HwTurnOnMotor

(

PDRIVE_INFO

DriveInfo

)

Definition at line 245 of file hardware.c.

{
    PCONTROLLER_INFO ControllerInfo = DriveInfo->ControllerInfo;
    UCHAR Unit = DriveInfo->UnitNumber;
    UCHAR Buffer;

    PAGED_CODE();

    /* turn on motor */
    Buffer = Unit;

    Buffer |= DOR_FDC_ENABLE;
    Buffer |= DOR_DMA_IO_INTERFACE_ENABLE;

    if(Unit == 0)
        Buffer |= DOR_FLOPPY_MOTOR_ON_A;
    else if (Unit == 1)
        Buffer |= DOR_FLOPPY_MOTOR_ON_B;
    else if (Unit == 2)
        Buffer |= DOR_FLOPPY_MOTOR_ON_C;
    else if (Unit == 3)
        Buffer |= DOR_FLOPPY_MOTOR_ON_D;

    TRACE_(FLOPPY, "HwTurnOnMotor: writing byte 0x%x to offset 0x%x\n", Buffer, DIGITAL_OUTPUT_REGISTER);
    WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, Buffer);

    return STATUS_SUCCESS;
}

Referenced by StartMotor().