ReactOS 0.4.15-dev-6055-g36cdd34
Macros | Functions
hardware.h File Reference
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Macros

#define FLOPPY_DEFAULT_IRQ   0x6
 
#define FDC_PORT_BYTES   0x8
 
#define STATUS_REGISTER_A   0x0 /* Read; PS/2 Only */
 
#define STATUS_REGISTER_B   0x1 /* Read; PS/2 Only */
 
#define DIGITAL_OUTPUT_REGISTER   0x2 /* Read/Write */
 
#define TAPE_DRIVE_REGISTER   0x3 /* Read/Write */
 
#define MAIN_STATUS_REGISTER   0x4 /* Read */
 
#define DATA_RATE_SELECT_REGISTER   0x4 /* Write */
 
#define FIFO   0x5 /* Read/Write */
 
#define RESERVED_REGISTER   0x6 /* Reserved */
 
#define DIGITAL_INPUT_REGISTER   0x7 /* Read; PS/2 Only */
 
#define CONFIGURATION_CONTROL_REGISTER   0x7 /* Write; PS/2 Only */
 
#define DSRA_DIRECTION   0x1
 
#define DSRA_WRITE_PROTECT   0x2
 
#define DSRA_INDEX   0x4
 
#define DSRA_HEAD_1_SELECT   0x8
 
#define DSRA_TRACK_0   0x10
 
#define DSRA_STEP   0x20
 
#define DSRA_SECOND_DRIVE_INSTALLED   0x40
 
#define DSRA_INTERRUPT_PENDING   0x80
 
#define DSRB_MOTOR_ENABLE_0   0x1
 
#define DSRB_MOTOR_ENABLE_1   0x2
 
#define DSRB_WRITE_ENABLE   0x4
 
#define DSRB_READ_DATA   0x8
 
#define DSRB_WRITE_DATA   0x10
 
#define DSRB_DRIVE_SELECT   0x20
 
#define DOR_FLOPPY_DRIVE_SELECT   0x3 /* Covers 2 bits, defined below */
 
#define DOR_FDC_ENABLE   0x4 /* from the website */
 
#define DOR_RESET   0x4 /* from the Intel guide; 0 = resetting, 1 = enabled */
 
#define DOR_DMA_IO_INTERFACE_ENABLE   0x8 /* Reserved on PS/2 */
 
#define DOR_FLOPPY_MOTOR_ON_A   0x10
 
#define DOR_FLOPPY_MOTOR_ON_B   0x20
 
#define DOR_FLOPPY_MOTOR_ON_C   0x40 /* Reserved on PS/2 */
 
#define DOR_FLOPPY_MOTOR_ON_D   0x80 /* Reserved on PS/2 */
 
#define DOR_FLOPPY_DRIVE_SELECT_A   0x0
 
#define DOR_FLOPPY_DRIVE_SELECT_B   0x1
 
#define DOR_FLOPPY_DRIVE_SELECT_C   0x2 /* Reserved on PS/2 */
 
#define DOR_FLOPPY_DRIVE_SELECT_D   0x3 /* Reserved on PS/2 */
 
#define MSR_FLOPPY_BUSY_0   0x1
 
#define MSR_FLOPPY_BUSY_1   0x2
 
#define MSR_FLOPPY_BUSY_2   0x4 /* Reserved on PS/2 */
 
#define MSR_FLOPPY_BUSY_3   0x8 /* Reserved on PS/2 */
 
#define MSR_READ_WRITE_IN_PROGRESS   0x10
 
#define MSR_NON_DMA_MODE   0x20
 
#define MSR_IO_DIRECTION   0x40 /* Determines meaning of Command Status Registers */
 
#define MSR_DATA_REG_READY_FOR_IO   0x80
 
#define DRSR_DSEL   0x3 /* covers two bits as defined below */
 
#define DRSR_PRECOMP   0x1c /* covers three bits as defined below */
 
#define DRSR_MBZ   0x20
 
#define DRSR_POWER_DOWN   0x40
 
#define DRSR_SW_RESET   0x80
 
#define DRSR_DSEL_500KBPS   0x0
 
#define DRSR_DSEL_300KBPS   0x1
 
#define DRSR_DSEL_250KBPS   0x2
 
#define DRSR_DSEL_1MBPS   0x3
 
#define SR0_UNIT_SELECTED_AT_INTERRUPT   0x3 /* Covers two bits as defined below */
 
#define SR0_HEAD_NUMBER_AT_INTERRUPT   0x4 /* Values defined below */
 
#define SR0_NOT_READY_ON_READ_WRITE   0x8 /* Unused in PS/2 */
 
#define SR0_SS_ACCESS_TO_HEAD_1   0x8 /* Unused in PS/2 */
 
#define SR0_EQUIPMENT_CHECK   0x10
 
#define SR0_SEEK_COMPLETE   0x20
 
#define SR0_LAST_COMMAND_STATUS   0xC0 /* Covers two bits as defined below */
 
#define SR0_UNIT_SELECTED_A   0x0
 
#define SR0_UNIT_SELECTED_B   0x1
 
#define SR0_UNIT_SELECTED_C   0x2
 
#define SR0_UNIT_SELECTED_D   0x3
 
#define SR0_PS2_UNIT_SELECTED_A   0x1 /* PS/2 uses only two drives: A = 01b B = 10b */
 
#define SR0_PST_UNIT_SELECTED_B   0x2
 
#define SR0_HEAD_0   0x0
 
#define SR0_HEAD_1   0x1
 
#define SR0_LCS_SUCCESS   0x0
 
#define SR0_LCS_TERMINATED_ABNORMALLY   0x40
 
#define SR0_LCS_INVALID_COMMAND_ISSUED   0x80
 
#define SR0_LCS_READY_SIGNAL_CHANGED   0xc0 /* Reserved on PS/2; a/k/a abnormal termination due to polling */
 
#define SR1_CANNOT_FIND_ID_ADDRESS   0x1 /* Mimics SR2_WRONG_CYLINDER_DETECTED */
 
#define SR1_WRITE_PROTECT_DETECTED   0x2
 
#define SR1_CANNOT_FIND_SECTOR_ID   0x4
 
#define SR1_OVERRUN   0x10
 
#define SR1_CRC_ERROR   0x20
 
#define SR1_END_OF_CYLINDER   0x80
 
#define SR2_MISSING_ADDRESS_MARK   0x1
 
#define SR2_BAD_CYLINDER   0x2
 
#define SR2_SCAN_COMMAND_FAILED   0x4
 
#define SR2_SCAN_COMMAND_EQUAL   0x8
 
#define SR2_WRONG_CYLINDER_DETECTED   0x10 /* Mimics SR1_CANNOT_FIND_ID_ADDRESS */
 
#define SR2_CRC_ERROR_IN_SECTOR_DATA   0x20
 
#define SR2_SECTOR_WITH_DELETED_DATA   0x40
 
#define SR3_UNIT_SELECTED   0x3 /* Covers two bits; defined below */
 
#define SR3_SIDE_HEAD_SELECT_STATUS   0x4 /* Values defined below */
 
#define SR3_TWO_SIDED_STATUS_SIGNAL   0x8
 
#define SR3_TRACK_ZERO_STATUS_SIGNAL   0x10
 
#define SR3_READY_STATUS_SIGNAL   0x20
 
#define SR3_WRITE_PROTECT_STATUS_SIGNAL   0x40
 
#define SR3_FAULT_STATUS_SIGNAL   0x80
 
#define SR3_UNIT_SELECTED_A   0x0
 
#define SR3_UNIT_SELECTED_B   0x1
 
#define SR3_UNIT_SELECTED_C   0x2
 
#define SR3_UNIT_SELECTED_D   0x3
 
#define SR3_SHSS_HEAD_0   0x0
 
#define SR3_SHSS_HEAD_1   0x1
 
#define DIR_HIGH_DENSITY_SELECT   0x1
 
#define DIR_DISKETTE_CHANGE   0x80
 
#define CCR_DRC   0x3 /* Covers two bits, defined below */
 
#define CCR_DRC_0   0x1
 
#define CCR_DRC_1   0x2
 
#define CCR_DRC_500000   0x0
 
#define CCR_DRC_250000   0x2
 
#define COMMAND_READ_TRACK   0x2
 
#define COMMAND_SPECIFY   0x3
 
#define COMMAND_SENSE_DRIVE_STATUS   0x4
 
#define COMMAND_WRITE_DATA   0x5
 
#define COMMAND_READ_DATA   0x6
 
#define COMMAND_RECALIBRATE   0x7
 
#define COMMAND_SENSE_INTERRUPT_STATUS   0x8
 
#define COMMAND_WRITE_DELETED_DATA   0x9
 
#define COMMAND_READ_ID   0xA
 
#define COMMAND_READ_DELETED_DATA   0xC
 
#define COMMAND_FORMAT_TRACK   0xD
 
#define COMMAND_SEEK   0xF
 
#define COMMAND_VERSION   0x10
 
#define COMMAND_SCAN_EQUAL   0x11
 
#define COMMAND_CONFIGURE   0x13
 
#define COMMAND_SCAN_LOW_OR_EQUAL   0x19
 
#define COMMAND_SCAN_HIGH_OR_EQUAL   0x1D
 
#define READ_DATA_DS0   0x1
 
#define READ_DATA_DS1   0x2
 
#define READ_DATA_HDS   0x4
 
#define READ_DATA_SK   0x20
 
#define READ_DATA_MFM   0x40
 
#define READ_DATA_MT   0x80
 
#define READ_ID_MFM   0x40
 
#define SPECIFY_HLT_1M   0x10 /* 16ms; based on intel data sheet */
 
#define SPECIFY_HLT_500K   0x8 /* 16ms; based on intel data sheet */
 
#define SPECIFY_HLT_300K   0x6 /* 16ms; based on intel data sheet */
 
#define SPECIFY_HLT_250K   0x4 /* 16ms; based on intel data sheet */
 
#define SPECIFY_HUT_1M   0x0 /* Need to figure out these eight values; 0 is max */
 
#define SPECIFY_HUT_500K   0x0
 
#define SPECIFY_HUT_300K   0x0
 
#define SPECIFY_HUT_250K   0x0
 
#define SPECIFY_SRT_1M   0x0
 
#define SPECIFY_SRT_500K   0x0
 
#define SPECIFY_SRT_300K   0x0
 
#define SPECIFY_SRT_250K   0x0
 
#define COMMAND_UNIT_SELECT   0x3 /* Covers two bits; defined below */
 
#define COMMAND_UNIT_SELECT_0   0x1
 
#define COMMAND_UNIT_SELECT_1   0x2
 
#define COMMAND_HEAD_NUMBER   0x4
 
#define COMMAND_HEAD_NUMBER_SHIFT   0x2
 
#define VERSION_ENHANCED   0x90
 
#define CUS_UNIT_0   0x0
 
#define CUS_UNIT_1   0x1
 
#define CONFIGURE_FIFOTHR   0xf
 
#define CONFIGURE_POLL   0x10
 
#define CONFIGURE_EFIFO   0x20
 
#define CONFIGURE_EIS   0x40
 
#define CONFIGURE_PRETRK   0xff
 
#define COMMAND_HEAD_0   0x0
 
#define COMMAND_HEAD_1   0x1
 
#define HW_128_BYTES_PER_SECTOR   0x0
 
#define HW_256_BYTES_PER_SECTOR   0x1
 
#define HW_512_BYTES_PER_SECTOR   0x2
 
#define HW_1024_BYTES_PER_SECTOR   0x3
 

Functions

NTSTATUS NTAPI HwTurnOnMotor (PDRIVE_INFO DriveInfo)
 
NTSTATUS NTAPI HwSenseDriveStatus (PDRIVE_INFO DriveInfo)
 
NTSTATUS NTAPI HwReadWriteData (PCONTROLLER_INFO ControllerInfo, BOOLEAN Read, UCHAR Unit, UCHAR Cylinder, UCHAR Head, UCHAR Sector, UCHAR BytesPerSector, UCHAR EndOfTrack, UCHAR Gap3Length, UCHAR DataLength)
 
NTSTATUS NTAPI HwRecalibrate (PDRIVE_INFO DriveInfo)
 
NTSTATUS NTAPI HwSenseInterruptStatus (PCONTROLLER_INFO ControllerInfo)
 
NTSTATUS NTAPI HwReadId (PDRIVE_INFO DriveInfo, UCHAR Head)
 
NTSTATUS NTAPI HwFormatTrack (PCONTROLLER_INFO ControllerInfo, UCHAR Unit, UCHAR Head, UCHAR BytesPerSector, UCHAR SectorsPerTrack, UCHAR Gap3Length, UCHAR FillerPattern)
 
NTSTATUS NTAPI HwSeek (PDRIVE_INFO DriveInfo, UCHAR Cylinder)
 
NTSTATUS NTAPI HwReadWriteResult (PCONTROLLER_INFO ControllerInfo)
 
NTSTATUS NTAPI HwGetVersion (PCONTROLLER_INFO ControllerInfo)
 
NTSTATUS NTAPI HwConfigure (PCONTROLLER_INFO ControllerInfo, BOOLEAN EIS, BOOLEAN EFIFO, BOOLEAN POLL, UCHAR FIFOTHR, UCHAR PRETRK)
 
NTSTATUS NTAPI HwRecalibrateResult (PCONTROLLER_INFO ControllerInfo)
 
NTSTATUS NTAPI HwDiskChanged (PDRIVE_INFO DriveInfo, PBOOLEAN DiskChanged)
 
NTSTATUS NTAPI HwSenseDriveStatusResult (PCONTROLLER_INFO ControllerInfo, PUCHAR Status)
 
NTSTATUS NTAPI HwSpecify (PCONTROLLER_INFO ControllerInfo, UCHAR HeadLoadTime, UCHAR HeadUnloadTime, UCHAR StepRateTime, BOOLEAN NonDma)
 
NTSTATUS NTAPI HwReadIdResult (PCONTROLLER_INFO ControllerInfo, PUCHAR CurCylinder, PUCHAR CurHead)
 
NTSTATUS NTAPI HwSetDataRate (PCONTROLLER_INFO ControllerInfo, UCHAR DataRate)
 
NTSTATUS NTAPI HwReset (PCONTROLLER_INFO Controller)
 
NTSTATUS NTAPI HwPowerOff (PCONTROLLER_INFO ControllerInfo)
 
VOID NTAPI HwDumpRegisters (PCONTROLLER_INFO ControllerInfo)
 
NTSTATUS NTAPI HwTurnOffMotor (PCONTROLLER_INFO ControllerInfo)
 

Macro Definition Documentation

◆ CCR_DRC

#define CCR_DRC   0x3 /* Covers two bits, defined below */

Definition at line 179 of file hardware.h.

◆ CCR_DRC_0

#define CCR_DRC_0   0x1

Definition at line 180 of file hardware.h.

◆ CCR_DRC_1

#define CCR_DRC_1   0x2

Definition at line 181 of file hardware.h.

◆ CCR_DRC_250000

#define CCR_DRC_250000   0x2

Definition at line 185 of file hardware.h.

◆ CCR_DRC_500000

#define CCR_DRC_500000   0x0

Definition at line 184 of file hardware.h.

◆ COMMAND_CONFIGURE

#define COMMAND_CONFIGURE   0x13

Definition at line 202 of file hardware.h.

◆ COMMAND_FORMAT_TRACK

#define COMMAND_FORMAT_TRACK   0xD

Definition at line 198 of file hardware.h.

◆ COMMAND_HEAD_0

#define COMMAND_HEAD_0   0x0

Definition at line 253 of file hardware.h.

◆ COMMAND_HEAD_1

#define COMMAND_HEAD_1   0x1

Definition at line 254 of file hardware.h.

◆ COMMAND_HEAD_NUMBER

#define COMMAND_HEAD_NUMBER   0x4

Definition at line 235 of file hardware.h.

◆ COMMAND_HEAD_NUMBER_SHIFT

#define COMMAND_HEAD_NUMBER_SHIFT   0x2

Definition at line 236 of file hardware.h.

◆ COMMAND_READ_DATA

#define COMMAND_READ_DATA   0x6

Definition at line 192 of file hardware.h.

◆ COMMAND_READ_DELETED_DATA

#define COMMAND_READ_DELETED_DATA   0xC

Definition at line 197 of file hardware.h.

◆ COMMAND_READ_ID

#define COMMAND_READ_ID   0xA

Definition at line 196 of file hardware.h.

◆ COMMAND_READ_TRACK

#define COMMAND_READ_TRACK   0x2

Definition at line 188 of file hardware.h.

◆ COMMAND_RECALIBRATE

#define COMMAND_RECALIBRATE   0x7

Definition at line 193 of file hardware.h.

◆ COMMAND_SCAN_EQUAL

#define COMMAND_SCAN_EQUAL   0x11

Definition at line 201 of file hardware.h.

◆ COMMAND_SCAN_HIGH_OR_EQUAL

#define COMMAND_SCAN_HIGH_OR_EQUAL   0x1D

Definition at line 204 of file hardware.h.

◆ COMMAND_SCAN_LOW_OR_EQUAL

#define COMMAND_SCAN_LOW_OR_EQUAL   0x19

Definition at line 203 of file hardware.h.

◆ COMMAND_SEEK

#define COMMAND_SEEK   0xF

Definition at line 199 of file hardware.h.

◆ COMMAND_SENSE_DRIVE_STATUS

#define COMMAND_SENSE_DRIVE_STATUS   0x4

Definition at line 190 of file hardware.h.

◆ COMMAND_SENSE_INTERRUPT_STATUS

#define COMMAND_SENSE_INTERRUPT_STATUS   0x8

Definition at line 194 of file hardware.h.

◆ COMMAND_SPECIFY

#define COMMAND_SPECIFY   0x3

Definition at line 189 of file hardware.h.

◆ COMMAND_UNIT_SELECT

#define COMMAND_UNIT_SELECT   0x3 /* Covers two bits; defined below */

Definition at line 232 of file hardware.h.

◆ COMMAND_UNIT_SELECT_0

#define COMMAND_UNIT_SELECT_0   0x1

Definition at line 233 of file hardware.h.

◆ COMMAND_UNIT_SELECT_1

#define COMMAND_UNIT_SELECT_1   0x2

Definition at line 234 of file hardware.h.

◆ COMMAND_VERSION

#define COMMAND_VERSION   0x10

Definition at line 200 of file hardware.h.

◆ COMMAND_WRITE_DATA

#define COMMAND_WRITE_DATA   0x5

Definition at line 191 of file hardware.h.

◆ COMMAND_WRITE_DELETED_DATA

#define COMMAND_WRITE_DELETED_DATA   0x9

Definition at line 195 of file hardware.h.

◆ CONFIGURATION_CONTROL_REGISTER

#define CONFIGURATION_CONTROL_REGISTER   0x7 /* Write; PS/2 Only */

Definition at line 52 of file hardware.h.

◆ CONFIGURE_EFIFO

#define CONFIGURE_EFIFO   0x20

Definition at line 248 of file hardware.h.

◆ CONFIGURE_EIS

#define CONFIGURE_EIS   0x40

Definition at line 249 of file hardware.h.

◆ CONFIGURE_FIFOTHR

#define CONFIGURE_FIFOTHR   0xf

Definition at line 246 of file hardware.h.

◆ CONFIGURE_POLL

#define CONFIGURE_POLL   0x10

Definition at line 247 of file hardware.h.

◆ CONFIGURE_PRETRK

#define CONFIGURE_PRETRK   0xff

Definition at line 250 of file hardware.h.

◆ CUS_UNIT_0

#define CUS_UNIT_0   0x0

Definition at line 242 of file hardware.h.

◆ CUS_UNIT_1

#define CUS_UNIT_1   0x1

Definition at line 243 of file hardware.h.

◆ DATA_RATE_SELECT_REGISTER

#define DATA_RATE_SELECT_REGISTER   0x4 /* Write */

Definition at line 48 of file hardware.h.

◆ DIGITAL_INPUT_REGISTER

#define DIGITAL_INPUT_REGISTER   0x7 /* Read; PS/2 Only */

Definition at line 51 of file hardware.h.

◆ DIGITAL_OUTPUT_REGISTER

#define DIGITAL_OUTPUT_REGISTER   0x2 /* Read/Write */

Definition at line 45 of file hardware.h.

◆ DIR_DISKETTE_CHANGE

#define DIR_DISKETTE_CHANGE   0x80

Definition at line 176 of file hardware.h.

◆ DIR_HIGH_DENSITY_SELECT

#define DIR_HIGH_DENSITY_SELECT   0x1

Definition at line 175 of file hardware.h.

◆ DOR_DMA_IO_INTERFACE_ENABLE

#define DOR_DMA_IO_INTERFACE_ENABLE   0x8 /* Reserved on PS/2 */

Definition at line 76 of file hardware.h.

◆ DOR_FDC_ENABLE

#define DOR_FDC_ENABLE   0x4 /* from the website */

Definition at line 74 of file hardware.h.

◆ DOR_FLOPPY_DRIVE_SELECT

#define DOR_FLOPPY_DRIVE_SELECT   0x3 /* Covers 2 bits, defined below */

Definition at line 73 of file hardware.h.

◆ DOR_FLOPPY_DRIVE_SELECT_A

#define DOR_FLOPPY_DRIVE_SELECT_A   0x0

Definition at line 83 of file hardware.h.

◆ DOR_FLOPPY_DRIVE_SELECT_B

#define DOR_FLOPPY_DRIVE_SELECT_B   0x1

Definition at line 84 of file hardware.h.

◆ DOR_FLOPPY_DRIVE_SELECT_C

#define DOR_FLOPPY_DRIVE_SELECT_C   0x2 /* Reserved on PS/2 */

Definition at line 85 of file hardware.h.

◆ DOR_FLOPPY_DRIVE_SELECT_D

#define DOR_FLOPPY_DRIVE_SELECT_D   0x3 /* Reserved on PS/2 */

Definition at line 86 of file hardware.h.

◆ DOR_FLOPPY_MOTOR_ON_A

#define DOR_FLOPPY_MOTOR_ON_A   0x10

Definition at line 77 of file hardware.h.

◆ DOR_FLOPPY_MOTOR_ON_B

#define DOR_FLOPPY_MOTOR_ON_B   0x20

Definition at line 78 of file hardware.h.

◆ DOR_FLOPPY_MOTOR_ON_C

#define DOR_FLOPPY_MOTOR_ON_C   0x40 /* Reserved on PS/2 */

Definition at line 79 of file hardware.h.

◆ DOR_FLOPPY_MOTOR_ON_D

#define DOR_FLOPPY_MOTOR_ON_D   0x80 /* Reserved on PS/2 */

Definition at line 80 of file hardware.h.

◆ DOR_RESET

#define DOR_RESET   0x4 /* from the Intel guide; 0 = resetting, 1 = enabled */

Definition at line 75 of file hardware.h.

◆ DRSR_DSEL

#define DRSR_DSEL   0x3 /* covers two bits as defined below */

Definition at line 99 of file hardware.h.

◆ DRSR_DSEL_1MBPS

#define DRSR_DSEL_1MBPS   0x3

Definition at line 109 of file hardware.h.

◆ DRSR_DSEL_250KBPS

#define DRSR_DSEL_250KBPS   0x2

Definition at line 108 of file hardware.h.

◆ DRSR_DSEL_300KBPS

#define DRSR_DSEL_300KBPS   0x1

Definition at line 107 of file hardware.h.

◆ DRSR_DSEL_500KBPS

#define DRSR_DSEL_500KBPS   0x0

Definition at line 106 of file hardware.h.

◆ DRSR_MBZ

#define DRSR_MBZ   0x20

Definition at line 101 of file hardware.h.

◆ DRSR_POWER_DOWN

#define DRSR_POWER_DOWN   0x40

Definition at line 102 of file hardware.h.

◆ DRSR_PRECOMP

#define DRSR_PRECOMP   0x1c /* covers three bits as defined below */

Definition at line 100 of file hardware.h.

◆ DRSR_SW_RESET

#define DRSR_SW_RESET   0x80

Definition at line 103 of file hardware.h.

◆ DSRA_DIRECTION

#define DSRA_DIRECTION   0x1

Definition at line 55 of file hardware.h.

◆ DSRA_HEAD_1_SELECT

#define DSRA_HEAD_1_SELECT   0x8

Definition at line 58 of file hardware.h.

◆ DSRA_INDEX

#define DSRA_INDEX   0x4

Definition at line 57 of file hardware.h.

◆ DSRA_INTERRUPT_PENDING

#define DSRA_INTERRUPT_PENDING   0x80

Definition at line 62 of file hardware.h.

◆ DSRA_SECOND_DRIVE_INSTALLED

#define DSRA_SECOND_DRIVE_INSTALLED   0x40

Definition at line 61 of file hardware.h.

◆ DSRA_STEP

#define DSRA_STEP   0x20

Definition at line 60 of file hardware.h.

◆ DSRA_TRACK_0

#define DSRA_TRACK_0   0x10

Definition at line 59 of file hardware.h.

◆ DSRA_WRITE_PROTECT

#define DSRA_WRITE_PROTECT   0x2

Definition at line 56 of file hardware.h.

◆ DSRB_DRIVE_SELECT

#define DSRB_DRIVE_SELECT   0x20

Definition at line 70 of file hardware.h.

◆ DSRB_MOTOR_ENABLE_0

#define DSRB_MOTOR_ENABLE_0   0x1

Definition at line 65 of file hardware.h.

◆ DSRB_MOTOR_ENABLE_1

#define DSRB_MOTOR_ENABLE_1   0x2

Definition at line 66 of file hardware.h.

◆ DSRB_READ_DATA

#define DSRB_READ_DATA   0x8

Definition at line 68 of file hardware.h.

◆ DSRB_WRITE_DATA

#define DSRB_WRITE_DATA   0x10

Definition at line 69 of file hardware.h.

◆ DSRB_WRITE_ENABLE

#define DSRB_WRITE_ENABLE   0x4

Definition at line 67 of file hardware.h.

◆ FDC_PORT_BYTES

#define FDC_PORT_BYTES   0x8

Definition at line 40 of file hardware.h.

◆ FIFO

#define FIFO   0x5 /* Read/Write */

Definition at line 49 of file hardware.h.

◆ FLOPPY_DEFAULT_IRQ

#define FLOPPY_DEFAULT_IRQ   0x6

Definition at line 39 of file hardware.h.

◆ HW_1024_BYTES_PER_SECTOR

#define HW_1024_BYTES_PER_SECTOR   0x3

Definition at line 260 of file hardware.h.

◆ HW_128_BYTES_PER_SECTOR

#define HW_128_BYTES_PER_SECTOR   0x0

Definition at line 257 of file hardware.h.

◆ HW_256_BYTES_PER_SECTOR

#define HW_256_BYTES_PER_SECTOR   0x1

Definition at line 258 of file hardware.h.

◆ HW_512_BYTES_PER_SECTOR

#define HW_512_BYTES_PER_SECTOR   0x2

Definition at line 259 of file hardware.h.

◆ MAIN_STATUS_REGISTER

#define MAIN_STATUS_REGISTER   0x4 /* Read */

Definition at line 47 of file hardware.h.

◆ MSR_DATA_REG_READY_FOR_IO

#define MSR_DATA_REG_READY_FOR_IO   0x80

Definition at line 96 of file hardware.h.

◆ MSR_FLOPPY_BUSY_0

#define MSR_FLOPPY_BUSY_0   0x1

Definition at line 89 of file hardware.h.

◆ MSR_FLOPPY_BUSY_1

#define MSR_FLOPPY_BUSY_1   0x2

Definition at line 90 of file hardware.h.

◆ MSR_FLOPPY_BUSY_2

#define MSR_FLOPPY_BUSY_2   0x4 /* Reserved on PS/2 */

Definition at line 91 of file hardware.h.

◆ MSR_FLOPPY_BUSY_3

#define MSR_FLOPPY_BUSY_3   0x8 /* Reserved on PS/2 */

Definition at line 92 of file hardware.h.

◆ MSR_IO_DIRECTION

#define MSR_IO_DIRECTION   0x40 /* Determines meaning of Command Status Registers */

Definition at line 95 of file hardware.h.

◆ MSR_NON_DMA_MODE

#define MSR_NON_DMA_MODE   0x20

Definition at line 94 of file hardware.h.

◆ MSR_READ_WRITE_IN_PROGRESS

#define MSR_READ_WRITE_IN_PROGRESS   0x10

Definition at line 93 of file hardware.h.

◆ READ_DATA_DS0

#define READ_DATA_DS0   0x1

Definition at line 207 of file hardware.h.

◆ READ_DATA_DS1

#define READ_DATA_DS1   0x2

Definition at line 208 of file hardware.h.

◆ READ_DATA_HDS

#define READ_DATA_HDS   0x4

Definition at line 209 of file hardware.h.

◆ READ_DATA_MFM

#define READ_DATA_MFM   0x40

Definition at line 211 of file hardware.h.

◆ READ_DATA_MT

#define READ_DATA_MT   0x80

Definition at line 212 of file hardware.h.

◆ READ_DATA_SK

#define READ_DATA_SK   0x20

Definition at line 210 of file hardware.h.

◆ READ_ID_MFM

#define READ_ID_MFM   0x40

Definition at line 215 of file hardware.h.

◆ RESERVED_REGISTER

#define RESERVED_REGISTER   0x6 /* Reserved */

Definition at line 50 of file hardware.h.

◆ SPECIFY_HLT_1M

#define SPECIFY_HLT_1M   0x10 /* 16ms; based on intel data sheet */

Definition at line 218 of file hardware.h.

◆ SPECIFY_HLT_250K

#define SPECIFY_HLT_250K   0x4 /* 16ms; based on intel data sheet */

Definition at line 221 of file hardware.h.

◆ SPECIFY_HLT_300K

#define SPECIFY_HLT_300K   0x6 /* 16ms; based on intel data sheet */

Definition at line 220 of file hardware.h.

◆ SPECIFY_HLT_500K

#define SPECIFY_HLT_500K   0x8 /* 16ms; based on intel data sheet */

Definition at line 219 of file hardware.h.

◆ SPECIFY_HUT_1M

#define SPECIFY_HUT_1M   0x0 /* Need to figure out these eight values; 0 is max */

Definition at line 222 of file hardware.h.

◆ SPECIFY_HUT_250K

#define SPECIFY_HUT_250K   0x0

Definition at line 225 of file hardware.h.

◆ SPECIFY_HUT_300K

#define SPECIFY_HUT_300K   0x0

Definition at line 224 of file hardware.h.

◆ SPECIFY_HUT_500K

#define SPECIFY_HUT_500K   0x0

Definition at line 223 of file hardware.h.

◆ SPECIFY_SRT_1M

#define SPECIFY_SRT_1M   0x0

Definition at line 226 of file hardware.h.

◆ SPECIFY_SRT_250K

#define SPECIFY_SRT_250K   0x0

Definition at line 229 of file hardware.h.

◆ SPECIFY_SRT_300K

#define SPECIFY_SRT_300K   0x0

Definition at line 228 of file hardware.h.

◆ SPECIFY_SRT_500K

#define SPECIFY_SRT_500K   0x0

Definition at line 227 of file hardware.h.

◆ SR0_EQUIPMENT_CHECK

#define SR0_EQUIPMENT_CHECK   0x10

Definition at line 116 of file hardware.h.

◆ SR0_HEAD_0

#define SR0_HEAD_0   0x0

Definition at line 129 of file hardware.h.

◆ SR0_HEAD_1

#define SR0_HEAD_1   0x1

Definition at line 130 of file hardware.h.

◆ SR0_HEAD_NUMBER_AT_INTERRUPT

#define SR0_HEAD_NUMBER_AT_INTERRUPT   0x4 /* Values defined below */

Definition at line 113 of file hardware.h.

◆ SR0_LAST_COMMAND_STATUS

#define SR0_LAST_COMMAND_STATUS   0xC0 /* Covers two bits as defined below */

Definition at line 118 of file hardware.h.

◆ SR0_LCS_INVALID_COMMAND_ISSUED

#define SR0_LCS_INVALID_COMMAND_ISSUED   0x80

Definition at line 135 of file hardware.h.

◆ SR0_LCS_READY_SIGNAL_CHANGED

#define SR0_LCS_READY_SIGNAL_CHANGED   0xc0 /* Reserved on PS/2; a/k/a abnormal termination due to polling */

Definition at line 136 of file hardware.h.

◆ SR0_LCS_SUCCESS

#define SR0_LCS_SUCCESS   0x0

Definition at line 133 of file hardware.h.

◆ SR0_LCS_TERMINATED_ABNORMALLY

#define SR0_LCS_TERMINATED_ABNORMALLY   0x40

Definition at line 134 of file hardware.h.

◆ SR0_NOT_READY_ON_READ_WRITE

#define SR0_NOT_READY_ON_READ_WRITE   0x8 /* Unused in PS/2 */

Definition at line 114 of file hardware.h.

◆ SR0_PS2_UNIT_SELECTED_A

#define SR0_PS2_UNIT_SELECTED_A   0x1 /* PS/2 uses only two drives: A = 01b B = 10b */

Definition at line 125 of file hardware.h.

◆ SR0_PST_UNIT_SELECTED_B

#define SR0_PST_UNIT_SELECTED_B   0x2

Definition at line 126 of file hardware.h.

◆ SR0_SEEK_COMPLETE

#define SR0_SEEK_COMPLETE   0x20

Definition at line 117 of file hardware.h.

◆ SR0_SS_ACCESS_TO_HEAD_1

#define SR0_SS_ACCESS_TO_HEAD_1   0x8 /* Unused in PS/2 */

Definition at line 115 of file hardware.h.

◆ SR0_UNIT_SELECTED_A

#define SR0_UNIT_SELECTED_A   0x0

Definition at line 121 of file hardware.h.

◆ SR0_UNIT_SELECTED_AT_INTERRUPT

#define SR0_UNIT_SELECTED_AT_INTERRUPT   0x3 /* Covers two bits as defined below */

Definition at line 112 of file hardware.h.

◆ SR0_UNIT_SELECTED_B

#define SR0_UNIT_SELECTED_B   0x1

Definition at line 122 of file hardware.h.

◆ SR0_UNIT_SELECTED_C

#define SR0_UNIT_SELECTED_C   0x2

Definition at line 123 of file hardware.h.

◆ SR0_UNIT_SELECTED_D

#define SR0_UNIT_SELECTED_D   0x3

Definition at line 124 of file hardware.h.

◆ SR1_CANNOT_FIND_ID_ADDRESS

#define SR1_CANNOT_FIND_ID_ADDRESS   0x1 /* Mimics SR2_WRONG_CYLINDER_DETECTED */

Definition at line 139 of file hardware.h.

◆ SR1_CANNOT_FIND_SECTOR_ID

#define SR1_CANNOT_FIND_SECTOR_ID   0x4

Definition at line 141 of file hardware.h.

◆ SR1_CRC_ERROR

#define SR1_CRC_ERROR   0x20

Definition at line 143 of file hardware.h.

◆ SR1_END_OF_CYLINDER

#define SR1_END_OF_CYLINDER   0x80

Definition at line 144 of file hardware.h.

◆ SR1_OVERRUN

#define SR1_OVERRUN   0x10

Definition at line 142 of file hardware.h.

◆ SR1_WRITE_PROTECT_DETECTED

#define SR1_WRITE_PROTECT_DETECTED   0x2

Definition at line 140 of file hardware.h.

◆ SR2_BAD_CYLINDER

#define SR2_BAD_CYLINDER   0x2

Definition at line 148 of file hardware.h.

◆ SR2_CRC_ERROR_IN_SECTOR_DATA

#define SR2_CRC_ERROR_IN_SECTOR_DATA   0x20

Definition at line 152 of file hardware.h.

◆ SR2_MISSING_ADDRESS_MARK

#define SR2_MISSING_ADDRESS_MARK   0x1

Definition at line 147 of file hardware.h.

◆ SR2_SCAN_COMMAND_EQUAL

#define SR2_SCAN_COMMAND_EQUAL   0x8

Definition at line 150 of file hardware.h.

◆ SR2_SCAN_COMMAND_FAILED

#define SR2_SCAN_COMMAND_FAILED   0x4

Definition at line 149 of file hardware.h.

◆ SR2_SECTOR_WITH_DELETED_DATA

#define SR2_SECTOR_WITH_DELETED_DATA   0x40

Definition at line 153 of file hardware.h.

◆ SR2_WRONG_CYLINDER_DETECTED

#define SR2_WRONG_CYLINDER_DETECTED   0x10 /* Mimics SR1_CANNOT_FIND_ID_ADDRESS */

Definition at line 151 of file hardware.h.

◆ SR3_FAULT_STATUS_SIGNAL

#define SR3_FAULT_STATUS_SIGNAL   0x80

Definition at line 162 of file hardware.h.

◆ SR3_READY_STATUS_SIGNAL

#define SR3_READY_STATUS_SIGNAL   0x20

Definition at line 160 of file hardware.h.

◆ SR3_SHSS_HEAD_0

#define SR3_SHSS_HEAD_0   0x0

Definition at line 171 of file hardware.h.

◆ SR3_SHSS_HEAD_1

#define SR3_SHSS_HEAD_1   0x1

Definition at line 172 of file hardware.h.

◆ SR3_SIDE_HEAD_SELECT_STATUS

#define SR3_SIDE_HEAD_SELECT_STATUS   0x4 /* Values defined below */

Definition at line 157 of file hardware.h.

◆ SR3_TRACK_ZERO_STATUS_SIGNAL

#define SR3_TRACK_ZERO_STATUS_SIGNAL   0x10

Definition at line 159 of file hardware.h.

◆ SR3_TWO_SIDED_STATUS_SIGNAL

#define SR3_TWO_SIDED_STATUS_SIGNAL   0x8

Definition at line 158 of file hardware.h.

◆ SR3_UNIT_SELECTED

#define SR3_UNIT_SELECTED   0x3 /* Covers two bits; defined below */

Definition at line 156 of file hardware.h.

◆ SR3_UNIT_SELECTED_A

#define SR3_UNIT_SELECTED_A   0x0

Definition at line 165 of file hardware.h.

◆ SR3_UNIT_SELECTED_B

#define SR3_UNIT_SELECTED_B   0x1

Definition at line 166 of file hardware.h.

◆ SR3_UNIT_SELECTED_C

#define SR3_UNIT_SELECTED_C   0x2

Definition at line 167 of file hardware.h.

◆ SR3_UNIT_SELECTED_D

#define SR3_UNIT_SELECTED_D   0x3

Definition at line 168 of file hardware.h.

◆ SR3_WRITE_PROTECT_STATUS_SIGNAL

#define SR3_WRITE_PROTECT_STATUS_SIGNAL   0x40

Definition at line 161 of file hardware.h.

◆ STATUS_REGISTER_A

#define STATUS_REGISTER_A   0x0 /* Read; PS/2 Only */

Definition at line 43 of file hardware.h.

◆ STATUS_REGISTER_B

#define STATUS_REGISTER_B   0x1 /* Read; PS/2 Only */

Definition at line 44 of file hardware.h.

◆ TAPE_DRIVE_REGISTER

#define TAPE_DRIVE_REGISTER   0x3 /* Read/Write */

Definition at line 46 of file hardware.h.

◆ VERSION_ENHANCED

#define VERSION_ENHANCED   0x90

Definition at line 239 of file hardware.h.

Function Documentation

◆ HwConfigure()

NTSTATUS NTAPI HwConfigure ( PCONTROLLER_INFO  ControllerInfo,
BOOLEAN  EIS,
BOOLEAN  EFIFO,
BOOLEAN  POLL,
UCHAR  FIFOTHR,
UCHAR  PRETRK 
)

Definition at line 703 of file hardware.c.

724{
725 UCHAR Buffer[4];
726 int i;
727
728 TRACE_(FLOPPY, "HwConfigure called\n");
729
730 PAGED_CODE();
731
732 Buffer[0] = COMMAND_CONFIGURE;
733 Buffer[1] = 0;
734 Buffer[2] = (EIS * CONFIGURE_EIS) + (EFIFO * CONFIGURE_EFIFO) + (POLL * CONFIGURE_POLL) + (FIFOTHR);
735 Buffer[3] = PRETRK;
736
737 for(i = 0; i < 4; i++)
738 if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
739 {
740 WARN_(FLOPPY, "HwConfigure: failed to write the fifo\n");
741 return STATUS_UNSUCCESSFUL;
742 }
743
744 return STATUS_SUCCESS;
745}
PAGED_CODE
#define PAGED_CODE()
Definition: Bus_PDO_QueryResourceRequirements.c:89
Buffer
Definition: bufpool.h:45
TRACE_
#define TRACE_(x)
Definition: compat.h:76
Send_Byte
static NTSTATUS NTAPI Send_Byte(PCONTROLLER_INFO ControllerInfo, UCHAR Byte)
Definition: hardware.c:111
CONFIGURE_POLL
#define CONFIGURE_POLL
Definition: hardware.h:247
CONFIGURE_EIS
#define CONFIGURE_EIS
Definition: hardware.h:249
CONFIGURE_EFIFO
#define CONFIGURE_EFIFO
Definition: hardware.h:248
COMMAND_CONFIGURE
#define COMMAND_CONFIGURE
Definition: hardware.h:202
i
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
WARN_
#define WARN_(ch,...)
Definition: debug.h:157
STATUS_SUCCESS
#define STATUS_SUCCESS
Definition: shellext.h:65
STATUS_UNSUCCESSFUL
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
UCHAR
unsigned char UCHAR
Definition: xmlstorage.h:181

Referenced by InitController().

◆ HwDiskChanged()

NTSTATUS NTAPI HwDiskChanged ( PDRIVE_INFO  DriveInfo,
PBOOLEAN  DiskChanged 
)

Definition at line 785 of file hardware.c.

797{
798 UCHAR Buffer;
799 PCONTROLLER_INFO ControllerInfo = (PCONTROLLER_INFO) DriveInfo->ControllerInfo;
800
801 Buffer = READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_INPUT_REGISTER);
802
803 TRACE_(FLOPPY, "HwDiskChanged: read 0x%x from DIR\n", Buffer);
804
805 if(ControllerInfo->Model30)
806 {
807 if(!(Buffer & DIR_DISKETTE_CHANGE))
808 {
809 INFO_(FLOPPY, "HdDiskChanged - Model30 - returning TRUE\n");
810 *DiskChanged = TRUE;
811 }
812 else
813 {
814 INFO_(FLOPPY, "HdDiskChanged - Model30 - returning FALSE\n");
815 *DiskChanged = FALSE;
816 }
817 }
818 else
819 {
820 if(Buffer & DIR_DISKETTE_CHANGE)
821 {
822 INFO_(FLOPPY, "HdDiskChanged - PS2 - returning TRUE\n");
823 *DiskChanged = TRUE;
824 }
825 else
826 {
827 INFO_(FLOPPY, "HdDiskChanged - PS2 - returning FALSE\n");
828 *DiskChanged = FALSE;
829 }
830 }
831
832 return STATUS_SUCCESS;
833}
TRUE
#define TRUE
Definition: types.h:120
FALSE
#define FALSE
Definition: types.h:117
PCONTROLLER_INFO
struct _CONTROLLER_INFO * PCONTROLLER_INFO
DIGITAL_INPUT_REGISTER
#define DIGITAL_INPUT_REGISTER
Definition: hardware.h:51
DIR_DISKETTE_CHANGE
#define DIR_DISKETTE_CHANGE
Definition: hardware.h:176
READ_PORT_UCHAR
#define READ_PORT_UCHAR(p)
Definition: pc98vid.h:22
INFO_
#define INFO_(ch,...)
Definition: debug.h:159
_CONTROLLER_INFO
Definition: fdc.h:38
_CONTROLLER_INFO::Model30
BOOLEAN Model30
Definition: floppy.h:82
_CONTROLLER_INFO::BaseAddress
PUCHAR BaseAddress
Definition: fdc.h:49
_DRIVE_INFO::ControllerInfo
struct _CONTROLLER_INFO * ControllerInfo
Definition: fdc.h:23

Referenced by DeviceIoctlPassive(), ReadWritePassive(), and ResetChangeFlag().

◆ HwDumpRegisters()

VOID NTAPI HwDumpRegisters ( PCONTROLLER_INFO  ControllerInfo)

Definition at line 1029 of file hardware.c.

1035{
1036 UNREFERENCED_PARAMETER(ControllerInfo);
1037
1038 INFO_(FLOPPY, "STATUS:\n");
1039 INFO_(FLOPPY, "STATUS_REGISTER_A = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + STATUS_REGISTER_A));
1040 INFO_(FLOPPY, "STATUS_REGISTER_B = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + STATUS_REGISTER_B));
1041 INFO_(FLOPPY, "DIGITAL_OUTPUT_REGISTER = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER));
1042 INFO_(FLOPPY, "MAIN_STATUS_REGISTER =0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + MAIN_STATUS_REGISTER));
1043 INFO_(FLOPPY, "DIGITAL_INPUT_REGISTER = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_INPUT_REGISTER));
1044}
STATUS_REGISTER_B
#define STATUS_REGISTER_B
Definition: hardware.h:44
STATUS_REGISTER_A
#define STATUS_REGISTER_A
Definition: hardware.h:43
DIGITAL_OUTPUT_REGISTER
#define DIGITAL_OUTPUT_REGISTER
Definition: hardware.h:45
MAIN_STATUS_REGISTER
#define MAIN_STATUS_REGISTER
Definition: hardware.h:47
UNREFERENCED_PARAMETER
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:317

Referenced by Get_Byte(), HwReset(), ReadWritePassive(), and Send_Byte().

◆ HwFormatTrack()

NTSTATUS NTAPI HwFormatTrack ( PCONTROLLER_INFO  ControllerInfo,
UCHAR  Unit,
UCHAR  Head,
UCHAR  BytesPerSector,
UCHAR  SectorsPerTrack,
UCHAR  Gap3Length,
UCHAR  FillerPattern 
)

Definition at line 611 of file hardware.c.

632{
633 UCHAR Buffer[6];
634 int i;
635
636 TRACE_(FLOPPY, "HwFormatTrack called\n");
637
638 PAGED_CODE();
639
640 Buffer[0] = COMMAND_FORMAT_TRACK;
641 Buffer[1] = (Head << COMMAND_HEAD_NUMBER_SHIFT) | Unit;
642 Buffer[2] = BytesPerSector;
643 Buffer[3] = SectorsPerTrack;
644 Buffer[4] = Gap3Length;
645 Buffer[5] = FillerPattern;
646
647 for(i = 0; i < 6; i++)
648 if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
649 {
650 WARN_(FLOPPY, "HwFormatTrack: unable to send bytes to floppy\n");
651 return STATUS_UNSUCCESSFUL;
652 }
653
654 return STATUS_SUCCESS;
655}
COMMAND_FORMAT_TRACK
#define COMMAND_FORMAT_TRACK
Definition: hardware.h:198
COMMAND_HEAD_NUMBER_SHIFT
#define COMMAND_HEAD_NUMBER_SHIFT
Definition: hardware.h:236
Unit
Unit
Definition: gdiplusenums.h:26
SectorsPerTrack
_In_ ULONG _In_ ULONG SectorsPerTrack
Definition: iofuncs.h:2071

◆ HwGetVersion()

NTSTATUS NTAPI HwGetVersion ( PCONTROLLER_INFO  ControllerInfo)

Definition at line 749 of file hardware.c.

762{
763 UCHAR Buffer;
764
765 PAGED_CODE();
766
767 if(Send_Byte(ControllerInfo, COMMAND_VERSION) != STATUS_SUCCESS)
768 {
769 WARN_(FLOPPY, "HwGetVersion: unable to write fifo\n");
770 return STATUS_UNSUCCESSFUL;
771 }
772
773 if(Get_Byte(ControllerInfo, &Buffer) != STATUS_SUCCESS)
774 {
775 WARN_(FLOPPY, "HwGetVersion: unable to write fifo\n");
776 return STATUS_UNSUCCESSFUL;
777 }
778
779 INFO_(FLOPPY, "HwGetVersion returning version 0x%x\n", Buffer);
780
781 return Buffer;
782}
Get_Byte
static NTSTATUS NTAPI Get_Byte(PCONTROLLER_INFO ControllerInfo, PUCHAR Byte)
Definition: hardware.c:158
COMMAND_VERSION
#define COMMAND_VERSION
Definition: hardware.h:200

Referenced by InitController().

◆ HwPowerOff()

NTSTATUS NTAPI HwPowerOff ( PCONTROLLER_INFO  ControllerInfo)

Definition at line 1010 of file hardware.c.

1020{
1021 TRACE_(FLOPPY, "HwPowerOff called on controller 0x%p\n", ControllerInfo);
1022
1023 WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DRSR_POWER_DOWN);
1024
1025 return STATUS_SUCCESS;
1026}
DRSR_POWER_DOWN
#define DRSR_POWER_DOWN
Definition: hardware.h:102
DATA_RATE_SELECT_REGISTER
#define DATA_RATE_SELECT_REGISTER
Definition: hardware.h:48
WRITE_PORT_UCHAR
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:21

Referenced by Unload().

◆ HwReadId()

NTSTATUS NTAPI HwReadId ( PDRIVE_INFO  DriveInfo,
UCHAR  Head 
)

Definition at line 576 of file hardware.c.

588{
589 UCHAR Buffer[2];
590 int i;
591
592 TRACE_(FLOPPY, "HwReadId called\n");
593
594 PAGED_CODE();
595
596 Buffer[0] = COMMAND_READ_ID | READ_ID_MFM;
597 Buffer[1] = (Head << COMMAND_HEAD_NUMBER_SHIFT) | DriveInfo->UnitNumber;
598
599 for(i = 0; i < 2; i++)
600 if(Send_Byte(DriveInfo->ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
601 {
602 WARN_(FLOPPY, "HwReadId: unable to send bytes to fifo\n");
603 return STATUS_UNSUCCESSFUL;
604 }
605
606 return STATUS_SUCCESS;
607}
COMMAND_READ_ID
#define COMMAND_READ_ID
Definition: hardware.h:196
READ_ID_MFM
#define READ_ID_MFM
Definition: hardware.h:215
_DRIVE_INFO::UnitNumber
UCHAR UnitNumber
Definition: fdc.h:24

Referenced by RWDetermineMediaType(), and RWSeekToCylinder().

◆ HwReadIdResult()

NTSTATUS NTAPI HwReadIdResult ( PCONTROLLER_INFO  ControllerInfo,
PUCHAR  CurCylinder,
PUCHAR  CurHead 
)

Definition at line 864 of file hardware.c.

883{
884 UCHAR Buffer[7] = {0,0,0,0,0,0,0};
885 int i;
886
887 PAGED_CODE();
888
889 for(i = 0; i < 7; i++)
890 if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
891 {
892 WARN_(FLOPPY, "ReadIdResult(): can't read from the controller\n");
893 return STATUS_UNSUCCESSFUL;
894 }
895
896 /* Validate that it did what we told it to */
897 INFO_(FLOPPY, "ReadId results: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", Buffer[0], Buffer[1], Buffer[2], Buffer[3],
898 Buffer[4], Buffer[5], Buffer[6]);
899
900 /* Last command successful? */
901 if((Buffer[0] & SR0_LAST_COMMAND_STATUS) != SR0_LCS_SUCCESS)
902 {
903 WARN_(FLOPPY, "ReadId didn't return last command success\n");
904 return STATUS_UNSUCCESSFUL;
905 }
906
907 /* ID mark found? */
908 if(Buffer[1] & SR1_CANNOT_FIND_ID_ADDRESS)
909 {
910 WARN_(FLOPPY, "ReadId didn't find an address mark\n");
911 return STATUS_UNSUCCESSFUL;
912 }
913
914 if(CurCylinder)
915 *CurCylinder = Buffer[3];
916
917 if(CurHead)
918 *CurHead = Buffer[4];
919
920 return STATUS_SUCCESS;
921}
SR0_LCS_SUCCESS
#define SR0_LCS_SUCCESS
Definition: hardware.h:133
SR0_LAST_COMMAND_STATUS
#define SR0_LAST_COMMAND_STATUS
Definition: hardware.h:118
SR1_CANNOT_FIND_ID_ADDRESS
#define SR1_CANNOT_FIND_ID_ADDRESS
Definition: hardware.h:139

Referenced by RWDetermineMediaType(), and RWSeekToCylinder().

◆ HwReadWriteData()

NTSTATUS NTAPI HwReadWriteData ( PCONTROLLER_INFO  ControllerInfo,
BOOLEAN  Read,
UCHAR  Unit,
UCHAR  Cylinder,
UCHAR  Head,
UCHAR  Sector,
UCHAR  BytesPerSector,
UCHAR  EndOfTrack,
UCHAR  Gap3Length,
UCHAR  DataLength 
)

Definition at line 322 of file hardware.c.

351{
352 UCHAR Buffer[9];
353 int i;
354
355 PAGED_CODE();
356
357 /* Shouldn't be using DataLength in this driver */
358 ASSERT(DataLength == 0xff);
359
360 /* Build the command to send */
361 if(Read)
362 Buffer[0] = COMMAND_READ_DATA;
363 else
364 Buffer[0] = COMMAND_WRITE_DATA;
365
366 Buffer[0] |= READ_DATA_MFM | READ_DATA_MT;
367
368 Buffer[1] = (Head << COMMAND_HEAD_NUMBER_SHIFT) | Unit;
369 Buffer[2] = Cylinder;
370 Buffer[3] = Head;
371 Buffer[4] = Sector;
372 Buffer[5] = BytesPerSector;
373 Buffer[6] = EndOfTrack;
374 Buffer[7] = Gap3Length;
375 Buffer[8] = DataLength;
376
377 /* Send the command */
378 for(i = 0; i < 9; i++)
379 {
380 INFO_(FLOPPY, "HwReadWriteData: Sending a command byte to the FIFO: 0x%x\n", Buffer[i]);
381
382 if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
383 {
384 WARN_(FLOPPY, "HwReadWriteData: Unable to write to the FIFO\n");
385 return STATUS_UNSUCCESSFUL;
386 }
387 }
388
389 return STATUS_SUCCESS;
390}
DataLength
_In_ ULONG _In_opt_ WDFREQUEST _In_opt_ PVOID _In_ size_t _In_ PVOID _In_ size_t _Out_ size_t * DataLength
Definition: cdrom.h:1444
READ_DATA_MT
#define READ_DATA_MT
Definition: hardware.h:212
READ_DATA_MFM
#define READ_DATA_MFM
Definition: hardware.h:211
COMMAND_WRITE_DATA
#define COMMAND_WRITE_DATA
Definition: hardware.h:191
COMMAND_READ_DATA
#define COMMAND_READ_DATA
Definition: hardware.h:192
ASSERT
#define ASSERT(a)
Definition: mode.c:44
Read
_In_ BOOLEAN Read
Definition: strmini.h:479

Referenced by ReadWritePassive().

◆ HwReadWriteResult()

NTSTATUS NTAPI HwReadWriteResult ( PCONTROLLER_INFO  ControllerInfo)

Definition at line 462 of file hardware.c.

477{
478 UCHAR Buffer[7];
479 int i;
480
481 PAGED_CODE();
482
483 for(i = 0; i < 7; i++)
484 if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
485 {
486 WARN_(FLOPPY, "HwReadWriteResult: unable to read fifo\n");
487 return STATUS_UNSUCCESSFUL;
488 }
489
490 /* Validate that it did what we told it to */
491 INFO_(FLOPPY, "HwReadWriteResult results: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", Buffer[0], Buffer[1], Buffer[2], Buffer[3],
492 Buffer[4], Buffer[5], Buffer[6]);
493
494 /* Last command successful? */
495 if((Buffer[0] & SR0_LAST_COMMAND_STATUS) != SR0_LCS_SUCCESS)
496 return STATUS_UNSUCCESSFUL;
497
498 return STATUS_SUCCESS;
499}

Referenced by ReadWritePassive().

◆ HwRecalibrate()

NTSTATUS NTAPI HwRecalibrate ( PDRIVE_INFO  DriveInfo)

Definition at line 503 of file hardware.c.

514{
515 PCONTROLLER_INFO ControllerInfo = DriveInfo->ControllerInfo;
516 UCHAR Unit = DriveInfo->UnitNumber;
517 UCHAR Buffer[2];
518 int i;
519
520 TRACE_(FLOPPY, "HwRecalibrate called\n");
521
522 PAGED_CODE();
523
524 Buffer[0] = COMMAND_RECALIBRATE;
525 Buffer[1] = Unit;
526
527 for(i = 0; i < 2; i++)
528 if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
529 {
530 WARN_(FLOPPY, "HwRecalibrate: unable to write FIFO\n");
531 return STATUS_UNSUCCESSFUL;
532 }
533
534 return STATUS_SUCCESS;
535}
COMMAND_RECALIBRATE
#define COMMAND_RECALIBRATE
Definition: hardware.h:193

Referenced by Recalibrate(), and RWDetermineMediaType().

◆ HwRecalibrateResult()

NTSTATUS NTAPI HwRecalibrateResult ( PCONTROLLER_INFO  ControllerInfo)

Definition at line 394 of file hardware.c.

409{
410 UCHAR Buffer[2];
411 int i;
412
413 PAGED_CODE();
414
415 if(Send_Byte(ControllerInfo, COMMAND_SENSE_INTERRUPT_STATUS) != STATUS_SUCCESS)
416 {
417 WARN_(FLOPPY, "HwRecalibrateResult: Unable to write the controller\n");
418 return STATUS_UNSUCCESSFUL;
419 }
420
421 for(i = 0; i < 2; i++)
422 if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
423 {
424 WARN_(FLOPPY, "HwRecalibrateResult: unable to read FIFO\n");
425 return STATUS_UNSUCCESSFUL;
426 }
427
428 /* Validate that it did what we told it to */
429 INFO_(FLOPPY, "HwRecalibrateResult results: ST0: 0x%x PCN: 0x%x\n", Buffer[0], Buffer[1]);
430
431 /*
432 * Buffer[0] = ST0
433 * Buffer[1] = PCN
434 */
435
436 /* Is the PCN 0? */
437 if(Buffer[1] != 0)
438 {
439 WARN_(FLOPPY, "HwRecalibrateResult: PCN not 0\n");
440 return STATUS_UNSUCCESSFUL;
441 }
442
443 /* test seek complete */
444 if((Buffer[0] & SR0_SEEK_COMPLETE) != SR0_SEEK_COMPLETE)
445 {
446 WARN_(FLOPPY, "HwRecalibrateResult: Failed to complete the seek\n");
447 return STATUS_UNSUCCESSFUL;
448 }
449
450 /* Is the equipment check flag set? Could be no disk in drive... */
451 if((Buffer[0] & SR0_EQUIPMENT_CHECK) == SR0_EQUIPMENT_CHECK)
452 {
453 WARN_(FLOPPY, "HwRecalibrateResult: Seeked to track 0 successfully, but EC is set; returning failure\n");
454 return STATUS_UNSUCCESSFUL;
455 }
456
457 return STATUS_SUCCESS;
458}
COMMAND_SENSE_INTERRUPT_STATUS
#define COMMAND_SENSE_INTERRUPT_STATUS
Definition: hardware.h:194
SR0_EQUIPMENT_CHECK
#define SR0_EQUIPMENT_CHECK
Definition: hardware.h:116
SR0_SEEK_COMPLETE
#define SR0_SEEK_COMPLETE
Definition: hardware.h:117

Referenced by Recalibrate(), and RWDetermineMediaType().

◆ HwReset()

NTSTATUS NTAPI HwReset ( PCONTROLLER_INFO  Controller)

Definition at line 973 of file hardware.c.

983{
984 TRACE_(FLOPPY, "HwReset called\n");
985
986 /* Write the reset bit in the DRSR */
987 WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DRSR_SW_RESET);
988
989 /* Check for the reset bit in the DOR and set it if necessary (see Intel doc) */
990 if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET))
991 {
992 HwDumpRegisters(ControllerInfo);
993 INFO_(FLOPPY, "HwReset: Setting Enable bit\n");
994 WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, DOR_DMA_IO_INTERFACE_ENABLE|DOR_RESET);
995 HwDumpRegisters(ControllerInfo);
996
997 if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET))
998 {
999 WARN_(FLOPPY, "HwReset: failed to set the DOR enable bit!\n");
1000 HwDumpRegisters(ControllerInfo);
1001 return STATUS_UNSUCCESSFUL;
1002 }
1003 }
1004
1005 return STATUS_SUCCESS;
1006}
HwDumpRegisters
VOID NTAPI HwDumpRegisters(PCONTROLLER_INFO ControllerInfo)
Definition: hardware.c:1029
DRSR_SW_RESET
#define DRSR_SW_RESET
Definition: hardware.h:103
DOR_RESET
#define DOR_RESET
Definition: hardware.h:75
DOR_DMA_IO_INTERFACE_ENABLE
#define DOR_DMA_IO_INTERFACE_ENABLE
Definition: hardware.h:76

Referenced by InitController().

◆ HwSeek()

NTSTATUS NTAPI HwSeek ( PDRIVE_INFO  DriveInfo,
UCHAR  Cylinder 
)

Definition at line 659 of file hardware.c.

671{
672 LARGE_INTEGER Delay;
673 UCHAR Buffer[3];
674 int i;
675
676 TRACE_(FLOPPY, "HwSeek called for cyl 0x%x\n", Cylinder);
677
678 PAGED_CODE();
679
680 Buffer[0] = COMMAND_SEEK;
681 Buffer[1] = DriveInfo->UnitNumber;
682 Buffer[2] = Cylinder;
683
684 for(i = 0; i < 3; i++)
685 if(Send_Byte(DriveInfo->ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
686 {
687 WARN_(FLOPPY, "HwSeek: failed to write fifo\n");
688 return STATUS_UNSUCCESSFUL;
689 }
690
691 /* Wait for the head to settle */
692 Delay.QuadPart = 10 * 1000;
693 Delay.QuadPart *= -1;
694 Delay.QuadPart *= DriveInfo->FloppyDeviceData.HeadSettleTime;
695
696 KeDelayExecutionThread(KernelMode, FALSE, &Delay);
697
698 return STATUS_SUCCESS;
699}
COMMAND_SEEK
#define COMMAND_SEEK
Definition: hardware.h:199
KeDelayExecutionThread
#define KeDelayExecutionThread(mode, foo, t)
Definition: env_spec_w32.h:484
KernelMode
#define KernelMode
Definition: asm.h:34
_CM_FLOPPY_DEVICE_DATA::HeadSettleTime
UCHAR HeadSettleTime
Definition: cmtypes.h:498
_DRIVE_INFO::FloppyDeviceData
CM_FLOPPY_DEVICE_DATA FloppyDeviceData
Definition: fdc.h:27
_LARGE_INTEGER
Definition: typedefs.h:103
_LARGE_INTEGER::QuadPart
LONGLONG QuadPart
Definition: typedefs.h:114

Referenced by ResetChangeFlag(), and RWSeekToCylinder().

◆ HwSenseDriveStatus()

NTSTATUS NTAPI HwSenseDriveStatus ( PDRIVE_INFO  DriveInfo)

Definition at line 287 of file hardware.c.

299{
300 UCHAR Buffer[2];
301 int i;
302
303 PAGED_CODE();
304
305 TRACE_(FLOPPY, "HwSenseDriveStatus called\n");
306
307 Buffer[0] = COMMAND_SENSE_DRIVE_STATUS;
308 Buffer[1] = DriveInfo->UnitNumber; /* hard-wired to head 0 for now */
309
310 for(i = 0; i < 2; i++)
311 if(Send_Byte(DriveInfo->ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
312 {
313 WARN_(FLOPPY, "HwSenseDriveStatus: failed to write FIFO\n");
314 return STATUS_UNSUCCESSFUL;
315 }
316
317 return STATUS_SUCCESS;
318}
COMMAND_SENSE_DRIVE_STATUS
#define COMMAND_SENSE_DRIVE_STATUS
Definition: hardware.h:190

Referenced by DeviceIoctlPassive().

◆ HwSenseDriveStatusResult()

NTSTATUS NTAPI HwSenseDriveStatusResult ( PCONTROLLER_INFO  ControllerInfo,
PUCHAR  Status 
)

Definition at line 836 of file hardware.c.

848{
849 PAGED_CODE();
850
851 if(Get_Byte(ControllerInfo, Status) != STATUS_SUCCESS)
852 {
853 WARN_(FLOPPY, "HwSenseDriveStatus: unable to read fifo\n");
854 return STATUS_UNSUCCESSFUL;
855 }
856
857 TRACE_(FLOPPY, "HwSenseDriveStatusResult: ST3: 0x%x\n", *Status);
858
859 return STATUS_SUCCESS;
860}
Status
Status
Definition: gdiplustypes.h:25

Referenced by DeviceIoctlPassive().

◆ HwSenseInterruptStatus()

NTSTATUS NTAPI HwSenseInterruptStatus ( PCONTROLLER_INFO  ControllerInfo)

Definition at line 539 of file hardware.c.

548{
549 UCHAR Buffer[2];
550 int i;
551
552 PAGED_CODE();
553
554 if(Send_Byte(ControllerInfo, COMMAND_SENSE_INTERRUPT_STATUS) != STATUS_SUCCESS)
555 {
556 WARN_(FLOPPY, "HwSenseInterruptStatus: failed to write controller\n");
557 return STATUS_UNSUCCESSFUL;
558 }
559
560 for(i = 0; i < 2; i++)
561 {
562 if(Get_Byte(ControllerInfo, &Buffer[i]) != STATUS_SUCCESS)
563 {
564 WARN_(FLOPPY, "HwSenseInterruptStatus: failed to read controller\n");
565 return STATUS_UNSUCCESSFUL;
566 }
567 }
568
569 INFO_(FLOPPY, "HwSenseInterruptStatus returned 0x%x 0x%x\n", Buffer[0], Buffer[1]);
570
571 return STATUS_SUCCESS;
572}

Referenced by InitController(), ResetChangeFlag(), and RWSeekToCylinder().

◆ HwSetDataRate()

NTSTATUS NTAPI HwSetDataRate ( PCONTROLLER_INFO  ControllerInfo,
UCHAR  DataRate 
)

Definition at line 204 of file hardware.c.

213{
214 TRACE_(FLOPPY, "HwSetDataRate called; writing rate code 0x%x to offset 0x%x\n", DataRate, DATA_RATE_SELECT_REGISTER);
215
216 WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DataRate);
217
218 return STATUS_SUCCESS;
219}

Referenced by InitController(), Recalibrate(), and RWDetermineMediaType().

◆ HwSpecify()

NTSTATUS NTAPI HwSpecify ( PCONTROLLER_INFO  ControllerInfo,
UCHAR  HeadLoadTime,
UCHAR  HeadUnloadTime,
UCHAR  StepRateTime,
BOOLEAN  NonDma 
)

Definition at line 925 of file hardware.c.

946{
947 UCHAR Buffer[3];
948 int i;
949
950 Buffer[0] = COMMAND_SPECIFY;
951 /*
952 Buffer[1] = (StepRateTime << 4) + HeadUnloadTime;
953 Buffer[2] = (HeadLoadTime << 1) + (NonDma ? 1 : 0);
954 */
955 Buffer[1] = 0xdf;
956 Buffer[2] = 0x2;
957
958 //INFO_(FLOPPY, "HwSpecify: sending 0x%x 0x%x 0x%x to FIFO\n", Buffer[0], Buffer[1], Buffer[2]);
959 WARN_(FLOPPY, "HWSPECIFY: FIXME - sending 0x3 0xd1 0x2 to FIFO\n");
960
961 for(i = 0; i < 3; i++)
962 if(Send_Byte(ControllerInfo, Buffer[i]) != STATUS_SUCCESS)
963 {
964 WARN_(FLOPPY, "HwSpecify: unable to write to controller\n");
965 return STATUS_UNSUCCESSFUL;
966 }
967
968 return STATUS_SUCCESS;
969}
COMMAND_SPECIFY
#define COMMAND_SPECIFY
Definition: hardware.h:189

Referenced by InitController(), and RWDetermineMediaType().

◆ HwTurnOffMotor()

NTSTATUS NTAPI HwTurnOffMotor ( PCONTROLLER_INFO  ControllerInfo)

Definition at line 223 of file hardware.c.

235{
236 TRACE_(FLOPPY, "HwTurnOffMotor: writing byte 0x%x to offset 0x%x\n", DOR_FDC_ENABLE|DOR_DMA_IO_INTERFACE_ENABLE, DIGITAL_OUTPUT_REGISTER);
237
238 WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, DOR_FDC_ENABLE|DOR_DMA_IO_INTERFACE_ENABLE);
239
240 return STATUS_SUCCESS;
241}
DOR_FDC_ENABLE
#define DOR_FDC_ENABLE
Definition: hardware.h:74

Referenced by MotorStopDpcFunc().

◆ HwTurnOnMotor()

NTSTATUS NTAPI HwTurnOnMotor ( PDRIVE_INFO  DriveInfo)

Definition at line 245 of file hardware.c.

257{
258 PCONTROLLER_INFO ControllerInfo = DriveInfo->ControllerInfo;
259 UCHAR Unit = DriveInfo->UnitNumber;
260 UCHAR Buffer;
261
262 PAGED_CODE();
263
264 /* turn on motor */
265 Buffer = Unit;
266
267 Buffer |= DOR_FDC_ENABLE;
268 Buffer |= DOR_DMA_IO_INTERFACE_ENABLE;
269
270 if(Unit == 0)
271 Buffer |= DOR_FLOPPY_MOTOR_ON_A;
272 else if (Unit == 1)
273 Buffer |= DOR_FLOPPY_MOTOR_ON_B;
274 else if (Unit == 2)
275 Buffer |= DOR_FLOPPY_MOTOR_ON_C;
276 else if (Unit == 3)
277 Buffer |= DOR_FLOPPY_MOTOR_ON_D;
278
279 TRACE_(FLOPPY, "HwTurnOnMotor: writing byte 0x%x to offset 0x%x\n", Buffer, DIGITAL_OUTPUT_REGISTER);
280 WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, Buffer);
281
282 return STATUS_SUCCESS;
283}
DOR_FLOPPY_MOTOR_ON_A
#define DOR_FLOPPY_MOTOR_ON_A
Definition: hardware.h:77
DOR_FLOPPY_MOTOR_ON_D
#define DOR_FLOPPY_MOTOR_ON_D
Definition: hardware.h:80
DOR_FLOPPY_MOTOR_ON_C
#define DOR_FLOPPY_MOTOR_ON_C
Definition: hardware.h:79
DOR_FLOPPY_MOTOR_ON_B
#define DOR_FLOPPY_MOTOR_ON_B
Definition: hardware.h:78

Referenced by StartMotor().