ReactOS  0.4.15-dev-2535-gcf6c191
page.c
Go to the documentation of this file.
1 /*
2  * COPYRIGHT: See COPYING in the top level directory
3  * PROJECT: ReactOS kernel
4  * FILE: ntoskrnl/mm/i386/page.c
5  * PURPOSE: Low level memory managment manipulation
6  *
7  * PROGRAMMERS: David Welch (welch@cwcom.net)
8  */
9 
10 /* INCLUDES ***************************************************************/
11 
12 #include <ntoskrnl.h>
13 #define NDEBUG
14 #include <debug.h>
15 
16 #include <mm/ARM3/miarm.h>
17 
18 #ifndef _MI_PAGING_LEVELS
19 #error "Dude, fix your stuff before using this file"
20 #endif
21 
22 /* GLOBALS *****************************************************************/
23 const
26 {
27  //
28  // These are the base MM_ protection flags
29  //
30  0,
31  PTE_READONLY | PTE_ENABLE_CACHE,
32  PTE_EXECUTE | PTE_ENABLE_CACHE,
33  PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
34  PTE_READWRITE | PTE_ENABLE_CACHE,
35  PTE_WRITECOPY | PTE_ENABLE_CACHE,
36  PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
37  PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
38  //
39  // These OR in the MM_NOCACHE flag
40  //
41  0,
42  PTE_READONLY | PTE_DISABLE_CACHE,
43  PTE_EXECUTE | PTE_DISABLE_CACHE,
44  PTE_EXECUTE_READ | PTE_DISABLE_CACHE,
45  PTE_READWRITE | PTE_DISABLE_CACHE,
46  PTE_WRITECOPY | PTE_DISABLE_CACHE,
47  PTE_EXECUTE_READWRITE | PTE_DISABLE_CACHE,
48  PTE_EXECUTE_WRITECOPY | PTE_DISABLE_CACHE,
49  //
50  // These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
51  //
52  0,
53  PTE_READONLY | PTE_ENABLE_CACHE,
54  PTE_EXECUTE | PTE_ENABLE_CACHE,
55  PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
56  PTE_READWRITE | PTE_ENABLE_CACHE,
57  PTE_WRITECOPY | PTE_ENABLE_CACHE,
58  PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
59  PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
60  //
61  // These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
62  //
63  0,
64  PTE_READONLY | PTE_WRITECOMBINED_CACHE,
65  PTE_EXECUTE | PTE_WRITECOMBINED_CACHE,
66  PTE_EXECUTE_READ | PTE_WRITECOMBINED_CACHE,
67  PTE_READWRITE | PTE_WRITECOMBINED_CACHE,
68  PTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
69  PTE_EXECUTE_READWRITE | PTE_WRITECOMBINED_CACHE,
70  PTE_EXECUTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
71 };
72 
73 const
75 {
108 };
109 
110 /* FUNCTIONS ***************************************************************/
111 
112 NTSTATUS
113 NTAPI
116 
118 NTAPI
120  PVOID Address)
121 {
122  PMMPTE PointerPte;
124 
125  /* Must be called for user mode only */
126  ASSERT(Process != NULL);
128 
129  /* And for our process */
131 
132  /* Lock for reading */
134 
136  {
138  return 0;
139  }
140 
141  /* Make sure we can read the PTE */
143 
144  PointerPte = MiAddressToPte(Address);
145  Page = PointerPte->u.Hard.Valid ? PFN_FROM_PTE(PointerPte) : 0;
146 
148  return Page;
149 }
150 
151 VOID
152 NTAPI
154  BOOLEAN* WasDirty, PPFN_NUMBER Page)
155 /*
156  * FUNCTION: Delete a virtual mapping
157  */
158 {
159  PMMPTE PointerPte;
160  MMPTE OldPte;
161 
162  DPRINT("MmDeleteVirtualMapping(%p, %p, %p, %p)\n", Process, Address, WasDirty, Page);
163 
164  ASSERT(((ULONG_PTR)Address % PAGE_SIZE) == 0);
165 
166  /* And we should be at low IRQL */
168 
169  /* Make sure our PDE is valid, and that everything is going fine */
170  if (Process == NULL)
171  {
173  {
174  DPRINT1("NULL process given for user-mode mapping at %p\n", Address);
175  KeBugCheck(MEMORY_MANAGEMENT);
176  }
177 #if (_MI_PAGING_LEVELS == 2)
178  if (!MiSynchronizeSystemPde(MiAddressToPde(Address)))
179 #else
181 #endif
182  {
183  /* There can't be a page if there is no PDE */
184  if (WasDirty)
185  *WasDirty = FALSE;
186  if (Page)
187  *Page = 0;
188  return;
189  }
190  }
191  else
192  {
194  {
195  DPRINT1("Process %p given for kernel-mode mapping at %p -- %lu pages starting at %Ix\n", Process, Address);
196  KeBugCheck(MEMORY_MANAGEMENT);
197  }
198 
199  /* Only for current process !!! */
202 
203  /* No PDE --> No page */
205  {
207  if (WasDirty)
208  *WasDirty = 0;
209  if (Page)
210  *Page = 0;
211  return;
212  }
213 
215  }
216 
217  PointerPte = MiAddressToPte(Address);
218  OldPte.u.Long = InterlockedExchangePte(PointerPte, 0);
219 
220  if (OldPte.u.Long == 0)
221  {
222  /* There was nothing here */
225  if (WasDirty)
226  *WasDirty = 0;
227  if (Page)
228  *Page = 0;
229  return;
230  }
231 
232  /* It must have been present, or not a swap entry */
233  ASSERT(OldPte.u.Hard.Valid || !FlagOn(OldPte.u.Long, 0x800));
234 
235  if (OldPte.u.Hard.Valid)
237 
239  {
240  /* Remove PDE reference */
243  {
245  MiDeletePte(MiAddressToPte(PointerPte), PointerPte, Process, NULL);
247  }
248 
250  }
251 
252  if (WasDirty)
253  *WasDirty = !!OldPte.u.Hard.Dirty;
254  if (Page)
255  *Page = OldPte.u.Hard.PageFrameNumber;
256 }
257 
258 
259 VOID
260 NTAPI
263  PVOID Address,
264  SWAPENTRY* SwapEntry)
265 {
266  PMMPTE PointerPte;
267  MMPTE OldPte;
268 
269  /* This should not be called for kernel space anymore */
270  ASSERT(Process != NULL);
272 
273  /* And we don't support deleting for other process */
275 
276  /* And we should be at low IRQL */
278 
279  /* We are tinkering with the PDE here. Ensure it will be there */
281 
282  /* Callers must ensure there is actually something there */
283  ASSERT(MiAddressToPde(Address)->u.Long != 0);
284 
286 
287  PointerPte = MiAddressToPte(Address);
288  OldPte.u.Long = InterlockedExchangePte(PointerPte, 0);
289  /* This must be a swap entry ! */
290  if (!FlagOn(OldPte.u.Long, 0x800) || OldPte.u.Hard.Valid)
291  {
292  KeBugCheckEx(MEMORY_MANAGEMENT, OldPte.u.Long, (ULONG_PTR)Process, (ULONG_PTR)Address, 0);
293  }
294 
295  /* This used to be a non-zero PTE, now we can let the PDE go. */
298  {
299  /* We can let it go */
301  MiDeletePte(MiAddressToPte(PointerPte), PointerPte, Process, NULL);
303  }
304 
306 
307  *SwapEntry = OldPte.u.Long >> 1;
308 }
309 
310 BOOLEAN
311 NTAPI
313 {
314  BOOLEAN Ret;
315 
317  {
318  ASSERT(Process == NULL);
319 #if _MI_PAGING_LEVELS == 2
320  if (!MiSynchronizeSystemPde(MiAddressToPde(Address)))
321 #else
323 #endif
324  {
325  /* It can't be present if there is no PDE */
326  return FALSE;
327  }
328 
329  return MiAddressToPte(Address)->u.Hard.Valid;
330  }
331 
332  ASSERT(Process != NULL);
334 
336 
338  {
339  /* It can't be present if there is no PDE */
341  return FALSE;
342  }
343 
345 
346  Ret = MiAddressToPte(Address)->u.Hard.Valid;
347 
349 
350  return Ret;
351 }
352 
353 BOOLEAN
354 NTAPI
356 {
357  BOOLEAN Ret;
358  PMMPTE PointerPte;
359 
361  {
362  ASSERT(Process == NULL);
363 #if _MI_PAGING_LEVELS == 2
364  if (!MiSynchronizeSystemPde(MiAddressToPde(Address)))
365 #else
367 #endif
368  {
369  /* It's not disabled if it's not present */
370  return FALSE;
371  }
372  }
373  else
374  {
375  ASSERT(Process != NULL);
377 
379 
381  {
382  /* It can't be disabled if there is no PDE */
384  return FALSE;
385  }
386 
388  }
389 
390  PointerPte = MiAddressToPte(Address);
391  Ret = !PointerPte->u.Hard.Valid
392  && !FlagOn(PointerPte->u.Long, 0x800)
393  && (PointerPte->u.Hard.PageFrameNumber != 0);
394 
397 
398  return Ret;
399 }
400 
401 BOOLEAN
402 NTAPI
404 {
405  BOOLEAN Ret;
406  PMMPTE PointerPte;
407 
408  /* We never set swap entries for kernel addresses */
410  {
411  ASSERT(Process == NULL);
412  return FALSE;
413  }
414 
415  ASSERT(Process != NULL);
417 
419 
421  {
422  /* There can't be a swap entry if there is no PDE */
424  return FALSE;
425  }
426 
428 
429  PointerPte = MiAddressToPte(Address);
430  Ret = !PointerPte->u.Hard.Valid && FlagOn(PointerPte->u.Long, 0x800);
431 
433 
434  return Ret;
435 }
436 
437 VOID
438 NTAPI
440 {
441  PMMPTE PointerPte;
442 
443  /* We never set swap entries for kernel addresses */
445  {
446  ASSERT(Process == NULL);
447  *SwapEntry = 0;
448  return;
449  }
450 
451  ASSERT(Process != NULL);
453 
455 
457  {
458  /* There can't be a swap entry if there is no PDE */
460  *SwapEntry = 0;
461  return;
462  }
463 
465 
466  PointerPte = MiAddressToPte(Address);
467  if (!PointerPte->u.Hard.Valid && FlagOn(PointerPte->u.Long, 0x800))
468  *SwapEntry = PointerPte->u.Long >> 1;
469  else
470  *SwapEntry = 0;
471 
473 }
474 
475 NTSTATUS
476 NTAPI
478  PVOID Address,
479  SWAPENTRY SwapEntry)
480 {
481  PMMPTE PointerPte;
482  ULONG_PTR Pte;
483 
484  /* This should not be called for kernel space anymore */
485  ASSERT(Process != NULL);
487 
488  /* And we don't support creating for other process */
490 
491  if (SwapEntry & (1 << 31))
492  {
493  KeBugCheck(MEMORY_MANAGEMENT);
494  }
495 
496  /* We are tinkering with the PDE here. Ensure it will be there */
499 
501 
502  PointerPte = MiAddressToPte(Address);
503  Pte = InterlockedExchangePte(PointerPte, SwapEntry << 1);
504  if (Pte != 0)
505  {
506  KeBugCheckEx(MEMORY_MANAGEMENT, SwapEntry, (ULONG_PTR)Process, (ULONG_PTR)Address, 0);
507  }
508 
509  /* This used to be a 0 PTE, now we need a valid PDE to keep it around */
512 
513  return STATUS_SUCCESS;
514 }
515 
516 
517 NTSTATUS
518 NTAPI
520  PVOID Address,
521  ULONG flProtect,
523 {
524  ULONG ProtectionMask;
525  PMMPTE PointerPte;
526  MMPTE TempPte;
527  ULONG_PTR Pte;
528 
529  DPRINT("MmCreateVirtualMappingUnsafe(%p, %p, %lu, %x)\n",
530  Process, Address, flProtect, Page);
531 
532  ASSERT(((ULONG_PTR)Address % PAGE_SIZE) == 0);
533 
534  ProtectionMask = MiMakeProtectionMask(flProtect);
535  /* Caller must have checked ! */
536  ASSERT(ProtectionMask != MM_INVALID_PROTECTION);
537  ASSERT(ProtectionMask != MM_NOACCESS);
538  ASSERT(ProtectionMask != MM_ZERO_ACCESS);
539 
540  /* Make sure our PDE is valid, and that everything is going fine */
541  if (Process == NULL)
542  {
544  {
545  DPRINT1("NULL process given for user-mode mapping at %p\n", Address);
546  KeBugCheck(MEMORY_MANAGEMENT);
547  }
548 #if _MI_PAGING_LEVELS == 2
549  if (!MiSynchronizeSystemPde(MiAddressToPde(Address)))
551 #endif
552  }
553  else
554  {
556  {
557  DPRINT1("Process %p given for kernel-mode mapping at %p -- %lu pages starting at %Ix\n", Process, Address);
558  KeBugCheck(MEMORY_MANAGEMENT);
559  }
560 
561  /* Only for current process !!! */
564 
566  }
567 
568  PointerPte = MiAddressToPte(Address);
569 
571  {
572  MI_MAKE_HARDWARE_PTE_KERNEL(&TempPte, PointerPte, ProtectionMask, Page);
573  }
574  else
575  {
576  MI_MAKE_HARDWARE_PTE_USER(&TempPte, PointerPte, ProtectionMask, Page);
577  }
578 
579  Pte = InterlockedExchangePte(PointerPte, TempPte.u.Long);
580  /* There should not have been anything valid here */
581  if (Pte != 0)
582  {
583  DPRINT1("Bad PTE %lx at %p for %p\n", Pte, PointerPte, Address);
584  KeBugCheck(MEMORY_MANAGEMENT);
585  }
586 
587  /* We don't need to flush the TLB here because it only caches valid translations
588  * and we're moving this PTE from invalid to valid so it can't be cached right now */
589 
591  {
592  /* Add PDE reference */
595  }
596 
597  return(STATUS_SUCCESS);
598 }
599 
600 NTSTATUS
601 NTAPI
603  PVOID Address,
604  ULONG flProtect,
606 {
608  if (!MmIsPageInUse(Page))
609  {
610  DPRINT1("Page %lx is not in use\n", Page);
611  KeBugCheck(MEMORY_MANAGEMENT);
612  }
613 
614  return MmCreateVirtualMappingUnsafe(Process, Address, flProtect, Page);
615 }
616 
617 ULONG
618 NTAPI
620 {
621  PMMPTE PointerPte;
622  ULONG Protect;
623 
625  {
626  ASSERT(Process == NULL);
627 
628 #if _MI_PAGING_LEVELS == 2
629  if (!MiSynchronizeSystemPde(MiAddressToPde(Address)))
630 #else
632 #endif
633  {
634  return PAGE_NOACCESS;
635  }
636  }
637  else
638  {
640  ASSERT(Process != NULL);
641 
643 
645 
647  {
648  /* It can't be present if there is no PDE */
650  return PAGE_NOACCESS;
651  }
652 
654  }
655 
656  PointerPte = MiAddressToPte(Address);
657 
658  if (!PointerPte->u.Flush.Valid)
659  {
661  }
662  else
663  {
664  if (PointerPte->u.Flush.CopyOnWrite)
666  else if (PointerPte->u.Flush.Write)
668  else
670 #if _MI_PAGING_LEVELS >= 3
671  /* PAE & AMD64 long mode support NoExecute bit */
672  if (!PointerPte->u.Flush.NoExecute)
673  Protect <<= 4;
674 #endif
675  if (PointerPte->u.Flush.CacheDisable)
677  if (PointerPte->u.Flush.WriteThrough)
679  }
680 
683 
684  return(Protect);
685 }
686 
687 VOID
688 NTAPI
690 {
691  ULONG ProtectionMask;
692  PMMPTE PointerPte;
693  MMPTE TempPte, OldPte;
694 
695  DPRINT("MmSetPageProtect(Process %p Address %p flProtect %x)\n",
696  Process, Address, flProtect);
697 
698  ASSERT(Process != NULL);
700 
702 
703  ProtectionMask = MiMakeProtectionMask(flProtect);
704  /* Caller must have checked ! */
705  ASSERT(ProtectionMask != MM_INVALID_PROTECTION);
706 
708 
710 
711  PointerPte = MiAddressToPte(Address);
712 
713  MI_MAKE_HARDWARE_PTE_USER(&TempPte, PointerPte, ProtectionMask, PFN_FROM_PTE(PointerPte));
714  /* Keep dirty & accessed bits */
715  TempPte.u.Hard.Accessed = PointerPte->u.Hard.Accessed;
716  TempPte.u.Hard.Dirty = PointerPte->u.Hard.Dirty;
717 
718  OldPte.u.Long = InterlockedExchangePte(PointerPte, TempPte.u.Long);
719 
720  // We should be able to bring a page back from PAGE_NOACCESS
721  if (!OldPte.u.Hard.Valid && (FlagOn(OldPte.u.Long, 0x800) || (OldPte.u.Hard.PageFrameNumber == 0)))
722  {
723  DPRINT1("Invalid Pte %lx\n", OldPte.u.Long);
724  KeBugCheck(MEMORY_MANAGEMENT);
725  }
726 
727  if (OldPte.u.Long != TempPte.u.Long)
729 
731 }
732 
733 VOID
734 NTAPI
736 {
737  PMMPTE PointerPte;
738 
739  DPRINT("MmSetDirtyBit(Process %p Address %p Bit %x)\n",
740  Process, Address, Bit);
741 
742  ASSERT(Process != NULL);
744 
746 
748 
750 
751  PointerPte = MiAddressToPte(Address);
752  // We shouldnl't set dirty bit on non-mapped adresses
753  if (!PointerPte->u.Hard.Valid && (FlagOn(PointerPte->u.Long, 0x800) || (PointerPte->u.Hard.PageFrameNumber == 0)))
754  {
755  DPRINT1("Invalid Pte %lx\n", PointerPte->u.Long);
756  KeBugCheck(MEMORY_MANAGEMENT);
757  }
758 
759  PointerPte->u.Hard.Dirty = !!Bit;
760 
761  if (!Bit)
763 
765 }
766 
767 CODE_SEG("INIT")
768 VOID
769 NTAPI
771 {
772  /* Nothing to do here */
773 }
774 
775 #ifdef _M_IX86
776 BOOLEAN
778 {
779  PMMPDE PointerPde = MiAddressToPde(Address);
780  PMMPTE PointerPte = MiAddressToPte(Address);
781 
782  if (PointerPde->u.Hard.Valid == 0)
783  {
784  if (!MiSynchronizeSystemPde(PointerPde))
785  return FALSE;
786  return PointerPte->u.Hard.Valid != 0;
787  }
788  return FALSE;
789 }
790 #endif
791 
792 /* EOF */
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble * u
Definition: glfuncs.h:240
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Definition: mm.h:91
ULONG64 Valid
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union _MMPTE::@2304 u
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_In_ HANDLE _Outptr_result_bytebuffer_ ViewSize PVOID _In_ ULONG_PTR _In_ SIZE_T _Inout_opt_ PLARGE_INTEGER _Inout_ PSIZE_T _In_ SECTION_INHERIT _In_ ULONG _In_ ULONG Protect
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ULONG64 CopyOnWrite
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uint32_t ULONG_PTR
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ULONG64 Dirty
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Definition: ping.c:68
ULONG64 WriteThrough
Definition: mmtypes.h:69
#define PAGE_EXECUTE
Definition: nt_native.h:1306
PFN_NUMBER Page
Definition: section.c:4757
CODE_SEG("INIT")
Definition: Interface.c:1810
#define MM_ZERO_ACCESS
Definition: miarm.h:43
FORCEINLINE VOID MiLockProcessWorkingSetUnsafe(IN PEPROCESS Process, IN PETHREAD Thread)
Definition: miarm.h:1152
FORCEINLINE VOID KeInvalidateTlbEntry(IN PVOID Address)
Definition: ke.h:260
FORCEINLINE VOID MiDecrementPageTableReferences(IN PVOID Address)
Definition: miarm.h:1813
VOID NTAPI MmDeleteVirtualMapping(IN PEPROCESS Process, IN PVOID Address, OUT PBOOLEAN WasDirty, OUT PPFN_NUMBER Page)
Definition: page.c:177
#define ASSERT(a)
Definition: mode.c:45
BOOLEAN NTAPI MmIsDisabledPage(PEPROCESS Process, PVOID Address)
Definition: page.c:309
ULONG64 Valid
Definition: mmtypes.h:150
HARDWARE_PTE_ARMV6 TempPte
Definition: winldr.c:76
NTSTATUS NTAPI MiFillSystemPageDirectory(IN PVOID Base, IN SIZE_T NumberOfBytes)
Definition: section.c:480
FORCEINLINE VOID MiLockProcessWorkingSetShared(IN PEPROCESS Process, IN PETHREAD Thread)
Definition: miarm.h:1129
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:790
#define MM_NOIRQL
Definition: miarm.h:236
ULONG NTAPI MiMakeProtectionMask(IN ULONG Protect)
Definition: section.c:158
#define InterlockedExchangePte(PointerPte, Value)
Definition: mm.h:165
#define PAGE_SIZE
Definition: env_spec_w32.h:49
#define FlagOn(_F, _SF)
Definition: ext2fs.h:179
ULONG_PTR Long
Definition: mmtypes.h:215
FORCEINLINE VOID MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte, IN PMMPTE MappingPte, IN ULONG_PTR ProtectionMask, IN PFN_NUMBER PageFrameNumber)
Definition: miarm.h:822
#define DISPATCH_LEVEL
Definition: env_spec_w32.h:696
ULONG_PTR SIZE_T
Definition: typedefs.h:80
MMPTE_HARDWARE Hard
Definition: mmtypes.h:217
ULONG NTAPI MmGetPageProtect(IN PEPROCESS Process, IN PVOID Address)
Definition: page.c:258
VOID NTAPI MmGetPageFileMapping(PEPROCESS Process, PVOID Address, SWAPENTRY *SwapEntry)
Definition: page.c:299
#define PAGE_WRITECOMBINE
Definition: mmtypes.h:78
ULONG_PTR SWAPENTRY
Definition: mm.h:51
_Must_inspect_result_ typedef _In_ PHYSICAL_ADDRESS _Inout_ PLARGE_INTEGER NumberOfBytes
Definition: iotypes.h:1035
#define NULL
Definition: types.h:112
#define PAGE_READONLY
Definition: compat.h:138
#define PAGE_WRITECOPY
Definition: nt_native.h:1305
#define DPRINT1
Definition: precomp.h:8
ULONG64 Write
Definition: mmtypes.h:67
PFN_NUMBER NTAPI MmGetPfnForProcess(IN PEPROCESS Process, IN PVOID Address)
Definition: page.c:206
_Must_inspect_result_ _In_ PLARGE_INTEGER _In_ PLARGE_INTEGER _In_ ULONG _In_ PFILE_OBJECT _In_ PVOID Process
Definition: fsrtlfuncs.h:219
FORCEINLINE VOID MiIncrementPageTableReferences(IN PVOID Address)
Definition: miarm.h:1801
unsigned int ULONG
Definition: retypes.h:1
ULONG64 PageFrameNumber
Definition: mmtypes.h:171
NTSTATUS NTAPI MmCreateVirtualMapping(IN PEPROCESS Process, IN PVOID Address, IN ULONG Protection, IN PPFN_NUMBER Pages, IN ULONG PageCount)
Definition: page.c:158
#define PAGE_EXECUTE_READ
Definition: nt_native.h:1307
#define PAGE_EXECUTE_READWRITE
Definition: nt_native.h:1308
#define STATUS_SUCCESS
Definition: shellext.h:65
FORCEINLINE VOID MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte, IN PMMPTE MappingPte, IN ULONG_PTR ProtectionMask, IN PFN_NUMBER PageFrameNumber)
Definition: miarm.h:783
#define DPRINT
Definition: sndvol32.h:71
#define PFN_FROM_PTE(v)
Definition: mm.h:92
ULONG64 NoExecute
Definition: mmtypes.h:81
#define MmSystemRangeStart
Definition: mm.h:32
ULONG64 Accessed
Definition: mmtypes.h:163
VOID NTAPI KeBugCheckEx(_In_ ULONG BugCheckCode, _In_ ULONG_PTR BugCheckParameter1, _In_ ULONG_PTR BugCheckParameter2, _In_ ULONG_PTR BugCheckParameter3, _In_ ULONG_PTR BugCheckParameter4)
Definition: rtlcompat.c:108
#define PAGE_READWRITE
Definition: nt_native.h:1304