|
#define | ACPI_SIG_AGDI "AGDI" /* Arm Generic Diagnostic Dump and Reset Device Interface */ |
|
#define | ACPI_SIG_APMT "APMT" /* Arm Performance Monitoring Unit table */ |
|
#define | ACPI_SIG_BDAT "BDAT" /* BIOS Data ACPI Table */ |
|
#define | ACPI_SIG_CCEL "CCEL" /* CC Event Log Table */ |
|
#define | ACPI_SIG_CDAT "CDAT" /* Coherent Device Attribute Table */ |
|
#define | ACPI_SIG_IORT "IORT" /* IO Remapping Table */ |
|
#define | ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ |
|
#define | ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ |
|
#define | ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ |
|
#define | ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ |
|
#define | ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */ |
|
#define | ACPI_SIG_MPST "MPST" /* Memory Power State Table */ |
|
#define | ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ |
|
#define | ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */ |
|
#define | ACPI_SIG_NHLT "NHLT" /* Non HD Audio Link Table */ |
|
#define | ACPI_SIG_PCCT "PCCT" /* Platform Communications Channel Table */ |
|
#define | ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */ |
|
#define | ACPI_SIG_PHAT "PHAT" /* Platform Health Assessment Table */ |
|
#define | ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */ |
|
#define | ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */ |
|
#define | ACPI_SIG_PRMT "PRMT" /* Platform Runtime Mechanism Table */ |
|
#define | ACPI_SIG_RASF "RASF" /* RAS Feature table */ |
|
#define | ACPI_SIG_RGRT "RGRT" /* Regulatory Graphics Resource Table */ |
|
#define | ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ |
|
#define | ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ |
|
#define | ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ |
|
#define | ACPI_SIG_SVKL "SVKL" /* Storage Volume Key Location Table */ |
|
#define | ACPI_SIG_TDEL "TDEL" /* TD Event Log Table */ |
|
#define | ACPI_AEST_PROCESSOR_ERROR_NODE 0 |
|
#define | ACPI_AEST_MEMORY_ERROR_NODE 1 |
|
#define | ACPI_AEST_SMMU_ERROR_NODE 2 |
|
#define | ACPI_AEST_VENDOR_ERROR_NODE 3 |
|
#define | ACPI_AEST_GIC_ERROR_NODE 4 |
|
#define | ACPI_AEST_NODE_TYPE_RESERVED 5 /* 5 and above are reserved */ |
|
#define | ACPI_AEST_CACHE_RESOURCE 0 |
|
#define | ACPI_AEST_TLB_RESOURCE 1 |
|
#define | ACPI_AEST_GENERIC_RESOURCE 2 |
|
#define | ACPI_AEST_RESOURCE_RESERVED 3 /* 3 and above are reserved */ |
|
#define | ACPI_AEST_CACHE_DATA 0 |
|
#define | ACPI_AEST_CACHE_INSTRUCTION 1 |
|
#define | ACPI_AEST_CACHE_UNIFIED 2 |
|
#define | ACPI_AEST_CACHE_RESERVED 3 /* 3 and above are reserved */ |
|
#define | ACPI_AEST_GIC_CPU 0 |
|
#define | ACPI_AEST_GIC_DISTRIBUTOR 1 |
|
#define | ACPI_AEST_GIC_REDISTRIBUTOR 2 |
|
#define | ACPI_AEST_GIC_ITS 3 |
|
#define | ACPI_AEST_GIC_RESERVED 4 /* 4 and above are reserved */ |
|
#define | ACPI_AEST_NODE_SYSTEM_REGISTER 0 |
|
#define | ACPI_AEST_NODE_MEMORY_MAPPED 1 |
|
#define | ACPI_AEST_XFACE_RESERVED 2 /* 2 and above are reserved */ |
|
#define | ACPI_AEST_NODE_FAULT_HANDLING 0 |
|
#define | ACPI_AEST_NODE_ERROR_RECOVERY 1 |
|
#define | ACPI_AEST_XRUPT_RESERVED 2 /* 2 and above are reserved */ |
|
#define | ACPI_AGDI_SIGNALING_MODE (1) |
|
#define | ACPI_APMT_NODE_ID_LENGTH 4 |
|
#define | ACPI_APMT_FLAGS_DUAL_PAGE (1<<0) |
|
#define | ACPI_APMT_FLAGS_AFFINITY (1<<1) |
|
#define | ACPI_APMT_FLAGS_ATOMIC (1<<2) |
|
#define | ACPI_APMT_FLAGS_DUAL_PAGE_NSUPP (0<<0) |
|
#define | ACPI_APMT_FLAGS_DUAL_PAGE_SUPP (1<<0) |
|
#define | ACPI_APMT_FLAGS_AFFINITY_PROC (0<<1) |
|
#define | ACPI_APMT_FLAGS_AFFINITY_PROC_CONTAINER (1<<1) |
|
#define | ACPI_APMT_FLAGS_ATOMIC_NSUPP (0<<2) |
|
#define | ACPI_APMT_FLAGS_ATOMIC_SUPP (1<<2) |
|
#define | ACPI_APMT_OVFLW_IRQ_FLAGS_MODE (1<<0) |
|
#define | ACPI_APMT_OVFLW_IRQ_FLAGS_TYPE (1<<1) |
|
#define | ACPI_APMT_OVFLW_IRQ_FLAGS_MODE_LEVEL (0<<0) |
|
#define | ACPI_APMT_OVFLW_IRQ_FLAGS_MODE_EDGE (1<<0) |
|
#define | ACPI_APMT_OVFLW_IRQ_FLAGS_TYPE_WIRED (0<<1) |
|
#define | ACPI_IORT_ID_SINGLE_MAPPING (1) |
|
#define | ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */ |
|
#define | ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */ |
|
#define | ACPI_IORT_HT_TRANSIENT (1) |
|
#define | ACPI_IORT_HT_WRITE (1<<1) |
|
#define | ACPI_IORT_HT_READ (1<<2) |
|
#define | ACPI_IORT_HT_OVERRIDE (1<<3) |
|
#define | ACPI_IORT_MF_COHERENCY (1) |
|
#define | ACPI_IORT_MF_ATTRIBUTES (1<<1) |
|
#define | ACPI_IORT_NC_STALL_SUPPORTED (1) |
|
#define | ACPI_IORT_NC_PASID_BITS (31<<1) |
|
#define | ACPI_IORT_ATS_SUPPORTED (1) /* The root complex ATS support */ |
|
#define | ACPI_IORT_PRI_SUPPORTED (1<<1) /* The root complex PRI support */ |
|
#define | ACPI_IORT_PASID_FWD_SUPPORTED (1<<2) /* The root complex PASID forward support */ |
|
#define | ACPI_IORT_PASID_MAX_WIDTH (0x1F) /* Bits 0-4 */ |
|
#define | ACPI_IORT_SMMU_V1 0x00000000 /* Generic SMMUv1 */ |
|
#define | ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */ |
|
#define | ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */ |
|
#define | ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */ |
|
#define | ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */ |
|
#define | ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium ThunderX SMMUv2 */ |
|
#define | ACPI_IORT_SMMU_DVM_SUPPORTED (1) |
|
#define | ACPI_IORT_SMMU_COHERENT_WALK (1<<1) |
|
#define | ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */ |
|
#define | ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* HiSilicon Hi161x SMMUv3 */ |
|
#define | ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */ |
|
#define | ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) |
|
#define | ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1) |
|
#define | ACPI_IORT_SMMU_V3_PXM_VALID (1<<3) |
|
#define | ACPI_IORT_SMMU_V3_DEVICEID_VALID (1<<4) |
|
#define | ACPI_IORT_RMR_REMAP_PERMITTED (1) |
|
#define | ACPI_IORT_RMR_ACCESS_PRIVILEGE (1<<1) |
|
#define | ACPI_IORT_RMR_ACCESS_ATTRIBUTES(flags) (((flags) >> 2) & 0xFF) |
|
#define | ACPI_IORT_RMR_ATTR_DEVICE_NGNRNE 0x00 |
|
#define | ACPI_IORT_RMR_ATTR_DEVICE_NGNRE 0x01 |
|
#define | ACPI_IORT_RMR_ATTR_DEVICE_NGRE 0x02 |
|
#define | ACPI_IORT_RMR_ATTR_DEVICE_GRE 0x03 |
|
#define | ACPI_IORT_RMR_ATTR_NORMAL_NC 0x04 |
|
#define | ACPI_IORT_RMR_ATTR_NORMAL_IWB_OWB 0x05 |
|
#define | ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */ |
|
#define | ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */ |
|
#define | ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */ |
|
#define | ACPI_IVHD_TT_ENABLE (1) |
|
#define | ACPI_IVHD_PASS_PW (1<<1) |
|
#define | ACPI_IVHD_RES_PASS_PW (1<<2) |
|
#define | ACPI_IVHD_ISOC (1<<3) |
|
#define | ACPI_IVHD_IOTLB (1<<4) |
|
#define | ACPI_IVMD_UNITY (1) |
|
#define | ACPI_IVMD_READ (1<<1) |
|
#define | ACPI_IVMD_WRITE (1<<2) |
|
#define | ACPI_IVMD_EXCLUSION_RANGE (1<<3) |
|
#define | ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */ |
|
#define | ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, UnitID */ |
|
#define | ACPI_IVHD_ENTRY_LENGTH 0xC0 |
|
#define | ACPI_IVHD_INIT_PASS (1) |
|
#define | ACPI_IVHD_EINT_PASS (1<<1) |
|
#define | ACPI_IVHD_NMI_PASS (1<<2) |
|
#define | ACPI_IVHD_SYSTEM_MGMT (3<<4) |
|
#define | ACPI_IVHD_LINT0_PASS (1<<6) |
|
#define | ACPI_IVHD_LINT1_PASS (1<<7) |
|
#define | ACPI_IVHD_ATS_DISABLED (1<<31) |
|
#define | ACPI_IVHD_IOAPIC 1 |
|
#define | ACPI_IVHD_HPET 2 |
|
#define | ACPI_IVRS_UID_NOT_PRESENT 0 |
|
#define | ACPI_IVRS_UID_IS_INTEGER 1 |
|
#define | ACPI_IVRS_UID_IS_STRING 2 |
|
#define | ACPI_LPIT_STATE_DISABLED (1) |
|
#define | ACPI_LPIT_NO_COUNTER (1<<1) |
|
#define | ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */ |
|
#define | ACPI_MADT_DUAL_PIC 1 |
|
#define | ACPI_MADT_MULTIPLE_APIC 0 |
|
#define | ACPI_MADT_CPEI_OVERRIDE (1) |
|
#define | ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ |
|
#define | ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ |
|
#define | ACPI_MADT_OVERRIDE_SPI_VALUES (1) |
|
#define | ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032 |
|
#define | ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE 2048 |
|
#define | ACPI_MP_WAKE_COMMAND_WAKEUP 1 |
|
#define | ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */ |
|
#define | ACPI_MADT_ONLINE_CAPABLE (2) /* 01: System HW supports enabling processor at runtime */ |
|
#define | ACPI_MADT_POLARITY_MASK (3) /* 00-01: Polarity of APIC I/O input signals */ |
|
#define | ACPI_MADT_TRIGGER_MASK (3<<2) /* 02-03: Trigger mode of APIC input signals */ |
|
#define | ACPI_MADT_POLARITY_CONFORMS 0 |
|
#define | ACPI_MADT_POLARITY_ACTIVE_HIGH 1 |
|
#define | ACPI_MADT_POLARITY_RESERVED 2 |
|
#define | ACPI_MADT_POLARITY_ACTIVE_LOW 3 |
|
#define | ACPI_MADT_TRIGGER_CONFORMS (0) |
|
#define | ACPI_MADT_TRIGGER_EDGE (1<<2) |
|
#define | ACPI_MADT_TRIGGER_RESERVED (2<<2) |
|
#define | ACPI_MADT_TRIGGER_LEVEL (3<<2) |
|
#define | ACPI_MPST_CHANNEL_INFO |
|
#define | ACPI_MPST_ENABLED 1 |
|
#define | ACPI_MPST_POWER_MANAGED 2 |
|
#define | ACPI_MPST_HOT_PLUG_CAPABLE 4 |
|
#define | ACPI_MPST_PRESERVE 1 |
|
#define | ACPI_MPST_AUTOENTRY 2 |
|
#define | ACPI_MPST_AUTOEXIT 4 |
|
#define | ACPI_NFIT_ADD_ONLINE_ONLY (1) /* 00: Add/Online Operation Only */ |
|
#define | ACPI_NFIT_PROXIMITY_VALID (1<<1) /* 01: Proximity Domain Valid */ |
|
#define | ACPI_NFIT_LOCATION_COOKIE_VALID (1<<2) /* 02: SPA location cookie valid (ACPI 6.4) */ |
|
#define | ACPI_NFIT_MEM_SAVE_FAILED (1) /* 00: Last SAVE to Memory Device failed */ |
|
#define | ACPI_NFIT_MEM_RESTORE_FAILED (1<<1) /* 01: Last RESTORE from Memory Device failed */ |
|
#define | ACPI_NFIT_MEM_FLUSH_FAILED (1<<2) /* 02: Platform flush failed */ |
|
#define | ACPI_NFIT_MEM_NOT_ARMED (1<<3) /* 03: Memory Device is not armed */ |
|
#define | ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4) /* 04: Memory Device observed SMART/health events */ |
|
#define | ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5) /* 05: SMART/health events enabled */ |
|
#define | ACPI_NFIT_MEM_MAP_FAILED (1<<6) /* 06: Mapping to SPA failed */ |
|
#define | ACPI_NFIT_CONTROL_BUFFERED (1) /* Block Data Windows implementation is buffered */ |
|
#define | ACPI_NFIT_CONTROL_MFG_INFO_VALID (1) /* Manufacturing fields are valid */ |
|
#define | ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */ |
|
#define | ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */ |
|
#define | ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */ |
|
#define | ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F |
|
#define | ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0 |
|
#define | ACPI_NFIT_MEMORY_ID_MASK 0x00000F00 |
|
#define | ACPI_NFIT_SOCKET_ID_MASK 0x0000F000 |
|
#define | ACPI_NFIT_NODE_ID_MASK 0x0FFF0000 |
|
#define | ACPI_NFIT_DIMM_NUMBER_OFFSET 0 |
|
#define | ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4 |
|
#define | ACPI_NFIT_MEMORY_ID_OFFSET 8 |
|
#define | ACPI_NFIT_SOCKET_ID_OFFSET 12 |
|
#define | ACPI_NFIT_NODE_ID_OFFSET 16 |
|
#define | ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) |
|
#define | ACPI_NFIT_GET_DIMM_NUMBER(handle) ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK) |
|
#define | ACPI_NFIT_GET_CHANNEL_NUMBER(handle) (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET) |
|
#define | ACPI_NFIT_GET_MEMORY_ID(handle) (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET) |
|
#define | ACPI_NFIT_GET_SOCKET_ID(handle) (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET) |
|
#define | ACPI_NFIT_GET_NODE_ID(handle) (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET) |
|
#define | ACPI_NHLT_RESERVED_HD_AUDIO 0 |
|
#define | ACPI_NHLT_RESERVED_DSP 1 |
|
#define | ACPI_NHLT_PDM 2 |
|
#define | ACPI_NHLT_SSP 3 |
|
#define | ACPI_NHLT_RESERVED_SLIMBUS 4 |
|
#define | ACPI_NHLT_RESERVED_SOUNDWIRE 5 |
|
#define | ACPI_NHLT_TYPE_RESERVED 6 /* 6 and above are reserved */ |
|
#define | ACPI_NHLT_PDM_DMIC 0xAE20 |
|
#define | ACPI_NHLT_BT_SIDEBAND 0xAE30 |
|
#define | ACPI_NHLT_I2S_TDM_CODECS 0xAE23 |
|
#define | ACPI_NHLT_LINK_BT_SIDEBAND 0 |
|
#define | ACPI_NHLT_LINK_FM 1 |
|
#define | ACPI_NHLT_LINK_MODEM 2 |
|
#define | ACPI_NHLT_LINK_SSP_ANALOG_CODEC 4 |
|
#define | ACPI_NHLT_PDM_ON_CAVS_1P8 0 |
|
#define | ACPI_NHLT_PDM_ON_CAVS_1P5 1 |
|
#define | ACPI_NHLT_DIR_RENDER 0 |
|
#define | ACPI_NHLT_DIR_CAPTURE 1 |
|
#define | ACPI_NHLT_DIR_RENDER_LOOPBACK 2 |
|
#define | ACPI_NHLT_DIR_RENDER_FEEDBACK 3 |
|
#define | ACPI_NHLT_DIR_RESERVED 4 /* 4 and above are reserved */ |
|
#define | ACPI_NHLT_CONFIG_TYPE_GENERIC 0x00 |
|
#define | ACPI_NHLT_CONFIG_TYPE_MIC_ARRAY 0x01 |
|
#define | ACPI_NHLT_CONFIG_TYPE_RENDER_FEEDBACK 0x03 |
|
#define | ACPI_NHLT_CONFIG_TYPE_RESERVED 0x04 /* 4 and above are reserved */ |
|
#define | ACPI_NHLT_SPKR_FRONT_LEFT 0x1 |
|
#define | ACPI_NHLT_SPKR_FRONT_RIGHT 0x2 |
|
#define | ACPI_NHLT_SPKR_FRONT_CENTER 0x4 |
|
#define | ACPI_NHLT_SPKR_LOW_FREQ 0x8 |
|
#define | ACPI_NHLT_SPKR_BACK_LEFT 0x10 |
|
#define | ACPI_NHLT_SPKR_BACK_RIGHT 0x20 |
|
#define | ACPI_NHLT_SPKR_FRONT_LEFT_OF_CENTER 0x40 |
|
#define | ACPI_NHLT_SPKR_FRONT_RIGHT_OF_CENTER 0x80 |
|
#define | ACPI_NHLT_SPKR_BACK_CENTER 0x100 |
|
#define | ACPI_NHLT_SPKR_SIDE_LEFT 0x200 |
|
#define | ACPI_NHLT_SPKR_SIDE_RIGHT 0x400 |
|
#define | ACPI_NHLT_SPKR_TOP_CENTER 0x800 |
|
#define | ACPI_NHLT_SPKR_TOP_FRONT_LEFT 0x1000 |
|
#define | ACPI_NHLT_SPKR_TOP_FRONT_CENTER 0x2000 |
|
#define | ACPI_NHLT_SPKR_TOP_FRONT_RIGHT 0x4000 |
|
#define | ACPI_NHLT_SPKR_TOP_BACK_LEFT 0x8000 |
|
#define | ACPI_NHLT_SPKR_TOP_BACK_CENTER 0x10000 |
|
#define | ACPI_NHLT_SPKR_TOP_BACK_RIGHT 0x20000 |
|
#define | ACPI_NHLT_GENERIC 0 |
|
#define | ACPI_NHLT_MIC 1 |
|
#define | ACPI_NHLT_RENDER 3 |
|
#define | ACPI_NHLT_ARRAY_TYPE_RESERVED 0x09 /* 9 and below are reserved */ |
|
#define | ACPI_NHLT_SMALL_LINEAR_2ELEMENT 0x0A |
|
#define | ACPI_NHLT_BIG_LINEAR_2ELEMENT 0x0B |
|
#define | ACPI_NHLT_FIRST_GEOMETRY_LINEAR_4ELEMENT 0x0C |
|
#define | ACPI_NHLT_PLANAR_LSHAPED_4ELEMENT 0x0D |
|
#define | ACPI_NHLT_SECOND_GEOMETRY_LINEAR_4ELEMENT 0x0E |
|
#define | ACPI_NHLT_VENDOR_DEFINED 0x0F |
|
#define | ACPI_NHLT_ARRAY_TYPE_MASK 0x0F |
|
#define | ACPI_NHLT_ARRAY_TYPE_EXT_MASK 0x10 |
|
#define | ACPI_NHLT_NO_EXTENSION 0x0 |
|
#define | ACPI_NHLT_MIC_SNR_SENSITIVITY_EXT (1<<4) |
|
#define | ACPI_NHLT_MIC_OMNIDIRECTIONAL 0 |
|
#define | ACPI_NHLT_MIC_SUBCARDIOID 1 |
|
#define | ACPI_NHLT_MIC_CARDIOID 2 |
|
#define | ACPI_NHLT_MIC_SUPER_CARDIOID 3 |
|
#define | ACPI_NHLT_MIC_HYPER_CARDIOID 4 |
|
#define | ACPI_NHLT_MIC_8_SHAPED 5 |
|
#define | ACPI_NHLT_MIC_RESERVED6 6 /* 6 is reserved */ |
|
#define | ACPI_NHLT_MIC_VENDOR_DEFINED 7 |
|
#define | ACPI_NHLT_MIC_RESERVED 8 /* 8 and above are reserved */ |
|
#define | ACPI_NHLT_MIC_POSITION_TOP 0 |
|
#define | ACPI_NHLT_MIC_POSITION_BOTTOM 1 |
|
#define | ACPI_NHLT_MIC_POSITION_LEFT 2 |
|
#define | ACPI_NHLT_MIC_POSITION_RIGHT 3 |
|
#define | ACPI_NHLT_MIC_POSITION_FRONT 4 |
|
#define | ACPI_NHLT_MIC_POSITION_BACK 5 |
|
#define | ACPI_NHLT_MIC_POSITION_RESERVED 6 /* 6 and above are reserved */ |
|
#define | ACPI_PCCT_DOORBELL 1 |
|
#define | ACPI_PCCT_INTERRUPT_POLARITY (1) |
|
#define | ACPI_PCCT_INTERRUPT_MODE (1<<1) |
|
#define | ACPI_PDTT_RUNTIME_TRIGGER (1) |
|
#define | ACPI_PDTT_WAIT_COMPLETION (1<<1) |
|
#define | ACPI_PDTT_TRIGGER_ORDER (1<<2) |
|
#define | ACPI_PHAT_TYPE_FW_VERSION_DATA 0 |
|
#define | ACPI_PHAT_TYPE_FW_HEALTH_DATA 1 |
|
#define | ACPI_PHAT_TYPE_RESERVED 2 /* 0x02-0xFFFF are reserved */ |
|
#define | ACPI_PHAT_ERRORS_FOUND 0 |
|
#define | ACPI_PHAT_NO_ERRORS 1 |
|
#define | ACPI_PHAT_UNKNOWN_ERRORS 2 |
|
#define | ACPI_PHAT_ADVISORY 3 |
|
#define | ACPI_PMTT_TYPE_SOCKET 0 |
|
#define | ACPI_PMTT_TYPE_CONTROLLER 1 |
|
#define | ACPI_PMTT_TYPE_DIMM 2 |
|
#define | ACPI_PMTT_TYPE_RESERVED 3 /* 0x03-0xFE are reserved */ |
|
#define | ACPI_PMTT_TYPE_VENDOR 0xFF |
|
#define | ACPI_PMTT_TOP_LEVEL 0x0001 |
|
#define | ACPI_PMTT_PHYSICAL 0x0002 |
|
#define | ACPI_PMTT_MEMORY_TYPE 0x000C |
|
#define | ACPI_PPTT_PHYSICAL_PACKAGE (1) |
|
#define | ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1) |
|
#define | ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2) /* ACPI 6.3 */ |
|
#define | ACPI_PPTT_ACPI_LEAF_NODE (1<<3) /* ACPI 6.3 */ |
|
#define | ACPI_PPTT_ACPI_IDENTICAL (1<<4) /* ACPI 6.3 */ |
|
#define | ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */ |
|
#define | ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */ |
|
#define | ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */ |
|
#define | ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */ |
|
#define | ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */ |
|
#define | ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */ |
|
#define | ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */ |
|
#define | ACPI_PPTT_CACHE_ID_VALID (1<<7) /* Cache ID valid */ |
|
#define | ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */ |
|
#define | ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */ |
|
#define | ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */ |
|
#define | ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */ |
|
#define | ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */ |
|
#define | ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */ |
|
#define | ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */ |
|
#define | ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */ |
|
#define | ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */ |
|
#define | ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */ |
|
#define | ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */ |
|
#define | ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */ |
|
#define | ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */ |
|
#define | ACPI_RASF_SCRUBBER_RUNNING 1 |
|
#define | ACPI_RASF_SPEED (7<<1) |
|
#define | ACPI_RASF_SPEED_SLOW (0<<1) |
|
#define | ACPI_RASF_SPEED_MEDIUM (4<<1) |
|
#define | ACPI_RASF_SPEED_FAST (7<<1) |
|
#define | ACPI_RASF_GENERATE_SCI (1<<15) |
|
#define | ACPI_RASF_COMMAND_COMPLETE (1) |
|
#define | ACPI_RASF_SCI_DOORBELL (1<<1) |
|
#define | ACPI_RASF_ERROR (1<<2) |
|
#define | ACPI_RASF_STATUS (0x1F<<3) |
|
#define | ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1) |
|
#define | ACPI_SDEV_SECURE_COMPONENTS_PRESENT (1<<1) |
|