cacheinfo.c File Reference

#include <ntoskrnl.h>
#include <x86x64/Cpuid.h>
#include <debug.h>

Include dependency graph for cacheinfo.c:

Go to the source code of this file.

Classes
struct	INTEL_CACHE_DESCRIPTOR

Macros
#define	NDEBUG

Functions
	C_ASSERT (sizeof(INTEL_CACHE_DESCRIPTOR)==6)
static const INTEL_CACHE_DESCRIPTOR *	FindIntelCacheDescriptor (_In_ UCHAR DescriptorCode)
	Finds the cache descriptor for the given descriptor value.
static ULONG	GetCacheInfoIntelLeaf2 (_Out_cap_(MaxCount) PCACHE_DESCRIPTOR CacheDescriptors, _In_ ULONG MaxCount)
	Retrieves cache information using CPUID leaf 2 for Intel processors.
static ULONG	GetCacheInfoAmdLegacy (_Out_cap_(MaxCount) PCACHE_DESCRIPTOR CacheDescriptors, _In_ ULONG MaxCount)
	Retrieves cache information for legacy AMD processors.
static ULONG	KiGetCacheInfoModern (_Out_cap_(MaxCount) PCACHE_DESCRIPTOR CacheDescriptors, _In_ ULONG MaxCount, _In_ ULONG CpuIdLeaf)
	Retrieves cache information for modern Intel/AMD processors.
static ULONG	NormalizeCacheDescriptors (_Inout_updates_(MaxCount) PCACHE_DESCRIPTOR CacheDescriptors, _In_ ULONG CacheCount, _In_ ULONG MaxCount)
	Normalizes the cache descriptors by removing duplicates and sorting them.
ULONG NTAPI	KiGetCpuCacheDescriptors (_Out_writes_(MaxCount) PCACHE_DESCRIPTOR CacheDescriptors, _In_ ULONG MaxCount, _In_ CPU_VENDORS Vendor)
	Retrieves cache descriptors for the current CPU.

Variables
static const INTEL_CACHE_DESCRIPTOR	IntelCacheDescriptors []
	Table of known Intel cache descriptors, as defined in the Intel SDM.

Macro Definition Documentation

NDEBUG

#define NDEBUG

Definition at line 12 of file cacheinfo.c.

Function Documentation

C_ASSERT()

C_ASSERT

(

sizeof(INTEL_CACHE_DESCRIPTOR)

= =6

)

FindIntelCacheDescriptor()

static const INTEL_CACHE_DESCRIPTOR * FindIntelCacheDescriptor ( _In_ UCHAR  DescriptorCode )

static

Finds the cache descriptor for the given descriptor value.

Parameters

[in]

DescriptorCode

- The cache descriptor code to find

Returns

A pointer to the INTEL_CACHE_DESCRIPTOR structure if found, or NULL if not found.

Definition at line 168 of file cacheinfo.c.

{
    ULONG Low = 0;
    ULONG High = RTL_NUMBER_OF(IntelCacheDescriptors);
 
    while (Low < High)
    {
        ULONG Mid = Low + (High - Low) / 2;
        const INTEL_CACHE_DESCRIPTOR* CacheDesc = &IntelCacheDescriptors[Mid];
        if (DescriptorCode < CacheDesc->Code)
        {
            High = Mid;
        }
        else if (DescriptorCode > CacheDesc->Code)
        {
            Low = Mid + 1;
        }
        else
        {
            return CacheDesc;
        }
    }
 
    return NULL;
}

Referenced by GetCacheInfoIntelLeaf2().

GetCacheInfoAmdLegacy()

static ULONG GetCacheInfoAmdLegacy ( _Out_cap_(MaxCount) PCACHE_DESCRIPTOR  CacheDescriptors, _In_ ULONG  MaxCount  )

static

Retrieves cache information for legacy AMD processors.

Parameters

[out]	CacheDescriptors	- An array to receive cache descriptors
[in]	MaxCount	- The maximum number of cache descriptors to fill

Returns

The number of cache descriptors filled

See also

• https://docs.amd.com/v/u/en-US/24594_3.38_APM_Vol3 (E.4.4 Function 8000_0005h—L1 Cache and TLB Information and E.4.5 Function 8000_0006h—L2 Cache and TLB and L3 Cache Information)
• https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/56255_OSRR.pdf

Definition at line 281 of file cacheinfo.c.

{
    CPUID_L1_TLB_INFO_REGS L1TlbInfo;
    CPUID_AMD_EXTENDED_CACHE_INFO_REGS CacheInfoRegs;
    ULONG Count = 0;
    static const UCHAR AssocMap[16] =
    {
        0, 1, 2, 0, 4, 0, 8, 0, 16, 0, 32, 48, 64, 96, 128, 0xFF
    };
 
    __cpuid(L1TlbInfo.AsInt32, CPUID_L1_TLB_INFO);
 
    /* L1 data cache */
    if ((L1TlbInfo.Amd.Ecx.Bits.L1DcSize != 0) && (Count < MaxCount))
    {
        CacheDescriptors[Count].Level = 1;
        CacheDescriptors[Count].Type = CacheData;
        CacheDescriptors[Count].Size = L1TlbInfo.Amd.Ecx.Bits.L1DcSize * 1024;
        CacheDescriptors[Count].Associativity = L1TlbInfo.Amd.Ecx.Bits.L1DcAssoc;
        CacheDescriptors[Count].LineSize = L1TlbInfo.Amd.Ecx.Bits.L1DcLineSize;
        Count++;
    }
 
    /* L1 instruction cache */
    if ((L1TlbInfo.Amd.Edx.Bits.L1IcSize != 0) && (Count < MaxCount))
    {
        CacheDescriptors[Count].Level = 1;
        CacheDescriptors[Count].Type = CacheInstruction;
        CacheDescriptors[Count].Size = L1TlbInfo.Amd.Edx.Bits.L1IcSize * 1024;
        CacheDescriptors[Count].Associativity = L1TlbInfo.Amd.Edx.Bits.L1IcAssoc;
        CacheDescriptors[Count].LineSize = L1TlbInfo.Amd.Edx.Bits.L1IcLineSize;
        Count++;
    }
 
    __cpuid(CacheInfoRegs.AsInt32, CPUID_EXTENDED_CACHE_INFO);
 
    /* L2 unified cache (Assoc 9 means look at leaf 0x8000001D) */
    if ((CacheInfoRegs.Ecx.Bits.L2Size != 0) && (CacheInfoRegs.Ecx.Bits.L2Assoc != 9) && (Count < MaxCount))
    {
        CacheDescriptors[Count].Level = 2;
        CacheDescriptors[Count].Type = CacheUnified;
        CacheDescriptors[Count].Size = CacheInfoRegs.Ecx.Bits.L2Size * 1024;
        CacheDescriptors[Count].Associativity = AssocMap[CacheInfoRegs.Ecx.Bits.L2Assoc];
        CacheDescriptors[Count].LineSize = CacheInfoRegs.Ecx.Bits.L2LineSize;
        Count++;
    }
 
    /* L3 unified cache (Assoc 9 means look at leaf 0x8000001D) */
    if ((CacheInfoRegs.Edx.Bits.L3Size != 0) && (CacheInfoRegs.Edx.Bits.L3Assoc != 9) && (Count < MaxCount))
    {
        CacheDescriptors[Count].Level = 3;
        CacheDescriptors[Count].Type = CacheUnified;
        CacheDescriptors[Count].Size = CacheInfoRegs.Edx.Bits.L3Size * 512 * 1024;
        CacheDescriptors[Count].Associativity = AssocMap[CacheInfoRegs.Edx.Bits.L3Assoc];
        CacheDescriptors[Count].LineSize = CacheInfoRegs.Edx.Bits.L3LineSize;
        Count++;
    }
 
    return Count;
}

Referenced by KiGetCpuCacheDescriptors().

GetCacheInfoIntelLeaf2()

static ULONG GetCacheInfoIntelLeaf2 ( _Out_cap_(MaxCount) PCACHE_DESCRIPTOR  CacheDescriptors, _In_ ULONG  MaxCount  )

static

Retrieves cache information using CPUID leaf 2 for Intel processors.

Parameters

[out]	CacheDescriptors	- An array to receive the cache descriptors
[in]	MaxCount	- The maximum number of cache descriptors to fill

Returns

The number of cache descriptors retrieved.

\See "Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture"

• "Table 21-12. Encoding of CPUID Leaf 2 Descriptors"

Definition at line 207 of file cacheinfo.c.

{
    CPUID_CACHE_INFO_REGS CacheInfoRegs;
    ULONG Passes, Pass, Reg, Byte;
    ULONG Count = 0;
 
    /* Query the cache info. The number of passes is stored in EAX[7..0] */
    __cpuid(CacheInfoRegs.AsInt32, CPUID_CACHE_INFO);
    Passes = CacheInfoRegs.Eax.CacheDescriptor[0];
 
    /* Now loop through each pass. Every CPUID call gives the next chunk
       of information. After n passes we have all info. The order is not
       deterministic. */
    for (Pass = 0; Pass < Passes; Pass++)
    {
        /* Query the information for the next pass */
        __cpuid(CacheInfoRegs.AsInt32, CPUID_CACHE_INFO);
 
        /* Loop through each register in the cache info */
        for (Reg = 0; Reg < ARRAYSIZE(CacheInfoRegs.Regs); Reg++)
        {
            const CPUID_CACHE_INFO_CACHE_TLB *CpuidReg = &CacheInfoRegs.Regs[Reg];
 
            if (CpuidReg->Bits.NotValid)
                continue;
 
            /* Loop through each byte in the register. For EAX we need to skip the first. */
            for (Byte = (Reg == 0) ? 1 : 0; Byte < 4; Byte++)
            {
                const INTEL_CACHE_DESCRIPTOR* IntelCacheDesc;
                UCHAR DescriptorCode = CpuidReg->CacheDescriptor[Byte];
                if (DescriptorCode == 0)
                    continue;
 
                IntelCacheDesc = FindIntelCacheDescriptor(DescriptorCode);
                if (IntelCacheDesc != NULL)
                {
                    /* Make sure there is enough space in the array */
                    if (Count >= MaxCount)
                    {
                        return Count;
                    }
 
                    CacheDescriptors[Count].Level = IntelCacheDesc->Level;
                    CacheDescriptors[Count].Associativity = IntelCacheDesc->Associativity;
                    CacheDescriptors[Count].LineSize = IntelCacheDesc->LineSize;
                    CacheDescriptors[Count].Size = IntelCacheDesc->SizeinKB * 1024;
                    CacheDescriptors[Count].Type = IntelCacheDesc->Type;
                    Count++;
                }
            }
        }
    }
 
    return Count;
}

Referenced by KiGetCpuCacheDescriptors().

KiGetCacheInfoModern()

static ULONG KiGetCacheInfoModern ( _Out_cap_(MaxCount) PCACHE_DESCRIPTOR  CacheDescriptors, _In_ ULONG  MaxCount, _In_ ULONG  CpuIdLeaf  )

static

Retrieves cache information for modern Intel/AMD processors.

Parameters

[out]	CacheDescriptors	- An array to receive cache descriptors
[in]	MaxCount	- The maximum number of cache descriptors to fill
[in]	CpuIdLeaf	- The CPUID leaf to use (0x04 for Intel, 0x8000001D for AMD)

Returns

The number of cache descriptors filled

Definition at line 355 of file cacheinfo.c.

{
    CPUID_CACHE_PARAMS_REGS Regs;
    ULONG Subleaf;
    ULONG Count;
 
    Count = 0;
 
    /* Iterate through subleaves, bail out at 32 or when all descriptors are filled */
    for (Subleaf = 0; (Subleaf < 32) && (Count < MaxCount); Subleaf++)
    {
        __cpuidex(Regs.AsInt32, CpuIdLeaf, Subleaf);
 
        switch (Regs.Eax.Bits.CacheType)
        {
            case CPUID_CACHE_PARAMS_CACHE_TYPE_DATA:
                CacheDescriptors[Count].Type = CacheData;
                break;
 
            case CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION:
                CacheDescriptors[Count].Type = CacheInstruction;
                break;
 
            case CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED:
                CacheDescriptors[Count].Type = CacheUnified;
                break;
 
            case CPUID_CACHE_PARAMS_CACHE_TYPE_NULL:
                return Count;
 
            default:
                continue;
        }
 
        if (Regs.Eax.Bits.FullyAssociativeCache)
        {
            CacheDescriptors[Count].Associativity = 0xFF;
        }
        else
        {
            ULONG Ways = Regs.Ebx.Bits.Ways + 1;
            CacheDescriptors[Count].Associativity = (Ways > 0xFE) ? 0xFE : (UCHAR)Ways;
        }
 
        CacheDescriptors[Count].Level = (UCHAR)Regs.Eax.Bits.CacheLevel;
        CacheDescriptors[Count].LineSize = (USHORT)(Regs.Ebx.Bits.LineSize + 1);
        CacheDescriptors[Count].Size = (Regs.Ebx.Bits.Ways + 1) *
                                       (Regs.Ebx.Bits.LinePartitions + 1) *
                                       (Regs.Ebx.Bits.LineSize + 1) *
                                       (Regs.NumberOfSets + 1);
        Count++;
    }
 
    return Count;
}

Referenced by KiGetCpuCacheDescriptors().

KiGetCpuCacheDescriptors()

ULONG NTAPI KiGetCpuCacheDescriptors	(	_Out_writes_(MaxCount) PCACHE_DESCRIPTOR	CacheDescriptors,
		_In_ ULONG	MaxCount,
		_In_ CPU_VENDORS	Vendor
	)

Retrieves cache descriptors for the current CPU.

Parameters

[out]	CacheDescriptors	- An array to receive the cache descriptors
[in]	MaxCount	- The maximum number of cache descriptors to fill
[in]	Vendor	- The CPU vendor

Returns

The number of cache descriptors retrieved

Definition at line 484 of file cacheinfo.c.

{
    CPUID_SIGNATURE_REGS Signature;
    CPUID_EXTENDED_FUNCTION_REGS ExtendedFunction;
    ULONG Count = 0;
 
    /* Get the maximum leaf and maximum extended leaf */
    __cpuid(Signature.AsInt32, CPUID_SIGNATURE);
    __cpuid(ExtendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION);
 
    /* Distinguish by vendor: AMD (and Hygon) have their own custom cpuid leaves. */
    if (Vendor == CPU_AMD)
    {
        if (ExtendedFunction.MaxLeaf >= CPUID_CACHE_PARAMS_AMD)
        {
            Count = KiGetCacheInfoModern(CacheDescriptors, MaxCount, CPUID_CACHE_PARAMS_AMD);
        }
 
        if ((Count == 0) && (ExtendedFunction.MaxLeaf >= CPUID_EXTENDED_CACHE_INFO))
        {
            Count = GetCacheInfoAmdLegacy(CacheDescriptors, MaxCount);
        }
    }
    else
    {
        if (Signature.MaxLeaf >= CPUID_CACHE_PARAMS)
        {
            Count = KiGetCacheInfoModern(CacheDescriptors, MaxCount, CPUID_CACHE_PARAMS);
        }
 
        if ((Count == 0) && (Signature.MaxLeaf >= CPUID_CACHE_INFO))
        {
            Count = GetCacheInfoIntelLeaf2(CacheDescriptors, MaxCount);
        }
    }
 
    /* Normalize the descriptors */
    Count = NormalizeCacheDescriptors(CacheDescriptors, Count, MaxCount);
 
    return Count;
}

Referenced by KiGetCacheInformation().

NormalizeCacheDescriptors()

static ULONG NormalizeCacheDescriptors ( _Inout_updates_(MaxCount) PCACHE_DESCRIPTOR  CacheDescriptors, _In_ ULONG  CacheCount, _In_ ULONG  MaxCount  )

static

Normalizes the cache descriptors by removing duplicates and sorting them.

Parameters

[in,out]	CacheDescriptors	- An array of cache descriptors
[in]	CacheCount	- The number of cache descriptors
[in]	MaxCount	- The maximum number of cache descriptors to fill

Returns

The number of valid cache descriptors after normalization

Definition at line 425 of file cacheinfo.c.

{
    ULONG l, r, i;
    ULONG NewCount = 0;
 
    /* Sort the array */
    for (l = 0; l < CacheCount; l++)
    {
        for (r = l + 1; r < CacheCount; r++)
        {
            /* Sort order: 1. Level (ascending), 2. Type (enum value, descending) */
            if ((CacheDescriptors[l].Level > CacheDescriptors[r].Level) ||
                ((CacheDescriptors[l].Level == CacheDescriptors[r].Level) &&
                 (CacheDescriptors[l].Type < CacheDescriptors[r].Type)))
            {
                CACHE_DESCRIPTOR Temp = CacheDescriptors[l];
                CacheDescriptors[l] = CacheDescriptors[r];
                CacheDescriptors[r] = Temp;
            }
        }
    }
 
    /* Remove duplicates */
    if (CacheCount > 0)
    {
        CacheDescriptors[0] = CacheDescriptors[0];
        NewCount = 1;
        for (i = 1; i < CacheCount; i++)
        {
            if ((CacheDescriptors[i].Level != CacheDescriptors[i - 1].Level) ||
                (CacheDescriptors[i].Type != CacheDescriptors[i - 1].Type))
            {
                CacheDescriptors[NewCount] = CacheDescriptors[i];
                NewCount++;
            }
        }
    }
 
    /* Clear stray entries */
    RtlZeroMemory(&CacheDescriptors[NewCount],
                  sizeof(CACHE_DESCRIPTOR) * (MaxCount - NewCount));
 
    return NewCount;
}

Referenced by KiGetCpuCacheDescriptors().

Variable Documentation

IntelCacheDescriptors

const INTEL_CACHE_DESCRIPTOR IntelCacheDescriptors[]

static

Table of known Intel cache descriptors, as defined in the Intel SDM.

Only data, instruction and unified caches are listed, TLBs and trace caches are ignored.

See also

"Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture" - "Table 21-12. Encoding of CPUID Leaf 2 Descriptors"

Note

For code 0x49 the L3 cache interpretation is used, which matches what Linux does:

• https://github.com/torvalds/linux/blob/06cf61899d6498b33e4b7c87d99d5bd471ccc375/arch/x86/kernel/cpu/cpuid_0x2_table.c#L21

Definition at line 39 of file cacheinfo.c.

Referenced by FindIntelCacheDescriptor().