ReactOS 0.4.15-dev-5875-g7c755d9
ioapic.h File Reference
#include <pshpack1.h>
#include <poppack.h>
Include dependency graph for ioapic.h:

Go to the source code of this file.

Classes

struct  _IOAPIC_ROUTE_ENTRY
 
struct  _IOAPIC_INFO
 

Macros

#define IOAPIC_IOREGSEL   0x0000 /* I/O Register Select (index) (R/W) */
 
#define IOAPIC_IOWIN   0x0010 /* I/O window (data) (R/W) */
 
#define IOAPIC_ID   0x0000 /* IO APIC ID (R/W) */
 
#define IOAPIC_VER   0x0001 /* IO APIC Version (R) */
 
#define IOAPIC_ARB   0x0002 /* IO APIC Arbitration ID (R) */
 
#define IOAPIC_REDTBL   0x0010 /* Redirection Table (0-23 64-bit registers) (R/W) */
 
#define IOAPIC_ID_MASK   (0xF << 24)
 
#define GET_IOAPIC_ID(x)   ((UCHAR)(((x) & IOAPIC_ID_MASK) >> 24))
 
#define SET_IOAPIC_ID(x)   ((x) << 24)
 
#define IOAPIC_VER_MASK   (0xFF)
 
#define GET_IOAPIC_VERSION(x)   (((x) & IOAPIC_VER_MASK))
 
#define IOAPIC_MRE_MASK   (0xFF << 16) /* Maximum Redirection Entry */
 
#define GET_IOAPIC_MRE(x)   (((x) & IOAPIC_MRE_MASK) >> 16)
 
#define IOAPIC_ARB_MASK   (0xF << 24)
 
#define GET_IOAPIC_ARB(x)   (((x) & IOAPIC_ARB_MASK) >> 24)
 
#define IOAPIC_TBL_DELMOD   (0x7 << 10) /* Delivery Mode (see APIC_DM_*) */
 
#define IOAPIC_TBL_DM   (0x1 << 11) /* Destination Mode */
 
#define IOAPIC_TBL_DS   (0x1 << 12) /* Delivery Status */
 
#define IOAPIC_TBL_INTPOL   (0x1 << 13) /* Interrupt Input Pin Polarity */
 
#define IOAPIC_TBL_RIRR   (0x1 << 14) /* Remote IRR */
 
#define IOAPIC_TBL_TM   (0x1 << 15) /* Trigger Mode */
 
#define IOAPIC_TBL_IM   (0x1 << 16) /* Interrupt Mask */
 
#define IOAPIC_TBL_DF0   (0xF << 56) /* Destination Field (physical mode) */
 
#define IOAPIC_TBL_DF1   (0xFF<< 56) /* Destination Field (logical mode) */
 
#define IOAPIC_TBL_VECTOR   (0xFF << 0) /* Vector (10h - FEh) */
 
#define IOAPIC_DEFAULT_BASE   0xFEC00000 /* Default I/O APIC Base Register Address */
 

Typedefs

typedef struct _IOAPIC_ROUTE_ENTRY IOAPIC_ROUTE_ENTRY
 
typedef struct _IOAPIC_ROUTE_ENTRYPIOAPIC_ROUTE_ENTRY
 
typedef struct _IOAPIC_INFO IOAPIC_INFO
 
typedef struct _IOAPIC_INFOPIOAPIC_INFO
 

Functions

VOID IOAPICSetupIrqs (VOID)
 
VOID IOAPICEnable (VOID)
 
VOID IOAPICSetupIds (VOID)
 
VOID IOAPICMaskIrq (ULONG Irq)
 
VOID IOAPICUnmaskIrq (ULONG Irq)
 
VOID HaliReconfigurePciInterrupts (VOID)
 
VOID IOAPICDump (VOID)
 

Variables

ULONG IRQCount
 
UCHAR BUSMap [MAX_BUS]
 
UCHAR PCIBUSMap [MAX_BUS]
 
IOAPIC_INFO IOAPICMap [MAX_IOAPIC]
 
ULONG IOAPICCount
 
ULONG APICMode
 
MP_CONFIGURATION_INTSRC IRQMap [MAX_IRQ_SOURCE]
 

Macro Definition Documentation

◆ GET_IOAPIC_ARB

#define GET_IOAPIC_ARB (   x)    (((x) & IOAPIC_ARB_MASK) >> 24)

Definition at line 26 of file ioapic.h.

◆ GET_IOAPIC_ID

#define GET_IOAPIC_ID (   x)    ((UCHAR)(((x) & IOAPIC_ID_MASK) >> 24))

Definition at line 17 of file ioapic.h.

◆ GET_IOAPIC_MRE

#define GET_IOAPIC_MRE (   x)    (((x) & IOAPIC_MRE_MASK) >> 16)

Definition at line 23 of file ioapic.h.

◆ GET_IOAPIC_VERSION

#define GET_IOAPIC_VERSION (   x)    (((x) & IOAPIC_VER_MASK))

Definition at line 21 of file ioapic.h.

◆ IOAPIC_ARB

#define IOAPIC_ARB   0x0002 /* IO APIC Arbitration ID (R) */

Definition at line 13 of file ioapic.h.

◆ IOAPIC_ARB_MASK

#define IOAPIC_ARB_MASK   (0xF << 24)

Definition at line 25 of file ioapic.h.

◆ IOAPIC_DEFAULT_BASE

#define IOAPIC_DEFAULT_BASE   0xFEC00000 /* Default I/O APIC Base Register Address */

Definition at line 76 of file ioapic.h.

◆ IOAPIC_ID

#define IOAPIC_ID   0x0000 /* IO APIC ID (R/W) */

Definition at line 11 of file ioapic.h.

◆ IOAPIC_ID_MASK

#define IOAPIC_ID_MASK   (0xF << 24)

Definition at line 16 of file ioapic.h.

◆ IOAPIC_IOREGSEL

#define IOAPIC_IOREGSEL   0x0000 /* I/O Register Select (index) (R/W) */

Definition at line 8 of file ioapic.h.

◆ IOAPIC_IOWIN

#define IOAPIC_IOWIN   0x0010 /* I/O window (data) (R/W) */

Definition at line 9 of file ioapic.h.

◆ IOAPIC_MRE_MASK

#define IOAPIC_MRE_MASK   (0xFF << 16) /* Maximum Redirection Entry */

Definition at line 22 of file ioapic.h.

◆ IOAPIC_REDTBL

#define IOAPIC_REDTBL   0x0010 /* Redirection Table (0-23 64-bit registers) (R/W) */

Definition at line 14 of file ioapic.h.

◆ IOAPIC_TBL_DELMOD

#define IOAPIC_TBL_DELMOD   (0x7 << 10) /* Delivery Mode (see APIC_DM_*) */

Definition at line 28 of file ioapic.h.

◆ IOAPIC_TBL_DF0

#define IOAPIC_TBL_DF0   (0xF << 56) /* Destination Field (physical mode) */

Definition at line 35 of file ioapic.h.

◆ IOAPIC_TBL_DF1

#define IOAPIC_TBL_DF1   (0xFF<< 56) /* Destination Field (logical mode) */

Definition at line 36 of file ioapic.h.

◆ IOAPIC_TBL_DM

#define IOAPIC_TBL_DM   (0x1 << 11) /* Destination Mode */

Definition at line 29 of file ioapic.h.

◆ IOAPIC_TBL_DS

#define IOAPIC_TBL_DS   (0x1 << 12) /* Delivery Status */

Definition at line 30 of file ioapic.h.

◆ IOAPIC_TBL_IM

#define IOAPIC_TBL_IM   (0x1 << 16) /* Interrupt Mask */

Definition at line 34 of file ioapic.h.

◆ IOAPIC_TBL_INTPOL

#define IOAPIC_TBL_INTPOL   (0x1 << 13) /* Interrupt Input Pin Polarity */

Definition at line 31 of file ioapic.h.

◆ IOAPIC_TBL_RIRR

#define IOAPIC_TBL_RIRR   (0x1 << 14) /* Remote IRR */

Definition at line 32 of file ioapic.h.

◆ IOAPIC_TBL_TM

#define IOAPIC_TBL_TM   (0x1 << 15) /* Trigger Mode */

Definition at line 33 of file ioapic.h.

◆ IOAPIC_TBL_VECTOR

#define IOAPIC_TBL_VECTOR   (0xFF << 0) /* Vector (10h - FEh) */

Definition at line 37 of file ioapic.h.

◆ IOAPIC_VER

#define IOAPIC_VER   0x0001 /* IO APIC Version (R) */

Definition at line 12 of file ioapic.h.

◆ IOAPIC_VER_MASK

#define IOAPIC_VER_MASK   (0xFF)

Definition at line 20 of file ioapic.h.

◆ SET_IOAPIC_ID

#define SET_IOAPIC_ID (   x)    ((x) << 24)

Definition at line 18 of file ioapic.h.

Typedef Documentation

◆ IOAPIC_INFO

◆ IOAPIC_ROUTE_ENTRY

◆ PIOAPIC_INFO

◆ PIOAPIC_ROUTE_ENTRY

Function Documentation

◆ HaliReconfigurePciInterrupts()

VOID HaliReconfigurePciInterrupts ( VOID  )

Definition at line 637 of file ioapic.c.

638{
639 ULONG i;
640
641 for (i = 0; i < IRQCount; i++)
642 {
643 if (BUSMap[IRQMap[i].SrcBusId] == MP_BUS_PCI)
644 {
645 DPRINT("%02x: IrqType %02x, IrqFlag %02x, SrcBusId %02x, SrcBusIrq %02x"
646 ", DstApicId %02x, DstApicInt %02x\n",
647 i, IRQMap[i].IrqType, IRQMap[i].IrqFlag, IRQMap[i].SrcBusId,
648 IRQMap[i].SrcBusIrq, IRQMap[i].DstApicId, IRQMap[i].DstApicInt);
649
651 IRQMap[i].SrcBusId,
652 (IRQMap[i].SrcBusIrq >> 2) & 0x1f,
653 &IRQMap[i].DstApicInt,
654 0x3c /*PCI_INTERRUPT_LINE*/,
655 1);
656
657 }
658 }
659}
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
ULONG NTAPI HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:123
UCHAR BUSMap[MAX_BUS]
Definition: ioapic.c:21
MP_CONFIGURATION_INTSRC IRQMap[MAX_IRQ_SOURCE]
Definition: ioapic.c:17
ULONG IRQCount
Definition: ioapic.c:18
#define MP_BUS_PCI
Definition: mps.h:113
@ PCIConfiguration
Definition: miniport.h:93
#define DPRINT
Definition: sndvol32.h:71
uint32_t ULONG
Definition: typedefs.h:59

◆ IOAPICDump()

VOID IOAPICDump ( VOID  )

Definition at line 527 of file ioapic.c.

528{
529 ULONG apic, i;
530 ULONG reg0, reg1, reg2=0;
531
532 DbgPrint("Number of MP IRQ sources: %d.\n", IRQCount);
533 for (i = 0; i < IOAPICCount; i++)
534 {
535 DbgPrint("Number of IO-APIC #%d registers: %d.\n",
537 IOAPICMap[i].EntryCount);
538 }
539
540 /*
541 * We are a bit conservative about what we expect. We have to
542 * know about every hardware change ASAP.
543 */
544 DbgPrint("Testing the IO APIC.......................\n");
545
546 for (apic = 0; apic < IOAPICCount; apic++)
547 {
548 reg0 = IOAPICRead(apic, IOAPIC_ID);
549 reg1 = IOAPICRead(apic, IOAPIC_VER);
550 if (GET_IOAPIC_VERSION(reg1) >= 0x10)
551 {
552 reg2 = IOAPICRead(apic, IOAPIC_ARB);
553 }
554
555 DbgPrint("\n");
556 DbgPrint("IO APIC #%d......\n", IOAPICMap[apic].ApicId);
557 DbgPrint(".... register #00: %08X\n", reg0);
558 DbgPrint("....... : physical APIC id: %02X\n", GET_IOAPIC_ID(reg0));
559 if (reg0 & 0xF0FFFFFF)
560 {
561 DbgPrint(" WARNING: Unexpected IO-APIC\n");
562 }
563
564 DbgPrint(".... register #01: %08X\n", reg1);
565 i = GET_IOAPIC_MRE(reg1);
566
567 DbgPrint("....... : max redirection entries: %04X\n", i);
568 if ((i != 0x0f) && /* older (Neptune) boards */
569 (i != 0x17) && /* typical ISA+PCI boards */
570 (i != 0x1b) && /* Compaq Proliant boards */
571 (i != 0x1f) && /* dual Xeon boards */
572 (i != 0x22) && /* bigger Xeon boards */
573 (i != 0x2E) &&
574 (i != 0x3F))
575 {
576 DbgPrint(" WARNING: Unexpected IO-APIC\n");
577 }
578
579 i = GET_IOAPIC_VERSION(reg1);
580 DbgPrint("....... : IO APIC version: %04X\n", i);
581 if ((i != 0x01) && /* 82489DX IO-APICs */
582 (i != 0x10) && /* oldest IO-APICs */
583 (i != 0x11) && /* Pentium/Pro IO-APICs */
584 (i != 0x13)) /* Xeon IO-APICs */
585 {
586 DbgPrint(" WARNING: Unexpected IO-APIC\n");
587 }
588
589 if (reg1 & 0xFF00FF00)
590 {
591 DbgPrint(" WARNING: Unexpected IO-APIC\n");
592 }
593
594 if (GET_IOAPIC_VERSION(reg1) >= 0x10)
595 {
596 DbgPrint(".... register #02: %08X\n", reg2);
597 DbgPrint("....... : arbitration: %02X\n",
598 GET_IOAPIC_ARB(reg2));
599 if (reg2 & 0xF0FFFFFF)
600 {
601 DbgPrint(" WARNING: Unexpected IO-APIC\n");
602 }
603 }
604
605 DbgPrint(".... IRQ redirection table:\n");
606 DbgPrint(" NR Log Phy Mask Trig IRR Pol"
607 " Stat Dest Deli Vect: \n");
608
609 for (i = 0; i <= GET_IOAPIC_MRE(reg1); i++)
610 {
612
613 *(((PULONG)&entry)+0) = IOAPICRead(apic, 0x10+i*2);
614 *(((PULONG)&entry)+1) = IOAPICRead(apic, 0x11+i*2);
615
616 DbgPrint(" %02x %03X %02X ",
617 i,
618 entry.dest.logical.logical_dest,
619 entry.dest.physical.physical_dest);
620
621 DbgPrint("%C %C %1d %C %C %C %03X %02X\n",
622 (entry.mask == 0) ? 'U' : 'M', // Unmasked/masked
623 (entry.trigger == 0) ? 'E' : 'L', // Edge/level sensitive
624 entry.irr,
625 (entry.polarity == 0) ? 'H' : 'L', // Active high/active low
626 (entry.delivery_status == 0) ? 'I' : 'S', // Idle / send pending
627 (entry.dest_mode == 0) ? 'P' : 'L', // Physical logical
628 entry.delivery_mode,
629 entry.vector);
630 }
631 }
632
633 DbgPrint(".................................... done.\n");
634}
#define IOAPIC_ID
Definition: apicp.h:284
#define IOAPIC_VER
Definition: apicp.h:285
#define IOAPIC_ARB
Definition: apicp.h:286
#define DbgPrint
Definition: hal.h:12
ULONG IOAPICCount
Definition: ioapic.c:25
IOAPIC_INFO IOAPICMap[MAX_IOAPIC]
Definition: ioapic.c:24
ULONG IOAPICRead(ULONG Apic, ULONG Offset)
Definition: ioapic.c:679
#define GET_IOAPIC_ID(x)
Definition: ioapic.h:17
#define GET_IOAPIC_ARB(x)
Definition: ioapic.h:26
#define GET_IOAPIC_VERSION(x)
Definition: ioapic.h:21
#define GET_IOAPIC_MRE(x)
Definition: ioapic.h:23
uint32_t entry
Definition: isohybrid.c:63
Definition: ioapic.h:40
uint32_t * PULONG
Definition: typedefs.h:59
_Must_inspect_result_ typedef _In_ ULONG ApicId
Definition: iotypes.h:1105

◆ IOAPICEnable()

VOID IOAPICEnable ( VOID  )

Definition at line 409 of file ioapic.c.

410{
411 ULONG i, tmp;
412
413 /* Setup IRQ to vector translation map */
414 memset(&IRQVectorMap, 0, sizeof(IRQVectorMap));
415
416 /*
417 * The number of IO-APIC IRQ registers (== #pins):
418 */
419 for (i = 0; i < IOAPICCount; i++)
420 {
421 tmp = IOAPICRead(i, IOAPIC_VER);
423 }
424
425 /*
426 * Do not trust the IO-APIC being empty at bootup
427 */
429}
ULONG IRQVectorMap[MAX_IRQ_SOURCE]
Definition: ioapic.c:27
static VOID IOAPICClearAll(VOID)
Definition: ioapic.c:398
#define memset(x, y, z)
Definition: compat.h:39
ULONG EntryCount
Definition: ioapic.h:73

Referenced by HalAllProcessorsStarted().

◆ IOAPICMaskIrq()

VOID IOAPICMaskIrq ( ULONG  Irq)

Definition at line 497 of file ioapic.c.

498{
500 ULONG Apic = IrqApicMap[Irq];
501
502 *(((PULONG)&Entry)+0) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq);
503 *(((PULONG)&Entry)+1) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq+1);
504 Entry.dest.logical.logical_dest &= ~(1 << KeGetCurrentProcessorNumber());
505 if (Entry.dest.logical.logical_dest == 0)
506 {
507 Entry.mask = 1;
508 }
509 IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq+1, *(((PULONG)&Entry)+1));
510 IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *(((PULONG)&Entry)+0));
511}
#define IOAPIC_REDTBL
Definition: apicp.h:287
ULONG IrqApicMap[MAX_IRQ_SOURCE]
Definition: ioapic.c:19
VOID IOAPICWrite(ULONG Apic, ULONG Offset, ULONG Value)
Definition: ioapic.c:688
FORCEINLINE ULONG KeGetCurrentProcessorNumber(VOID)
Definition: ke.h:337
base of all file and directory entries
Definition: entries.h:83

Referenced by HalDisableSystemInterrupt().

◆ IOAPICSetupIds()

VOID IOAPICSetupIds ( VOID  )

Definition at line 432 of file ioapic.c.

433{
434 ULONG tmp, apic, i;
435 UCHAR old_id;
436
437 /*
438 * Set the IOAPIC ID to the value stored in the MPC table.
439 */
440 for (apic = 0; apic < IOAPICCount; apic++)
441 {
442
443 /* Read the register 0 value */
444 tmp = IOAPICRead(apic, IOAPIC_ID);
445
446 old_id = IOAPICMap[apic].ApicId;
447
448 if (IOAPICMap[apic].ApicId >= 0xf)
449 {
450 DPRINT1("BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
451 apic, IOAPICMap[apic].ApicId);
452 DPRINT1("... fixing up to %d. (tell your hw vendor)\n",
453 GET_IOAPIC_ID(tmp));
454 IOAPICMap[apic].ApicId = GET_IOAPIC_ID(tmp);
455 }
456
457 /*
458 * We need to adjust the IRQ routing table
459 * if the ID changed.
460 */
461 if (old_id != IOAPICMap[apic].ApicId)
462 {
463 for (i = 0; i < IRQCount; i++)
464 {
465 if (IRQMap[i].DstApicId == old_id)
466 {
468 }
469 }
470 }
471
472 /*
473 * Read the right value from the MPC table and
474 * write it into the ID register.
475 */
476 DPRINT("Changing IO-APIC physical APIC ID to %d\n",
477 IOAPICMap[apic].ApicId);
478
479 tmp &= ~IOAPIC_ID_MASK;
480 tmp |= SET_IOAPIC_ID(IOAPICMap[apic].ApicId);
481
482 IOAPICWrite(apic, IOAPIC_ID, tmp);
483
484 /*
485 * Sanity check
486 */
487 tmp = IOAPICRead(apic, 0);
488 if (GET_IOAPIC_ID(tmp) != IOAPICMap[apic].ApicId)
489 {
490 DPRINT1("Could not set I/O APIC ID!\n");
491 ASSERT(FALSE);
492 }
493 }
494}
#define DPRINT1
Definition: precomp.h:8
#define FALSE
Definition: types.h:117
#define SET_IOAPIC_ID(x)
Definition: ioapic.h:18
#define ASSERT(a)
Definition: mode.c:44
UCHAR ApicId
Definition: ioapic.h:70
unsigned char UCHAR
Definition: xmlstorage.h:181

Referenced by HalAllProcessorsStarted().

◆ IOAPICSetupIrqs()

VOID IOAPICSetupIrqs ( VOID  )

Definition at line 296 of file ioapic.c.

297{
299 ULONG apic, pin, idx, irq, first_notcon = 1, vector, trigger;
300
301 DPRINT("Init IO_APIC IRQs\n");
302
303 /* Setup IRQ to vector translation map */
304 memset(&IRQVectorMap, 0, sizeof(IRQVectorMap));
305
306 for (apic = 0; apic < IOAPICCount; apic++)
307 {
308 for (pin = 0; pin < IOAPICMap[apic].EntryCount; pin++)
309 {
310 /*
311 * add it to the IO-APIC irq-routing table
312 */
313 memset(&entry,0,sizeof(entry));
314
315 entry.delivery_mode = (APIC_DM_LOWEST >> 8);
316 entry.dest_mode = 1; /* logical delivery */
317 entry.mask = 1; /* disable IRQ */
318 entry.dest.logical.logical_dest = 0;
319
321 if (idx == (ULONG)-1)
322 {
323 if (first_notcon)
324 {
325 DPRINT(" IO-APIC (apicid-pin) %d-%d\n", IOAPICMap[apic].ApicId, pin);
326 first_notcon = 0;
327 }
328 else
329 {
330 DPRINT(", %d-%d\n", IOAPICMap[apic].ApicId, pin);
331 }
332 continue;
333 }
334
335 trigger = IRQTrigger(idx);
336 entry.polarity = IRQPolarity(idx);
337
338 if (trigger)
339 {
340 entry.trigger = 1;
341 }
342
343 irq = Pin2Irq(idx, apic, pin);
344
346 entry.vector = vector;
347
348 DPRINT("vector 0x%.08x assigned to irq 0x%.02x\n", vector, irq);
349
350 if (irq == 0)
351 {
352 /* Mask timer IRQ */
353 entry.mask = 1;
354 }
355
356 if ((apic == 0) && (irq < 16))
357 {
359 }
360 IOAPICWrite(apic, IOAPIC_REDTBL+2*pin+1, *(((PULONG)&entry)+1));
361 IOAPICWrite(apic, IOAPIC_REDTBL+2*pin, *(((PULONG)&entry)+0));
362
363 IrqApicMap[irq] = apic;
364
365 DPRINT("Vector %x, Pin %x, Irq %x\n", vector, pin, irq);
366 }
367 }
368}
unsigned int idx
Definition: utils.c:41
unsigned char irq
Definition: dsp.h:13
static ULONG Pin2Irq(ULONG idx, ULONG apic, ULONG pin)
Definition: ioapic.c:194
static ULONG IOAPICGetIrqEntry(ULONG apic, ULONG pin, ULONG type)
Definition: ioapic.c:276
static ULONG IRQPolarity(ULONG idx)
Definition: ioapic.c:78
static ULONG IRQTrigger(ULONG idx)
Definition: ioapic.c:136
VOID Disable8259AIrq(ULONG irq)
Definition: ioapic.c:661
static ULONG AssignIrqVector(ULONG irq)
Definition: ioapic.c:237
#define INT_VECTORED
Definition: mps.h:163
Definition: regsvr.c:104

Referenced by HalAllProcessorsStarted().

◆ IOAPICUnmaskIrq()

VOID IOAPICUnmaskIrq ( ULONG  Irq)

Definition at line 514 of file ioapic.c.

515{
517 ULONG Apic = IrqApicMap[Irq];
518
519 *(((PULONG)&Entry)+0) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq);
520 *(((PULONG)&Entry)+1) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq+1);
521 Entry.dest.logical.logical_dest |= 1 << KeGetCurrentProcessorNumber();
522 Entry.mask = 0;
523 IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq+1, *(((PULONG)&Entry)+1));
524 IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *(((PULONG)&Entry)+0));
525}

Referenced by HalEnableSystemInterrupt().

Variable Documentation

◆ APICMode

ULONG APICMode
extern

Definition at line 49 of file apic.c.

Referenced by APICSetup(), HaliGetSmpConfig(), and HaliInitBSP().

◆ BUSMap

UCHAR BUSMap[MAX_BUS]
extern

◆ IOAPICCount

ULONG IOAPICCount
extern

◆ IOAPICMap

◆ IRQCount

◆ IRQMap

◆ PCIBUSMap

UCHAR PCIBUSMap[MAX_BUS]
extern

Definition at line 22 of file ioapic.c.

Referenced by HaliMPBusInfo().