ioapic.h File Reference

#include <pshpack1.h>
#include <poppack.h>

Include dependency graph for ioapic.h:

Go to the source code of this file.

Classes
struct	_IOAPIC_ROUTE_ENTRY
struct	_IOAPIC_INFO

Macros
#define	IOAPIC_IOREGSEL   0x0000 /* I/O Register Select (index) (R/W) */
#define	IOAPIC_IOWIN   0x0010 /* I/O window (data) (R/W) */
#define	IOAPIC_ID   0x0000 /* IO APIC ID (R/W) */
#define	IOAPIC_VER   0x0001 /* IO APIC Version (R) */
#define	IOAPIC_ARB   0x0002 /* IO APIC Arbitration ID (R) */
#define	IOAPIC_REDTBL   0x0010 /* Redirection Table (0-23 64-bit registers) (R/W) */
#define	IOAPIC_ID_MASK   (0xF << 24)
#define	GET_IOAPIC_ID(x)   ((UCHAR)(((x) & IOAPIC_ID_MASK) >> 24))
#define	SET_IOAPIC_ID(x)   ((x) << 24)
#define	IOAPIC_VER_MASK   (0xFF)
#define	GET_IOAPIC_VERSION(x)   (((x) & IOAPIC_VER_MASK))
#define	IOAPIC_MRE_MASK   (0xFF << 16) /* Maximum Redirection Entry */
#define	GET_IOAPIC_MRE(x)   (((x) & IOAPIC_MRE_MASK) >> 16)
#define	IOAPIC_ARB_MASK   (0xF << 24)
#define	GET_IOAPIC_ARB(x)   (((x) & IOAPIC_ARB_MASK) >> 24)
#define	IOAPIC_TBL_DELMOD   (0x7 << 10) /* Delivery Mode (see APIC_DM_*) */
#define	IOAPIC_TBL_DM   (0x1 << 11) /* Destination Mode */
#define	IOAPIC_TBL_DS   (0x1 << 12) /* Delivery Status */
#define	IOAPIC_TBL_INTPOL   (0x1 << 13) /* Interrupt Input Pin Polarity */
#define	IOAPIC_TBL_RIRR   (0x1 << 14) /* Remote IRR */
#define	IOAPIC_TBL_TM   (0x1 << 15) /* Trigger Mode */
#define	IOAPIC_TBL_IM   (0x1 << 16) /* Interrupt Mask */
#define	IOAPIC_TBL_DF0   (0xF << 56) /* Destination Field (physical mode) */
#define	IOAPIC_TBL_DF1   (0xFF<< 56) /* Destination Field (logical mode) */
#define	IOAPIC_TBL_VECTOR   (0xFF << 0) /* Vector (10h - FEh) */
#define	IOAPIC_DEFAULT_BASE   0xFEC00000 /* Default I/O APIC Base Register Address */

Typedefs
typedef struct _IOAPIC_ROUTE_ENTRY	IOAPIC_ROUTE_ENTRY
typedef struct _IOAPIC_ROUTE_ENTRY *	PIOAPIC_ROUTE_ENTRY
typedef struct _IOAPIC_INFO	IOAPIC_INFO
typedef struct _IOAPIC_INFO *	PIOAPIC_INFO

Functions
VOID	IOAPICSetupIrqs (VOID)
VOID	IOAPICEnable (VOID)
VOID	IOAPICSetupIds (VOID)
VOID	IOAPICMaskIrq (ULONG Irq)
VOID	IOAPICUnmaskIrq (ULONG Irq)
VOID	HaliReconfigurePciInterrupts (VOID)
VOID	IOAPICDump (VOID)

Variables
ULONG	IRQCount
UCHAR	BUSMap [MAX_BUS]
UCHAR	PCIBUSMap [MAX_BUS]
IOAPIC_INFO	IOAPICMap [MAX_IOAPIC]
ULONG	IOAPICCount
ULONG	APICMode
MP_CONFIGURATION_INTSRC	IRQMap [MAX_IRQ_SOURCE]

Macro Definition Documentation

GET_IOAPIC_ARB

#define GET_IOAPIC_ARB

(

x

)

(((x) & IOAPIC_ARB_MASK) >> 24)

Definition at line 26 of file ioapic.h.

GET_IOAPIC_ID

#define GET_IOAPIC_ID

(

x

)

((UCHAR)(((x) & IOAPIC_ID_MASK) >> 24))

Definition at line 17 of file ioapic.h.

GET_IOAPIC_MRE

#define GET_IOAPIC_MRE

(

x

)

(((x) & IOAPIC_MRE_MASK) >> 16)

Definition at line 23 of file ioapic.h.

GET_IOAPIC_VERSION

#define GET_IOAPIC_VERSION

(

x

)

(((x) & IOAPIC_VER_MASK))

Definition at line 21 of file ioapic.h.

IOAPIC_ARB

#define IOAPIC_ARB   0x0002 /* IO APIC Arbitration ID (R) */

Definition at line 13 of file ioapic.h.

IOAPIC_ARB_MASK

#define IOAPIC_ARB_MASK   (0xF << 24)

Definition at line 25 of file ioapic.h.

IOAPIC_DEFAULT_BASE

#define IOAPIC_DEFAULT_BASE   0xFEC00000 /* Default I/O APIC Base Register Address */

Definition at line 76 of file ioapic.h.

IOAPIC_ID

#define IOAPIC_ID   0x0000 /* IO APIC ID (R/W) */

Definition at line 11 of file ioapic.h.

IOAPIC_ID_MASK

#define IOAPIC_ID_MASK   (0xF << 24)

Definition at line 16 of file ioapic.h.

IOAPIC_IOREGSEL

#define IOAPIC_IOREGSEL   0x0000 /* I/O Register Select (index) (R/W) */

Definition at line 8 of file ioapic.h.

IOAPIC_IOWIN

#define IOAPIC_IOWIN   0x0010 /* I/O window (data) (R/W) */

Definition at line 9 of file ioapic.h.

IOAPIC_MRE_MASK

#define IOAPIC_MRE_MASK   (0xFF << 16) /* Maximum Redirection Entry */

Definition at line 22 of file ioapic.h.

IOAPIC_REDTBL

#define IOAPIC_REDTBL   0x0010 /* Redirection Table (0-23 64-bit registers) (R/W) */

Definition at line 14 of file ioapic.h.

IOAPIC_TBL_DELMOD

#define IOAPIC_TBL_DELMOD   (0x7 << 10) /* Delivery Mode (see APIC_DM_*) */

Definition at line 28 of file ioapic.h.

IOAPIC_TBL_DF0

#define IOAPIC_TBL_DF0   (0xF << 56) /* Destination Field (physical mode) */

Definition at line 35 of file ioapic.h.

IOAPIC_TBL_DF1

#define IOAPIC_TBL_DF1   (0xFF<< 56) /* Destination Field (logical mode) */

Definition at line 36 of file ioapic.h.

IOAPIC_TBL_DM

#define IOAPIC_TBL_DM   (0x1 << 11) /* Destination Mode */

Definition at line 29 of file ioapic.h.

IOAPIC_TBL_DS

#define IOAPIC_TBL_DS   (0x1 << 12) /* Delivery Status */

Definition at line 30 of file ioapic.h.

IOAPIC_TBL_IM

#define IOAPIC_TBL_IM   (0x1 << 16) /* Interrupt Mask */

Definition at line 34 of file ioapic.h.

IOAPIC_TBL_INTPOL

#define IOAPIC_TBL_INTPOL   (0x1 << 13) /* Interrupt Input Pin Polarity */

Definition at line 31 of file ioapic.h.

IOAPIC_TBL_RIRR

#define IOAPIC_TBL_RIRR   (0x1 << 14) /* Remote IRR */

Definition at line 32 of file ioapic.h.

IOAPIC_TBL_TM

#define IOAPIC_TBL_TM   (0x1 << 15) /* Trigger Mode */

Definition at line 33 of file ioapic.h.

IOAPIC_TBL_VECTOR

#define IOAPIC_TBL_VECTOR   (0xFF << 0) /* Vector (10h - FEh) */

Definition at line 37 of file ioapic.h.

IOAPIC_VER

#define IOAPIC_VER   0x0001 /* IO APIC Version (R) */

Definition at line 12 of file ioapic.h.

IOAPIC_VER_MASK

#define IOAPIC_VER_MASK   (0xFF)

Definition at line 20 of file ioapic.h.

SET_IOAPIC_ID

#define SET_IOAPIC_ID

(

x

)

((x) << 24)

Definition at line 18 of file ioapic.h.

Typedef Documentation

IOAPIC_INFO

typedef struct _IOAPIC_INFO IOAPIC_INFO

IOAPIC_ROUTE_ENTRY

typedef struct _IOAPIC_ROUTE_ENTRY IOAPIC_ROUTE_ENTRY

PIOAPIC_INFO

typedef struct _IOAPIC_INFO * PIOAPIC_INFO

PIOAPIC_ROUTE_ENTRY

typedef struct _IOAPIC_ROUTE_ENTRY * PIOAPIC_ROUTE_ENTRY

Function Documentation

HaliReconfigurePciInterrupts()

VOID HaliReconfigurePciInterrupts

(

VOID

)

Definition at line 634 of file ioapic.c.

{
   ULONG i;
 
   for (i = 0; i < IRQCount; i++)
   {
      if (BUSMap[IRQMap[i].SrcBusId] == MP_BUS_PCI)
      {
         DPRINT("%02lx: IrqType %02x, IrqFlag %04x, SrcBusId %02x"
                ", SrcBusIrq %02x, DstApicId %02x, DstApicInt %02x\n",
                i, IRQMap[i].IrqType, IRQMap[i].IrqFlag, IRQMap[i].SrcBusId,
                IRQMap[i].SrcBusIrq, IRQMap[i].DstApicId, IRQMap[i].DstApicInt);
 
     HalSetBusDataByOffset(PCIConfiguration,
                                   IRQMap[i].SrcBusId,
                       (IRQMap[i].SrcBusIrq >> 2) & 0x1f,
                       &IRQMap[i].DstApicInt,
                       0x3c /*PCI_INTERRUPT_LINE*/,
                       1);
 
      }
   }
}

IOAPICDump()

VOID IOAPICDump

(

VOID

)

Definition at line 524 of file ioapic.c.

{
   ULONG apic, i;
   ULONG reg0, reg1, reg2=0;
 
   DbgPrint("Number of MP IRQ sources: %d.\n", IRQCount);
   for (i = 0; i < IOAPICCount; i++)
   {
      DbgPrint("Number of IO-APIC #%d registers: %d.\n",
           IOAPICMap[i].ApicId,
               IOAPICMap[i].EntryCount);
   }
 
   /*
    * We are a bit conservative about what we expect.  We have to
    * know about every hardware change ASAP.
    */
   DbgPrint("Testing the IO APIC.......................\n");
 
   for (apic = 0; apic < IOAPICCount; apic++)
   {
      reg0 = IOAPICRead(apic, IOAPIC_ID);
      reg1 = IOAPICRead(apic, IOAPIC_VER);
      if (GET_IOAPIC_VERSION(reg1) >= 0x10)
      {
         reg2 = IOAPICRead(apic, IOAPIC_ARB);
      }
 
      DbgPrint("\n");
      DbgPrint("IO APIC #%d......\n", IOAPICMap[apic].ApicId);
      DbgPrint(".... register #00: %08X\n", reg0);
      DbgPrint(".......    : physical APIC id: %02X\n", GET_IOAPIC_ID(reg0));
      if (reg0 & 0xF0FFFFFF)
      {
         DbgPrint("  WARNING: Unexpected IO-APIC\n");
      }
 
      DbgPrint(".... register #01: %08X\n", reg1);
      i = GET_IOAPIC_MRE(reg1);
 
      DbgPrint(".......     : max redirection entries: %04X\n", i);
      if ((i != 0x0f) &&    /* older (Neptune) boards */
      (i != 0x17) &&    /* typical ISA+PCI boards */
      (i != 0x1b) &&    /* Compaq Proliant boards */
      (i != 0x1f) &&    /* dual Xeon boards */
          (i != 0x22) &&   /* bigger Xeon boards */
      (i != 0x2E) &&
      (i != 0x3F))
      {
         DbgPrint("  WARNING: Unexpected IO-APIC\n");
      }
 
      i = GET_IOAPIC_VERSION(reg1);
      DbgPrint(".......     : IO APIC version: %04X\n", i);
      if ((i != 0x01) &&    /* 82489DX IO-APICs */
      (i != 0x10) &&    /* oldest IO-APICs */
      (i != 0x11) &&    /* Pentium/Pro IO-APICs */
      (i != 0x13))      /* Xeon IO-APICs */
      {
         DbgPrint("  WARNING: Unexpected IO-APIC\n");
      }
 
      if (reg1 & 0xFF00FF00)
      {
         DbgPrint("  WARNING: Unexpected IO-APIC\n");
      }
 
      if (GET_IOAPIC_VERSION(reg1) >= 0x10)
      {
     DbgPrint(".... register #02: %08X\n", reg2);
     DbgPrint(".......     : arbitration: %02X\n",
              GET_IOAPIC_ARB(reg2));
     if (reg2 & 0xF0FFFFFF)
     {
            DbgPrint("  WARNING: Unexpected IO-APIC\n");
         }
      }
 
      DbgPrint(".... IRQ redirection table:\n");
      DbgPrint(" NR Log Phy Mask Trig IRR Pol"
           " Stat Dest Deli Vect:   \n");
 
      for (i = 0; i <= GET_IOAPIC_MRE(reg1); i++)
      {
         IOAPIC_ROUTE_ENTRY entry;
 
     *(((PULONG)&entry)+0) = IOAPICRead(apic, 0x10+i*2);
     *(((PULONG)&entry)+1) = IOAPICRead(apic, 0x11+i*2);
 
     DbgPrint(" %02x %03X %02X  ",
          i,
          entry.dest.logical.logical_dest,
          entry.dest.physical.physical_dest);
 
         DbgPrint("%C    %C    %1d  %C    %C    %C     %03X    %02X\n",
          (entry.mask == 0) ? 'U' : 'M',            // Unmasked/masked
          (entry.trigger == 0) ? 'E' : 'L',         // Edge/level sensitive
          entry.irr,
          (entry.polarity == 0) ? 'H' : 'L',        // Active high/active low
          (entry.delivery_status == 0) ? 'I' : 'S', // Idle / send pending
          (entry.dest_mode == 0) ? 'P' : 'L',       // Physical logical
          entry.delivery_mode,
          entry.vector);
      }
   }
 
   DbgPrint(".................................... done.\n");
}

IOAPICEnable()

VOID IOAPICEnable

(

VOID

)

Definition at line 409 of file ioapic.c.

{
   ULONG i, tmp;
 
   /* Setup IRQ to vector translation map */
   memset(&IRQVectorMap, 0, sizeof(IRQVectorMap));
 
   /*
    * The number of IO-APIC IRQ registers (== #pins):
    */
   for (i = 0; i < IOAPICCount; i++)
   {
      tmp = IOAPICRead(i, IOAPIC_VER);
      IOAPICMap[i].EntryCount = GET_IOAPIC_MRE(tmp) + 1;
   }
 
   /*
    * Do not trust the IO-APIC being empty at bootup
    */
   IOAPICClearAll();
}

Referenced by HalAllProcessorsStarted().

IOAPICMaskIrq()

VOID IOAPICMaskIrq

(

ULONG

Irq

)

Definition at line 494 of file ioapic.c.

{
   IOAPIC_ROUTE_ENTRY Entry;
   ULONG Apic = IrqApicMap[Irq];
 
   *(((PULONG)&Entry)+0) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq);
   *(((PULONG)&Entry)+1) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq+1);
   Entry.dest.logical.logical_dest &= ~(1 << KeGetCurrentProcessorNumber());
   if (Entry.dest.logical.logical_dest == 0)
   {
      Entry.mask = 1;
   }
   IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq+1, *(((PULONG)&Entry)+1));
   IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *(((PULONG)&Entry)+0));
}

Referenced by HalDisableSystemInterrupt().

IOAPICSetupIds()

VOID IOAPICSetupIds

(

VOID

)

Definition at line 432 of file ioapic.c.

{
  ULONG tmp, apic, i;
  UCHAR old_id;
 
  /*
   * Set the IOAPIC ID to the value stored in the MPC table.
   */
  for (apic = 0; apic < IOAPICCount; apic++)
  {
 
    /* Read the register 0 value */
    tmp = IOAPICRead(apic, IOAPIC_ID);
 
    old_id = IOAPICMap[apic].ApicId;
 
    if (IOAPICMap[apic].ApicId >= 0xf)
    {
      DPRINT1("BIOS bug, IO-APIC#%lu ID is %u in the MPC table\n", apic, IOAPICMap[apic].ApicId);
      IOAPICMap[apic].ApicId = GET_IOAPIC_ID(tmp);
      DPRINT1(" Fixed up to %u. (Tell your hardware vendor)\n", IOAPICMap[apic].ApicId);
    }
 
    /*
     * We need to adjust the IRQ routing table
     * if the ID changed.
     */
    if (old_id != IOAPICMap[apic].ApicId)
    {
      for (i = 0; i < IRQCount; i++)
      {
    if (IRQMap[i].DstApicId == old_id)
    {
      IRQMap[i].DstApicId = IOAPICMap[apic].ApicId;
    }
      }
    }
 
    /*
     * Read the right value from the MPC table and
     * write it into the ID register.
     */
    DPRINT("Changing IO-APIC physical APIC ID to %u\n", IOAPICMap[apic].ApicId);
 
    tmp &= ~IOAPIC_ID_MASK;
    tmp |= SET_IOAPIC_ID(IOAPICMap[apic].ApicId);
 
    IOAPICWrite(apic, IOAPIC_ID, tmp);
 
    /*
     * Sanity check
     */
    tmp = IOAPICRead(apic, 0);
    if (GET_IOAPIC_ID(tmp) != IOAPICMap[apic].ApicId)
    {
      DPRINT1("Could not set I/O APIC ID!\n");
      ASSERT(FALSE);
    }
  }
}

Referenced by HalAllProcessorsStarted().

IOAPICSetupIrqs()

VOID IOAPICSetupIrqs

(

VOID

)

Definition at line 296 of file ioapic.c.

{
   IOAPIC_ROUTE_ENTRY entry;
   ULONG apic, pin, idx, irq, first_notcon = 1, vector, trigger;
 
   DPRINT("Init IO_APIC IRQs\n");
 
   /* Setup IRQ to vector translation map */
   memset(&IRQVectorMap, 0, sizeof(IRQVectorMap));
 
   for (apic = 0; apic < IOAPICCount; apic++)
   {
      for (pin = 0; pin < IOAPICMap[apic].EntryCount; pin++)
      {
         /*
      * add it to the IO-APIC irq-routing table
      */
     memset(&entry,0,sizeof(entry));
 
     entry.delivery_mode = (APIC_DM_LOWEST >> 8);
     entry.dest_mode = 1;  /* logical delivery */
     entry.mask = 1;       /* disable IRQ */
         entry.dest.logical.logical_dest = 0;
 
     idx = IOAPICGetIrqEntry(apic,pin,INT_VECTORED);
     if (idx == (ULONG)-1)
     {
        if (first_notcon)
        {
            DPRINT(" IO-APIC (apicid-pin) %u-%lu\n", IOAPICMap[apic].ApicId, pin);
           first_notcon = 0;
        }
        else
        {
               DPRINT(", %u-%lu\n", IOAPICMap[apic].ApicId, pin);
            }
        continue;
     }
 
         trigger = IRQTrigger(idx);
     entry.polarity = IRQPolarity(idx);
 
     if (trigger)
     {
        entry.trigger = 1;
     }
 
     irq = Pin2Irq(idx, apic, pin);
 
     vector = AssignIrqVector(irq);
     entry.vector = vector;
 
         DPRINT("Vector 0x%.08lx assigned to irq 0x%.02lx\n", vector, irq);
 
         if (irq == 0)
         {
            /* Mask timer IRQ */
            entry.mask = 1;
         }
 
         if ((apic == 0) && (irq < 16))
     {
        Disable8259AIrq(irq);
     }
         IOAPICWrite(apic, IOAPIC_REDTBL+2*pin+1, *(((PULONG)&entry)+1));
     IOAPICWrite(apic, IOAPIC_REDTBL+2*pin, *(((PULONG)&entry)+0));
 
     IrqApicMap[irq] = apic;
 
         DPRINT("Vector %lx, Pin %lx, Irq %lx\n", vector, pin, irq);
      }
   }
}

Referenced by HalAllProcessorsStarted().

IOAPICUnmaskIrq()

VOID IOAPICUnmaskIrq

(

ULONG

Irq

)

Definition at line 511 of file ioapic.c.

{
   IOAPIC_ROUTE_ENTRY Entry;
   ULONG Apic = IrqApicMap[Irq];
 
   *(((PULONG)&Entry)+0) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq);
   *(((PULONG)&Entry)+1) = IOAPICRead(Apic, IOAPIC_REDTBL+2*Irq+1);
   Entry.dest.logical.logical_dest |= 1 << KeGetCurrentProcessorNumber();
   Entry.mask = 0;
   IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq+1, *(((PULONG)&Entry)+1));
   IOAPICWrite(Apic, IOAPIC_REDTBL+2*Irq, *(((PULONG)&Entry)+0));
}

Referenced by HalEnableSystemInterrupt().

Variable Documentation

APICMode

ULONG APICMode

extern

Definition at line 49 of file apic.c.

Referenced by APICSetup(), HaliGetSmpConfig(), and HaliInitBSP().

BUSMap

UCHAR BUSMap[MAX_BUS]

extern

Definition at line 21 of file ioapic.c.

Referenced by HaliMPBusInfo(), HaliReconfigurePciInterrupts(), IRQPolarity(), IRQTrigger(), and Pin2Irq().

IOAPICCount

ULONG IOAPICCount

extern

Definition at line 25 of file ioapic.c.

Referenced by HaliMPIOApicInfo(), IOAPICClearAll(), IOAPICDump(), IOAPICEnable(), IOAPICSetupIds(), and IOAPICSetupIrqs().

IOAPICMap

IOAPIC_INFO IOAPICMap[MAX_IOAPIC]

extern

Definition at line 24 of file ioapic.c.

Referenced by HaliConstructDefaultIOIrqMPTable(), HaliMPIOApicInfo(), IOAPICDump(), IOAPICEnable(), IOAPICGetIrqEntry(), IOAPICRead(), IOAPICSetupIds(), IOAPICSetupIrqs(), IOAPICWrite(), and Pin2Irq().

IRQCount

ULONG IRQCount

extern

Definition at line 18 of file ioapic.c.

Referenced by HaliGetSmpConfig(), HaliMPIntSrcInfo(), HaliReconfigurePciInterrupts(), IOAPICDump(), IOAPICGetIrqEntry(), and IOAPICSetupIds().

IRQMap

MP_CONFIGURATION_INTSRC IRQMap[MAX_IRQ_SOURCE]

extern

Definition at line 17 of file ioapic.c.

Referenced by HaliMPIntSrcInfo(), HaliReconfigurePciInterrupts(), IOAPICGetIrqEntry(), IOAPICSetupIds(), IRQPolarity(), IRQTrigger(), and Pin2Irq().

PCIBUSMap

UCHAR PCIBUSMap[MAX_BUS]

extern

Definition at line 22 of file ioapic.c.

Referenced by HaliMPBusInfo().