ReactOS 0.4.16-dev-2633-g8dc9e50
Classes | Macros | Typedefs | Functions | Variables
intel.c File Reference
#include "pciidex.h"
Include dependency graph for intel.c:

Go to the source code of this file.

Classes

struct  _INTEL_CONTROLLER_INFO
 
struct  _INTEL_HW_EXTENSION
 

Macros

#define PCI_DEV_PIIX_82371FB   0x1230
 
#define PCI_DEV_MPIIX_82371MX   0x1234
 
#define PCI_DEV_PIIX3_82371SB   0x7010
 
#define PCI_DEV_PIIX4_82371AB   0x7111
 
#define PCI_DEV_PIIX4E_82372FB   0x7601
 
#define PCI_DEV_PIIX4E_82443MX   0x7199
 
#define PCI_DEV_PIIX4E_82451NX   0x84CA
 
#define PCI_DEV_ICH_82801AA   0x2411
 
#define PCI_DEV_ICH0_82801AB   0x2421
 
#define PCI_DEV_ICH2_82801BAM   0x244A
 
#define PCI_DEV_ICH2_82801BA   0x244B
 
#define PCI_DEV_C_ICH_82801E   0x245B
 
#define PCI_DEV_ICH3_M_82801CAM   0x248A
 
#define PCI_DEV_ICH3_S_82801CA   0x248B
 
#define PCI_DEV_ICH4_L_82801DBL   0x24C1
 
#define PCI_DEV_ICH4_M_82801DBM   0x24CA
 
#define PCI_DEV_ICH4_82801DB   0x24CB
 
#define PCI_DEV_ICH5_82801EB_SATA   0x24D1
 
#define PCI_DEV_ICH5_82801EB_IDE   0x24DB
 
#define PCI_DEV_ICH5_R_82801ER   0x24DF
 
#define PCI_DEV_ICH5_6300ESB_IDE   0x25A2
 
#define PCI_DEV_ICH5_6300ESB_SATA   0x25A3
 
#define PCI_DEV_ICH5_6300ESB_RAID   0x25B0
 
#define PCI_DEV_ICH6_82801FB_SATA   0x2651
 
#define PCI_DEV_ICH6_R_82801FB   0x2652
 
#define PCI_DEV_ICH6_M_82801FBM   0x2653
 
#define PCI_DEV_ICH6_82801FB_IDE   0x266F
 
#define PCI_DEV_ESB2_63XXESB   0x2680
 
#define PCI_DEV_ICH7_6321ESB   0x269E
 
#define PCI_DEV_ICH7_82801GB   0x27C0
 
#define PCI_DEV_ICH7_M_82801GBM   0x27C4
 
#define PCI_DEV_ICH7_82801G   0x27DF
 
#define PCI_DEV_ICH8_82801H   0x2820
 
#define PCI_DEV_ICH8_R_82801HR   0x2825
 
#define PCI_DEV_ICH8_M_82801HM   0x2828
 
#define PCI_DEV_ICH8_M_82801HBM   0x2850
 
#define PCI_DEV_ICH9_R_82801IR_1   0x2920
 
#define PCI_DEV_ICH9_R_82801IR_2   0x2921
 
#define PCI_DEV_ICH9_82801I   0x2926
 
#define PCI_DEV_ICH9_M_82801IBM_1   0x2928
 
#define PCI_DEV_ICH9_M_82801IBM_2   0x292D
 
#define PCI_DEV_ICH9_M_82801IBM_3   0x292E
 
#define PCI_DEV_ICH10_82801JD_1   0x3A00
 
#define PCI_DEV_ICH10_82801JD_2   0x3A06
 
#define PCI_DEV_ICH10_82801JI_1   0x3A20
 
#define PCI_DEV_ICH10_82801JI_2   0x3A26
 
#define PCI_DEV_SCH_ATOM_Z5XX   0x811A
 
#define PCI_DEV_EP80579   0x5028
 
#define PCI_DEV_PCH_5SERIES_1   0x3B20
 
#define PCI_DEV_PCH_5SERIES_2   0x3B21
 
#define PCI_DEV_PCH_5SERIES_3   0x3B26
 
#define PCI_DEV_PCH_5SERIES_4   0x3B28
 
#define PCI_DEV_PCH_5SERIES_5   0x3B2D
 
#define PCI_DEV_PCH_5SERIES_6   0x3B2E
 
#define PCI_DEV_PCH_6SERIES_1   0x1C00
 
#define PCI_DEV_PCH_6SERIES_2   0x1C01
 
#define PCI_DEV_PCH_6SERIES_3   0x1C08
 
#define PCI_DEV_PCH_6SERIES_4   0x1C09
 
#define PCI_DEV_PCH_7SERIES_1   0x1E00
 
#define PCI_DEV_PCH_7SERIES_2   0x1E01
 
#define PCI_DEV_PCH_7SERIES_3   0x1E08
 
#define PCI_DEV_PCH_7SERIES_4   0x1E09
 
#define PCI_DEV_PCH_X79_1   0x1D00
 
#define PCI_DEV_PCH_X79_2   0x1D08
 
#define PCI_DEV_PCH_8900_1   0x2326
 
#define PCI_DEV_PCH_8900_2   0x23A6
 
#define PCI_DEV_ATOM_C2000_1   0x1F20
 
#define PCI_DEV_ATOM_C2000_2   0x1F21
 
#define PCI_DEV_ATOM_C2000_3   0x1F30
 
#define PCI_DEV_ATOM_C2000_4   0x1F31
 
#define PCI_DEV_PCH_8SERIES_1   0x8C00
 
#define PCI_DEV_PCH_8SERIES_2   0x8C01
 
#define PCI_DEV_PCH_8SERIES_3   0x8C08
 
#define PCI_DEV_PCH_8SERIES_4   0x8C09
 
#define PCI_DEV_PCH_8SERIES_5   0x9C00
 
#define PCI_DEV_PCH_8SERIES_6   0x9C01
 
#define PCI_DEV_PCH_8SERIES_7   0x9C08
 
#define PCI_DEV_PCH_8SERIES_8   0x9C09
 
#define PCI_DEV_ATOM_E3800_1   0x0F20
 
#define PCI_DEV_ATOM_E3800_2   0x0F21
 
#define PCI_DEV_PCH_X99_1   0x8D00
 
#define PCI_DEV_PCH_X99_2   0x8D08
 
#define PCI_DEV_PCH_X99_3   0x8D60
 
#define PCI_DEV_PCH_X99_4   0x8D68
 
#define PCI_DEV_PCH_9SERIES_1   0x8C80
 
#define PCI_DEV_PCH_9SERIES_2   0x8C81
 
#define PCI_DEV_PCH_9SERIES_3   0x8C88
 
#define PCI_DEV_PCH_9SERIES_4   0x8C89
 
#define PCI_DEV_BRIDGE_450KX   0x84C4
 
#define PCI_DEV_BRIDGE_450NX   0x84CB
 
#define BRIDGE_450KX_REV_B0   0x04
 
#define BRIDGE_450NX_REV_B0   0x00
 
#define BRIDGE_450NX_REV_B1   0x02
 
#define BRIDGE_450NX_REV_C0   0x04
 
#define PXB_REG_CONFIG   0x40
 
#define PXB_CONFIG_BUF_RESTREAM   0x0040
 
#define PXB_CONFIG_PCI_BUS_LOCK   0x4000
 
#define PIIX_REG_IDETIM(Channel)   (0x40 + ((Channel) * 2))
 
#define MPIIX_REG_IDETIM   0x6C
 
#define PIIX_IDETIM_TIME(Drive)   (0x0001 << (4 * (Drive)))
 
#define PIIX_IDETIM_IE(Drive)   (0x0002 << (4 * (Drive)))
 
#define PIIX_IDETIM_PPE(Drive)   (0x0004 << (4 * (Drive)))
 
#define PIIX_IDETIM_DTE(Drive)   (0x0008 << (4 * (Drive)))
 
#define PIIX_IDETIM_RCT_MASK   0x0300
 
#define PIIX_IDETIM_RSV_MASK   0x0C00
 
#define PIIX_IDETIM_ISP_MASK   0x3000
 
#define PIIX_IDETIM_SITRE   0x4000
 
#define PIIX_IDETIM_SECONDARY   0x4000
 
#define PIIX_IDETIM_IDE   0x8000
 
#define PIIX_IDETIM_RCT(Value)   ((Value) << 8)
 
#define PIIX_IDETIM_ISP(Value)   ((Value) << 12)
 
#define PIIX_IDETIM_SETTINGS(Drive, Value)   ((Value) << (4 * (Drive)))
 
#define PIIX_REG_SIDETIM   0x44
 
#define PIIX_SIDETIM_ISPRCT_MASK(Channel)   (0x0F << ((Channel) * 4))
 
#define PIIX_SIDETIM_RCT(Channel, Value)   ((Value) << ((Channel) * 4))
 
#define PIIX_SIDETIM_ISP(Channel, Value)   ((Value) << (((Channel) * 4) + 2))
 
#define PIIX_REG_UDMACTL   0x48
 
#define PIIX_UDMACTL_EN_MASK(Channel)   (0x03 << ((Channel) * 2))
 
#define PIIX_UDMACTL_EN(Channel, Drive)   (0x01 << ((Channel) * 2 + (Drive)))
 
#define PIIX_REG_UDMATIM(Channel)   (0x4A + (Channel))
 
#define PIIX_UDMATIM_CT_MASK   0x33
 
#define PIIX_UDMATIM_CT(Drive, Value)   ((Value) << ((Drive) * 4))
 
#define PIIX_REG_CONFIG   0x54
 
#define PIIX_CONFIG_KEEP_MASK   0x0FF0
 
#define PIIX_CONFIG_CR(Channel)   (0x0030 << ((Channel) * 2))
 
#define PIIX_CONFIG_CLOCK_UDMA66(Channel, Drive)   (0x0001 << (((Channel) * 2) + Drive))
 
#define PIIX_CONFIG_CLOCK_UDMA100(Channel, Drive)   (0x1000 << (((Channel) * 2) + Drive))
 
#define PIIX_CONFIG_WR_PING_PONG   0x0400
 
#define SCH_REG_DTIM(Drive)   (0x80 + (Drive) * 4)
 
#define SCH_DTIM_PM_MASK   0x00000007
 
#define SCH_DTIM_MDM_MASK   0x00000300
 
#define SCH_DTIM_UDM_MASK   0x00070000
 
#define SCH_DTIM_PPE   0x40000000
 
#define SCH_DTIM_USD   0x80000000
 
#define SCH_DTIM_PM(Mode)   (Mode)
 
#define SCH_DTIM_MDM(Mode)   ((Mode) << 8)
 
#define SCH_DTIM_UDM(Mode)   ((Mode) << 16)
 
#define HW_FLAGS_TYPE_MASK   0x000F
 
#define HW_FLAGS_DISABLE_DMA   0x0010
 
#define HW_FLAGS_HAS_CFG_REG   0x0080
 
#define HW_FLAGS_HAS_UDMA_REG   0x8000
 
#define TYPE_MPIIX   0
 
#define TYPE_PIIX   1
 
#define TYPE_PIIX3   2
 
#define TYPE_PIIX4   (3 | HW_FLAGS_HAS_UDMA_REG)
 
#define TYPE_ICH   (4 | HW_FLAGS_HAS_UDMA_REG | HW_FLAGS_HAS_CFG_REG)
 
#define TYPE_SATA   5
 
#define TYPE_SCH   6
 

Typedefs

typedef struct _INTEL_CONTROLLER_INFO INTEL_CONTROLLER_INFO
 
typedef struct _INTEL_CONTROLLER_INFO * PINTEL_CONTROLLER_INFO
 
typedef struct _INTEL_HW_EXTENSION INTEL_HW_EXTENSION
 
typedef struct _INTEL_HW_EXTENSION * PINTEL_HW_EXTENSION
 

Functions

static VOID IntelPiixChooseDeviceSpeed (_In_ ULONG Channel, _In_ PCHANNEL_DEVICE_CONFIG Device)
 
static VOID IntelPiixSetTransferMode (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
 
static VOID IntelSchSetTransferMode (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
 
static VOID IntelPiixLegacyPrepareIo (_In_ PVOID ChannelContext, _In_ PATA_DEVICE_REQUEST Request)
 
static USHORT IntelPiixLegacyComputeIdeTiming (_In_ PCHANNEL_DEVICE_CONFIG Device, _In_ ULONG Number, _In_ ULONG Mode)
 
static VOID IntelPiixLegacySetTransferMode (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
 
static BOOLEAN IntelPciBridgeErrataMatch (_In_ PVOID Context, _In_ ULONG BusNumber, _In_ PCI_SLOT_NUMBER PciSlot, _In_ PPCI_COMMON_HEADER PciConfig)
 
static VOID IntelInitChannel (_In_ PATA_CONTROLLER Controller, _In_ const INTEL_CONTROLLER_INFO *ControllerInfo, _In_ PCHANNEL_DATA_PATA ChanData)
 
NTSTATUS IntelGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
 

Variables

static PCIIDEX_PAGED_DATA const INTEL_CONTROLLER_INFO IntelControllerList []
 
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelPiixEnableBits [MAX_IDE_CHANNEL]
 
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelMpiixEnableBits [MAX_IDE_CHANNEL]
 
static const UCHAR IntelClockSettings [5][2]
 
static const ULONG IntelTimingModeToCycleTime [5]
 
static const UCHAR IntelModeSettings []
 
static const UCHAR IntelUdmaSettings []
 
static const ULONG IntelDmaModeToTimingMode []
 

Macro Definition Documentation

◆ BRIDGE_450KX_REV_B0

#define BRIDGE_450KX_REV_B0   0x04

Definition at line 143 of file intel.c.

◆ BRIDGE_450NX_REV_B0

#define BRIDGE_450NX_REV_B0   0x00

Definition at line 145 of file intel.c.

◆ BRIDGE_450NX_REV_B1

#define BRIDGE_450NX_REV_B1   0x02

Definition at line 146 of file intel.c.

◆ BRIDGE_450NX_REV_C0

#define BRIDGE_450NX_REV_C0   0x04

Definition at line 147 of file intel.c.

◆ HW_FLAGS_DISABLE_DMA

#define HW_FLAGS_DISABLE_DMA   0x0010

Definition at line 245 of file intel.c.

◆ HW_FLAGS_HAS_CFG_REG

#define HW_FLAGS_HAS_CFG_REG   0x0080

Definition at line 246 of file intel.c.

◆ HW_FLAGS_HAS_UDMA_REG

#define HW_FLAGS_HAS_UDMA_REG   0x8000

Definition at line 247 of file intel.c.

◆ HW_FLAGS_TYPE_MASK

#define HW_FLAGS_TYPE_MASK   0x000F

Definition at line 244 of file intel.c.

◆ MPIIX_REG_IDETIM

#define MPIIX_REG_IDETIM   0x6C

Definition at line 164 of file intel.c.

◆ PCI_DEV_ATOM_C2000_1

#define PCI_DEV_ATOM_C2000_1   0x1F20

Definition at line 113 of file intel.c.

◆ PCI_DEV_ATOM_C2000_2

#define PCI_DEV_ATOM_C2000_2   0x1F21

Definition at line 114 of file intel.c.

◆ PCI_DEV_ATOM_C2000_3

#define PCI_DEV_ATOM_C2000_3   0x1F30

Definition at line 115 of file intel.c.

◆ PCI_DEV_ATOM_C2000_4

#define PCI_DEV_ATOM_C2000_4   0x1F31

Definition at line 116 of file intel.c.

◆ PCI_DEV_ATOM_E3800_1

#define PCI_DEV_ATOM_E3800_1   0x0F20

Definition at line 127 of file intel.c.

◆ PCI_DEV_ATOM_E3800_2

#define PCI_DEV_ATOM_E3800_2   0x0F21

Definition at line 128 of file intel.c.

◆ PCI_DEV_BRIDGE_450KX

#define PCI_DEV_BRIDGE_450KX   0x84C4

Definition at line 140 of file intel.c.

◆ PCI_DEV_BRIDGE_450NX

#define PCI_DEV_BRIDGE_450NX   0x84CB

Definition at line 141 of file intel.c.

◆ PCI_DEV_C_ICH_82801E

#define PCI_DEV_C_ICH_82801E   0x245B

Definition at line 41 of file intel.c.

◆ PCI_DEV_EP80579

#define PCI_DEV_EP80579   0x5028

Definition at line 88 of file intel.c.

◆ PCI_DEV_ESB2_63XXESB

#define PCI_DEV_ESB2_63XXESB   0x2680

Definition at line 62 of file intel.c.

◆ PCI_DEV_ICH0_82801AB

#define PCI_DEV_ICH0_82801AB   0x2421

Definition at line 36 of file intel.c.

◆ PCI_DEV_ICH10_82801JD_1

#define PCI_DEV_ICH10_82801JD_1   0x3A00

Definition at line 81 of file intel.c.

◆ PCI_DEV_ICH10_82801JD_2

#define PCI_DEV_ICH10_82801JD_2   0x3A06

Definition at line 82 of file intel.c.

◆ PCI_DEV_ICH10_82801JI_1

#define PCI_DEV_ICH10_82801JI_1   0x3A20

Definition at line 83 of file intel.c.

◆ PCI_DEV_ICH10_82801JI_2

#define PCI_DEV_ICH10_82801JI_2   0x3A26

Definition at line 84 of file intel.c.

◆ PCI_DEV_ICH2_82801BA

#define PCI_DEV_ICH2_82801BA   0x244B

Definition at line 39 of file intel.c.

◆ PCI_DEV_ICH2_82801BAM

#define PCI_DEV_ICH2_82801BAM   0x244A

Definition at line 38 of file intel.c.

◆ PCI_DEV_ICH3_M_82801CAM

#define PCI_DEV_ICH3_M_82801CAM   0x248A

Definition at line 43 of file intel.c.

◆ PCI_DEV_ICH3_S_82801CA

#define PCI_DEV_ICH3_S_82801CA   0x248B

Definition at line 44 of file intel.c.

◆ PCI_DEV_ICH4_82801DB

#define PCI_DEV_ICH4_82801DB   0x24CB

Definition at line 48 of file intel.c.

◆ PCI_DEV_ICH4_L_82801DBL

#define PCI_DEV_ICH4_L_82801DBL   0x24C1

Definition at line 46 of file intel.c.

◆ PCI_DEV_ICH4_M_82801DBM

#define PCI_DEV_ICH4_M_82801DBM   0x24CA

Definition at line 47 of file intel.c.

◆ PCI_DEV_ICH5_6300ESB_IDE

#define PCI_DEV_ICH5_6300ESB_IDE   0x25A2

Definition at line 53 of file intel.c.

◆ PCI_DEV_ICH5_6300ESB_RAID

#define PCI_DEV_ICH5_6300ESB_RAID   0x25B0

Definition at line 55 of file intel.c.

◆ PCI_DEV_ICH5_6300ESB_SATA

#define PCI_DEV_ICH5_6300ESB_SATA   0x25A3

Definition at line 54 of file intel.c.

◆ PCI_DEV_ICH5_82801EB_IDE

#define PCI_DEV_ICH5_82801EB_IDE   0x24DB

Definition at line 51 of file intel.c.

◆ PCI_DEV_ICH5_82801EB_SATA

#define PCI_DEV_ICH5_82801EB_SATA   0x24D1

Definition at line 50 of file intel.c.

◆ PCI_DEV_ICH5_R_82801ER

#define PCI_DEV_ICH5_R_82801ER   0x24DF

Definition at line 52 of file intel.c.

◆ PCI_DEV_ICH6_82801FB_IDE

#define PCI_DEV_ICH6_82801FB_IDE   0x266F

Definition at line 60 of file intel.c.

◆ PCI_DEV_ICH6_82801FB_SATA

#define PCI_DEV_ICH6_82801FB_SATA   0x2651

Definition at line 57 of file intel.c.

◆ PCI_DEV_ICH6_M_82801FBM

#define PCI_DEV_ICH6_M_82801FBM   0x2653

Definition at line 59 of file intel.c.

◆ PCI_DEV_ICH6_R_82801FB

#define PCI_DEV_ICH6_R_82801FB   0x2652

Definition at line 58 of file intel.c.

◆ PCI_DEV_ICH7_6321ESB

#define PCI_DEV_ICH7_6321ESB   0x269E

Definition at line 64 of file intel.c.

◆ PCI_DEV_ICH7_82801G

#define PCI_DEV_ICH7_82801G   0x27DF

Definition at line 67 of file intel.c.

◆ PCI_DEV_ICH7_82801GB

#define PCI_DEV_ICH7_82801GB   0x27C0

Definition at line 65 of file intel.c.

◆ PCI_DEV_ICH7_M_82801GBM

#define PCI_DEV_ICH7_M_82801GBM   0x27C4

Definition at line 66 of file intel.c.

◆ PCI_DEV_ICH8_82801H

#define PCI_DEV_ICH8_82801H   0x2820

Definition at line 69 of file intel.c.

◆ PCI_DEV_ICH8_M_82801HBM

#define PCI_DEV_ICH8_M_82801HBM   0x2850

Definition at line 72 of file intel.c.

◆ PCI_DEV_ICH8_M_82801HM

#define PCI_DEV_ICH8_M_82801HM   0x2828

Definition at line 71 of file intel.c.

◆ PCI_DEV_ICH8_R_82801HR

#define PCI_DEV_ICH8_R_82801HR   0x2825

Definition at line 70 of file intel.c.

◆ PCI_DEV_ICH9_82801I

#define PCI_DEV_ICH9_82801I   0x2926

Definition at line 76 of file intel.c.

◆ PCI_DEV_ICH9_M_82801IBM_1

#define PCI_DEV_ICH9_M_82801IBM_1   0x2928

Definition at line 77 of file intel.c.

◆ PCI_DEV_ICH9_M_82801IBM_2

#define PCI_DEV_ICH9_M_82801IBM_2   0x292D

Definition at line 78 of file intel.c.

◆ PCI_DEV_ICH9_M_82801IBM_3

#define PCI_DEV_ICH9_M_82801IBM_3   0x292E

Definition at line 79 of file intel.c.

◆ PCI_DEV_ICH9_R_82801IR_1

#define PCI_DEV_ICH9_R_82801IR_1   0x2920

Definition at line 74 of file intel.c.

◆ PCI_DEV_ICH9_R_82801IR_2

#define PCI_DEV_ICH9_R_82801IR_2   0x2921

Definition at line 75 of file intel.c.

◆ PCI_DEV_ICH_82801AA

#define PCI_DEV_ICH_82801AA   0x2411

Definition at line 34 of file intel.c.

◆ PCI_DEV_MPIIX_82371MX

#define PCI_DEV_MPIIX_82371MX   0x1234

Definition at line 25 of file intel.c.

◆ PCI_DEV_PCH_5SERIES_1

#define PCI_DEV_PCH_5SERIES_1   0x3B20

Definition at line 90 of file intel.c.

◆ PCI_DEV_PCH_5SERIES_2

#define PCI_DEV_PCH_5SERIES_2   0x3B21

Definition at line 91 of file intel.c.

◆ PCI_DEV_PCH_5SERIES_3

#define PCI_DEV_PCH_5SERIES_3   0x3B26

Definition at line 92 of file intel.c.

◆ PCI_DEV_PCH_5SERIES_4

#define PCI_DEV_PCH_5SERIES_4   0x3B28

Definition at line 93 of file intel.c.

◆ PCI_DEV_PCH_5SERIES_5

#define PCI_DEV_PCH_5SERIES_5   0x3B2D

Definition at line 94 of file intel.c.

◆ PCI_DEV_PCH_5SERIES_6

#define PCI_DEV_PCH_5SERIES_6   0x3B2E

Definition at line 95 of file intel.c.

◆ PCI_DEV_PCH_6SERIES_1

#define PCI_DEV_PCH_6SERIES_1   0x1C00

Definition at line 97 of file intel.c.

◆ PCI_DEV_PCH_6SERIES_2

#define PCI_DEV_PCH_6SERIES_2   0x1C01

Definition at line 98 of file intel.c.

◆ PCI_DEV_PCH_6SERIES_3

#define PCI_DEV_PCH_6SERIES_3   0x1C08

Definition at line 99 of file intel.c.

◆ PCI_DEV_PCH_6SERIES_4

#define PCI_DEV_PCH_6SERIES_4   0x1C09

Definition at line 100 of file intel.c.

◆ PCI_DEV_PCH_7SERIES_1

#define PCI_DEV_PCH_7SERIES_1   0x1E00

Definition at line 102 of file intel.c.

◆ PCI_DEV_PCH_7SERIES_2

#define PCI_DEV_PCH_7SERIES_2   0x1E01

Definition at line 103 of file intel.c.

◆ PCI_DEV_PCH_7SERIES_3

#define PCI_DEV_PCH_7SERIES_3   0x1E08

Definition at line 104 of file intel.c.

◆ PCI_DEV_PCH_7SERIES_4

#define PCI_DEV_PCH_7SERIES_4   0x1E09

Definition at line 105 of file intel.c.

◆ PCI_DEV_PCH_8900_1

#define PCI_DEV_PCH_8900_1   0x2326

Definition at line 110 of file intel.c.

◆ PCI_DEV_PCH_8900_2

#define PCI_DEV_PCH_8900_2   0x23A6

Definition at line 111 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_1

#define PCI_DEV_PCH_8SERIES_1   0x8C00

Definition at line 118 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_2

#define PCI_DEV_PCH_8SERIES_2   0x8C01

Definition at line 119 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_3

#define PCI_DEV_PCH_8SERIES_3   0x8C08

Definition at line 120 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_4

#define PCI_DEV_PCH_8SERIES_4   0x8C09

Definition at line 121 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_5

#define PCI_DEV_PCH_8SERIES_5   0x9C00

Definition at line 122 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_6

#define PCI_DEV_PCH_8SERIES_6   0x9C01

Definition at line 123 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_7

#define PCI_DEV_PCH_8SERIES_7   0x9C08

Definition at line 124 of file intel.c.

◆ PCI_DEV_PCH_8SERIES_8

#define PCI_DEV_PCH_8SERIES_8   0x9C09

Definition at line 125 of file intel.c.

◆ PCI_DEV_PCH_9SERIES_1

#define PCI_DEV_PCH_9SERIES_1   0x8C80

Definition at line 135 of file intel.c.

◆ PCI_DEV_PCH_9SERIES_2

#define PCI_DEV_PCH_9SERIES_2   0x8C81

Definition at line 136 of file intel.c.

◆ PCI_DEV_PCH_9SERIES_3

#define PCI_DEV_PCH_9SERIES_3   0x8C88

Definition at line 137 of file intel.c.

◆ PCI_DEV_PCH_9SERIES_4

#define PCI_DEV_PCH_9SERIES_4   0x8C89

Definition at line 138 of file intel.c.

◆ PCI_DEV_PCH_X79_1

#define PCI_DEV_PCH_X79_1   0x1D00

Definition at line 107 of file intel.c.

◆ PCI_DEV_PCH_X79_2

#define PCI_DEV_PCH_X79_2   0x1D08

Definition at line 108 of file intel.c.

◆ PCI_DEV_PCH_X99_1

#define PCI_DEV_PCH_X99_1   0x8D00

Definition at line 130 of file intel.c.

◆ PCI_DEV_PCH_X99_2

#define PCI_DEV_PCH_X99_2   0x8D08

Definition at line 131 of file intel.c.

◆ PCI_DEV_PCH_X99_3

#define PCI_DEV_PCH_X99_3   0x8D60

Definition at line 132 of file intel.c.

◆ PCI_DEV_PCH_X99_4

#define PCI_DEV_PCH_X99_4   0x8D68

Definition at line 133 of file intel.c.

◆ PCI_DEV_PIIX3_82371SB

#define PCI_DEV_PIIX3_82371SB   0x7010

Definition at line 27 of file intel.c.

◆ PCI_DEV_PIIX4_82371AB

#define PCI_DEV_PIIX4_82371AB   0x7111

Definition at line 29 of file intel.c.

◆ PCI_DEV_PIIX4E_82372FB

#define PCI_DEV_PIIX4E_82372FB   0x7601

Definition at line 30 of file intel.c.

◆ PCI_DEV_PIIX4E_82443MX

#define PCI_DEV_PIIX4E_82443MX   0x7199

Definition at line 31 of file intel.c.

◆ PCI_DEV_PIIX4E_82451NX

#define PCI_DEV_PIIX4E_82451NX   0x84CA

Definition at line 32 of file intel.c.

◆ PCI_DEV_PIIX_82371FB

#define PCI_DEV_PIIX_82371FB   0x1230

Definition at line 24 of file intel.c.

◆ PCI_DEV_SCH_ATOM_Z5XX

#define PCI_DEV_SCH_ATOM_Z5XX   0x811A

Definition at line 86 of file intel.c.

◆ PIIX_CONFIG_CLOCK_UDMA100

#define PIIX_CONFIG_CLOCK_UDMA100 (   Channel,
  Drive 
)    (0x1000 << (((Channel) * 2) + Drive))

Definition at line 225 of file intel.c.

◆ PIIX_CONFIG_CLOCK_UDMA66

#define PIIX_CONFIG_CLOCK_UDMA66 (   Channel,
  Drive 
)    (0x0001 << (((Channel) * 2) + Drive))

Definition at line 223 of file intel.c.

◆ PIIX_CONFIG_CR

#define PIIX_CONFIG_CR (   Channel)    (0x0030 << ((Channel) * 2))

Definition at line 221 of file intel.c.

◆ PIIX_CONFIG_KEEP_MASK

#define PIIX_CONFIG_KEEP_MASK   0x0FF0

Definition at line 218 of file intel.c.

◆ PIIX_CONFIG_WR_PING_PONG

#define PIIX_CONFIG_WR_PING_PONG   0x0400

Definition at line 227 of file intel.c.

◆ PIIX_IDETIM_DTE

#define PIIX_IDETIM_DTE (   Drive)    (0x0008 << (4 * (Drive)))

Definition at line 169 of file intel.c.

◆ PIIX_IDETIM_IDE

#define PIIX_IDETIM_IDE   0x8000

Definition at line 176 of file intel.c.

◆ PIIX_IDETIM_IE

#define PIIX_IDETIM_IE (   Drive)    (0x0002 << (4 * (Drive)))

Definition at line 167 of file intel.c.

◆ PIIX_IDETIM_ISP

#define PIIX_IDETIM_ISP (   Value)    ((Value) << 12)

Definition at line 179 of file intel.c.

◆ PIIX_IDETIM_ISP_MASK

#define PIIX_IDETIM_ISP_MASK   0x3000

Definition at line 173 of file intel.c.

◆ PIIX_IDETIM_PPE

#define PIIX_IDETIM_PPE (   Drive)    (0x0004 << (4 * (Drive)))

Definition at line 168 of file intel.c.

◆ PIIX_IDETIM_RCT

#define PIIX_IDETIM_RCT (   Value)    ((Value) << 8)

Definition at line 178 of file intel.c.

◆ PIIX_IDETIM_RCT_MASK

#define PIIX_IDETIM_RCT_MASK   0x0300

Definition at line 171 of file intel.c.

◆ PIIX_IDETIM_RSV_MASK

#define PIIX_IDETIM_RSV_MASK   0x0C00

Definition at line 172 of file intel.c.

◆ PIIX_IDETIM_SECONDARY

#define PIIX_IDETIM_SECONDARY   0x4000

Definition at line 175 of file intel.c.

◆ PIIX_IDETIM_SETTINGS

#define PIIX_IDETIM_SETTINGS (   Drive,
  Value 
)    ((Value) << (4 * (Drive)))

Definition at line 180 of file intel.c.

◆ PIIX_IDETIM_SITRE

#define PIIX_IDETIM_SITRE   0x4000

Definition at line 174 of file intel.c.

◆ PIIX_IDETIM_TIME

#define PIIX_IDETIM_TIME (   Drive)    (0x0001 << (4 * (Drive)))

Definition at line 166 of file intel.c.

◆ PIIX_REG_CONFIG

#define PIIX_REG_CONFIG   0x54

Definition at line 216 of file intel.c.

◆ PIIX_REG_IDETIM

#define PIIX_REG_IDETIM (   Channel)    (0x40 + ((Channel) * 2))

Definition at line 163 of file intel.c.

◆ PIIX_REG_SIDETIM

#define PIIX_REG_SIDETIM   0x44

Definition at line 185 of file intel.c.

◆ PIIX_REG_UDMACTL

#define PIIX_REG_UDMACTL   0x48

Definition at line 194 of file intel.c.

◆ PIIX_REG_UDMATIM

#define PIIX_REG_UDMATIM (   Channel)    (0x4A + (Channel))

Definition at line 206 of file intel.c.

◆ PIIX_SIDETIM_ISP

#define PIIX_SIDETIM_ISP (   Channel,
  Value 
)    ((Value) << (((Channel) * 4) + 2))

Definition at line 189 of file intel.c.

◆ PIIX_SIDETIM_ISPRCT_MASK

#define PIIX_SIDETIM_ISPRCT_MASK (   Channel)    (0x0F << ((Channel) * 4))

Definition at line 187 of file intel.c.

◆ PIIX_SIDETIM_RCT

#define PIIX_SIDETIM_RCT (   Channel,
  Value 
)    ((Value) << ((Channel) * 4))

Definition at line 188 of file intel.c.

◆ PIIX_UDMACTL_EN

#define PIIX_UDMACTL_EN (   Channel,
  Drive 
)    (0x01 << ((Channel) * 2 + (Drive)))

Definition at line 199 of file intel.c.

◆ PIIX_UDMACTL_EN_MASK

#define PIIX_UDMACTL_EN_MASK (   Channel)    (0x03 << ((Channel) * 2))

Definition at line 196 of file intel.c.

◆ PIIX_UDMATIM_CT

#define PIIX_UDMATIM_CT (   Drive,
  Value 
)    ((Value) << ((Drive) * 4))

Definition at line 211 of file intel.c.

◆ PIIX_UDMATIM_CT_MASK

#define PIIX_UDMATIM_CT_MASK   0x33

Definition at line 208 of file intel.c.

◆ PXB_CONFIG_BUF_RESTREAM

#define PXB_CONFIG_BUF_RESTREAM   0x0040

Definition at line 154 of file intel.c.

◆ PXB_CONFIG_PCI_BUS_LOCK

#define PXB_CONFIG_PCI_BUS_LOCK   0x4000

Definition at line 155 of file intel.c.

◆ PXB_REG_CONFIG

#define PXB_REG_CONFIG   0x40

Definition at line 152 of file intel.c.

◆ SCH_DTIM_MDM

#define SCH_DTIM_MDM (   Mode)    ((Mode) << 8)

Definition at line 241 of file intel.c.

◆ SCH_DTIM_MDM_MASK

#define SCH_DTIM_MDM_MASK   0x00000300

Definition at line 235 of file intel.c.

◆ SCH_DTIM_PM

#define SCH_DTIM_PM (   Mode)    (Mode)

Definition at line 240 of file intel.c.

◆ SCH_DTIM_PM_MASK

#define SCH_DTIM_PM_MASK   0x00000007

Definition at line 234 of file intel.c.

◆ SCH_DTIM_PPE

#define SCH_DTIM_PPE   0x40000000

Definition at line 237 of file intel.c.

◆ SCH_DTIM_UDM

#define SCH_DTIM_UDM (   Mode)    ((Mode) << 16)

Definition at line 242 of file intel.c.

◆ SCH_DTIM_UDM_MASK

#define SCH_DTIM_UDM_MASK   0x00070000

Definition at line 236 of file intel.c.

◆ SCH_DTIM_USD

#define SCH_DTIM_USD   0x80000000

Definition at line 238 of file intel.c.

◆ SCH_REG_DTIM

#define SCH_REG_DTIM (   Drive)    (0x80 + (Drive) * 4)

Definition at line 232 of file intel.c.

◆ TYPE_ICH

#define TYPE_ICH   (4 | HW_FLAGS_HAS_UDMA_REG | HW_FLAGS_HAS_CFG_REG)

Definition at line 257 of file intel.c.

◆ TYPE_MPIIX

#define TYPE_MPIIX   0

Definition at line 253 of file intel.c.

◆ TYPE_PIIX

#define TYPE_PIIX   1

Definition at line 254 of file intel.c.

◆ TYPE_PIIX3

#define TYPE_PIIX3   2

Definition at line 255 of file intel.c.

◆ TYPE_PIIX4

#define TYPE_PIIX4   (3 | HW_FLAGS_HAS_UDMA_REG)

Definition at line 256 of file intel.c.

◆ TYPE_SATA

#define TYPE_SATA   5

Definition at line 258 of file intel.c.

◆ TYPE_SCH

#define TYPE_SCH   6

Definition at line 259 of file intel.c.

Typedef Documentation

◆ INTEL_CONTROLLER_INFO

typedef struct _INTEL_CONTROLLER_INFO INTEL_CONTROLLER_INFO

◆ INTEL_HW_EXTENSION

typedef struct _INTEL_HW_EXTENSION INTEL_HW_EXTENSION

◆ PINTEL_CONTROLLER_INFO

typedef struct _INTEL_CONTROLLER_INFO * PINTEL_CONTROLLER_INFO

◆ PINTEL_HW_EXTENSION

typedef struct _INTEL_HW_EXTENSION * PINTEL_HW_EXTENSION

Function Documentation

◆ IntelGetControllerProperties()

NTSTATUS IntelGetControllerProperties ( _Inout_ PATA_CONTROLLER  Controller)

Definition at line 969 of file intel.c.

971{
972 const INTEL_CONTROLLER_INFO* ControllerInfo;
973 ULONG i, ExtensionSize, HwFlags;
974 NTSTATUS Status;
975
976 PAGED_CODE();
977 ASSERT(Controller->Pci.VendorID == PCI_VEN_INTEL);
978
979 for (i = 0; i < RTL_NUMBER_OF(IntelControllerList); ++i)
980 {
981 ControllerInfo = &IntelControllerList[i];
982
983 if (Controller->Pci.DeviceID == ControllerInfo->DeviceID)
984 break;
985 }
986 if (i == RTL_NUMBER_OF(IntelControllerList))
987 return STATUS_NO_MATCH;
988
989 Controller->Flags |= CTRL_FLAG_DMA_INTERRUPT;
990
991 if (ControllerInfo->Type == TYPE_SCH)
992 Controller->MaxChannels = 1;
993
994 if (ControllerInfo->Type == TYPE_PIIX || ControllerInfo->Type == TYPE_MPIIX)
995 ExtensionSize = sizeof(INTEL_HW_EXTENSION);
996 else
997 ExtensionSize = 0;
998
999 Status = PciIdeCreateChannelData(Controller, ExtensionSize);
1000 if (!NT_SUCCESS(Status))
1001 return Status;
1002
1003 switch (ControllerInfo->Type)
1004 {
1005 case TYPE_MPIIX:
1006 /*
1007 * This is a bridge device and there are no PCI BAR resources allocated,
1008 * so mark the controller as a legacy device.
1009 */
1010 Controller->Flags &= ~CTRL_FLAG_NATIVE_PCI;
1011 Controller->ChannelEnableBits = IntelMpiixEnableBits;
1012 break;
1013
1014 case TYPE_PIIX:
1015 case TYPE_PIIX3:
1016 case TYPE_PIIX4:
1017 case TYPE_ICH:
1018 Controller->ChannelEnableBits = IntelPiixEnableBits;
1019 break;
1020
1021 case TYPE_SATA:
1022 // TODO: Implement the map support
1023 //Controller->ChannelEnabledTest = IntelCombinedEnabledTest;
1024 //HwFlags = TYPE_ICH;
1025 break;
1026
1027 default:
1028 break;
1029 }
1030 HwFlags = ControllerInfo->Type;
1031
1032 if (PciFindDevice(IntelPciBridgeErrataMatch, NULL))
1033 HwFlags |= HW_FLAGS_DISABLE_DMA;
1034
1035 for (i = 0; i < Controller->MaxChannels; ++i)
1036 {
1037 PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
1038
1039 ChanData->HwFlags = HwFlags;
1040
1041 IntelInitChannel(Controller, ControllerInfo, ChanData);
1042
1043 if (HwFlags & HW_FLAGS_DISABLE_DMA)
1044 ChanData->TransferModeSupported &= PIO_ALL;
1045 }
1046
1047 return STATUS_SUCCESS;
1048}
PAGED_CODE
#define PAGED_CODE()
Definition: Bus_PDO_EvalMethod.c:89
RTL_NUMBER_OF
#define RTL_NUMBER_OF(x)
Definition: RtlRegistry.c:12
PIO_ALL
#define PIO_ALL
Definition: ata_user.h:19
NTSTATUS
LONG NTSTATUS
Definition: precomp.h:26
NULL
#define NULL
Definition: types.h:112
NT_SUCCESS
#define NT_SUCCESS(StatCode)
Definition: apphelp.c:33
Status
Status
Definition: gdiplustypes.h:25
i
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
IntelInitChannel
static VOID IntelInitChannel(_In_ PATA_CONTROLLER Controller, _In_ const INTEL_CONTROLLER_INFO *ControllerInfo, _In_ PCHANNEL_DATA_PATA ChanData)
Definition: intel.c:836
IntelPciBridgeErrataMatch
static BOOLEAN IntelPciBridgeErrataMatch(_In_ PVOID Context, _In_ ULONG BusNumber, _In_ PCI_SLOT_NUMBER PciSlot, _In_ PPCI_COMMON_HEADER PciConfig)
Definition: intel.c:772
TYPE_PIIX4
#define TYPE_PIIX4
Definition: intel.c:256
TYPE_SCH
#define TYPE_SCH
Definition: intel.c:259
IntelPiixEnableBits
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelPiixEnableBits[MAX_IDE_CHANNEL]
Definition: intel.c:366
TYPE_PIIX
#define TYPE_PIIX
Definition: intel.c:254
IntelMpiixEnableBits
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelMpiixEnableBits[MAX_IDE_CHANNEL]
Definition: intel.c:373
TYPE_ICH
#define TYPE_ICH
Definition: intel.c:257
TYPE_MPIIX
#define TYPE_MPIIX
Definition: intel.c:253
HW_FLAGS_DISABLE_DMA
#define HW_FLAGS_DISABLE_DMA
Definition: intel.c:245
TYPE_PIIX3
#define TYPE_PIIX3
Definition: intel.c:255
IntelControllerList
static PCIIDEX_PAGED_DATA const INTEL_CONTROLLER_INFO IntelControllerList[]
Definition: intel.c:273
TYPE_SATA
#define TYPE_SATA
Definition: intel.c:258
INTEL_HW_EXTENSION
struct _INTEL_HW_EXTENSION INTEL_HW_EXTENSION
ASSERT
#define ASSERT(a)
Definition: mode.c:44
STATUS_NO_MATCH
#define STATUS_NO_MATCH
Definition: ntstatus.h:873
PCI_VEN_INTEL
#define PCI_VEN_INTEL
Definition: pata.h:19
PciIdeCreateChannelData
NTSTATUS PciIdeCreateChannelData(_In_ PATA_CONTROLLER Controller, _In_ ULONG HwExtensionSize)
Definition: pata_generic.c:1072
PciFindDevice
BOOLEAN PciFindDevice(_In_ __callback PATA_PCI_MATCH_FN MatchFunction, _In_ PVOID Context)
Definition: pciidex.c:13
CTRL_FLAG_DMA_INTERRUPT
#define CTRL_FLAG_DMA_INTERRUPT
Definition: pciidex.h:230
ExtensionSize
WORD ExtensionSize
Definition: apisets.c:17
STATUS_SUCCESS
#define STATUS_SUCCESS
Definition: shellext.h:65
_CHANNEL_DATA_PATA
Definition: pciidex.h:293
_CHANNEL_DATA_PATA::HwFlags
ULONG HwFlags
Definition: pciidex.h:316
_INTEL_CONTROLLER_INFO
Definition: intel.c:250
_INTEL_CONTROLLER_INFO::DeviceID
USHORT DeviceID
Definition: intel.c:251
_INTEL_CONTROLLER_INFO::Type
USHORT Type
Definition: intel.c:252
ULONG
uint32_t ULONG
Definition: typedefs.h:59

Referenced by PciIdeGetControllerProperties().

◆ IntelInitChannel()

static VOID IntelInitChannel ( _In_ PATA_CONTROLLER  Controller,
_In_ const INTEL_CONTROLLER_INFO *  ControllerInfo,
_In_ PCHANNEL_DATA_PATA  ChanData 
)
static

Definition at line 836 of file intel.c.

840{
841 ULONG SupportedMode;
842
843 PAGED_CODE();
844
845 switch (ControllerInfo->Type)
846 {
847 case TYPE_MPIIX:
848 case TYPE_PIIX:
849 {
850 PINTEL_HW_EXTENSION HwExt = (PVOID)ChanData->HwExt;
851
852 if (ControllerInfo->Type == TYPE_MPIIX)
853 HwExt->Register = MPIIX_REG_IDETIM;
854 else
855 HwExt->Register = PIIX_REG_IDETIM(ChanData->Channel);
856
857 ChanData->SetTransferMode = IntelPiixLegacySetTransferMode;
858 ChanData->PrepareIo = IntelPiixLegacyPrepareIo;
859 break;
860 }
861
862 case TYPE_PIIX3:
863 case TYPE_PIIX4:
864 case TYPE_ICH:
865 ChanData->SetTransferMode = IntelPiixSetTransferMode;
866 break;
867
868 case TYPE_SCH:
869 ChanData->SetTransferMode = IntelSchSetTransferMode;
870 break;
871
872 default:
873 ChanData->SetTransferMode = SataSetTransferMode;
874 break;
875 }
876
877 switch (ControllerInfo->Type)
878 {
879 case TYPE_MPIIX:
880 SupportedMode = PIO_ALL;
881 break;
882
883 case TYPE_PIIX:
884 case TYPE_PIIX3:
885 SupportedMode = PIO_ALL | SWDMA_MODE2 | MWDMA_MODES(1, 2);
886 break;
887
888 case TYPE_PIIX4:
889 SupportedMode = PIO_ALL | SWDMA_MODE2 | MWDMA_MODES(1, 2) | UDMA_MODES(0, 2);
890 break;
891
892 case TYPE_ICH:
893 {
894 /* Errata: MW DMA Mode-1 Tdh (unable to drive MWDMA1 and SWDMA2 timings) */
895 SupportedMode = PIO_ALL | MWDMA_MODE2 | UDMA_MODES(0, 5);
896
897 if (Controller->Pci.DeviceID == PCI_DEV_ICH_82801AA ||
898 Controller->Pci.DeviceID == PCI_DEV_ICH0_82801AB)
899 {
900 /* Errata: IDE Bus Master Concurrency */
901 if (Controller->Pci.RevisionID == 0)
902 {
903 SupportedMode = PIO_ALL;
904 }
905 else
906 {
907 /* ICH is UDMA4 */
908 SupportedMode &= ~UDMA_MODE5;
909
910 /* ICH0 is UDMA2 */
911 if (Controller->Pci.DeviceID == PCI_DEV_ICH0_82801AB)
912 SupportedMode &= ~(UDMA_MODE3 | UDMA_MODE4);
913 }
914 }
915
916 /* Check for 80-conductor cable */
917 if (SupportedMode & UDMA_80C_ALL)
918 {
919 USHORT IdeConfigReg = PciRead16(Controller, PIIX_REG_CONFIG);
920 if (!(IdeConfigReg & PIIX_CONFIG_CR(ChanData->Channel)))
921 {
922 INFO("CH %lu: BIOS detected 40-conductor cable\n", ChanData->Channel);
923 SupportedMode &= ~UDMA_80C_ALL;
924 }
925 }
926 break;
927 }
928
929 case TYPE_SCH:
930 {
931 ULONG DeviceTimingReg[2];
932
933 SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 5);
934
935 /* Check for 80-conductor cable */
936 PciRead(Controller, &DeviceTimingReg, SCH_REG_DTIM(0), sizeof(DeviceTimingReg));
937 if ((DeviceTimingReg[0] & SCH_DTIM_UDM_MASK) <= SCH_DTIM_UDM(2) &&
938 (DeviceTimingReg[1] & SCH_DTIM_UDM_MASK) <= SCH_DTIM_UDM(2))
939 {
940 INFO("CH %lu: BIOS hasn't selected mode faster than UDMA 2, "
941 "assume 40-conductor cable\n",
942 ChanData->Channel);
943 SupportedMode &= ~UDMA_80C_ALL;
944 }
945 break;
946 }
947
948 case TYPE_SATA:
949 {
950 SupportedMode = SATA_ALL;
951
952 // TODO: Read the port map register and set CHANNEL_FLAG_NO_SLAVE when appropriate
953 ERR("CH %lu: PMR %02X PCS %04X\n",
954 ChanData->Channel,
955 PciRead8(Controller, 0x90),
956 PciRead16(Controller, 0x92));
957 break;
958 }
959
960 default:
961 ASSERT(FALSE);
962 UNREACHABLE;
963 }
964 ChanData->TransferModeSupported = SupportedMode;
965}
MWDMA_ALL
#define MWDMA_ALL
Definition: ata_user.h:27
ERR
#define ERR(fmt,...)
Definition: precomp.h:57
FALSE
#define FALSE
Definition: types.h:117
INFO
#define INFO
Definition: debug.h:89
SWDMA_MODE2
#define SWDMA_MODE2
Definition: ide.h:285
UDMA_MODE4
#define UDMA_MODE4
Definition: ide.h:295
MWDMA_MODE2
#define MWDMA_MODE2
Definition: ide.h:289
UDMA_MODE3
#define UDMA_MODE3
Definition: ide.h:294
SCH_DTIM_UDM_MASK
#define SCH_DTIM_UDM_MASK
Definition: intel.c:236
SCH_DTIM_UDM
#define SCH_DTIM_UDM(Mode)
Definition: intel.c:242
SCH_REG_DTIM
#define SCH_REG_DTIM(Drive)
Definition: intel.c:232
IntelSchSetTransferMode
static VOID IntelSchSetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: intel.c:622
PCI_DEV_ICH_82801AA
#define PCI_DEV_ICH_82801AA
Definition: intel.c:34
PIIX_REG_CONFIG
#define PIIX_REG_CONFIG
Definition: intel.c:216
IntelPiixLegacySetTransferMode
static VOID IntelPiixLegacySetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: intel.c:729
IntelPiixSetTransferMode
static VOID IntelPiixSetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: intel.c:488
PCI_DEV_ICH0_82801AB
#define PCI_DEV_ICH0_82801AB
Definition: intel.c:36
PIIX_REG_IDETIM
#define PIIX_REG_IDETIM(Channel)
Definition: intel.c:163
MPIIX_REG_IDETIM
#define MPIIX_REG_IDETIM
Definition: intel.c:164
IntelPiixLegacyPrepareIo
static VOID IntelPiixLegacyPrepareIo(_In_ PVOID ChannelContext, _In_ PATA_DEVICE_REQUEST Request)
Definition: intel.c:662
PIIX_CONFIG_CR
#define PIIX_CONFIG_CR(Channel)
Definition: intel.c:221
if
if(dx< 0)
Definition: linetemp.h:194
UNREACHABLE
#define UNREACHABLE
SATA_ALL
#define SATA_ALL
Definition: pata.h:37
UDMA_MODES
#define UDMA_MODES(MinMode, MaxMode)
Definition: pata.h:49
MWDMA_MODES
#define MWDMA_MODES(MinMode, MaxMode)
Definition: pata.h:45
UDMA_80C_ALL
#define UDMA_80C_ALL
Definition: pata.h:41
PciRead
VOID PciRead(_In_ PATA_CONTROLLER Controller, _Out_writes_bytes_all_(BufferLength) PVOID Buffer, _In_ ULONG ConfigDataOffset, _In_ ULONG BufferLength)
Definition: pciidex.c:72
PciRead8
FORCEINLINE UCHAR PciRead8(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
Definition: pciidex.h:847
PciRead16
FORCEINLINE USHORT PciRead16(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
Definition: pciidex.h:859
SataSetTransferMode
CHANNEL_SET_MODE_EX SataSetTransferMode
Definition: pciidex.h:633
USHORT
unsigned short USHORT
Definition: pedump.c:61
_INTEL_HW_EXTENSION
Definition: intel.c:263
_INTEL_HW_EXTENSION::Register
ULONG Register
Definition: intel.c:264
PVOID
void * PVOID
Definition: typedefs.h:50

Referenced by IntelGetControllerProperties().

◆ IntelPciBridgeErrataMatch()

static BOOLEAN IntelPciBridgeErrataMatch ( _In_ PVOID  Context,
_In_ ULONG  BusNumber,
_In_ PCI_SLOT_NUMBER  PciSlot,
_In_ PPCI_COMMON_HEADER  PciConfig 
)
static

Definition at line 772 of file intel.c.

777{
778 UNREFERENCED_PARAMETER(Context);
779
780 PAGED_CODE();
781
782 if (PciConfig->VendorID != PCI_VEN_INTEL)
783 return FALSE;
784
785 /* 450KX errata: 0-Byte Length Write failure */
786 if ((PciConfig->DeviceID == PCI_DEV_BRIDGE_450KX) &&
787 (PciConfig->RevisionID < BRIDGE_450KX_REV_B0))
788 {
789 WARN("Enabling workaround for the 450KX #2\n");
790 return TRUE;
791 }
792
793 /* 450NX errata */
794 if (PciConfig->DeviceID == PCI_DEV_BRIDGE_450NX)
795 {
796 USHORT ConfigReg;
797
798 /* PXB livelock */
799 if (PciConfig->RevisionID == BRIDGE_450NX_REV_B0)
800 {
801 WARN("Enabling workaround for the 450NX #19\n");
802 return TRUE;
803 }
804
805 HalGetBusDataByOffset(PCIConfiguration,
806 BusNumber,
807 PciSlot.u.AsULONG,
808 &ConfigReg,
809 PXB_REG_CONFIG,
810 sizeof(ConfigReg));
811 INFO("PXB CFG: %04X\n", ConfigReg);
812
813 /* PXB arbiter deadlock */
814 if ((PciConfig->RevisionID != BRIDGE_450NX_REV_B1) &&
815 (ConfigReg & PXB_CONFIG_PCI_BUS_LOCK))
816 {
817 WARN("Enabling workaround for the 450NX #20\n");
818 return TRUE;
819 }
820
821 /* PCI data corruption */
822 if ((PciConfig->RevisionID == BRIDGE_450NX_REV_C0) &&
823 (ConfigReg & PXB_CONFIG_BUF_RESTREAM))
824 {
825 WARN("Enabling workaround for the 450NX #25\n");
826 return TRUE;
827 }
828 }
829
830 return FALSE;
831}
WARN
#define WARN(fmt,...)
Definition: precomp.h:61
TRUE
#define TRUE
Definition: types.h:120
HalGetBusDataByOffset
ULONG NTAPI HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:73
BRIDGE_450NX_REV_B0
#define BRIDGE_450NX_REV_B0
Definition: intel.c:145
PCI_DEV_BRIDGE_450NX
#define PCI_DEV_BRIDGE_450NX
Definition: intel.c:141
PXB_CONFIG_PCI_BUS_LOCK
#define PXB_CONFIG_PCI_BUS_LOCK
Definition: intel.c:155
PXB_REG_CONFIG
#define PXB_REG_CONFIG
Definition: intel.c:152
BRIDGE_450NX_REV_C0
#define BRIDGE_450NX_REV_C0
Definition: intel.c:147
PCI_DEV_BRIDGE_450KX
#define PCI_DEV_BRIDGE_450KX
Definition: intel.c:140
BRIDGE_450NX_REV_B1
#define BRIDGE_450NX_REV_B1
Definition: intel.c:146
PXB_CONFIG_BUF_RESTREAM
#define PXB_CONFIG_BUF_RESTREAM
Definition: intel.c:154
BRIDGE_450KX_REV_B0
#define BRIDGE_450KX_REV_B0
Definition: intel.c:143
UNREFERENCED_PARAMETER
#define UNREFERENCED_PARAMETER(P)
Definition: ntbasedef.h:329
PciSlot
_In_ ULONG _In_ PCI_SLOT_NUMBER PciSlot
Definition: pciidex.h:66
BusNumber
_In_ ULONG BusNumber
Definition: pciidex.h:65
PciConfig
_In_ ULONG _In_ PCI_SLOT_NUMBER _In_ PPCI_COMMON_HEADER PciConfig
Definition: pciidex.h:67
PCIConfiguration
@ PCIConfiguration
Definition: miniport.h:93
Context
_In_ PVOID Context
Definition: storport.h:2269
_PCI_SLOT_NUMBER::AsULONG
ULONG AsULONG
Definition: iotypes.h:3498
_PCI_SLOT_NUMBER::u
union _PCI_SLOT_NUMBER::@4410 u

Referenced by IntelGetControllerProperties().

◆ IntelPiixChooseDeviceSpeed()

static VOID IntelPiixChooseDeviceSpeed ( _In_ ULONG  Channel,
_In_ PCHANNEL_DEVICE_CONFIG  Device 
)
static

Definition at line 433 of file intel.c.

436{
437 ULONG Mode;
438
439 /* PIO speed */
440 for (Mode = Device->PioMode; Mode > PIO_MODE(0); Mode--)
441 {
442 if (!(Device->SupportedModes & (1 << Mode)))
443 continue;
444
445 if (IntelTimingModeToCycleTime[Mode] >= Device->MinPioCycleTime)
446 break;
447 }
448 if (Mode != Device->PioMode)
449 INFO("CH %lu: Downgrade PIO speed from %lu to %lu\n", Channel, Device->PioMode, Mode);
450 Device->PioMode = Mode;
451
452 /* UDMA works independently of any PIO mode */
453 if (Device->DmaMode == PIO_MODE(0) || Device->DmaMode >= UDMA_MODE(0))
454 return;
455
456 /* DMA speed */
457 for (Mode = Device->DmaMode; Mode > PIO_MODE(0); Mode--)
458 {
459 ULONG MinimumCycleTime, TimingMode;
460
461 if (!(Device->SupportedModes & ~PIO_ALL & (1 << Mode)))
462 continue;
463
464 ASSERT((Mode == SWDMA_MODE(2)) || (Mode == MWDMA_MODE(1)) || (Mode == MWDMA_MODE(2)));
465
466 if (Device->DmaMode >= MWDMA_MODE(0))
467 MinimumCycleTime = Device->MinMwDmaCycleTime;
468 else
469 MinimumCycleTime = Device->MinSwDmaCycleTime;
470
471 TimingMode = IntelDmaModeToTimingMode[Mode - SWDMA_MODE(2)];
472
473 if (IntelTimingModeToCycleTime[TimingMode] >= MinimumCycleTime)
474 break;
475 }
476 if (Mode != Device->DmaMode)
477 {
478 if (Mode == PIO_MODE(0))
479 WARN("CH %lu: Too slow device '%s', disabling DMA\n", Channel, Device->FriendlyName);
480 else
481 INFO("CH %lu: Downgrade DMA speed from %lu to %lu\n", Channel, Device->DmaMode, Mode);
482 }
483 Device->DmaMode = Mode;
484}
PIO_MODE
#define PIO_MODE(n)
Definition: ata_user.h:36
MWDMA_MODE
#define MWDMA_MODE(n)
Definition: ata_user.h:38
SWDMA_MODE
#define SWDMA_MODE(n)
Definition: ata_user.h:37
UDMA_MODE
#define UDMA_MODE(n)
Definition: ata_user.h:39
Mode
_In_ ULONG Mode
Definition: hubbusif.h:303
IntelTimingModeToCycleTime
static const ULONG IntelTimingModeToCycleTime[5]
Definition: intel.c:390
IntelDmaModeToTimingMode
static const ULONG IntelDmaModeToTimingMode[]
Definition: intel.c:418
Channel
_In_ ULONG Channel
Definition: pciidex.h:74
Device
_Must_inspect_result_ _In_ WDFDEVICE Device
Definition: wdfchildlist.h:474

Referenced by IntelPiixLegacySetTransferMode(), and IntelPiixSetTransferMode().

◆ IntelPiixLegacyComputeIdeTiming()

static USHORT IntelPiixLegacyComputeIdeTiming ( _In_ PCHANNEL_DEVICE_CONFIG  Device,
_In_ ULONG  Number,
_In_ ULONG  Mode 
)
static

Definition at line 685 of file intel.c.

689{
690 USHORT IdeTimReg;
691 ULONG TimingMode;
692
693 if (Mode > PIO_MODE(4))
694 {
695 ASSERT((Mode == SWDMA_MODE(2)) || (Mode == MWDMA_MODE(1)) || (Mode == MWDMA_MODE(2)));
696
697 TimingMode = IntelDmaModeToTimingMode[Mode - SWDMA_MODE(2)];
698 }
699 else
700 {
701 TimingMode = Mode;
702 }
703
704 IdeTimReg = PIIX_IDETIM_ISP(IntelClockSettings[TimingMode][0]);
705 IdeTimReg |= PIIX_IDETIM_RCT(IntelClockSettings[TimingMode][1]);
706 IdeTimReg |= PIIX_IDETIM_SETTINGS(Number, IntelModeSettings[TimingMode]);
707
708 if (Device->IsFixedDisk)
709 IdeTimReg |= PIIX_IDETIM_PPE(Number);
710
711 if (((TimingMode == PIO_MODE(2)) && Device->IoReadySupported))
712 IdeTimReg |= PIIX_IDETIM_IE(Number);
713
714 return IdeTimReg;
715}
PIIX_IDETIM_RCT
#define PIIX_IDETIM_RCT(Value)
Definition: intel.c:178
PIIX_IDETIM_SETTINGS
#define PIIX_IDETIM_SETTINGS(Drive, Value)
Definition: intel.c:180
PIIX_IDETIM_ISP
#define PIIX_IDETIM_ISP(Value)
Definition: intel.c:179
IntelModeSettings
static const UCHAR IntelModeSettings[]
Definition: intel.c:399
PIIX_IDETIM_IE
#define PIIX_IDETIM_IE(Drive)
Definition: intel.c:167
IntelClockSettings
static const UCHAR IntelClockSettings[5][2]
Definition: intel.c:379
PIIX_IDETIM_PPE
#define PIIX_IDETIM_PPE(Drive)
Definition: intel.c:168
Number
_In_ ULONG Number
Definition: haltypes.h:1872

Referenced by IntelPiixLegacySetTransferMode().

◆ IntelPiixLegacyPrepareIo()

static VOID IntelPiixLegacyPrepareIo ( _In_ PVOID  ChannelContext,
_In_ PATA_DEVICE_REQUEST  Request 
)
static

Definition at line 662 of file intel.c.

665{
666 PCHANNEL_DATA_PATA ChanData = ChannelContext;
667 PINTEL_HW_EXTENSION HwExt = (PVOID)ChanData->HwExt;
668 ULONG Index = (Request->Flags & REQUEST_FLAG_PROGRAM_DMA) ? 1 : 0;
669 USHORT NewTimingReg = HwExt->Device[DEV_NUMBER(Request->Device)].Timing[Index];
670
671 /* Set the proper device timings */
672 if (HwExt->CurrentTiming != NewTimingReg)
673 {
674 HwExt->CurrentTiming = NewTimingReg;
675
676 PciWrite16(ChanData->Controller, HwExt->Register, NewTimingReg);
677 TRACE("CH %lu: IDETIM %04X\n", ChanData->Channel, NewTimingReg);
678 }
679
680 PataPrepareIo(ChanData, Request);
681}
REQUEST_FLAG_PROGRAM_DMA
#define REQUEST_FLAG_PROGRAM_DMA
Definition: ata_shared.h:342
PataPrepareIo
CHANNEL_PREPARE_IO PataPrepareIo
Definition: pciidex.h:700
DEV_NUMBER
#define DEV_NUMBER(Device)
Definition: pciidex.h:56
PciWrite16
FORCEINLINE VOID PciWrite16(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset, _In_ USHORT Value)
Definition: pciidex.h:893
TRACE
#define TRACE(s)
Definition: solgame.cpp:4
_CHANNEL_DATA_PATA::HwExt
PUCHAR HwExt[ANYSIZE_ARRAY]
Definition: pciidex.h:317
_INTEL_HW_EXTENSION::CurrentTiming
USHORT CurrentTiming
Definition: intel.c:265
_INTEL_HW_EXTENSION::Device
struct _INTEL_HW_EXTENSION::@1173 Device[MAX_IDE_DEVICE]
Index
_In_ WDFCOLLECTION _In_ ULONG Index
Definition: wdfcollection.h:182
Request
_In_ WDFREQUEST Request
Definition: wdfdevice.h:547

Referenced by IntelInitChannel().

◆ IntelPiixLegacySetTransferMode()

static VOID IntelPiixLegacySetTransferMode ( _In_ PATA_CONTROLLER  Controller,
_In_ ULONG  Channel,
_In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *  DeviceList 
)
static

Definition at line 729 of file intel.c.

733{
734 PCHANNEL_DATA_PATA ChanData = Controller->Channels[Channel];
735 PINTEL_HW_EXTENSION HwExt = (PVOID)ChanData->HwExt;
736 USHORT IdeTimReg;
737 ULONG i;
738
739 /* Clear the current mode configuration */
740 IdeTimReg = PciRead16(Controller, HwExt->Register);
741 IdeTimReg &= PIIX_IDETIM_IDE | PIIX_IDETIM_SITRE | PIIX_IDETIM_RSV_MASK;
742 PciWrite16(Controller, HwExt->Register, IdeTimReg);
743
744 for (i = 0; i < MAX_IDE_DEVICE; ++i)
745 {
746 PCHANNEL_DEVICE_CONFIG Device = DeviceList[i];
747
748 if (!Device)
749 continue;
750
751 IntelPiixChooseDeviceSpeed(Channel, Device);
752
753 /* Compute the timing bits for this device */
754 HwExt->Device[i].Timing[0] = IntelPiixLegacyComputeIdeTiming(Device, i, Device->PioMode);
755 HwExt->Device[i].Timing[1] = IntelPiixLegacyComputeIdeTiming(Device, i, Device->DmaMode);
756
757 INFO("CH %lu: Drive #%lu PIO:%04X DMA:04X\n",
758 Channel, i, HwExt->Device[i].Timing[0], HwExt->Device[i].Timing[1]);
759 }
760
761 /* Force reload of timings */
762 HwExt->CurrentTiming = 0;
763}
DeviceList
PDEVICE_LIST DeviceList
Definition: utils.c:27
MAX_IDE_DEVICE
#define MAX_IDE_DEVICE
Definition: ide.h:32
PIIX_IDETIM_SITRE
#define PIIX_IDETIM_SITRE
Definition: intel.c:174
PIIX_IDETIM_RSV_MASK
#define PIIX_IDETIM_RSV_MASK
Definition: intel.c:172
IntelPiixChooseDeviceSpeed
static VOID IntelPiixChooseDeviceSpeed(_In_ ULONG Channel, _In_ PCHANNEL_DEVICE_CONFIG Device)
Definition: intel.c:433
IntelPiixLegacyComputeIdeTiming
static USHORT IntelPiixLegacyComputeIdeTiming(_In_ PCHANNEL_DEVICE_CONFIG Device, _In_ ULONG Number, _In_ ULONG Mode)
Definition: intel.c:685
PIIX_IDETIM_IDE
#define PIIX_IDETIM_IDE
Definition: intel.c:176
_CHANNEL_DEVICE_CONFIG
Definition: ata_shared.h:132

Referenced by IntelInitChannel().

◆ IntelPiixSetTransferMode()

static VOID IntelPiixSetTransferMode ( _In_ PATA_CONTROLLER  Controller,
_In_ ULONG  Channel,
_In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *  DeviceList 
)
static

Definition at line 488 of file intel.c.

492{
493 PCHANNEL_DATA_PATA ChanData = Controller->Channels[Channel];
494 USHORT IdeTimReg, IdeConfigReg;
495 UCHAR IdeSlaveTimReg, IdeUdmaCtrlReg, IdeUdmaTimReg;
496 ULONG i;
497
498 IdeUdmaCtrlReg = 0;
499 IdeUdmaTimReg = 0;
500 IdeConfigReg = 0;
501
502 IdeTimReg = PciRead16(Controller, PIIX_REG_IDETIM(Channel));
503 IdeSlaveTimReg = PciRead8(Controller, PIIX_REG_SIDETIM);
504 if (ChanData->HwFlags & HW_FLAGS_HAS_UDMA_REG)
505 {
506 IdeUdmaCtrlReg = PciRead8(Controller, PIIX_REG_UDMACTL);
507 IdeUdmaTimReg = PciRead8(Controller, PIIX_REG_UDMATIM(Channel));
508 if (ChanData->HwFlags & HW_FLAGS_HAS_CFG_REG)
509 {
510 IdeConfigReg = PciRead16(Controller, PIIX_REG_CONFIG);
511 }
512 }
513
514 INFO("CH %lu: Config (before)\n"
515 "IDETIM %04X\n"
516 "SIDETIM %02X\n"
517 "UDMACTL %02X\n"
518 "UDMATIM %02X\n"
519 "CONFIG %04X\n",
520 Channel, IdeTimReg, IdeSlaveTimReg, IdeUdmaCtrlReg, IdeUdmaTimReg, IdeConfigReg);
521
522 /* Clear the current mode configuration */
523 IdeTimReg &= PIIX_IDETIM_IDE | PIIX_IDETIM_RSV_MASK;
524 IdeSlaveTimReg &= ~PIIX_SIDETIM_ISPRCT_MASK(Channel);
525 IdeUdmaCtrlReg &= ~PIIX_UDMACTL_EN_MASK(Channel);
526 IdeUdmaTimReg &= ~PIIX_UDMATIM_CT_MASK;
527 IdeConfigReg &= PIIX_CONFIG_KEEP_MASK;
528
529 for (i = 0; i < MAX_IDE_DEVICE; ++i)
530 {
531 PCHANNEL_DEVICE_CONFIG Device = DeviceList[i];
532 ULONG TimingMode;
533
534 if (!Device)
535 continue;
536
537 IntelPiixChooseDeviceSpeed(Channel, Device);
538
539 TimingMode = Device->PioMode;
540
541 /* UDMA timings */
542 if (Device->DmaMode >= UDMA_MODE(0))
543 {
544 /* UDMA works independently of any PIO mode */
545 IdeUdmaTimReg |= PIIX_UDMATIM_CT(i, IntelUdmaSettings[Device->DmaMode - UDMA_MODE(0)]);
546 IdeUdmaCtrlReg |= PIIX_UDMACTL_EN(Channel, i);
547
548 if (Device->DmaMode == UDMA_MODE(5))
549 IdeConfigReg |= PIIX_CONFIG_CLOCK_UDMA100(Channel, i);
550 else if (Device->DmaMode > UDMA_MODE(2))
551 IdeConfigReg |= PIIX_CONFIG_CLOCK_UDMA66(Channel, i);
552 }
553 /* DMA timings */
554 else if (Device->DmaMode != PIO_MODE(0))
555 {
556 ASSERT((Device->DmaMode == SWDMA_MODE(2)) ||
557 (Device->DmaMode == MWDMA_MODE(1)) ||
558 (Device->DmaMode == MWDMA_MODE(2)));
559
560 /* Find the fastest mode while satisfying PIO timings */
561 TimingMode = IntelDmaModeToTimingMode[Device->DmaMode - SWDMA_MODE(2)];
562 if (TimingMode < Device->PioMode)
563 {
564 /*
565 * No common mode, we have to slow down the device's PIO speed
566 * by forcing the compatible PIO timings for PIO transfers.
567 */
568 IdeTimReg |= PIIX_IDETIM_DTE(i);
569 }
570 }
571
572 /* DMA and PIO timings */
573 if (i == 0)
574 {
575 IdeTimReg |= PIIX_IDETIM_ISP(IntelClockSettings[TimingMode][0]);
576 IdeTimReg |= PIIX_IDETIM_RCT(IntelClockSettings[TimingMode][1]);
577 }
578 else
579 {
580 IdeSlaveTimReg |= PIIX_SIDETIM_ISP(Channel, IntelClockSettings[TimingMode][0]);
581 IdeSlaveTimReg |= PIIX_SIDETIM_RCT(Channel, IntelClockSettings[TimingMode][1]);
582
583 /* Enable effect of the PIIX_REG_SIDETIM register */
584 IdeTimReg |= PIIX_IDETIM_SITRE;
585 }
586
587 IdeTimReg |= PIIX_IDETIM_SETTINGS(i, IntelModeSettings[TimingMode]);
588
589 if (((TimingMode == PIO_MODE(2)) && Device->IoReadySupported))
590 IdeTimReg |= PIIX_IDETIM_IE(i);
591
592 if (Device->IsFixedDisk)
593 IdeTimReg |= PIIX_IDETIM_PPE(i);
594 }
595
596 PciWrite8(Controller, PIIX_REG_SIDETIM, IdeSlaveTimReg);
597 PciWrite16(Controller, PIIX_REG_IDETIM(Channel), IdeTimReg);
598 if (ChanData->HwFlags & HW_FLAGS_HAS_UDMA_REG)
599 {
600 PciWrite8(Controller, PIIX_REG_UDMACTL, IdeUdmaCtrlReg);
601 PciWrite8(Controller, PIIX_REG_UDMATIM(Channel), IdeUdmaTimReg);
602 if (ChanData->HwFlags & HW_FLAGS_HAS_CFG_REG)
603 {
604 /* Enable this feature for performance enhancement */
605 IdeConfigReg |= PIIX_CONFIG_WR_PING_PONG;
606
607 PciWrite16(Controller, PIIX_REG_CONFIG, IdeConfigReg);
608 }
609 }
610
611 INFO("CH %lu: Config (after)\n"
612 "IDETIM %04X\n"
613 "SIDETIM %02X\n"
614 "UDMACTL %02X\n"
615 "UDMATIM %02X\n"
616 "CONFIG %04X\n",
617 Channel, IdeTimReg, IdeSlaveTimReg, IdeUdmaCtrlReg, IdeUdmaTimReg, IdeConfigReg);
618}
PIIX_CONFIG_WR_PING_PONG
#define PIIX_CONFIG_WR_PING_PONG
Definition: intel.c:227
PIIX_CONFIG_KEEP_MASK
#define PIIX_CONFIG_KEEP_MASK
Definition: intel.c:218
PIIX_REG_UDMATIM
#define PIIX_REG_UDMATIM(Channel)
Definition: intel.c:206
PIIX_SIDETIM_ISP
#define PIIX_SIDETIM_ISP(Channel, Value)
Definition: intel.c:189
HW_FLAGS_HAS_UDMA_REG
#define HW_FLAGS_HAS_UDMA_REG
Definition: intel.c:247
PIIX_IDETIM_DTE
#define PIIX_IDETIM_DTE(Drive)
Definition: intel.c:169
HW_FLAGS_HAS_CFG_REG
#define HW_FLAGS_HAS_CFG_REG
Definition: intel.c:246
IntelUdmaSettings
static const UCHAR IntelUdmaSettings[]
Definition: intel.c:408
PIIX_CONFIG_CLOCK_UDMA66
#define PIIX_CONFIG_CLOCK_UDMA66(Channel, Drive)
Definition: intel.c:223
PIIX_REG_UDMACTL
#define PIIX_REG_UDMACTL
Definition: intel.c:194
PIIX_UDMATIM_CT
#define PIIX_UDMATIM_CT(Drive, Value)
Definition: intel.c:211
PIIX_REG_SIDETIM
#define PIIX_REG_SIDETIM
Definition: intel.c:185
PIIX_UDMACTL_EN
#define PIIX_UDMACTL_EN(Channel, Drive)
Definition: intel.c:199
PIIX_CONFIG_CLOCK_UDMA100
#define PIIX_CONFIG_CLOCK_UDMA100(Channel, Drive)
Definition: intel.c:225
PIIX_SIDETIM_RCT
#define PIIX_SIDETIM_RCT(Channel, Value)
Definition: intel.c:188
PciWrite8
FORCEINLINE VOID PciWrite8(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset, _In_ UCHAR Value)
Definition: pciidex.h:883
UCHAR
unsigned char UCHAR
Definition: typedefs.h:53

Referenced by IntelInitChannel().

◆ IntelSchSetTransferMode()

static VOID IntelSchSetTransferMode ( _In_ PATA_CONTROLLER  Controller,
_In_ ULONG  Channel,
_In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *  DeviceList 
)
static

Definition at line 622 of file intel.c.

626{
627 ULONG i;
628
629 for (i = 0; i < MAX_IDE_DEVICE; ++i)
630 {
631 PCHANNEL_DEVICE_CONFIG Device = DeviceList[i];
632 ULONG DeviceTimingReg;
633
634 if (!Device)
635 continue;
636
637 DeviceTimingReg = PciRead32(Controller, SCH_REG_DTIM(i));
638 DeviceTimingReg &= ~(SCH_DTIM_PM_MASK |
639 SCH_DTIM_MDM_MASK |
640 SCH_DTIM_UDM_MASK |
641 SCH_DTIM_PPE |
642 SCH_DTIM_USD);
643
644 if (Device->IsFixedDisk)
645 DeviceTimingReg |= SCH_DTIM_PPE;
646
647 /* DMA timings */
648 if (Device->DmaMode >= UDMA_MODE(0))
649 DeviceTimingReg |= SCH_DTIM_USD | SCH_DTIM_UDM(Device->DmaMode - UDMA_MODE(0));
650 else if (Device->DmaMode >= MWDMA_MODE(0))
651 DeviceTimingReg |= SCH_DTIM_MDM(Device->DmaMode - MWDMA_MODE(0));
652
653 /* PIO timings */
654 DeviceTimingReg |= SCH_DTIM_PM(Device->PioMode);
655
656 PciWrite32(Controller, SCH_REG_DTIM(i), DeviceTimingReg);
657 }
658}
SCH_DTIM_PM_MASK
#define SCH_DTIM_PM_MASK
Definition: intel.c:234
SCH_DTIM_USD
#define SCH_DTIM_USD
Definition: intel.c:238
SCH_DTIM_PM
#define SCH_DTIM_PM(Mode)
Definition: intel.c:240
SCH_DTIM_MDM_MASK
#define SCH_DTIM_MDM_MASK
Definition: intel.c:235
SCH_DTIM_PPE
#define SCH_DTIM_PPE
Definition: intel.c:237
SCH_DTIM_MDM
#define SCH_DTIM_MDM(Mode)
Definition: intel.c:241
PciWrite32
FORCEINLINE VOID PciWrite32(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset, _In_ ULONG Value)
Definition: pciidex.h:903
PciRead32
FORCEINLINE ULONG PciRead32(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
Definition: pciidex.h:871

Referenced by IntelInitChannel().

Variable Documentation

◆ IntelClockSettings

const UCHAR IntelClockSettings[5][2]
static
Initial value:
=
{
{ 0, 0 },
{ 0, 0 },
{ 1, 0 },
{ 2, 1 },
{ 2, 3 },
}

Definition at line 379 of file intel.c.

Referenced by IntelPiixLegacyComputeIdeTiming(), and IntelPiixSetTransferMode().

◆ IntelControllerList

PCIIDEX_PAGED_DATA const INTEL_CONTROLLER_INFO IntelControllerList[]
static

Definition at line 273 of file intel.c.

Referenced by IntelGetControllerProperties().

◆ IntelDmaModeToTimingMode

const ULONG IntelDmaModeToTimingMode[]
static
Initial value:
= {
PIO_MODE(2),
PIO_MODE(0),
PIO_MODE(3),
}

Definition at line 418 of file intel.c.

Referenced by IntelPiixChooseDeviceSpeed(), IntelPiixLegacyComputeIdeTiming(), and IntelPiixSetTransferMode().

◆ IntelModeSettings

const UCHAR IntelModeSettings[]
static
Initial value:
=
{
0,
0,
PIIX_IDETIM_TIME(0),
PIIX_IDETIM_TIME(0) | PIIX_IDETIM_IE(0),
PIIX_IDETIM_TIME(0) | PIIX_IDETIM_IE(0),
}
PIIX_IDETIM_TIME
#define PIIX_IDETIM_TIME(Drive)
Definition: intel.c:166

Definition at line 399 of file intel.c.

Referenced by IntelPiixLegacyComputeIdeTiming(), and IntelPiixSetTransferMode().

◆ IntelMpiixEnableBits

PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelMpiixEnableBits[MAX_IDE_CHANNEL]
static
Initial value:
=
{
{ 0x6D, 0xC0, 0x80 },
{ 0x6D, 0xC0, 0xC0 },
}

Definition at line 373 of file intel.c.

Referenced by IntelGetControllerProperties().

◆ IntelPiixEnableBits

PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelPiixEnableBits[MAX_IDE_CHANNEL]
static
Initial value:
=
{
{ 0x41, 0x80, 0x80 },
{ 0x43, 0x80, 0x80 },
}

Definition at line 366 of file intel.c.

Referenced by IntelGetControllerProperties().

◆ IntelTimingModeToCycleTime

const ULONG IntelTimingModeToCycleTime[5]
static
Initial value:
=
{
900,
900,
240,
180,
120,
}
See also
IntelClockSettings

Definition at line 390 of file intel.c.

Referenced by IntelPiixChooseDeviceSpeed().

◆ IntelUdmaSettings

const UCHAR IntelUdmaSettings[]
static
Initial value:
=
{
0,
1,
2,
1,
2,
1
}

Definition at line 408 of file intel.c.

Referenced by IntelPiixSetTransferMode().