ReactOS 0.4.16-dev-2633-g8dc9e50
Classes | Macros | Typedefs | Functions
pata.h File Reference
#include <pshpack1.h>
#include <poppack.h>
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Classes

struct  _PCIIDE_PRD_TABLE_ENTRY
 
struct  _ATA_TIMING
 

Macros

#define PCI_VEN_ATI   0x1002
 
#define PCI_VEN_AMD   0x1022
 
#define PCI_VEN_NVIDIA   0x10DE
 
#define PCI_VEN_PC_TECH   0x1042
 
#define PCI_VEN_CMD   0x1095
 
#define PCI_VEN_VIA   0x1106
 
#define PCI_VEN_SERVERWORKS   0x1166
 
#define PCI_VEN_TOSHIBA   0x1179
 
#define PCI_VEN_CAVIUM   0x177D
 
#define PCI_VEN_INTEL   0x8086
 
#define CHANNEL_PCAT_MAX_DEVICES   2
 
#define CHANNEL_PC98_MAX_DEVICES   4
 
#define PC98_ATA_BANK   0x432
 
#define PC98_ATA_BANK_32BIT_PORT   0x08
 
#define ATA_IO_WAIT()   KeStallExecutionProcessor(1)
 
#define NUM_TO_BITMAP(num)   (0xFFFFFFFF >> (RTL_BITS_OF(ULONG) - (num)))
 
#define SATA_ALL    (PIO_ALL | MWDMA_ALL | UDMA_ALL)
 
#define UDMA_80C_ALL    (UDMA_MODE3 | UDMA_MODE4 | UDMA_MODE5 | UDMA_MODE6)
 
#define MWDMA_MODES(MinMode, MaxMode)    (NUM_TO_BITMAP(MWDMA_MODE((MaxMode) + 1)) & ~NUM_TO_BITMAP(MWDMA_MODE(MinMode)))
 
#define UDMA_MODES(MinMode, MaxMode)    (NUM_TO_BITMAP(UDMA_MODE((MaxMode) + 1)) & ~NUM_TO_BITMAP(UDMA_MODE(MinMode)))
 
#define IDE_DC_ALWAYS   0x08
 
#define IDE_DRIVE_SELECT   0xA0
 
#define IDE_HIGH_ORDER_BYTE   0x80
 
#define IDE_FEATURE_PIO   0x00
 
#define IDE_FEATURE_DMA   0x01
 
#define IDE_FEATURE_DMADIR   0x04
 
#define ATAPI_MAX_DRQ_DATA_BLOCK   0xFFFE
 
#define PCIIDE_LEGACY_RESOURCE_COUNT   3
 
#define PCIIDE_LEGACY_COMMAND_IO_RANGE_LENGTH   8
 
#define PCIIDE_LEGACY_CONTROL_IO_RANGE_LENGTH   1
 
#define PCIIDE_LEGACY_PRIMARY_COMMAND_BASE   0x1F0
 
#define PCIIDE_LEGACY_PRIMARY_CONTROL_BASE   0x3F6
 
#define PCIIDE_LEGACY_PRIMARY_IRQ   14
 
#define PCIIDE_LEGACY_SECONDARY_COMMAND_BASE   0x170
 
#define PCIIDE_LEGACY_SECONDARY_CONTROL_BASE   0x376
 
#define PCIIDE_LEGACY_SECONDARY_IRQ   15
 
#define PCIIDE_COMMAND_IO_RANGE_LENGTH   8
 
#define PCIIDE_CONTROL_IO_RANGE_LENGTH   4
 
#define PCIIDE_CONTROL_IO_BAR_OFFSET   2
 
#define PCIIDE_DMA_IO_BAR   4
 
#define PCIIDE_DMA_IO_RANGE_LENGTH   16
 
#define PCIIDE_DMA_SECONDARY_CHANNEL_OFFSET   8
 
#define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE   0x01
 
#define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE_CAPABLE   0x02
 
#define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE   0x04
 
#define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE_CAPABLE   0x08
 
#define PCIIDE_PROGIF_DMA_CAPABLE   0x80
 
#define PCIIDE_DMA_COMMAND   0
 
#define PCIIDE_DMA_STATUS   2
 
#define PCIIDE_DMA_PRDT_PHYSICAL_ADDRESS   4
 
#define PCIIDE_DMA_COMMAND_STOP   0x00
 
#define PCIIDE_DMA_COMMAND_START   0x01
 
#define PCIIDE_DMA_COMMAND_READ_FROM_SYSTEM_MEMORY   0x00
 
#define PCIIDE_DMA_COMMAND_WRITE_TO_SYSTEM_MEMORY   0x08
 
#define PCIIDE_DMA_STATUS_ACTIVE   0x01
 
#define PCIIDE_DMA_STATUS_ERROR   0x02
 
#define PCIIDE_DMA_STATUS_INTERRUPT   0x04
 
#define PCIIDE_DMA_STATUS_RESERVED1   0x08
 
#define PCIIDE_DMA_STATUS_RESERVED2   0x10
 
#define PCIIDE_DMA_STATUS_DRIVE0_DMA_CAPABLE   0x20
 
#define PCIIDE_DMA_STATUS_DRIVE1_DMA_CAPABLE   0x40
 
#define PCIIDE_DMA_STATUS_SIMPLEX   0x80
 
#define ATAPI_INT_REASON_COD   0x01
 
#define ATAPI_INT_REASON_IO   0x02
 
#define ATAPI_INT_REASON_RELEASE   0x04
 
#define ATAPI_INT_REASON_TAG   0xF8
 
#define ATAPI_INT_REASON_MASK   (ATAPI_INT_REASON_IO | ATAPI_INT_REASON_COD)
 
#define ATAPI_INT_REASON_STATUS_NEC   0x00
 
#define ATAPI_INT_REASON_STATUS   (ATAPI_INT_REASON_IO | ATAPI_INT_REASON_COD)
 
#define ATAPI_INT_REASON_DATA_OUT   IDE_STATUS_DRQ
 
#define ATAPI_INT_REASON_AWAIT_CDB   (IDE_STATUS_DRQ | ATAPI_INT_REASON_COD)
 
#define ATAPI_INT_REASON_DATA_IN   (ATAPI_INT_REASON_IO | IDE_STATUS_DRQ)
 
#define ATA_TIME_BUSY_SELECT   3000
 30 ms
 
#define ATA_TIME_BUSY_NORMAL   50000
 500 ms
 
#define ATA_TIME_BUSY_POLL   5
 50 us
 
#define ATA_TIME_DRQ_CLEAR   1000
 10 ms
 
#define ATA_TIME_PHASE_CHANGE   100
 1 ms
 
#define ATA_TIME_DRQ_ASSERT   15
 150 us
 
#define ATA_TIME_RESET_SELECT   (2000 / PORT_TIMER_TICK_MS)
 2 s
 
#define ATA_TIME_BUSY_RESET   (10000 / PORT_TIMER_TICK_MS)
 10 s
 
#define CMD_FLAG_NONE   0x00000000
 
#define CMD_FLAG_TRANSFER_MASK   0x00000003
 
#define CMD_FLAG_AWAIT_CDB   0x00000004
 
#define CMD_FLAG_DATA_IN   0x00000040
 
#define CMD_FLAG_DATA_OUT   0x00000080
 
#define CMD_FLAG_AWAIT_INTERRUPT   0x80000000
 
#define CMD_FLAG_ATAPI_PIO_TRANSFER   0x00000001
 
#define CMD_FLAG_ATA_PIO_TRANSFER   0x00000002
 
#define CMD_FLAG_DMA_TRANSFER   0x00000003
 
#define PATA_CHANNEL_SLOT   0
 
#define PATA_CHANNEL_QUEUE_DEPTH   1
 
#define PCIIDE_PRD_LENGTH_MASK   0xFFFF
 
#define PCIIDE_PRD_END_OF_TABLE   0x80000000
 
#define PCIIDE_PRD_LIMIT   0x10000
 
#define SHARED_CMD_TIMINGS   0x00000001
 
#define SHARED_DATA_TIMINGS   0x00000002
 
#define SHARED_ADDR_TIMINGS   0x00000004
 
#define ATA_READ_BLOCK_16(Port, Buffer, Count, Ctx, MmioFlag)    AtaReadBlock16(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)
 
#define ATA_WRITE_BLOCK_16(Port, Buffer, Count, Ctx, MmioFlag)    AtaWriteBlock16(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)
 
#define ATA_READ_BLOCK_32(Port, Buffer, Count, Ctx, MmioFlag)    AtaReadBlock32(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)
 
#define ATA_WRITE_BLOCK_32(Port, Buffer, Count, Ctx, MmioFlag)    AtaWriteBlock32(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)
 
#define ATA_READ(Port, Ctx, MmioFlag)    AtaReadPortUchar(Port, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)
 
#define ATA_WRITE(Port, Value, Ctx, MmioFlag)    AtaWritePortUchar(Port, Value, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)
 
#define ATA_WRITE_ULONG(Port, Value, Ctx, MmioFlag)    AtaWritePortUlong(Port, Value, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)
 

Typedefs

typedef struct _PCIIDE_PRD_TABLE_ENTRY PCIIDE_PRD_TABLE_ENTRY
 
typedef struct _PCIIDE_PRD_TABLE_ENTRY * PPCIIDE_PRD_TABLE_ENTRY
 
typedef USHORT ATATIM
 
typedef struct _ATA_TIMING ATA_TIMING
 
typedef struct _ATA_TIMING * PATA_TIMING
 

Functions

 C_ASSERT (CMD_FLAG_DMA_TRANSFER==(CMD_FLAG_ATAPI_PIO_TRANSFER|CMD_FLAG_ATA_PIO_TRANSFER))
 
 C_ASSERT (CMD_FLAG_DATA_IN==REQUEST_FLAG_DATA_IN)
 
 C_ASSERT (CMD_FLAG_DATA_OUT==REQUEST_FLAG_DATA_OUT)
 
 C_ASSERT (CMD_FLAG_AWAIT_INTERRUPT==REQUEST_FLAG_POLL)
 
FORCEINLINE ATATIM CLAMP_TIMING (_In_ ATATIM Value, _In_ ATATIM Minimum, _In_ ATATIM Maximum)
 
FORCEINLINE VOID ATA_SELECT_DEVICE (_In_ PCHANNEL_DATA_PATA ChanData, _In_ UCHAR DeviceNumber, _In_ UCHAR DeviceSelect)
 
FORCEINLINE UCHAR ATA_WAIT (_In_ PCHANNEL_DATA_PATA ChanData, _In_range_(>, 0) ULONG Timeout, _In_ UCHAR Mask, _In_ UCHAR Value)
 

Macro Definition Documentation

◆ ATA_IO_WAIT

#define ATA_IO_WAIT ( )    KeStallExecutionProcessor(1)

Delay of 400ns

Definition at line 32 of file pata.h.

◆ ATA_READ

#define ATA_READ (   Port,
  Ctx,
  MmioFlag 
)     AtaReadPortUchar(Port, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)

Definition at line 260 of file pata.h.

◆ ATA_READ_BLOCK_16

#define ATA_READ_BLOCK_16 (   Port,
  Buffer,
  Count,
  Ctx,
  MmioFlag 
)     AtaReadBlock16(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)

Definition at line 248 of file pata.h.

◆ ATA_READ_BLOCK_32

#define ATA_READ_BLOCK_32 (   Port,
  Buffer,
  Count,
  Ctx,
  MmioFlag 
)     AtaReadBlock32(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)

Definition at line 254 of file pata.h.

◆ ATA_TIME_BUSY_NORMAL

#define ATA_TIME_BUSY_NORMAL   50000

500 ms

Definition at line 170 of file pata.h.

◆ ATA_TIME_BUSY_POLL

#define ATA_TIME_BUSY_POLL   5

50 us

Definition at line 171 of file pata.h.

◆ ATA_TIME_BUSY_RESET

#define ATA_TIME_BUSY_RESET   (10000 / PORT_TIMER_TICK_MS)

10 s

Definition at line 179 of file pata.h.

◆ ATA_TIME_BUSY_SELECT

#define ATA_TIME_BUSY_SELECT   3000

30 ms

Definition at line 169 of file pata.h.

◆ ATA_TIME_DRQ_ASSERT

#define ATA_TIME_DRQ_ASSERT   15

150 us

Definition at line 176 of file pata.h.

◆ ATA_TIME_DRQ_CLEAR

#define ATA_TIME_DRQ_CLEAR   1000

10 ms

Definition at line 172 of file pata.h.

◆ ATA_TIME_PHASE_CHANGE

#define ATA_TIME_PHASE_CHANGE   100

1 ms

Definition at line 173 of file pata.h.

◆ ATA_TIME_RESET_SELECT

#define ATA_TIME_RESET_SELECT   (2000 / PORT_TIMER_TICK_MS)

2 s

Definition at line 178 of file pata.h.

◆ ATA_WRITE

#define ATA_WRITE (   Port,
  Value,
  Ctx,
  MmioFlag 
)     AtaWritePortUchar(Port, Value, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)

Definition at line 263 of file pata.h.

◆ ATA_WRITE_BLOCK_16

#define ATA_WRITE_BLOCK_16 (   Port,
  Buffer,
  Count,
  Ctx,
  MmioFlag 
)     AtaWriteBlock16(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)

Definition at line 251 of file pata.h.

◆ ATA_WRITE_BLOCK_32

#define ATA_WRITE_BLOCK_32 (   Port,
  Buffer,
  Count,
  Ctx,
  MmioFlag 
)     AtaWriteBlock32(Port, Buffer, Count, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)

Definition at line 257 of file pata.h.

◆ ATA_WRITE_ULONG

#define ATA_WRITE_ULONG (   Port,
  Value,
  Ctx,
  MmioFlag 
)     AtaWritePortUlong(Port, Value, (Ctx)->ChanInfo & CHANNEL_FLAG_##MmioFlag)

Definition at line 266 of file pata.h.

◆ ATAPI_INT_REASON_AWAIT_CDB

#define ATAPI_INT_REASON_AWAIT_CDB   (IDE_STATUS_DRQ | ATAPI_INT_REASON_COD)

CDB - Ready for Command Packet

Definition at line 163 of file pata.h.

◆ ATAPI_INT_REASON_COD

#define ATAPI_INT_REASON_COD   0x01

ATAPI Interrupt Status Command or Data

Definition at line 140 of file pata.h.

◆ ATAPI_INT_REASON_DATA_IN

#define ATAPI_INT_REASON_DATA_IN   (ATAPI_INT_REASON_IO | IDE_STATUS_DRQ)

Data To Host - Send command parameter data to the host

Definition at line 166 of file pata.h.

◆ ATAPI_INT_REASON_DATA_OUT

#define ATAPI_INT_REASON_DATA_OUT   IDE_STATUS_DRQ

Data From Host - Receive command parameter data from the host

Definition at line 160 of file pata.h.

◆ ATAPI_INT_REASON_IO

#define ATAPI_INT_REASON_IO   0x02

Read direction

Definition at line 143 of file pata.h.

◆ ATAPI_INT_REASON_MASK

#define ATAPI_INT_REASON_MASK   (ATAPI_INT_REASON_IO | ATAPI_INT_REASON_COD)

Definition at line 151 of file pata.h.

◆ ATAPI_INT_REASON_RELEASE

#define ATAPI_INT_REASON_RELEASE   0x04

Bus release

Definition at line 146 of file pata.h.

◆ ATAPI_INT_REASON_STATUS

#define ATAPI_INT_REASON_STATUS   (ATAPI_INT_REASON_IO | ATAPI_INT_REASON_COD)

Status - Register contains Completion Status

Definition at line 157 of file pata.h.

◆ ATAPI_INT_REASON_STATUS_NEC

#define ATAPI_INT_REASON_STATUS_NEC   0x00

Status - Register contains Completion Status (NEC CDR-260)

Definition at line 154 of file pata.h.

◆ ATAPI_INT_REASON_TAG

#define ATAPI_INT_REASON_TAG   0xF8

Command Tag for the command

Definition at line 149 of file pata.h.

◆ ATAPI_MAX_DRQ_DATA_BLOCK

#define ATAPI_MAX_DRQ_DATA_BLOCK   0xFFFE

If a larger transfer is attempted, the 16-bit ByteCount register might overflow. In this case we round down the length to the closest multiple of 2.

Definition at line 65 of file pata.h.

◆ CHANNEL_PC98_MAX_DEVICES

#define CHANNEL_PC98_MAX_DEVICES   4

Master/Slave devices for Bank 0 and Bank 1

Definition at line 25 of file pata.h.

◆ CHANNEL_PCAT_MAX_DEVICES

#define CHANNEL_PCAT_MAX_DEVICES   2

Master/Slave devices

Definition at line 22 of file pata.h.

◆ CMD_FLAG_ATA_PIO_TRANSFER

#define CMD_FLAG_ATA_PIO_TRANSFER   0x00000002

Definition at line 189 of file pata.h.

◆ CMD_FLAG_ATAPI_PIO_TRANSFER

#define CMD_FLAG_ATAPI_PIO_TRANSFER   0x00000001

Definition at line 188 of file pata.h.

◆ CMD_FLAG_AWAIT_CDB

#define CMD_FLAG_AWAIT_CDB   0x00000004

Definition at line 183 of file pata.h.

◆ CMD_FLAG_AWAIT_INTERRUPT

#define CMD_FLAG_AWAIT_INTERRUPT   0x80000000

Definition at line 186 of file pata.h.

◆ CMD_FLAG_DATA_IN

#define CMD_FLAG_DATA_IN   0x00000040

Definition at line 184 of file pata.h.

◆ CMD_FLAG_DATA_OUT

#define CMD_FLAG_DATA_OUT   0x00000080

Definition at line 185 of file pata.h.

◆ CMD_FLAG_DMA_TRANSFER

#define CMD_FLAG_DMA_TRANSFER   0x00000003

Definition at line 190 of file pata.h.

◆ CMD_FLAG_NONE

#define CMD_FLAG_NONE   0x00000000

Definition at line 181 of file pata.h.

◆ CMD_FLAG_TRANSFER_MASK

#define CMD_FLAG_TRANSFER_MASK   0x00000003

Definition at line 182 of file pata.h.

◆ IDE_DC_ALWAYS

#define IDE_DC_ALWAYS   0x08

Definition at line 52 of file pata.h.

◆ IDE_DRIVE_SELECT

#define IDE_DRIVE_SELECT   0xA0

Definition at line 53 of file pata.h.

◆ IDE_FEATURE_DMA

#define IDE_FEATURE_DMA   0x01

Definition at line 58 of file pata.h.

◆ IDE_FEATURE_DMADIR

#define IDE_FEATURE_DMADIR   0x04

Definition at line 59 of file pata.h.

◆ IDE_FEATURE_PIO

#define IDE_FEATURE_PIO   0x00

Definition at line 57 of file pata.h.

◆ IDE_HIGH_ORDER_BYTE

#define IDE_HIGH_ORDER_BYTE   0x80

Definition at line 55 of file pata.h.

◆ MWDMA_MODES

#define MWDMA_MODES (   MinMode,
  MaxMode 
)     (NUM_TO_BITMAP(MWDMA_MODE((MaxMode) + 1)) & ~NUM_TO_BITMAP(MWDMA_MODE(MinMode)))

Used to specify a range of MWDMA modes

Definition at line 45 of file pata.h.

◆ NUM_TO_BITMAP

#define NUM_TO_BITMAP (   num)    (0xFFFFFFFF >> (RTL_BITS_OF(ULONG) - (num)))

Definition at line 34 of file pata.h.

◆ PATA_CHANNEL_QUEUE_DEPTH

#define PATA_CHANNEL_QUEUE_DEPTH   1

Definition at line 194 of file pata.h.

◆ PATA_CHANNEL_SLOT

#define PATA_CHANNEL_SLOT   0

The IDE interface has one slot per channel

Definition at line 193 of file pata.h.

◆ PC98_ATA_BANK

#define PC98_ATA_BANK   0x432

PC-98 ATA bank register

Definition at line 28 of file pata.h.

◆ PC98_ATA_BANK_32BIT_PORT

#define PC98_ATA_BANK_32BIT_PORT   0x08

Definition at line 29 of file pata.h.

◆ PCI_VEN_AMD

#define PCI_VEN_AMD   0x1022

Definition at line 11 of file pata.h.

◆ PCI_VEN_ATI

#define PCI_VEN_ATI   0x1002

Definition at line 10 of file pata.h.

◆ PCI_VEN_CAVIUM

#define PCI_VEN_CAVIUM   0x177D

Definition at line 18 of file pata.h.

◆ PCI_VEN_CMD

#define PCI_VEN_CMD   0x1095

Definition at line 14 of file pata.h.

◆ PCI_VEN_INTEL

#define PCI_VEN_INTEL   0x8086

Definition at line 19 of file pata.h.

◆ PCI_VEN_NVIDIA

#define PCI_VEN_NVIDIA   0x10DE

Definition at line 12 of file pata.h.

◆ PCI_VEN_PC_TECH

#define PCI_VEN_PC_TECH   0x1042

Definition at line 13 of file pata.h.

◆ PCI_VEN_SERVERWORKS

#define PCI_VEN_SERVERWORKS   0x1166

Definition at line 16 of file pata.h.

◆ PCI_VEN_TOSHIBA

#define PCI_VEN_TOSHIBA   0x1179

Definition at line 17 of file pata.h.

◆ PCI_VEN_VIA

#define PCI_VEN_VIA   0x1106

Definition at line 15 of file pata.h.

◆ PCIIDE_COMMAND_IO_RANGE_LENGTH

#define PCIIDE_COMMAND_IO_RANGE_LENGTH   8

Definition at line 82 of file pata.h.

◆ PCIIDE_CONTROL_IO_BAR_OFFSET

#define PCIIDE_CONTROL_IO_BAR_OFFSET   2

Definition at line 84 of file pata.h.

◆ PCIIDE_CONTROL_IO_RANGE_LENGTH

#define PCIIDE_CONTROL_IO_RANGE_LENGTH   4

Definition at line 83 of file pata.h.

◆ PCIIDE_DMA_COMMAND

#define PCIIDE_DMA_COMMAND   0

IDE Bus Master I/O Registers

Definition at line 106 of file pata.h.

◆ PCIIDE_DMA_COMMAND_READ_FROM_SYSTEM_MEMORY

#define PCIIDE_DMA_COMMAND_READ_FROM_SYSTEM_MEMORY   0x00

Definition at line 117 of file pata.h.

◆ PCIIDE_DMA_COMMAND_START

#define PCIIDE_DMA_COMMAND_START   0x01

Definition at line 116 of file pata.h.

◆ PCIIDE_DMA_COMMAND_STOP

#define PCIIDE_DMA_COMMAND_STOP   0x00

IDE Bus Master Command Register

Definition at line 115 of file pata.h.

◆ PCIIDE_DMA_COMMAND_WRITE_TO_SYSTEM_MEMORY

#define PCIIDE_DMA_COMMAND_WRITE_TO_SYSTEM_MEMORY   0x08

Definition at line 118 of file pata.h.

◆ PCIIDE_DMA_IO_BAR

#define PCIIDE_DMA_IO_BAR   4

Definition at line 85 of file pata.h.

◆ PCIIDE_DMA_IO_RANGE_LENGTH

#define PCIIDE_DMA_IO_RANGE_LENGTH   16

Definition at line 86 of file pata.h.

◆ PCIIDE_DMA_PRDT_PHYSICAL_ADDRESS

#define PCIIDE_DMA_PRDT_PHYSICAL_ADDRESS   4

Definition at line 108 of file pata.h.

◆ PCIIDE_DMA_SECONDARY_CHANNEL_OFFSET

#define PCIIDE_DMA_SECONDARY_CHANNEL_OFFSET   8

Offset from base address

Definition at line 89 of file pata.h.

◆ PCIIDE_DMA_STATUS

#define PCIIDE_DMA_STATUS   2

Definition at line 107 of file pata.h.

◆ PCIIDE_DMA_STATUS_ACTIVE

#define PCIIDE_DMA_STATUS_ACTIVE   0x01

IDE Bus Master Status Register

Definition at line 125 of file pata.h.

◆ PCIIDE_DMA_STATUS_DRIVE0_DMA_CAPABLE

#define PCIIDE_DMA_STATUS_DRIVE0_DMA_CAPABLE   0x20

Definition at line 130 of file pata.h.

◆ PCIIDE_DMA_STATUS_DRIVE1_DMA_CAPABLE

#define PCIIDE_DMA_STATUS_DRIVE1_DMA_CAPABLE   0x40

Definition at line 131 of file pata.h.

◆ PCIIDE_DMA_STATUS_ERROR

#define PCIIDE_DMA_STATUS_ERROR   0x02

Definition at line 126 of file pata.h.

◆ PCIIDE_DMA_STATUS_INTERRUPT

#define PCIIDE_DMA_STATUS_INTERRUPT   0x04

Definition at line 127 of file pata.h.

◆ PCIIDE_DMA_STATUS_RESERVED1

#define PCIIDE_DMA_STATUS_RESERVED1   0x08

Definition at line 128 of file pata.h.

◆ PCIIDE_DMA_STATUS_RESERVED2

#define PCIIDE_DMA_STATUS_RESERVED2   0x10

Definition at line 129 of file pata.h.

◆ PCIIDE_DMA_STATUS_SIMPLEX

#define PCIIDE_DMA_STATUS_SIMPLEX   0x80

Definition at line 132 of file pata.h.

◆ PCIIDE_LEGACY_COMMAND_IO_RANGE_LENGTH

#define PCIIDE_LEGACY_COMMAND_IO_RANGE_LENGTH   8

Definition at line 72 of file pata.h.

◆ PCIIDE_LEGACY_CONTROL_IO_RANGE_LENGTH

#define PCIIDE_LEGACY_CONTROL_IO_RANGE_LENGTH   1

Definition at line 73 of file pata.h.

◆ PCIIDE_LEGACY_PRIMARY_COMMAND_BASE

#define PCIIDE_LEGACY_PRIMARY_COMMAND_BASE   0x1F0

Definition at line 74 of file pata.h.

◆ PCIIDE_LEGACY_PRIMARY_CONTROL_BASE

#define PCIIDE_LEGACY_PRIMARY_CONTROL_BASE   0x3F6

Definition at line 75 of file pata.h.

◆ PCIIDE_LEGACY_PRIMARY_IRQ

#define PCIIDE_LEGACY_PRIMARY_IRQ   14

Definition at line 76 of file pata.h.

◆ PCIIDE_LEGACY_RESOURCE_COUNT

#define PCIIDE_LEGACY_RESOURCE_COUNT   3

Legacy ranges and interrupts

Definition at line 71 of file pata.h.

◆ PCIIDE_LEGACY_SECONDARY_COMMAND_BASE

#define PCIIDE_LEGACY_SECONDARY_COMMAND_BASE   0x170

Definition at line 77 of file pata.h.

◆ PCIIDE_LEGACY_SECONDARY_CONTROL_BASE

#define PCIIDE_LEGACY_SECONDARY_CONTROL_BASE   0x376

Definition at line 78 of file pata.h.

◆ PCIIDE_LEGACY_SECONDARY_IRQ

#define PCIIDE_LEGACY_SECONDARY_IRQ   15

Definition at line 79 of file pata.h.

◆ PCIIDE_PRD_END_OF_TABLE

#define PCIIDE_PRD_END_OF_TABLE   0x80000000

Definition at line 210 of file pata.h.

◆ PCIIDE_PRD_LENGTH_MASK

#define PCIIDE_PRD_LENGTH_MASK   0xFFFF

Definition at line 209 of file pata.h.

◆ PCIIDE_PRD_LIMIT

#define PCIIDE_PRD_LIMIT   0x10000

64 kB boundary

Definition at line 215 of file pata.h.

◆ PCIIDE_PROGIF_DMA_CAPABLE

#define PCIIDE_PROGIF_DMA_CAPABLE   0x80

Definition at line 99 of file pata.h.

◆ PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE

#define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE   0x01

Programming Interface Register

Definition at line 95 of file pata.h.

◆ PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE_CAPABLE

#define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE_CAPABLE   0x02

Definition at line 96 of file pata.h.

◆ PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE

#define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE   0x04

Definition at line 97 of file pata.h.

◆ PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE_CAPABLE

#define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE_CAPABLE   0x08

Definition at line 98 of file pata.h.

◆ SATA_ALL

#define SATA_ALL    (PIO_ALL | MWDMA_ALL | UDMA_ALL)

Supported transfer modes by SATA devices

Definition at line 37 of file pata.h.

◆ SHARED_ADDR_TIMINGS

#define SHARED_ADDR_TIMINGS   0x00000004

Definition at line 232 of file pata.h.

◆ SHARED_CMD_TIMINGS

#define SHARED_CMD_TIMINGS   0x00000001

Definition at line 230 of file pata.h.

◆ SHARED_DATA_TIMINGS

#define SHARED_DATA_TIMINGS   0x00000002

Definition at line 231 of file pata.h.

◆ UDMA_80C_ALL

#define UDMA_80C_ALL    (UDMA_MODE3 | UDMA_MODE4 | UDMA_MODE5 | UDMA_MODE6)

UDMA modes that require the presence of an 80-conductor ATA cable

Definition at line 41 of file pata.h.

◆ UDMA_MODES

#define UDMA_MODES (   MinMode,
  MaxMode 
)     (NUM_TO_BITMAP(UDMA_MODE((MaxMode) + 1)) & ~NUM_TO_BITMAP(UDMA_MODE(MinMode)))

Used to specify a range of UDMA modes

Definition at line 49 of file pata.h.

Typedef Documentation

◆ ATA_TIMING

typedef struct _ATA_TIMING ATA_TIMING

◆ ATATIM

typedef USHORT ATATIM

Definition at line 217 of file pata.h.

◆ PATA_TIMING

typedef struct _ATA_TIMING * PATA_TIMING

◆ PCIIDE_PRD_TABLE_ENTRY

typedef struct _PCIIDE_PRD_TABLE_ENTRY PCIIDE_PRD_TABLE_ENTRY

Physical Region Descriptor Table Entry

◆ PPCIIDE_PRD_TABLE_ENTRY

typedef struct _PCIIDE_PRD_TABLE_ENTRY * PPCIIDE_PRD_TABLE_ENTRY

Function Documentation

◆ ATA_SELECT_DEVICE()

FORCEINLINE VOID ATA_SELECT_DEVICE ( _In_ PCHANNEL_DATA_PATA  ChanData,
_In_ UCHAR  DeviceNumber,
_In_ UCHAR  DeviceSelect 
)

Definition at line 271 of file pata.h.

275{
276#if defined(_M_IX86)
277 /* NEC extension to allow 4 drives per channel */
278 if ((ChanData->ChanInfo & CHANNEL_FLAG_CBUS) &&
279 (ChanData->LastAtaBankId != DeviceNumber))
280 {
281 UCHAR AtaBank;
282
283 ChanData->LastAtaBankId = DeviceNumber;
284
285 /* The 0x432 port is used to select the primary (0) or secondary (1) IDE channel */
286 AtaBank = DeviceNumber >> 1;
287
288 if (ChanData->ChanInfo & CHANNEL_FLAG_IO32)
289 AtaBank |= PC98_ATA_BANK_32BIT_PORT;
290
291 WRITE_PORT_UCHAR((PUCHAR)PC98_ATA_BANK, AtaBank);
292 }
293#endif
294
295 ATA_WRITE(ChanData->Regs.Device, DeviceSelect, ChanData, MRES_TF);
296 ATA_IO_WAIT();
297}
DeviceNumber
_In_ PCHAR _In_ ULONG DeviceNumber
Definition: classpnp.h:1230
ATA_IO_WAIT
#define ATA_IO_WAIT()
Definition: pata.h:32
ATA_WRITE
#define ATA_WRITE(Port, Value, Ctx, MmioFlag)
Definition: pata.h:263
PC98_ATA_BANK
#define PC98_ATA_BANK
Definition: pata.h:28
PC98_ATA_BANK_32BIT_PORT
#define PC98_ATA_BANK_32BIT_PORT
Definition: pata.h:29
WRITE_PORT_UCHAR
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:21
CHANNEL_FLAG_IO32
#define CHANNEL_FLAG_IO32
Definition: pciidex.h:260
CHANNEL_FLAG_CBUS
#define CHANNEL_FLAG_CBUS
Definition: pciidex.h:283
UCHAR
unsigned char UCHAR
Definition: typedefs.h:53
PUCHAR
unsigned char * PUCHAR
Definition: typedefs.h:53

Referenced by PataChangeInterruptMode(), PataIsDevicePresent(), PataResetChannel(), and PataStartIo().

◆ ATA_WAIT()

FORCEINLINE UCHAR ATA_WAIT ( _In_ PCHANNEL_DATA_PATA  ChanData,
_In_range_(>, 0) ULONG  Timeout,
_In_ UCHAR  Mask,
_In_ UCHAR  Value 
)

Definition at line 301 of file pata.h.

306{
307 UCHAR IdeStatus;
308 ULONG i;
309
310 for (i = 0; i < Timeout; ++i)
311 {
312 IdeStatus = ChanData->ReadStatus(ChanData);
313 if ((IdeStatus & Mask) == Value)
314 break;
315
316 if (IdeStatus == 0xFF)
317 break;
318
319 KeStallExecutionProcessor(10);
320 }
321
322 return IdeStatus;
323}
Mask
unsigned int Mask
Definition: fpcontrol.c:82
i
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
KeStallExecutionProcessor
#define KeStallExecutionProcessor(MicroSeconds)
Definition: precomp.h:27
Timeout
static ULONG Timeout
Definition: ping.c:61
ULONG
uint32_t ULONG
Definition: typedefs.h:59
Value
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING _Out_opt_ PUSHORT _Inout_opt_ PUNICODE_STRING Value
Definition: wdfregistry.h:413

Referenced by PataChangeInterruptMode(), PataIdentifyDevice(), PataPoll(), PataProcessAtapiRequest(), PataProcessAtaRequest(), and PataStartIo().

◆ C_ASSERT() [1/4]

C_ASSERT ( CMD_FLAG_AWAIT_INTERRUPT  = =REQUEST_FLAG_POLL)

◆ C_ASSERT() [2/4]

C_ASSERT ( CMD_FLAG_DATA_IN  = =REQUEST_FLAG_DATA_IN)

◆ C_ASSERT() [3/4]

C_ASSERT ( CMD_FLAG_DATA_OUT  = =REQUEST_FLAG_DATA_OUT)

◆ C_ASSERT() [4/4]

C_ASSERT ( CMD_FLAG_DMA_TRANSFER  = =(CMD_FLAG_ATAPI_PIO_TRANSFER|CMD_FLAG_ATA_PIO_TRANSFER))

◆ CLAMP_TIMING()

FORCEINLINE ATATIM CLAMP_TIMING ( _In_ ATATIM  Value,
_In_ ATATIM  Minimum,
_In_ ATATIM  Maximum 
)

Definition at line 236 of file pata.h.

240{
241 if (Value < Minimum)
242 return Minimum;
243 if (Value > Maximum)
244 return Maximum;
245 return Value;
246}

Referenced by ViaClampTimings().