ReactOS 0.4.16-dev-36-g301675c
precomp.h
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1/*
2 * PROJECT: ReactOS API Tests
3 * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later)
4 * PURPOSE: Precompiled header for isapnp_unittest
5 * COPYRIGHT: Copyright 2024 Dmitry Borisov <di.sean@protonmail.com>
6 */
7
8#pragma once
9
10#include <apitest.h>
11
12#define WIN32_NO_STATUS
13#include <ndk/rtlfuncs.h>
14
16
17#define UNIT_TEST
18#include <isapnphw.h>
19#include <isapnpres.h>
20
21/* KERNEL DEFINITIONS (MOCK) **************************************************/
22
23#define PAGED_CODE()
24#define CODE_SEG(segment)
25#define DPRINT(...) do { if (0) { trace(__VA_ARGS__); } } while (0)
26#define DPRINT1(...) do { if (0) { trace(__VA_ARGS__); } } while (0)
27#define KeStallExecutionProcessor(MicroSeconds)
28
32{
33 PULONG_PTR Mem = HeapAlloc(GetProcessHeap(), 0, NumberOfBytes + 2 * sizeof(PVOID));
34 if (Mem == NULL)
35 return NULL;
36
37 Mem[0] = NumberOfBytes;
38 Mem[1] = Tag;
39
40 return (PVOID)(Mem + 2);
41}
42
46{
48
49 if (Result != NULL)
51
52 return Result;
53}
54
56VOID
58{
59 PULONG_PTR Mem = MemPtr;
60
61 Mem -= 2;
62 ok(Mem[1] == Tag, "Tag is %lx, expected %lx\n", Tag, Mem[1]);
63 HeapFree(GetProcessHeap(), 0, Mem);
64}
65
69{
70 PVOID* Mem = MemPtr;
71
72 Mem -= 2;
73 return (SIZE_T)Mem[0];
74}
75
76/* ISAPNP DRIVER DEFINITIONS (MOCK) *******************************************/
77
78#define TAG_ISAPNP 'pasI'
79
80typedef struct _ISAPNP_FDO_EXTENSION
81{
87
88typedef struct _ISAPNP_PDO_EXTENSION
89{
91
93
97
98/* TEST DEFINITIONS ***********************************************************/
99
100typedef enum _ISAPNP_STATE
101{
105 IsaConfgure = 3
107
109{
112
113#define TEST_MAX_SUPPORTED_DEVICES 7
114
115typedef struct _ISAPNP_CARD
116{
132
133UCHAR
134NTAPI
137
138VOID
139NTAPI
143
144VOID
147 _In_ PVOID PnpRom,
148 _In_ ULONG RomSize,
149 _In_ ULONG LogicalDevices);
150
151VOID
154
155VOID
159
160VOID
164
165VOID
169
170VOID
174
175VOID
179
180VOID
184
185VOID
189
192
193VOID
196
197VOID
200
201#define expect_resource_list_header(ResourceList, ExpectedIface, ExpectedCount) \
202 do { \
203 ok_eq_int((ResourceList)->List[0].InterfaceType, (ExpectedIface)); \
204 ok_eq_ulong((ResourceList)->List[0].BusNumber, 0UL); \
205 ok_eq_int((ResourceList)->List[0].PartialResourceList.Version, 1); /* 0 */ \
206 ok_eq_int((ResourceList)->List[0].PartialResourceList.Revision, 1); /* 0x3000 */ \
207 ok_eq_ulong((ResourceList)->List[0].PartialResourceList.Count, (ExpectedCount)); \
208 } while (0)
209
210#define expect_requirements_list_header(ReqList, ExpectedIface, ExpectedCount) \
211 do { \
212 ok_eq_int((ReqList)->InterfaceType, (ExpectedIface)); \
213 ok_eq_ulong((ReqList)->BusNumber, 0UL); \
214 ok_eq_ulong((ReqList)->SlotNumber, 0UL); \
215 ok_eq_ulong((ReqList)->AlternativeLists, (ExpectedCount)); \
216 } while (0)
217
218#define expect_alt_list_header(AltList, ExpectedCount) \
219 do { \
220 ok_eq_int((AltList)->Version, 1); \
221 ok_eq_int((AltList)->Revision, 1); \
222 ok_eq_ulong((AltList)->Count, (ExpectedCount)); \
223 } while (0)
224
225#define expect_port_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
226 ExpectedLength, ExpectedAlign, ExpectedMin, ExpectedMax) \
227 do { \
228 ok((Desc)->Type == CmResourceTypePort, \
229 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypePort); \
230 ok((Desc)->Option == (ExpectedOption), \
231 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
232 ok((Desc)->Flags == (ExpectedFlags), \
233 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
234 ok((Desc)->ShareDisposition == (ExpectedShare), \
235 "Desc->ShareDisposition = %u, expected %u\n", \
236 (Desc)->ShareDisposition, (ExpectedShare)); \
237 ok((Desc)->u.Port.Length == (ExpectedLength), \
238 "Desc->u.Port.Length = %lx, expected %lx\n", \
239 (Desc)->u.Port.Length, (ExpectedLength)); \
240 ok((Desc)->u.Port.Alignment == (ExpectedAlign), \
241 "Desc->u.Port.Alignment = %lu, expected %lu\n", \
242 (Desc)->u.Port.Alignment, (ExpectedAlign)); \
243 ok((Desc)->u.Port.MinimumAddress.QuadPart == (ExpectedMin), \
244 "Desc->u.Port.MinimumAddress = 0x%I64x, expected 0x%I64x\n", \
245 (Desc)->u.Port.MinimumAddress.QuadPart, (ExpectedMin)); \
246 ok((Desc)->u.Port.MaximumAddress.QuadPart == (ExpectedMax), \
247 "Desc->u.Port.MaximumAddress = 0x%I64x, expected 0x%I64x\n", \
248 (Desc)->u.Port.MaximumAddress.QuadPart, (ExpectedMax)); \
249 } while (0)
250
251#define expect_irq_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
252 ExpectedMin, ExpectedMax) \
253 do { \
254 ok((Desc)->Type == CmResourceTypeInterrupt, \
255 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeInterrupt); \
256 ok((Desc)->Option == (ExpectedOption), \
257 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
258 ok((Desc)->Flags == (ExpectedFlags), \
259 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
260 ok((Desc)->ShareDisposition == (ExpectedShare), \
261 "Desc->ShareDisposition = %u, expected %u\n", \
262 (Desc)->ShareDisposition, (ExpectedShare)); \
263 ok((Desc)->u.Interrupt.MinimumVector == (ExpectedMin), \
264 "Desc->u.Interrupt.MinimumVector = %lu, expected %lu\n", \
265 (Desc)->u.Interrupt.MinimumVector, (ExpectedMin)); \
266 ok((Desc)->u.Interrupt.MaximumVector == (ExpectedMax), \
267 "Desc->u.Interrupt.MaximumVector = %lu, expected %lu\n", \
268 (Desc)->u.Interrupt.MaximumVector, (ExpectedMax)); \
269 } while (0)
270
271#define expect_dma_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
272 ExpectedMin, ExpectedMax) \
273 do { \
274 ok((Desc)->Type == CmResourceTypeDma, \
275 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeDma); \
276 ok((Desc)->Option == (ExpectedOption), \
277 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
278 ok((Desc)->Flags == (ExpectedFlags), \
279 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
280 ok((Desc)->ShareDisposition == (ExpectedShare), \
281 "Desc->ShareDisposition = %u, expected %u\n", \
282 (Desc)->ShareDisposition, (ExpectedShare)); \
283 ok((Desc)->u.Dma.MinimumChannel == (ExpectedMin), \
284 "Desc->u.Dma.MinimumChannel = %lu, expected %lu\n", \
285 (Desc)->u.Dma.MinimumChannel, (ExpectedMin)); \
286 ok((Desc)->u.Dma.MaximumChannel == (ExpectedMax), \
287 "Desc->u.Dma.MaximumChannel = %lu, expected %lu\n", \
288 (Desc)->u.Dma.MaximumChannel, (ExpectedMax)); \
289 } while (0)
290
291#define expect_mem_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
292 ExpectedLength, ExpectedAlign, ExpectedMin, ExpectedMax) \
293 do { \
294 ok((Desc)->Type == CmResourceTypeMemory, \
295 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeMemory); \
296 ok((Desc)->Option == (ExpectedOption), \
297 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
298 ok((Desc)->Flags == (ExpectedFlags), \
299 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
300 ok((Desc)->ShareDisposition == (ExpectedShare), \
301 "Desc->ShareDisposition = %u, expected %u\n", \
302 (Desc)->ShareDisposition, (ExpectedShare)); \
303 ok((Desc)->u.Memory.Length == (ExpectedLength), \
304 "Desc->u.Memory.Length = %lx, expected %lx\n", \
305 (Desc)->u.Memory.Length, (ExpectedLength)); \
306 ok((Desc)->u.Memory.Alignment == (ExpectedAlign), \
307 "Desc->u.Memory.Alignment = %lx, expected %lx\n", \
308 (Desc)->u.Memory.Alignment, (ExpectedAlign)); \
309 ok((Desc)->u.Memory.MinimumAddress.QuadPart == (ExpectedMin), \
310 "Desc->u.Memory.MinimumAddress = 0x%I64x, expected 0x%I64x\n", \
311 (Desc)->u.Memory.MinimumAddress.QuadPart, (ExpectedMin)); \
312 ok((Desc)->u.Memory.MaximumAddress.QuadPart == (ExpectedMax), \
313 "Desc->u.Memory.MaximumAddress = 0x%I64x, expected 0x%I64x\n", \
314 (Desc)->u.Memory.MaximumAddress.QuadPart, (ExpectedMax)); \
315 } while (0)
316
317#define expect_cfg_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
318 ExpectedPriority, ExpectedRes1, ExpectedRes2) \
319 do { \
320 ok((Desc)->Type == CmResourceTypeConfigData, \
321 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeConfigData); \
322 ok((Desc)->Option == (ExpectedOption), \
323 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
324 ok((Desc)->Flags == (ExpectedFlags), \
325 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
326 ok((Desc)->ShareDisposition == (ExpectedShare), \
327 "Desc->ShareDisposition = %u, expected %u\n", \
328 (Desc)->ShareDisposition, (ExpectedShare)); \
329 ok((Desc)->u.ConfigData.Priority == (ExpectedPriority), \
330 "Desc->u.ConfigData.Priority = %lx, expected %lx\n", \
331 (Desc)->u.ConfigData.Priority, (ExpectedPriority)); \
332 ok((Desc)->u.ConfigData.Reserved1 == (ExpectedRes1), \
333 "Desc->u.ConfigData.Reserved1 = %lx, expected %lx\n", \
334 (Desc)->u.ConfigData.Reserved2, (ExpectedRes1)); \
335 ok((Desc)->u.ConfigData.Reserved2 == (ExpectedRes2), \
336 "Desc->u.ConfigData.Reserved2 = %lx, expected %lx\n", \
337 (Desc)->u.ConfigData.Reserved2, (ExpectedRes2)); \
338 } while (0)
339
340#define expect_port_res(Desc, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedStart) \
341 do { \
342 ok((Desc)->Type == CmResourceTypePort, \
343 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypePort); \
344 ok((Desc)->Flags == (ExpectedFlags), \
345 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
346 ok((Desc)->ShareDisposition == (ExpectedShare), \
347 "Desc->ShareDisposition = %u, expected %u\n", \
348 (Desc)->ShareDisposition, (ExpectedShare)); \
349 ok((Desc)->u.Port.Length == (ExpectedLength), \
350 "Desc->u.Port.Length = %lx, expected %lx\n", \
351 (Desc)->u.Port.Length, (ExpectedLength)); \
352 ok((Desc)->u.Port.Start.QuadPart == (ExpectedStart), \
353 "Desc->u.Port.Start = 0x%I64x, expected 0x%I64x\n", \
354 (Desc)->u.Port.Start.QuadPart, (ExpectedStart)); \
355 } while (0)
356
357#define expect_irq_res(Desc, ExpectedFlags, ExpectedShare, \
358 ExpectedLevel, ExpectedVector, ExpectedAffinity) \
359 do { \
360 ok((Desc)->Type == CmResourceTypeInterrupt, \
361 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeInterrupt); \
362 ok((Desc)->Flags == (ExpectedFlags), \
363 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
364 ok((Desc)->ShareDisposition == (ExpectedShare), \
365 "Desc->ShareDisposition = %u, expected %u\n", \
366 (Desc)->ShareDisposition, (ExpectedShare)); \
367 ok((Desc)->u.Interrupt.Level == (ExpectedLevel), \
368 "Desc->u.Interrupt.Level = %lu\n", (Desc)->u.Interrupt.Level); \
369 ok((Desc)->u.Interrupt.Vector == (ExpectedVector), \
370 "Desc->u.Interrupt.Vector = %lu\n", (Desc)->u.Interrupt.Vector); \
371 ok((Desc)->u.Interrupt.Affinity == (ExpectedAffinity), \
372 "Desc->u.Interrupt.Affinity = %Ix\n", (Desc)->u.Interrupt.Affinity); \
373 } while (0)
374
375#define expect_dma_res(Desc, ExpectedFlags, ExpectedShare, ExpectedChannel) \
376 do { \
377 ok((Desc)->Type == CmResourceTypeDma, \
378 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeDma); \
379 ok((Desc)->Flags == (ExpectedFlags), \
380 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
381 ok((Desc)->ShareDisposition == (ExpectedShare), \
382 "Desc->ShareDisposition = %u, expected %u\n", \
383 (Desc)->ShareDisposition, (ExpectedShare)); \
384 ok((Desc)->u.Dma.Channel == (ExpectedChannel), \
385 "Desc->u.Dma.Channel = %lu, expected %lu\n", \
386 (Desc)->u.Dma.Channel, (ExpectedChannel)); \
387 ok((Desc)->u.Dma.Port == 0ul, \
388 "Desc->u.Dma.Port = %lu, expected %lu\n", \
389 (Desc)->u.Dma.Port, 0ul); \
390 ok((Desc)->u.Dma.Reserved1 == 0ul, \
391 "Desc->u.Dma.Reserved1 = %lx, expected 0\n", (Desc)->u.Dma.Reserved1); \
392 } while (0)
393
394#define expect_mem_res(Desc, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedStart) \
395 do { \
396 ok((Desc)->Type == CmResourceTypeMemory, \
397 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeMemory); \
398 ok((Desc)->Flags == (ExpectedFlags), \
399 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
400 ok((Desc)->ShareDisposition == (ExpectedShare), \
401 "Desc->ShareDisposition = %u, expected %u\n", \
402 (Desc)->ShareDisposition, (ExpectedShare)); \
403 ok((Desc)->u.Memory.Length == (ExpectedLength), \
404 "Desc->u.Memory.Length = %lx, expected %lx\n", \
405 (Desc)->u.Memory.Length, (ExpectedLength)); \
406 ok((Desc)->u.Memory.Start.QuadPart == (ExpectedStart), \
407 "Desc->u.Memory.Start = 0x%I64x, expected 0x%I64x\n", \
408 (Desc)->u.Memory.Start.QuadPart, (ExpectedStart)); \
409 } while (0)
#define ok(value,...)
Definition: atltest.h:57
Definition: card.h:28
#define NULL
Definition: types.h:112
#define GetProcessHeap()
Definition: compat.h:736
#define HeapAlloc
Definition: compat.h:733
#define HeapFree(x, y, z)
Definition: compat.h:735
#define ExAllocatePoolWithTag(hernya, size, tag)
Definition: env_spec_w32.h:350
CPPORT Port[4]
Definition: headless.c:35
#define ExFreePoolWithTag(_P, _T)
Definition: module.h:1109
VOID DrvTestCard1Dev2Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:660
PCM_RESOURCE_LIST DrvTestCard1Dev6CreateConfigurationResources(VOID)
Definition: res_card.c:1260
_ISAPNP_STATE
Definition: precomp.h:101
@ IsaSleep
Definition: precomp.h:103
@ IsaConfgure
Definition: precomp.h:105
@ IsaIsolation
Definition: precomp.h:104
@ IsaWaitForKey
Definition: precomp.h:102
VOID DrvCreateCard1(_In_ PISAPNP_CARD Card)
Definition: res_card.c:226
struct _ISAPNP_CARD * PISAPNP_CARD
enum _ISAPNP_STATE ISAPNP_STATE
struct _ISAPNP_FDO_EXTENSION ISAPNP_FDO_EXTENSION
VOID DrvTestCard1Dev6Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:1162
struct _ISAPNP_FDO_EXTENSION * PISAPNP_FDO_EXTENSION
struct _ISAPNP_PDO_EXTENSION * PISAPNP_PDO_EXTENSION
FORCEINLINE SIZE_T GetPoolAllocSize(PVOID MemPtr)
Definition: precomp.h:68
VOID DrvTestCard1Dev7Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:1331
VOID DrvTestCard1Dev5Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:970
#define TEST_MAX_SUPPORTED_DEVICES
Definition: precomp.h:113
struct _ISAPNP_PDO_EXTENSION ISAPNP_PDO_EXTENSION
PVOID PDEVICE_OBJECT
Definition: precomp.h:15
VOID IsaBusCreateCard(_Inout_ PISAPNP_CARD Card, _In_ PVOID PnpRom, _In_ ULONG RomSize, _In_ ULONG LogicalDevices)
Definition: isabus.c:439
VOID DrvTestCard1Dev6ConfigurationResult(_In_ PISAPNP_CARD_LOGICAL_DEVICE LogDev)
Definition: res_card.c:1171
FORCEINLINE PVOID ExAllocatePoolZero(ULONG PoolType, SIZE_T NumberOfBytes, ULONG Tag)
Definition: precomp.h:45
struct _ISAPNP_CARD_LOGICAL_DEVICE * PISAPNP_CARD_LOGICAL_DEVICE
VOID DrvCreateCard2(_In_ PISAPNP_CARD Card)
Definition: empty_card.c:44
VOID DrvTestCard1Dev1Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:560
VOID DrvTestCard1Dev3Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:760
struct _ISAPNP_CARD ISAPNP_CARD
struct _ISAPNP_CARD_LOGICAL_DEVICE ISAPNP_CARD_LOGICAL_DEVICE
VOID DrvTestCard1Dev4Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:838
#define _Inout_
Definition: ms_sal.h:378
#define _In_
Definition: ms_sal.h:308
#define READ_PORT_UCHAR(p)
Definition: pc98vid.h:22
#define WRITE_PORT_UCHAR(p, d)
Definition: pc98vid.h:21
ISAPNP_CARD_LOGICAL_DEVICE LogDev[TEST_MAX_SUPPORTED_DEVICES]
Definition: precomp.h:130
PUCHAR ReadDataPort
Definition: precomp.h:126
UCHAR Lfsr
Definition: precomp.h:119
UCHAR SerialIdResponse
Definition: precomp.h:123
ULONG LogicalDevices
Definition: precomp.h:129
UCHAR SerialIsolationIdx
Definition: precomp.h:122
UCHAR IsolationRead
Definition: precomp.h:124
UCHAR DeviceNumberReg
Definition: precomp.h:121
ISAPNP_STATE State
Definition: precomp.h:117
ULONG RomSize
Definition: precomp.h:128
ULONG RomIdx
Definition: precomp.h:127
UCHAR LfsrCount
Definition: precomp.h:118
PUCHAR PnpRom
Definition: precomp.h:125
UCHAR SelectNumberReg
Definition: precomp.h:120
PUCHAR ReadDataPort
Definition: isapnp.h:64
LIST_ENTRY DeviceListHead
Definition: precomp.h:82
PCM_RESOURCE_LIST ResourceList
Definition: isapnp.h:89
PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList
Definition: isapnp.h:87
ULONG ResourceListSize
Definition: isapnp.h:90
PISAPNP_LOGICAL_DEVICE IsaPnpDevice
Definition: isapnp.h:85
Definition: typedefs.h:120
uint32_t * PULONG_PTR
Definition: typedefs.h:65
#define NTAPI
Definition: typedefs.h:36
ULONG_PTR SIZE_T
Definition: typedefs.h:80
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
unsigned char * PUCHAR
Definition: typedefs.h:53
uint32_t ULONG
Definition: typedefs.h:59
_Must_inspect_result_ _In_ WDFDEVICE _In_ BOOLEAN _In_opt_ PVOID Tag
Definition: wdfdevice.h:4065
_Must_inspect_result_ _In_ WDFDEVICE _In_ DEVICE_REGISTRY_PROPERTY _In_ _Strict_type_match_ POOL_TYPE PoolType
Definition: wdfdevice.h:3815
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING _Out_opt_ PUSHORT _Inout_opt_ PUNICODE_STRING Value
Definition: wdfregistry.h:413
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
Definition: wdfresource.h:309
#define FORCEINLINE
Definition: wdftypes.h:67
_At_(*)(_In_ PWSK_CLIENT Client, _In_opt_ PUNICODE_STRING NodeName, _In_opt_ PUNICODE_STRING ServiceName, _In_opt_ ULONG NameSpace, _In_opt_ GUID *Provider, _In_opt_ PADDRINFOEXW Hints, _Outptr_ PADDRINFOEXW *Result, _In_opt_ PEPROCESS OwningProcess, _In_opt_ PETHREAD OwningThread, _Inout_ PIRP Irp Result)(Mem)) NTSTATUS(WSKAPI *PFN_WSK_GET_ADDRESS_INFO
Definition: wsk.h:409
_Must_inspect_result_ typedef _In_ PHYSICAL_ADDRESS _Inout_ PLARGE_INTEGER NumberOfBytes
Definition: iotypes.h:1036
unsigned char UCHAR
Definition: xmlstorage.h:181