12#define WIN32_NO_STATUS
24#define CODE_SEG(segment)
25#define DPRINT(...) do { if (0) { trace(__VA_ARGS__); } } while (0)
26#define DPRINT1(...) do { if (0) { trace(__VA_ARGS__); } } while (0)
27#define KeStallExecutionProcessor(MicroSeconds)
40 return (
PVOID)(Mem + 2);
62 ok(Mem[1] ==
Tag,
"Tag is %lx, expected %lx\n",
Tag, Mem[1]);
78#define TAG_ISAPNP 'pasI'
113#define TEST_MAX_SUPPORTED_DEVICES 7
201#define expect_resource_list_header(ResourceList, ExpectedIface, ExpectedCount) \
203 ok_eq_int((ResourceList)->List[0].InterfaceType, (ExpectedIface)); \
204 ok_eq_ulong((ResourceList)->List[0].BusNumber, 0UL); \
205 ok_eq_int((ResourceList)->List[0].PartialResourceList.Version, 1); \
206 ok_eq_int((ResourceList)->List[0].PartialResourceList.Revision, 1); \
207 ok_eq_ulong((ResourceList)->List[0].PartialResourceList.Count, (ExpectedCount)); \
210#define expect_requirements_list_header(ReqList, ExpectedIface, ExpectedCount) \
212 ok_eq_int((ReqList)->InterfaceType, (ExpectedIface)); \
213 ok_eq_ulong((ReqList)->BusNumber, 0UL); \
214 ok_eq_ulong((ReqList)->SlotNumber, 0UL); \
215 ok_eq_ulong((ReqList)->AlternativeLists, (ExpectedCount)); \
218#define expect_alt_list_header(AltList, ExpectedCount) \
220 ok_eq_int((AltList)->Version, 1); \
221 ok_eq_int((AltList)->Revision, 1); \
222 ok_eq_ulong((AltList)->Count, (ExpectedCount)); \
225#define expect_port_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
226 ExpectedLength, ExpectedAlign, ExpectedMin, ExpectedMax) \
228 ok((Desc)->Type == CmResourceTypePort, \
229 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypePort); \
230 ok((Desc)->Option == (ExpectedOption), \
231 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
232 ok((Desc)->Flags == (ExpectedFlags), \
233 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
234 ok((Desc)->ShareDisposition == (ExpectedShare), \
235 "Desc->ShareDisposition = %u, expected %u\n", \
236 (Desc)->ShareDisposition, (ExpectedShare)); \
237 ok((Desc)->u.Port.Length == (ExpectedLength), \
238 "Desc->u.Port.Length = %lx, expected %lx\n", \
239 (Desc)->u.Port.Length, (ExpectedLength)); \
240 ok((Desc)->u.Port.Alignment == (ExpectedAlign), \
241 "Desc->u.Port.Alignment = %lu, expected %lu\n", \
242 (Desc)->u.Port.Alignment, (ExpectedAlign)); \
243 ok((Desc)->u.Port.MinimumAddress.QuadPart == (ExpectedMin), \
244 "Desc->u.Port.MinimumAddress = 0x%I64x, expected 0x%I64x\n", \
245 (Desc)->u.Port.MinimumAddress.QuadPart, (ExpectedMin)); \
246 ok((Desc)->u.Port.MaximumAddress.QuadPart == (ExpectedMax), \
247 "Desc->u.Port.MaximumAddress = 0x%I64x, expected 0x%I64x\n", \
248 (Desc)->u.Port.MaximumAddress.QuadPart, (ExpectedMax)); \
251#define expect_irq_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
252 ExpectedMin, ExpectedMax) \
254 ok((Desc)->Type == CmResourceTypeInterrupt, \
255 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeInterrupt); \
256 ok((Desc)->Option == (ExpectedOption), \
257 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
258 ok((Desc)->Flags == (ExpectedFlags), \
259 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
260 ok((Desc)->ShareDisposition == (ExpectedShare), \
261 "Desc->ShareDisposition = %u, expected %u\n", \
262 (Desc)->ShareDisposition, (ExpectedShare)); \
263 ok((Desc)->u.Interrupt.MinimumVector == (ExpectedMin), \
264 "Desc->u.Interrupt.MinimumVector = %lu, expected %lu\n", \
265 (Desc)->u.Interrupt.MinimumVector, (ExpectedMin)); \
266 ok((Desc)->u.Interrupt.MaximumVector == (ExpectedMax), \
267 "Desc->u.Interrupt.MaximumVector = %lu, expected %lu\n", \
268 (Desc)->u.Interrupt.MaximumVector, (ExpectedMax)); \
271#define expect_dma_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
272 ExpectedMin, ExpectedMax) \
274 ok((Desc)->Type == CmResourceTypeDma, \
275 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeDma); \
276 ok((Desc)->Option == (ExpectedOption), \
277 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
278 ok((Desc)->Flags == (ExpectedFlags), \
279 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
280 ok((Desc)->ShareDisposition == (ExpectedShare), \
281 "Desc->ShareDisposition = %u, expected %u\n", \
282 (Desc)->ShareDisposition, (ExpectedShare)); \
283 ok((Desc)->u.Dma.MinimumChannel == (ExpectedMin), \
284 "Desc->u.Dma.MinimumChannel = %lu, expected %lu\n", \
285 (Desc)->u.Dma.MinimumChannel, (ExpectedMin)); \
286 ok((Desc)->u.Dma.MaximumChannel == (ExpectedMax), \
287 "Desc->u.Dma.MaximumChannel = %lu, expected %lu\n", \
288 (Desc)->u.Dma.MaximumChannel, (ExpectedMax)); \
291#define expect_mem_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
292 ExpectedLength, ExpectedAlign, ExpectedMin, ExpectedMax) \
294 ok((Desc)->Type == CmResourceTypeMemory, \
295 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeMemory); \
296 ok((Desc)->Option == (ExpectedOption), \
297 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
298 ok((Desc)->Flags == (ExpectedFlags), \
299 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
300 ok((Desc)->ShareDisposition == (ExpectedShare), \
301 "Desc->ShareDisposition = %u, expected %u\n", \
302 (Desc)->ShareDisposition, (ExpectedShare)); \
303 ok((Desc)->u.Memory.Length == (ExpectedLength), \
304 "Desc->u.Memory.Length = %lx, expected %lx\n", \
305 (Desc)->u.Memory.Length, (ExpectedLength)); \
306 ok((Desc)->u.Memory.Alignment == (ExpectedAlign), \
307 "Desc->u.Memory.Alignment = %lx, expected %lx\n", \
308 (Desc)->u.Memory.Alignment, (ExpectedAlign)); \
309 ok((Desc)->u.Memory.MinimumAddress.QuadPart == (ExpectedMin), \
310 "Desc->u.Memory.MinimumAddress = 0x%I64x, expected 0x%I64x\n", \
311 (Desc)->u.Memory.MinimumAddress.QuadPart, (ExpectedMin)); \
312 ok((Desc)->u.Memory.MaximumAddress.QuadPart == (ExpectedMax), \
313 "Desc->u.Memory.MaximumAddress = 0x%I64x, expected 0x%I64x\n", \
314 (Desc)->u.Memory.MaximumAddress.QuadPart, (ExpectedMax)); \
317#define expect_cfg_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, \
318 ExpectedPriority, ExpectedRes1, ExpectedRes2) \
320 ok((Desc)->Type == CmResourceTypeConfigData, \
321 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeConfigData); \
322 ok((Desc)->Option == (ExpectedOption), \
323 "Desc->Option = %u, expected %u\n", (Desc)->Option, (ExpectedOption)); \
324 ok((Desc)->Flags == (ExpectedFlags), \
325 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
326 ok((Desc)->ShareDisposition == (ExpectedShare), \
327 "Desc->ShareDisposition = %u, expected %u\n", \
328 (Desc)->ShareDisposition, (ExpectedShare)); \
329 ok((Desc)->u.ConfigData.Priority == (ExpectedPriority), \
330 "Desc->u.ConfigData.Priority = %lx, expected %lx\n", \
331 (Desc)->u.ConfigData.Priority, (ExpectedPriority)); \
332 ok((Desc)->u.ConfigData.Reserved1 == (ExpectedRes1), \
333 "Desc->u.ConfigData.Reserved1 = %lx, expected %lx\n", \
334 (Desc)->u.ConfigData.Reserved2, (ExpectedRes1)); \
335 ok((Desc)->u.ConfigData.Reserved2 == (ExpectedRes2), \
336 "Desc->u.ConfigData.Reserved2 = %lx, expected %lx\n", \
337 (Desc)->u.ConfigData.Reserved2, (ExpectedRes2)); \
340#define expect_port_res(Desc, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedStart) \
342 ok((Desc)->Type == CmResourceTypePort, \
343 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypePort); \
344 ok((Desc)->Flags == (ExpectedFlags), \
345 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
346 ok((Desc)->ShareDisposition == (ExpectedShare), \
347 "Desc->ShareDisposition = %u, expected %u\n", \
348 (Desc)->ShareDisposition, (ExpectedShare)); \
349 ok((Desc)->u.Port.Length == (ExpectedLength), \
350 "Desc->u.Port.Length = %lx, expected %lx\n", \
351 (Desc)->u.Port.Length, (ExpectedLength)); \
352 ok((Desc)->u.Port.Start.QuadPart == (ExpectedStart), \
353 "Desc->u.Port.Start = 0x%I64x, expected 0x%I64x\n", \
354 (Desc)->u.Port.Start.QuadPart, (ExpectedStart)); \
357#define expect_irq_res(Desc, ExpectedFlags, ExpectedShare, \
358 ExpectedLevel, ExpectedVector, ExpectedAffinity) \
360 ok((Desc)->Type == CmResourceTypeInterrupt, \
361 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeInterrupt); \
362 ok((Desc)->Flags == (ExpectedFlags), \
363 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
364 ok((Desc)->ShareDisposition == (ExpectedShare), \
365 "Desc->ShareDisposition = %u, expected %u\n", \
366 (Desc)->ShareDisposition, (ExpectedShare)); \
367 ok((Desc)->u.Interrupt.Level == (ExpectedLevel), \
368 "Desc->u.Interrupt.Level = %lu\n", (Desc)->u.Interrupt.Level); \
369 ok((Desc)->u.Interrupt.Vector == (ExpectedVector), \
370 "Desc->u.Interrupt.Vector = %lu\n", (Desc)->u.Interrupt.Vector); \
371 ok((Desc)->u.Interrupt.Affinity == (ExpectedAffinity), \
372 "Desc->u.Interrupt.Affinity = %Ix\n", (Desc)->u.Interrupt.Affinity); \
375#define expect_dma_res(Desc, ExpectedFlags, ExpectedShare, ExpectedChannel) \
377 ok((Desc)->Type == CmResourceTypeDma, \
378 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeDma); \
379 ok((Desc)->Flags == (ExpectedFlags), \
380 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
381 ok((Desc)->ShareDisposition == (ExpectedShare), \
382 "Desc->ShareDisposition = %u, expected %u\n", \
383 (Desc)->ShareDisposition, (ExpectedShare)); \
384 ok((Desc)->u.Dma.Channel == (ExpectedChannel), \
385 "Desc->u.Dma.Channel = %lu, expected %lu\n", \
386 (Desc)->u.Dma.Channel, (ExpectedChannel)); \
387 ok((Desc)->u.Dma.Port == 0ul, \
388 "Desc->u.Dma.Port = %lu, expected %lu\n", \
389 (Desc)->u.Dma.Port, 0ul); \
390 ok((Desc)->u.Dma.Reserved1 == 0ul, \
391 "Desc->u.Dma.Reserved1 = %lx, expected 0\n", (Desc)->u.Dma.Reserved1); \
394#define expect_mem_res(Desc, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedStart) \
396 ok((Desc)->Type == CmResourceTypeMemory, \
397 "Desc->Type = %u, expected %u\n", (Desc)->Type, CmResourceTypeMemory); \
398 ok((Desc)->Flags == (ExpectedFlags), \
399 "Desc->Flags = %x, expected %x\n", (Desc)->Flags, (ExpectedFlags)); \
400 ok((Desc)->ShareDisposition == (ExpectedShare), \
401 "Desc->ShareDisposition = %u, expected %u\n", \
402 (Desc)->ShareDisposition, (ExpectedShare)); \
403 ok((Desc)->u.Memory.Length == (ExpectedLength), \
404 "Desc->u.Memory.Length = %lx, expected %lx\n", \
405 (Desc)->u.Memory.Length, (ExpectedLength)); \
406 ok((Desc)->u.Memory.Start.QuadPart == (ExpectedStart), \
407 "Desc->u.Memory.Start = 0x%I64x, expected 0x%I64x\n", \
408 (Desc)->u.Memory.Start.QuadPart, (ExpectedStart)); \
#define HeapFree(x, y, z)
#define ExAllocatePoolWithTag(hernya, size, tag)
#define ExFreePoolWithTag(_P, _T)
VOID DrvTestCard1Dev2Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
PCM_RESOURCE_LIST DrvTestCard1Dev6CreateConfigurationResources(VOID)
VOID DrvCreateCard1(_In_ PISAPNP_CARD Card)
struct _ISAPNP_CARD * PISAPNP_CARD
enum _ISAPNP_STATE ISAPNP_STATE
struct _ISAPNP_FDO_EXTENSION ISAPNP_FDO_EXTENSION
VOID DrvTestCard1Dev6Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
struct _ISAPNP_FDO_EXTENSION * PISAPNP_FDO_EXTENSION
struct _ISAPNP_PDO_EXTENSION * PISAPNP_PDO_EXTENSION
FORCEINLINE SIZE_T GetPoolAllocSize(PVOID MemPtr)
VOID DrvTestCard1Dev7Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
VOID DrvTestCard1Dev5Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
#define TEST_MAX_SUPPORTED_DEVICES
struct _ISAPNP_PDO_EXTENSION ISAPNP_PDO_EXTENSION
VOID IsaBusCreateCard(_Inout_ PISAPNP_CARD Card, _In_ PVOID PnpRom, _In_ ULONG RomSize, _In_ ULONG LogicalDevices)
VOID DrvTestCard1Dev6ConfigurationResult(_In_ PISAPNP_CARD_LOGICAL_DEVICE LogDev)
FORCEINLINE PVOID ExAllocatePoolZero(ULONG PoolType, SIZE_T NumberOfBytes, ULONG Tag)
struct _ISAPNP_CARD_LOGICAL_DEVICE * PISAPNP_CARD_LOGICAL_DEVICE
VOID DrvCreateCard2(_In_ PISAPNP_CARD Card)
VOID DrvTestCard1Dev1Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
VOID DrvTestCard1Dev3Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
struct _ISAPNP_CARD ISAPNP_CARD
struct _ISAPNP_CARD_LOGICAL_DEVICE ISAPNP_CARD_LOGICAL_DEVICE
VOID DrvTestCard1Dev4Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
#define READ_PORT_UCHAR(p)
#define WRITE_PORT_UCHAR(p, d)
ISAPNP_CARD_LOGICAL_DEVICE LogDev[TEST_MAX_SUPPORTED_DEVICES]
LIST_ENTRY DeviceListHead
PCM_RESOURCE_LIST ResourceList
PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList
PISAPNP_LOGICAL_DEVICE IsaPnpDevice
#define RtlZeroMemory(Destination, Length)
_Must_inspect_result_ _In_ WDFDEVICE _In_ BOOLEAN _In_opt_ PVOID Tag
_Must_inspect_result_ _In_ WDFDEVICE _In_ DEVICE_REGISTRY_PROPERTY _In_ _Strict_type_match_ POOL_TYPE PoolType
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING _Out_opt_ PUSHORT _Inout_opt_ PUNICODE_STRING Value
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
_At_(*)(_In_ PWSK_CLIENT Client, _In_opt_ PUNICODE_STRING NodeName, _In_opt_ PUNICODE_STRING ServiceName, _In_opt_ ULONG NameSpace, _In_opt_ GUID *Provider, _In_opt_ PADDRINFOEXW Hints, _Outptr_ PADDRINFOEXW *Result, _In_opt_ PEPROCESS OwningProcess, _In_opt_ PETHREAD OwningThread, _Inout_ PIRP Irp Result)(Mem)) NTSTATUS(WSKAPI *PFN_WSK_GET_ADDRESS_INFO
_Must_inspect_result_ typedef _In_ PHYSICAL_ADDRESS _Inout_ PLARGE_INTEGER NumberOfBytes