ReactOS 0.4.16-dev-297-gc569aee
res_card.c
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1/*
2 * PROJECT: ReactOS API Tests
3 * LICENSE: LGPL-2.1-or-later (https://spdx.org/licenses/LGPL-2.1-or-later)
4 * PURPOSE: Dummy card resource tests for the ISA PnP bus driver
5 * COPYRIGHT: Copyright 2024 Dmitry Borisov <di.sean@protonmail.com>
6 */
7
8/* INCLUDES *******************************************************************/
9
10#include "precomp.h"
11
12/* GLOBALS ********************************************************************/
13
15{
16 0x49, 0xF3, // Vendor ID 0xF349 'ROS'
17 0x12, 0x34, // Product ID 0x1234
18 0xFF, 0xFF, 0xFF, 0xFF, // Serial Number
19 0xFF, // Checksum (dummy)
20
21 0x0A, 0x10, 0x10, // PnP version 1.0, vendor version 1.0
22
23 0x82, 6, 0x00, // ANSI identifier 'Test 1'
24 'T', 'e', 's', 't', ' ', '1',
25
26 /* ********************* DEVICE 1 ********************* */
27
28 0x15, // Logical device ID
29 0xC9, 0xF3, // Vendor ID 0xF3C9 'ROS'
30 0x12, 0x34, // Product ID 0x1234
31 0x00,
32
33 0x82, 12, 0x00, // ANSI identifier 'Test 1 Dev 1'
34 'T', 'e', 's', 't', ' ', '1', ' ',
35 'D', 'e', 'v', ' ', '1',
36
37 // (A) Fixed
38 // (B) Dependent
39 // (C) Fixed
40 // (D) End
41
42 0x47, 0x01, 0x30, 0x03, 0x40, 0x03, 0x04, 0x02, // I/O Base 16-bit 0x330-0x340, len 2, align 4
43
44 0x30, // Start dependent Function
45
46 0x47, 0x00, 0x00, 0x06, 0x80, 0x07, 0x01, 0x08, // I/O Base 10-bit 0x600-0x780, len 8, align 1
47 0x4B, 0x16, 0xFC, 0x0C, // Fixed I/O 0x16, length 12 (NOTE: We fill byte 2 with garbage)
48
49 0x22, 0x20, 0x00, // IRQ 5 positive edge triggered
50 0x23, 0x1C, 0x00, 0x08, // IRQ 2, 3, 4 active low, level-sensitive
51
52 0x31, 0x02, // Start dependent Function
53
54 0x81, 0x09, 0x00, // Memory Range
55 0x1B, // Writeable, read-cacheable, write-through, supports range length, 32-bit memory only
56 0x80, 0x0C, // Range minimum 0xC8000
57 0xC0, 0x0D, // Range maximum 0xDC000
58 0x40, 0xFF, // Base alignment 0xFF40
59 0x40, 0x00, // Range length 0x4000
60
61 0x81, 0x09, 0x00, // Memory Range
62 0x66, // Non-writeable, read-cacheable, write-through,
63 // supports high address, 8-bit, shadowable, expansion ROM
64 0x40, 0x0D, // Range minimum 0xD4000
65 0x80, 0x0D, // Range maximum 0xD8000
66 0x00, 0x00, // Base alignment 0x10000 (NOTE: Special case)
67 0x40, 0x00, // Range length 0x4000
68
69 0x2A, 0x03, 0x04, // DMA 0 or 1. 8-bit only, ISA Master, not use count by byte/word, ISA compat
70
71 0x38, // End dependent Function
72
73 0x2A, 0x04, 0x41, // DMA 3. 8- and 16-bit, not use count by byte/word, Type B
74
75 /* ********************* DEVICE 2 ********************* */
76
77 0x15, // Logical device ID
78 0xC9, 0xF3, // Vendor ID 0xF3C9 'ROS'
79 0x12, 0x35, // Product ID 0x1235
80 0x00,
81
82 // (A) Fixed
83 // (B) Dependent
84 // (C) End
85
86 0x47, 0x01, 0x00, 0x05, 0x06, 0x05, 0x01, 0x01, // I/O Base 16-bit 0x500-0x506, len 1, align 1
87
88 0x30, // Start dependent Function
89
90 0x47, 0x01, 0x00, 0x06, 0x07, 0x06, 0x01, 0x01, // I/O Base 16-bit 0x600-0x607, len 1, align 1
91
92 0x30, // Start dependent Function
93
94 0x47, 0x01, 0x00, 0x07, 0x08, 0x07, 0x01, 0x01, // I/O Base 16-bit 0x700-0x708, len 1, align 1
95
96 0x38, // End dependent Function
97
98 /* ********************* DEVICE 3 ********************* */
99
100 0x15, // Logical device ID
101 0xC9, 0xF3, // Vendor ID 0xF3C9 'ROS'
102 0x12, 0x36, // Product ID 0x1236
103 0x00,
104
105 // (A) Dependent
106 // (B) Fixed
107 // (C) End
108
109 0x30, // Start dependent Function
110
111 0x47, 0x01, 0x00, 0x06, 0x07, 0x06, 0x01, 0x01, // I/O Base 16-bit 0x600-0x607, len 1, align 1
112
113 0x30, // Start dependent Function
114
115 0x47, 0x01, 0x00, 0x07, 0x08, 0x07, 0x01, 0x01, // I/O Base 16-bit 0x700-0x708, len 1, align 1
116
117 0x38, // End dependent Function
118
119 0x47, 0x01, 0x00, 0x05, 0x06, 0x05, 0x01, 0x01, // I/O Base 16-bit 0x500-0x506, len 1, align 1
120
121 /* ********************* DEVICE 4 ********************* */
122
123 0x15, // Logical device ID
124 0xC9, 0xF3, // Vendor ID 0xF3C9 'ROS'
125 0x12, 0x36, // Product ID 0x1236
126 0x00,
127
128 // (A) Dependent
129 // (B) End
130
131 0x30, // Start dependent Function
132
133 0x47, 0x01, 0x00, 0x06, 0x07, 0x06, 0x01, 0x01, // I/O Base 16-bit 0x600-0x607, len 1, align 1
134
135 0x30, // Start dependent Function
136
137 0x47, 0x01, 0x00, 0x07, 0x08, 0x07, 0x01, 0x01, // I/O Base 16-bit 0x700-0x708, len 1, align 1
138
139 0x38, // End dependent Function
140
141 /* ********************* DEVICE 5 ********************* */
142
143 // We cannot mix 24- and 32-bit memory descriptors, so create a separate logical device
144
145 0x15, // Logical device ID
146 0xC9, 0xF3, // Vendor ID 0xF3C9 'ROS'
147 0xAB, 0xCD, // Product ID 0xABCD
148 0x00,
149
150 0x1C, // Compatible device ID
151 0xAD, 0x34, // Vendor ID 0x34AD 'MEM'
152 0x56, 0x78, // Product ID 0x5678
153
154 0x82, 12, 0x00, // ANSI identifier 'Test 1 Dev 2'
155 'T', 'e', 's', 't', ' ', '1', ' ',
156 'D', 'e', 'v', ' ', '2',
157
158 // (A) Fixed
159 // (B) End
160
161 0x85, 0x11, 0x00, // 32-bit Memory Range
162 0x66, // Non-writeable, read-cacheable, write-through,
163 // supports high address, 8-bit, shadowable, expansion ROM
164 0x00, 0x00, 0x0D, 0x00, // Range minimum 0xD0000
165 0x00, 0x00, 0x0E, 0x00, // Range maximum 0xE0000
166 0x00, 0x01, 0x00, 0x00, // Base alignment 0x100
167 0x00, 0x80, 0x00, 0x00, // Range length 0x8000
168
169 0x86, 0x09, 0x00, // 32-bit Fixed Memory Range
170 0x66, // Non-writeable, read-cacheable, write-through,
171 // supports high address, 8-bit, shadowable, expansion ROM
172 0x00, 0x80, 0x0C, 0x00, // Range base address 0xC8000
173 0x00, 0x80, 0x00, 0x00, // Length 0x008000
174
175 /* ********************* DEVICE 6 ********************* */
176
177 0x15, // Logical device ID
178 0xC9, 0xF3, // Vendor ID 0xF3C9 'ROS'
179 0xA0, 0x01, // Product ID 0xA001
180 0x00,
181
182 // NOTE: We don't supply any ANSI identifiers here
183
184 0x81, 0x09, 0x00, // Memory Range
185 0x6E, // Non-writeable, read-cacheable, write-through,
186 // supports high address, 16-bit, shadowable, expansion ROM
187 0x00, 0x0A, // Range minimum 0xA0000
188 0x40, 0x0A, // Range maximum 0xA4000
189 0x04, 0x00, // Base alignment 4
190 0x10, 0x00, // Range length 0x1000
191
192 0x81, 0x09, 0x00, // Memory Range
193 0x66, // Non-writeable, read-cacheable, write-through,
194 // supports high address, 8-bit, shadowable, expansion ROM
195 0x00, 0x08, // Range minimum 0x8000
196 0x00, 0x09, // Range maximum 0x9000
197 0x04, 0x00, // Base alignment 4
198 0x01, 0x00, // Range length 0x100
199
200 0x2A, 0x40, 0x04, // DMA 6
201
202 0x22, 0x20, 0x00, // IRQ 5 positive edge triggered
203
204 0x4B, 0x80, 0x00, 0x08, // Fixed I/O 0x80, length 8
205
206 /* ********************* DEVICE 7 ********************* */
207
208 0x15, // Logical device ID
209 0xB0, 0x15, // Vendor ID 0x15B0 'EMP'
210 0x20, 0x00, // Product ID 0x2000
211 0x00,
212
213 // No resource requirements for this device
214
215 0x73, '1', '2', '3', // Vendor defined valid tag
216
217 /* **************************************************** */
218
219 0x79, // END
220 0xFF, // Checksum (dummy)
221};
222
223/* FUNCTIONS ******************************************************************/
224
225VOID
228{
230
232
233 /* NOTE: Boot resources of the devices should be made from the requirements */
234
235 /* ********************* DEVICE 1 ********************* */
236 LogDev = &Card->LogDev[0];
237
238 /*
239 * Assign some I/O base but don't enable decodes.
240 * The driver will ignore such I/O configuration.
241 */
242 LogDev->Registers[0x60] = 0x03;
243 LogDev->Registers[0x61] = 0x90;
244
245 /* ******************* DEVICE 2, 3, 4 ***************** */
246 LogDev++;
247 LogDev++;
248 LogDev++;
249
250 /* ********************* DEVICE 5 ********************* */
251 LogDev++;
252
253 /* Enable decodes */
254 LogDev->Registers[0x30] = 0x01;
255
256 /* No DMA is active */
257 LogDev->Registers[0x74] = 0x04;
258 LogDev->Registers[0x75] = 0x04;
259
260 /* Memory 32 Base #0 0xD6000 */
261 LogDev->Registers[0x76] = 0x00;
262 LogDev->Registers[0x77] = 0x0D;
263 LogDev->Registers[0x78] = 0x60;
264 LogDev->Registers[0x79] = 0x00;
265 /* Memory 32 Control #0 - enable range length, 8-bit memory */
266 LogDev->Registers[0x7A] = 0x00;
267 /* Memory 32 Range length #0 0xFFFF8000 (32kB) */
268 LogDev->Registers[0x7B] = 0xFF;
269 LogDev->Registers[0x7C] = 0xFF;
270 LogDev->Registers[0x7D] = 0x80;
271 LogDev->Registers[0x7E] = 0x00;
272
273 /* Memory 32 Base #1 0xC8000 */
274 LogDev->Registers[0x80] = 0x00;
275 LogDev->Registers[0x81] = 0x0C;
276 LogDev->Registers[0x82] = 0x80;
277 LogDev->Registers[0x83] = 0x00;
278 /* Memory 32 Control #1 - enable upper limit, 8-bit memory */
279 LogDev->Registers[0x84] = 0x01;
280 /* Memory 32 Limit #1 0xD0000 (0xC8000 + 0x8000 = 0xD0000) */
281 LogDev->Registers[0x85] = 0x00;
282 LogDev->Registers[0x86] = 0x0D;
283 LogDev->Registers[0x87] = 0x00;
284 LogDev->Registers[0x88] = 0x00;
285
286 /* ********************* DEVICE 6 ********************* */
287 LogDev++;
288
289 /* Enable decodes */
290 LogDev->Registers[0x30] = 0x01;
291
292 /* Memory Base #0 0xA0000 */
293 LogDev->Registers[0x40] = 0x0A;
294 LogDev->Registers[0x41] = 0x00;
295 /*
296 * Memory Control #0 - enable upper limit, 8-bit memory.
297 * The resource descriptor is 16-bit,
298 * so we can test the configuration code that touches this register.
299 */
300 LogDev->Registers[0x42] = 0x01;
301 /* Memory Limit #0 0xA4000 (0xA0000 + 0x4000 = 0xA4000) */
302 LogDev->Registers[0x43] = 0x0A;
303 LogDev->Registers[0x44] = 0x40;
304
305 /* Memory Control #1 - enable range length, 8-bit memory */
306 LogDev->Registers[0x4A] = 0x00;
307 /* Memory Base #1 is disabled */
308
309 /* I/O Base 80 */
310 LogDev->Registers[0x60] = 0x00;
311 LogDev->Registers[0x61] = 0x80;
312
313 /* IRQ 5 low-to-high transition */
314 LogDev->Registers[0x70] = 0x05 | 0xF0; // We add some garbage, must be ignored by the driver
315 LogDev->Registers[0x71] = 0x02;
316
317 /* DMA 6 */
318 LogDev->Registers[0x74] = 0x06 | 0xF8; // Ditto
319
320 /* No DMA is active */
321 LogDev->Registers[0x75] = 0x04;
322
323 /* ********************* DEVICE 7 ********************* */
324
325 /* No resources on purpose */
326}
327
328/* No boot resources */
329static
330VOID
333{
335}
336
337/*
338 * Interface 1 Bus 0 Slot 0 AlternativeLists 2
339 *
340 * AltList 0, AltList->Count 8 Ver.1 Rev.30
341 * [0:1:11] IO: Min 0:330, Max 0:341, Align 4 Len 2
342 * [0:1:5] IO: Min 0:600, Max 0:787, Align 1 Len 8
343 * [0:1:5] IO: Min 0:16, Max 0:21, Align 1 Len C
344 * [0:1:1] INT: Min 5 Max 5
345 * [0:1:1] INT: Min 2 Max 2
346 * [8:1:1] INT: Min 3 Max 3
347 * [8:1:1] INT: Min 4 Max 4
348 * [0:0:0] DMA: Min 2 Max 2
349 *
350 * AltList 1, AltList->Count 6 Ver.1 Rev.31
351 * [0:1:11] IO: Min 0:330, Max 0:341, Align 4 Len 2
352 * [0:1:10] MEM: Min 0:C8000, Max 0:DFFFF, Align FF40 Len 4000
353 * [0:1:10] MEM: Min 0:D4000, Max 0:DBFFF, Align 10000 Len 4000
354 * [0:0:0] DMA: Min 0 Max 0
355 * [8:0:0] DMA: Min 1 Max 1
356 * [0:0:0] DMA: Min 2 Max 2
357 */
358static
359VOID
362{
364 PIO_RESOURCE_LIST AltList;
365
366 ok(ReqList != NULL, "ReqList is NULL\n");
367 if (ReqList == NULL)
368 {
369 skip("No ReqList\n");
370 return;
371 }
373
374 /************************* LIST 0 ************************/
375
376 AltList = &ReqList->List[0];
377 Descriptor = &AltList->Descriptors[0];
378
379 expect_alt_list_header(AltList, 8UL);
380
382 0,
385 2ul,
386 4ul,
387 0x330ull,
388 0x341ull);
389 Descriptor++;
390
392 0,
395 8ul,
396 1ul,
397 0x600ull,
398 0x787ull);
399 Descriptor++;
400
402 0,
405 12ul,
406 1ul,
407 0x16ull,
408 0x21ull);
409 Descriptor++;
410
412 0,
415 5ul,
416 5ul);
417 Descriptor++;
418
419 // NOTE: The native driver returns CM_RESOURCE_INTERRUPT_LATCHED
420 // and CmResourceShareDeviceExclusive for some reason
421#if 0
423 0,
426 2ul,
427 2ul);
428#else
430 0,
433 2ul,
434 2ul);
435#endif
436 Descriptor++;
437
438#if 0
443 3ul,
444 3ul);
445#else
450 3ul,
451 3ul);
452#endif
453 Descriptor++;
454
455#if 0
460 4ul,
461 4ul);
462#else
467 4ul,
468 4ul);
469#endif
470 Descriptor++;
471
473 0,
476 2ul,
477 2ul);
478 Descriptor++;
479
480 /************************* LIST 1 ************************/
481
482 AltList = (PIO_RESOURCE_LIST)(AltList->Descriptors + AltList->Count);
483 Descriptor = &AltList->Descriptors[0];
484
485 expect_alt_list_header(AltList, 6UL);
486
488 0,
491 2ul,
492 4ul,
493 0x330ull,
494 0x341ull);
495 Descriptor++;
496
498 0,
501 0x4000ul,
502 0xFF40ul,
503 0xC8000ull,
504 0xDFFFFull);
505 Descriptor++;
506
507 // NOTE: The native driver returns CM_RESOURCE_MEMORY_24 only for some reason
508#if 0
510 0,
513 0x4000ul,
514 0x10000ul,
515 0xD4000ull,
516 0xDBFFFull);
517#else
519 0,
522 0x4000ul,
523 0x10000ul,
524 0xD4000ull,
525 0xDBFFFull);
526#endif
527 Descriptor++;
528
530 0,
533 0ul,
534 0ul);
535 Descriptor++;
536
541 1ul,
542 1ul);
543 Descriptor++;
544
546 0,
549 2ul,
550 2ul);
551 Descriptor++;
552
553 /*********************************************************/
554
555 ok_int(ReqList->ListSize, GetPoolAllocSize(ReqList));
556 ok_int(ReqList->ListSize, (ULONG_PTR)Descriptor - (ULONG_PTR)ReqList);
557}
558
559VOID
563{
566}
567
568/* No boot resources */
569static
570VOID
573{
575}
576
577/*
578 * Interface 1 Bus 0 Slot 0 AlternativeLists 2
579 *
580 * AltList 0, AltList->Count 2 Ver.1 Rev.30
581 * [0:1:11] IO: Min 0:500, Max 0:506, Align 1 Len 1
582 * [0:1:11] IO: Min 0:600, Max 0:607, Align 1 Len 1
583 *
584 * AltList 1, AltList->Count 2 Ver.1 Rev.31
585 * [0:1:11] IO: Min 0:500, Max 0:506, Align 1 Len 1
586 * [0:1:11] IO: Min 0:700, Max 0:708, Align 1 Len 1
587 */
588static
589VOID
592{
594 PIO_RESOURCE_LIST AltList;
595
596 ok(ReqList != NULL, "ReqList is NULL\n");
597 if (ReqList == NULL)
598 {
599 skip("No ReqList\n");
600 return;
601 }
603
604 /************************* LIST 0 ************************/
605
606 AltList = &ReqList->List[0];
607 Descriptor = &AltList->Descriptors[0];
608
609 expect_alt_list_header(AltList, 2UL);
610
612 0,
615 1ul,
616 1ul,
617 0x500ull,
618 0x506ull);
619 Descriptor++;
620
622 0,
625 1ul,
626 1ul,
627 0x600ull,
628 0x607ull);
629 Descriptor++;
630
631 /************************* LIST 1 ************************/
632
633 AltList = (PIO_RESOURCE_LIST)(AltList->Descriptors + AltList->Count);
634 Descriptor = &AltList->Descriptors[0];
635
636 expect_alt_list_header(AltList, 2UL);
637
639 0,
642 1ul,
643 1ul,
644 0x500ull,
645 0x506ull);
646 Descriptor++;
647
649 0,
652 1ul,
653 1ul,
654 0x700ull,
655 0x708ull);
656 Descriptor++;
657}
658
659VOID
663{
666}
667
668/* No boot resources */
669static
670VOID
673{
675}
676
677/*
678 * Interface 1 Bus 0 Slot 0 AlternativeLists 2
679 *
680 * AltList 0, AltList->Count 2 Ver.1 Rev.30
681 * [0:1:11] IO: Min 0:600, Max 0:607, Align 1 Len 1
682 * [0:1:11] IO: Min 0:500, Max 0:506, Align 1 Len 1
683 *
684 * AltList 1, AltList->Count 2 Ver.1 Rev.31
685 * [0:1:11] IO: Min 0:700, Max 0:708, Align 1 Len 1
686 * [0:1:11] IO: Min 0:500, Max 0:506, Align 1 Len 1
687 */
688static
689VOID
692{
694 PIO_RESOURCE_LIST AltList;
695
696 ok(ReqList != NULL, "ReqList is NULL\n");
697 if (ReqList == NULL)
698 {
699 skip("No ReqList\n");
700 return;
701 }
703
704 /************************* LIST 0 ************************/
705
706 AltList = &ReqList->List[0];
707 Descriptor = &AltList->Descriptors[0];
708
709 expect_alt_list_header(AltList, 2UL);
710
712 0,
715 1ul,
716 1ul,
717 0x600ull,
718 0x607ull);
719 Descriptor++;
720
722 0,
725 1ul,
726 1ul,
727 0x500ull,
728 0x506ull);
729 Descriptor++;
730
731 /************************* LIST 1 ************************/
732
733 AltList = (PIO_RESOURCE_LIST)(AltList->Descriptors + AltList->Count);
734 Descriptor = &AltList->Descriptors[0];
735
736 expect_alt_list_header(AltList, 2UL);
737
739 0,
742 1ul,
743 1ul,
744 0x700ull,
745 0x708ull);
746 Descriptor++;
747
749 0,
752 1ul,
753 1ul,
754 0x500ull,
755 0x506ull);
756 Descriptor++;
757}
758
759VOID
763{
766}
767
768/* No boot resources */
769static
770VOID
773{
775}
776
777/*
778 * Interface 1 Bus 0 Slot 0 AlternativeLists 2
779 *
780 * AltList 0, AltList->Count 1 Ver.1 Rev.30
781 * [0:1:11] IO: Min 0:600, Max 0:607, Align 1 Len 1
782 *
783 * AltList 1, AltList->Count 1 Ver.1 Rev.31
784 * [0:1:11] IO: Min 0:700, Max 0:708, Align 1 Len 1
785 */
786static
787VOID
790{
792 PIO_RESOURCE_LIST AltList;
793
794 ok(ReqList != NULL, "ReqList is NULL\n");
795 if (ReqList == NULL)
796 {
797 skip("No ReqList\n");
798 return;
799 }
801
802 /************************* LIST 0 ************************/
803
804 AltList = &ReqList->List[0];
805 Descriptor = &AltList->Descriptors[0];
806
807 expect_alt_list_header(AltList, 1UL);
808
810 0,
813 1ul,
814 1ul,
815 0x600ull,
816 0x607ull);
817 Descriptor++;
818
819 /************************* LIST 1 ************************/
820
821 AltList = (PIO_RESOURCE_LIST)(AltList->Descriptors + AltList->Count);
822 Descriptor = &AltList->Descriptors[0];
823
824 expect_alt_list_header(AltList, 1UL);
825
827 0,
830 1ul,
831 1ul,
832 0x700ull,
833 0x708ull);
834 Descriptor++;
835}
836
837VOID
841{
844}
845
846/*
847 * FullList Count 1
848 * List #0 Iface 1 Bus #0 Ver.0 Rev.3000 Count 2
849 * [1:11] MEM: 0:D6000 Len 8000
850 * [1:11] MEM: 0:C8000 Len 8000
851 */
852static
853VOID
856{
858
859 ok(ResourceList != NULL, "ResourceList is NULL\n");
860 if (ResourceList == NULL)
861 {
862 skip("No ResourceList\n");
863 return;
864 }
866
867 Descriptor = &ResourceList->List[0].PartialResourceList.PartialDescriptors[0];
868
872 0x8000ul,
873 0xD6000ull);
874 Descriptor++;
875
879 0x8000ul,
880 0xC8000ull);
881 Descriptor++;
882
883 /*********************************************************/
884
886}
887
888/*
889 * Interface 1 Bus 0 Slot 0 AlternativeLists 1
890 *
891 * AltList 0, AltList->Count 3 Ver.1 Rev.30
892 * [1:3:0] CFG: Priority 2000 Res1 720075 Res2 650072
893 * [1:1:11] MEM: Min 0:D6000, Max 0:DDFFF, Align 1 Len 8000
894 * [1:1:11] MEM: Min 0:C8000, Max 0:CFFFF, Align 1 Len 8000
895 *
896 * OR (decodes disabled)
897 *
898 * AltList 0, AltList->Count 2 Ver.1 Rev.30
899 * [0:1:10] MEM: Min 0:D0000, Max 0:E7FFF, Align 100 Len 8000
900 * [0:1:10] MEM: Min 0:C8000, Max 0:CFFFF, Align 1 Len 8000
901 */
902static
903VOID
906{
908 PIO_RESOURCE_LIST AltList;
909 ULONG Count;
910
911 ok(ReqList != NULL, "ReqList is NULL\n");
912 if (ReqList == NULL)
913 {
914 skip("No ReqList\n");
915 return;
916 }
918
919 /************************* LIST 0 ************************/
920
921 AltList = &ReqList->List[0];
922 Descriptor = &AltList->Descriptors[0];
923
925 Count = 3;
926 else
927 Count = 2;
929
930 /* TODO: Should we support this? */
932 {
935 0,
937 0x2000ul,
938 0ul,
939 0ul);
940 Descriptor++;
941 }
942
944 0,
947 0x8000ul,
948 0x100ul,
949 0xD0000ull,
950 0xE7FFFull);
951 Descriptor++;
952
954 0,
957 0x8000ul,
958 0x1ul,
959 0xC8000ull,
960 0xCFFFFull);
961 Descriptor++;
962
963 /*********************************************************/
964
965 ok_int(ReqList->ListSize, GetPoolAllocSize(ReqList));
966 ok_int(ReqList->ListSize, (ULONG_PTR)Descriptor - (ULONG_PTR)ReqList);
967}
968
969VOID
973{
976}
977
978/*
979 * FullList Count 1
980 * List #0 Iface 1 Bus #0 Ver.0 Rev.3000 Count 4
981 * [1:11] MEM: 0:A0000 Len 4000
982 * [1:5] IO: Start 0:80, Len 8
983 * [1:0] DMA: Channel 6 Port 0 Res 0
984 * [1:1] INT: Lev 5 Vec 5 Aff FFFFFFFF
985 */
986static
987VOID
990{
992
993 ok(ResourceList != NULL, "ResourceList is NULL\n");
994 if (ResourceList == NULL)
995 {
996 skip("No ResourceList\n");
997 return;
998 }
1000
1001 Descriptor = &ResourceList->List[0].PartialResourceList.PartialDescriptors[0];
1002
1006 8ul,
1007 0x80ull);
1008 Descriptor++;
1009
1013 5ul,
1014 5ul,
1015 (KAFFINITY)-1);
1016 Descriptor++;
1017
1019 0,
1021 6ul);
1022 Descriptor++;
1023
1027 0x4000ul,
1028 0xA0000ull);
1029 Descriptor++;
1030
1031 /*********************************************************/
1032
1034}
1035
1036/*
1037 * Interface 1 Bus 0 Slot 0 AlternativeLists 1
1038 *
1039 * AltList 0, AltList->Count 6 Ver.1 Rev.30
1040 * [1:3:0] CFG: Priority 2000 Res1 7 Res2 0
1041 * [1:1:11] MEM: Min 0:A0000, Max 0:A3FFF, Align 1 Len 4000
1042 * [0:1:10] MEM: Min 0:80000, Max 0:900FF, Align 4 Len 100
1043 * [1:0:0] DMA: Min 6 Max 6
1044 * [1:1:1] INT: Min 5 Max 5
1045 * [1:1:5] IO: Min 0:80, Max 0:87, Align 1 Len 8
1046 *
1047 * OR (decodes disabled)
1048 *
1049 * AltList 0, AltList->Count 5 Ver.1 Rev.30
1050 * [0:1:10] MEM: Min 0:A0000, Max 0:A4FFF, Align 4 Len 1000
1051 * [0:1:10] MEM: Min 0:80000, Max 0:900FF, Align 4 Len 100
1052 * [0:0:0] DMA: Min 6 Max 6
1053 * [0:1:1] INT: Min 5 Max 5
1054 * [0:1:5] IO: Min 0:80, Max 0:87, Align 1 Len 8
1055 */
1056static
1057VOID
1060{
1062 PIO_RESOURCE_LIST AltList;
1063 ULONG Count;
1064
1065 ok(ReqList != NULL, "ReqList is NULL\n");
1066 if (ReqList == NULL)
1067 {
1068 skip("No ReqList\n");
1069 return;
1070 }
1071 expect_requirements_list_header(ReqList, Isa, 1UL);
1072
1073 /************************* LIST 0 ************************/
1074
1075 AltList = &ReqList->List[0];
1076 Descriptor = &AltList->Descriptors[0];
1077
1079 Count = 6;
1080 else
1081 Count = 5;
1082 expect_alt_list_header(AltList, Count);
1083
1084 /* TODO: Should we support this? */
1086 {
1089 0,
1091 0x2000ul,
1092 0ul,
1093 0ul);
1094 Descriptor++;
1095 }
1096
1098 0,
1101 0x1000ul,
1102 0x4ul,
1103 0xA0000ull,
1104 0xA4FFFull);
1105 Descriptor++;
1106
1107 // NOTE: The native driver returns CM_RESOURCE_MEMORY_24 only for some reason
1108#if 0
1110 0,
1113 0x100ul,
1114 0x4ul,
1115 0x80000ull,
1116 0x900FFull);
1117#else
1119 0,
1122 0x100ul,
1123 0x4ul,
1124 0x80000ull,
1125 0x900FFull);
1126#endif
1127 Descriptor++;
1128
1130 0,
1133 6ul,
1134 6ul);
1135 Descriptor++;
1136
1138 0,
1141 5ul,
1142 5ul);
1143 Descriptor++;
1144
1146 0,
1149 8ul,
1150 1ul,
1151 0x80ull,
1152 0x87ull);
1153 Descriptor++;
1154
1155 /*********************************************************/
1156
1157 ok_int(ReqList->ListSize, GetPoolAllocSize(ReqList));
1158 ok_int(ReqList->ListSize, (ULONG_PTR)Descriptor - (ULONG_PTR)ReqList);
1159}
1160
1161VOID
1165{
1168}
1169
1170VOID
1173{
1174 ULONG i, Offset;
1175
1176 /* Memory Base #0 = 0xA2000 */
1177 ok_eq_int(LogDev->Registers[0x40], 0x0A);
1178 ok_eq_int(LogDev->Registers[0x41], 0x20);
1179 /* Memory Control #0 = upper limit enabled, 16-bit memory */
1180 ok_eq_int(LogDev->Registers[0x42], 0x03);
1181 /* Memory Upper limit #0 = 0xA3000 (0xA2000 + 0x1000) */
1182 ok_eq_int(LogDev->Registers[0x43], 0x0A);
1183 ok_eq_int(LogDev->Registers[0x44], 0x30);
1184
1185 /* Memory Base #1 = 0x89000 */
1186 ok_eq_int(LogDev->Registers[0x48], 0x08);
1187 ok_eq_int(LogDev->Registers[0x49], 0x90);
1188 /* Memory Control #1 = range length enabled, 8-bit memory */
1189 ok_eq_int(LogDev->Registers[0x4A], 0x00);
1190 /* Memory Upper limit #1 = 0xFFFF00 (0x100) */
1191 ok_eq_int(LogDev->Registers[0x4B], 0xFF);
1192 ok_eq_int(LogDev->Registers[0x4C], 0xFF);
1193
1194 /* Memory #2-3 should be disabled */
1195 for (i = 2; i < 4; ++i)
1196 {
1197 Offset = 0x40 + i * 8;
1198
1199 /* Memory Base */
1200 ok_eq_int(LogDev->Registers[Offset ], 0x00);
1201 ok_eq_int(LogDev->Registers[Offset + 1], 0x00);
1202 /* Memory Control */
1203 ok_eq_int(LogDev->Registers[Offset + 2], 0x00);
1204 /* Memory Upper limit or range length */
1205 ok_eq_int(LogDev->Registers[Offset + 3], 0x00);
1206 ok_eq_int(LogDev->Registers[Offset + 4], 0x00);
1207 }
1208
1209 /* Memory 32 #0-3 should be disabled */
1210 for (i = 0; i < 4; ++i)
1211 {
1212 if (i == 0)
1213 Offset = 0x76;
1214 else
1215 Offset = 0x70 + i * 16;
1216
1217 /* Memory 32 Base */
1218 ok_eq_int(LogDev->Registers[Offset ], 0x00);
1219 ok_eq_int(LogDev->Registers[Offset + 1], 0x00);
1220 ok_eq_int(LogDev->Registers[Offset + 2], 0x00);
1221 ok_eq_int(LogDev->Registers[Offset + 3], 0x00);
1222 /* Memory 32 Control */
1223 ok_eq_int(LogDev->Registers[Offset + 4], 0x00);
1224 /* Memory 32 Upper limit or range length */
1225 ok_eq_int(LogDev->Registers[Offset + 5], 0x00);
1226 ok_eq_int(LogDev->Registers[Offset + 6], 0x00);
1227 ok_eq_int(LogDev->Registers[Offset + 7], 0x00);
1228 ok_eq_int(LogDev->Registers[Offset + 8], 0x00);
1229 }
1230
1231 /* I/O Base #0 = 0x80 */
1232 ok_eq_int(LogDev->Registers[0x60], 0x00);
1233 ok_eq_int(LogDev->Registers[0x61], 0x80);
1234
1235 /* I/O Base #1-6 should be disabled */
1236 for (i = 1; i < 6; ++i)
1237 {
1238 Offset = 0x60 + i * 2;
1239
1240 ok_eq_int(LogDev->Registers[Offset ], 0x00);
1241 ok_eq_int(LogDev->Registers[Offset + 1], 0x00);
1242 }
1243
1244 /* IRQ select #0 = IRQ 5 low-to-high transition */
1245 ok_eq_int(LogDev->Registers[0x70], 0x05);
1246 ok_eq_int(LogDev->Registers[0x71], 0x02);
1247
1248 /* IRQ select #1 should be disabled */
1249 ok_eq_int(LogDev->Registers[0x72], 0x00);
1250 ok_eq_int(LogDev->Registers[0x73], 0x00);
1251
1252 /* DMA select #0 = DMA 6 */
1253 ok_eq_int(LogDev->Registers[0x74], 0x06);
1254
1255 /* DMA select #1 = No DMA is active */
1256 ok_eq_int(LogDev->Registers[0x75], 0x04);
1257}
1258
1261{
1264 ULONG ListSize;
1265
1266#define RESOURCE_COUNT 5
1267 /*
1268 * Make the following resources from the requirements:
1269 *
1270 * FullList Count 1
1271 * List #0 Iface 1 Bus #0 Ver.1 Rev.1 Count 5
1272 * [1:11] MEM: 0:A2000 Len 1000
1273 * [1:11] MEM: 0:89000 Len 100
1274 * [0:0] DMA: Channel 6 Port 0 Res 0
1275 * [1:1] INT: Lev 5 Vec 3F Aff FFFFFFFF
1276 * [1:5] IO: Start 0:80, Len 8
1277 */
1278 ListSize = FIELD_OFFSET(CM_RESOURCE_LIST, List[0].PartialResourceList.PartialDescriptors) +
1279 sizeof(*Descriptor) * RESOURCE_COUNT;
1280
1282 if (ResourceList == NULL)
1283 return NULL;
1284 ResourceList->Count = 1;
1285 ResourceList->List[0].InterfaceType = Isa;
1286 ResourceList->List[0].BusNumber = 0;
1287 ResourceList->List[0].PartialResourceList.Version = 1;
1288 ResourceList->List[0].PartialResourceList.Revision = 1;
1289 ResourceList->List[0].PartialResourceList.Count = RESOURCE_COUNT;
1290
1291 Descriptor = &ResourceList->List[0].PartialResourceList.PartialDescriptors[0];
1292
1294 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
1296 Descriptor->u.Memory.Start.LowPart = 0xA2000;
1297 Descriptor->u.Memory.Length = 0x1000;
1298 ++Descriptor;
1299
1301 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
1303 Descriptor->u.Memory.Start.LowPart = 0x89000;
1304 Descriptor->u.Memory.Length = 0x100;
1305 ++Descriptor;
1306
1308 Descriptor->ShareDisposition = CmResourceShareUndetermined;
1310 Descriptor->u.Dma.Channel = 6;
1311 ++Descriptor;
1312
1314 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
1316 Descriptor->u.Interrupt.Level = 5;
1317 Descriptor->u.Interrupt.Vector = 0x3F;
1318 Descriptor->u.Interrupt.Affinity = (KAFFINITY)-1;
1319 ++Descriptor;
1320
1322 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
1324 Descriptor->u.Memory.Start.LowPart = 0x80;
1325 Descriptor->u.Memory.Length = 8;
1326
1327 return ResourceList;
1328}
1329
1330VOID
1334{
1335 /* No resources */
1337 ok_eq_pointer(ReqList, NULL);
1338}
static SIZE_T GetPoolAllocSize(PVOID MemPtr)
#define ok_eq_pointer(value, expected)
Definition: apitest.h:59
#define ok_eq_size(value, expected)
Definition: apitest.h:69
#define ok_eq_int(value, expected)
Definition: apitest.h:60
#define ok(value,...)
Definition: atltest.h:57
#define skip(...)
Definition: atltest.h:64
#define ok_int(expression, result)
Definition: atltest.h:134
Definition: card.h:28
#define NULL
Definition: types.h:112
#define GetProcessHeap()
Definition: compat.h:736
ULONG_PTR KAFFINITY
Definition: compat.h:85
#define HeapAlloc
Definition: compat.h:733
#define HEAP_ZERO_MEMORY
Definition: compat.h:134
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
#define CmResourceTypeConfigData
Definition: hwresource.cpp:130
#define CmResourceTypeMemory
Definition: hwresource.cpp:125
#define CmResourceTypeDma
Definition: hwresource.cpp:126
@ Isa
Definition: hwresource.cpp:138
#define CmResourceTypePort
Definition: hwresource.cpp:123
#define CmResourceTypeInterrupt
Definition: hwresource.cpp:124
VOID IsaBusCreateCard(_Inout_ PISAPNP_CARD Card, _In_ PVOID PnpRom, _In_ ULONG RomSize, _In_ ULONG LogicalDevices)
Definition: isabus.c:439
#define expect_alt_list_header(AltList, ExpectedCount)
Definition: precomp.h:218
#define expect_requirements_list_header(ReqList, ExpectedIface, ExpectedCount)
Definition: precomp.h:210
#define expect_dma_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, ExpectedMin, ExpectedMax)
Definition: precomp.h:271
#define expect_resource_list_header(ResourceList, ExpectedIface, ExpectedCount)
Definition: precomp.h:201
#define expect_port_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedAlign, ExpectedMin, ExpectedMax)
Definition: precomp.h:225
#define expect_irq_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, ExpectedMin, ExpectedMax)
Definition: precomp.h:251
#define expect_irq_res(Desc, ExpectedFlags, ExpectedShare, ExpectedLevel, ExpectedVector, ExpectedAffinity)
Definition: precomp.h:357
#define expect_mem_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedAlign, ExpectedMin, ExpectedMax)
Definition: precomp.h:291
#define expect_mem_res(Desc, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedStart)
Definition: precomp.h:394
#define expect_cfg_req(Desc, ExpectedOption, ExpectedFlags, ExpectedShare, ExpectedPriority, ExpectedRes1, ExpectedRes2)
Definition: precomp.h:317
#define expect_port_res(Desc, ExpectedFlags, ExpectedShare, ExpectedLength, ExpectedStart)
Definition: precomp.h:340
#define expect_dma_res(Desc, ExpectedFlags, ExpectedShare, ExpectedChannel)
Definition: precomp.h:375
#define CM_RESOURCE_PORT_IO
Definition: cmtypes.h:109
#define CM_RESOURCE_DMA_8
Definition: cmtypes.h:131
#define CM_RESOURCE_MEMORY_READ_ONLY
Definition: cmtypes.h:121
#define CM_RESOURCE_PORT_16_BIT_DECODE
Definition: cmtypes.h:112
#define CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
Definition: cmtypes.h:143
#define CM_RESOURCE_MEMORY_24
Definition: cmtypes.h:125
#define CM_RESOURCE_INTERRUPT_LATCHED
Definition: cmtypes.h:144
#define CM_RESOURCE_PORT_10_BIT_DECODE
Definition: cmtypes.h:110
#define _In_
Definition: no_sal2.h:158
int Count
Definition: noreturn.cpp:7
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
VOID DrvTestCard1Dev2Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:660
static VOID DrvTestCard1Dev1QueryResourceRequirements(_In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:360
static VOID DrvTestCard1Dev1QueryResources(_In_ PCM_RESOURCE_LIST ResourceList)
Definition: res_card.c:331
PCM_RESOURCE_LIST DrvTestCard1Dev6CreateConfigurationResources(VOID)
Definition: res_card.c:1260
VOID DrvCreateCard1(_In_ PISAPNP_CARD Card)
Definition: res_card.c:226
static VOID DrvTestCard1Dev2QueryResources(_In_ PCM_RESOURCE_LIST ResourceList)
Definition: res_card.c:571
VOID DrvTestCard1Dev6Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:1162
static VOID DrvTestCard1Dev2QueryResourceRequirements(_In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:590
VOID DrvTestCard1Dev7Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:1331
static VOID DrvTestCard1Dev6QueryResources(_In_ PCM_RESOURCE_LIST ResourceList)
Definition: res_card.c:988
VOID DrvTestCard1Dev5Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:970
VOID DrvTestCard1Dev6ConfigurationResult(_In_ PISAPNP_CARD_LOGICAL_DEVICE LogDev)
Definition: res_card.c:1171
#define RESOURCE_COUNT
static VOID DrvTestCard1Dev5QueryResourceRequirements(_In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:904
static VOID DrvTestCard1Dev3QueryResources(_In_ PCM_RESOURCE_LIST ResourceList)
Definition: res_card.c:671
static UCHAR DrvpTestPnpRom[]
Definition: res_card.c:14
static VOID DrvTestCard1Dev4QueryResources(_In_ PCM_RESOURCE_LIST ResourceList)
Definition: res_card.c:771
VOID DrvTestCard1Dev1Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:560
VOID DrvTestCard1Dev3Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:760
static VOID DrvTestCard1Dev4QueryResourceRequirements(_In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:788
static VOID DrvTestCard1Dev6QueryResourceRequirements(_In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:1058
static VOID DrvTestCard1Dev5QueryResources(_In_ PCM_RESOURCE_LIST ResourceList)
Definition: res_card.c:854
VOID DrvTestCard1Dev4Resources(_In_ PCM_RESOURCE_LIST ResourceList, _In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:838
static VOID DrvTestCard1Dev3QueryResourceRequirements(_In_ PIO_RESOURCE_REQUIREMENTS_LIST ReqList)
Definition: res_card.c:690
IO_RESOURCE_DESCRIPTOR Descriptors[1]
Definition: iotypes.h:2737
#define FIELD_OFFSET(t, f)
Definition: typedefs.h:255
uint32_t ULONG_PTR
Definition: typedefs.h:65
uint32_t ULONG
Definition: typedefs.h:59
_Must_inspect_result_ _In_ WDFIORESREQLIST _In_opt_ PWDF_OBJECT_ATTRIBUTES _Out_ WDFIORESLIST * ResourceList
Definition: wdfresource.h:309
_Must_inspect_result_ _In_ WDFIORESLIST _In_ PIO_RESOURCE_DESCRIPTOR Descriptor
Definition: wdfresource.h:342
_Must_inspect_result_ _In_ WDFCMRESLIST List
Definition: wdfresource.h:550
@ CmResourceShareDeviceExclusive
Definition: cmtypes.h:241
@ CmResourceShareShared
Definition: cmtypes.h:243
@ CmResourceShareUndetermined
Definition: cmtypes.h:240
struct _IO_RESOURCE_LIST * PIO_RESOURCE_LIST
#define IO_RESOURCE_ALTERNATIVE
#define IO_RESOURCE_PREFERRED
unsigned char UCHAR
Definition: xmlstorage.h:181