#include <ntddk.h>#include <ntstrsafe.h>#include <ntintsafe.h>#include <initguid.h>#include <wdmguid.h>#include <ata.h>#include <ide.h>#include <scsi.h>#include <reactos/drivers/ata/ata_shared.h>#include <reactos/drivers/ata/ata_user.h>#include "debug.h"#include "ahci.h"#include <debug/driverdbg.h>#include "pata.h"
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Classes | |
| struct | _ATA_PCI_ENABLE_BITS |
| struct | _ATA_CONTROLLER |
| struct | _CHANNEL_DATA_COMMON |
| struct | _CHANNEL_DATA_PATA |
| struct | _CHANNEL_INFO_AHCI |
| struct | _CHANNEL_DATA_AHCI |
| struct | _PCIIDEX_DRIVER_EXTENSION |
| struct | _COMMON_DEVICE_EXTENSION |
| struct | _FDO_DEVICE_EXTENSION |
| struct | _PDO_DEVICE_EXTENSION |
Macro Definition Documentation
◆ ASSUME
| #define ASSUME | ( | cond | ) |
◆ CHANNEL_FLAG_64_BIT_DMA
◆ CHANNEL_FLAG_CBUS
◆ CHANNEL_FLAG_COMMAND_PORT_BASE_MAPPED
◆ CHANNEL_FLAG_CONTROL_PORT_BASE_MAPPED
◆ CHANNEL_FLAG_DMA_BEFORE_CMD
◆ CHANNEL_FLAG_DMA_PORT_BASE_MAPPED
◆ CHANNEL_FLAG_DRIVE0_DMA_CAPABLE
◆ CHANNEL_FLAG_DRIVE1_DMA_CAPABLE
◆ CHANNEL_FLAG_FBS_ENABLED
◆ CHANNEL_FLAG_HAS_ACPI_GTM
◆ CHANNEL_FLAG_HAS_FBS
◆ CHANNEL_FLAG_HAS_NCQ
◆ CHANNEL_FLAG_IO32
◆ CHANNEL_FLAG_IS_EXTERNAL
◆ CHANNEL_FLAG_IS_PMP
◆ CHANNEL_FLAG_MRES_CTRL
◆ CHANNEL_FLAG_MRES_DMA
◆ CHANNEL_FLAG_MRES_TF
◆ CHANNEL_FLAG_NO_ATAPI_DMA
◆ CHANNEL_FLAG_NO_SLAVE
◆ CHANNEL_FLAG_PIO_FOR_LBA48_XFER
◆ CHANNEL_FLAG_PIO_VIA_DMA
◆ CHANNEL_FLAG_PRIMARY_ADDRESS_CLAIMED
◆ CHANNEL_FLAG_SECONDARY_ADDRESS_CLAIMED
◆ CTRL_FLAG_DMA_INTERRUPT
◆ CTRL_FLAG_IS_AHCI
◆ CTRL_FLAG_IS_SIMPLEX
◆ CTRL_FLAG_MANUAL_RES
◆ CTRL_FLAG_NATIVE_PCI
◆ CTRL_FLAG_NON_PNP
◆ CTRL_FLAG_SATA_HBA_ACPI
◆ CTRL_FLAG_USE_TEST_FUNCTION
◆ DEV_NUMBER
| #define DEV_NUMBER | ( | Device | ) | ((Device)->TransportFlags & DEVICE_NUMBER_MASK) |
◆ DO_IS_FDO
◆ IS_FDO
◆ IS_PRIMARY_CHANNEL
| #define IS_PRIMARY_CHANNEL | ( | PdoExtension | ) | (PdoExtension->Channel == 0) |
◆ MAX_CHANNELS
◆ PCIIDEX_PAGED_DATA
◆ PDO_FLAG_NOT_PRESENT
◆ PDO_FLAG_REPORTED_MISSING
◆ PORT_TIMER_TICK_MS
◆ RANGE_IS_MAPPED
◆ RANGE_IS_MEMORY
◆ RANGE_IS_VALID
◆ TAG_PCIIDEX
Typedef Documentation
◆ ATA_CONTROLLER
| typedef struct _ATA_CONTROLLER ATA_CONTROLLER |
◆ ATA_PCI_ENABLE_BITS
◆ CHANNEL_ALLOCATE_MEMORY
◆ CHANNEL_CHECK_INTERRUPT
| typedef BOOLEAN() CHANNEL_CHECK_INTERRUPT(_In_ PCHANNEL_DATA_PATA ChanData) |
◆ CHANNEL_DATA_AHCI
◆ CHANNEL_DATA_COMMON
◆ CHANNEL_DATA_PATA
◆ CHANNEL_ENABLE_INTERRUPTS
◆ CHANNEL_FREE_MEMORY
◆ CHANNEL_INFO_AHCI
◆ CHANNEL_LOAD_TASK_FILE
| typedef VOID() CHANNEL_LOAD_TASK_FILE(_In_ PCHANNEL_DATA_PATA ChanData, _In_ PATA_DEVICE_REQUEST Request) |
◆ CHANNEL_READ_SCR
| typedef BOOLEAN() CHANNEL_READ_SCR(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ PULONG Result) |
◆ CHANNEL_READ_STATUS
| typedef UCHAR() CHANNEL_READ_STATUS(_In_ PCHANNEL_DATA_PATA ChanData) |
◆ CHANNEL_SAVE_TASK_FILE
| typedef VOID() CHANNEL_SAVE_TASK_FILE(_In_ PCHANNEL_DATA_PATA ChanData, _Inout_ PATA_DEVICE_REQUEST Request) |
◆ CHANNEL_WRITE_SCR
| typedef BOOLEAN() CHANNEL_WRITE_SCR(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ ULONG Value) |
◆ COMMON_DEVICE_EXTENSION
◆ CONTROLLER_ATTACH_CHANNEL_EX
◆ CONTROLLER_FREE_RESOURCES
| typedef VOID() CONTROLLER_FREE_RESOURCES(_In_ PATA_CONTROLLER Controller) |
◆ FDO_DEVICE_EXTENSION
◆ PATA_CONTROLLER
| typedef struct _ATA_CONTROLLER * PATA_CONTROLLER |
◆ PATA_PCI_ENABLE_BITS
| typedef struct _ATA_PCI_ENABLE_BITS * PATA_PCI_ENABLE_BITS |
◆ PATA_PCI_MATCH_FN
| typedef ATA_PCI_MATCH_FN* PATA_PCI_MATCH_FN |
◆ PCHANNEL_ALLOCATE_MEMORY
◆ PCHANNEL_CHECK_INTERRUPT
◆ PCHANNEL_DATA_AHCI
| typedef struct _CHANNEL_DATA_AHCI * PCHANNEL_DATA_AHCI |
◆ PCHANNEL_DATA_COMMON
| typedef struct _CHANNEL_DATA_COMMON * PCHANNEL_DATA_COMMON |
◆ PCHANNEL_DATA_PATA
| typedef struct _CHANNEL_DATA_PATA * PCHANNEL_DATA_PATA |
◆ PCHANNEL_ENABLE_INTERRUPTS
◆ PCHANNEL_FREE_MEMORY
| typedef CHANNEL_FREE_MEMORY* PCHANNEL_FREE_MEMORY |
◆ PCHANNEL_INFO_AHCI
| typedef struct _CHANNEL_INFO_AHCI * PCHANNEL_INFO_AHCI |
◆ PCHANNEL_LOAD_TASK_FILE
◆ PCHANNEL_READ_SCR
| typedef CHANNEL_READ_SCR* PCHANNEL_READ_SCR |
◆ PCHANNEL_READ_STATUS
| typedef CHANNEL_READ_STATUS* PCHANNEL_READ_STATUS |
◆ PCHANNEL_SAVE_TASK_FILE
◆ PCHANNEL_SET_MODE_EX
| typedef CHANNEL_SET_MODE_EX* PCHANNEL_SET_MODE_EX |
◆ PCHANNEL_WRITE_SCR
| typedef CHANNEL_WRITE_SCR* PCHANNEL_WRITE_SCR |
◆ PCIIDE_PRD_TABLE_ENTRY
◆ PCIIDEX_DRIVER_EXTENSION
◆ PCOMMON_DEVICE_EXTENSION
◆ PCONTROLLER_ATTACH_CHANNEL_EX
◆ PCONTROLLER_CHANNEL_ENABLED
| typedef CONTROLLER_CHANNEL_ENABLED* PCONTROLLER_CHANNEL_ENABLED |
◆ PCONTROLLER_FREE_RESOURCES
◆ PCONTROLLER_START
| typedef CONTROLLER_START* PCONTROLLER_START |
◆ PCONTROLLER_STOP
| typedef CONTROLLER_STOP* PCONTROLLER_STOP |
◆ PDO_DEVICE_EXTENSION
◆ PFDO_DEVICE_EXTENSION
| typedef struct _FDO_DEVICE_EXTENSION * PFDO_DEVICE_EXTENSION |
◆ PPCIIDE_PRD_TABLE_ENTRY
◆ PPCIIDEX_DRIVER_EXTENSION
◆ PPDO_DEVICE_EXTENSION
| typedef struct _PDO_DEVICE_EXTENSION * PPDO_DEVICE_EXTENSION |
Function Documentation
◆ _Dispatch_type_() [1/3]
| _Dispatch_type_ | ( | IRP_MJ_PNP | ) |
Definition at line 1331 of file isapnp.c.
1341{
1344
1345 PAGED_CODE();
1346
1349 else
1351}
static PIO_STACK_LOCATION IoGetCurrentIrpStackLocation(PIRP Irp)
Definition: Bus_PDO_EvalMethod.c:152
NTSTATUS IsaFdoPnp(_In_ PISAPNP_FDO_EXTENSION FdoExt, _Inout_ PIRP Irp, _In_ PIO_STACK_LOCATION IrpSp)
Definition: fdo.c:123
NTSTATUS IsaPdoPnp(_In_ PISAPNP_PDO_EXTENSION PdoDeviceExtension, _Inout_ PIRP Irp, _In_ PIO_STACK_LOCATION IrpSp)
Definition: pdo.c:867
Definition: Bus_PDO_EvalMethod.c:95
Definition: isapnp.h:42
Definition: isapnp.h:49
Definition: isapnp.h:70
◆ _Dispatch_type_() [2/3]
| _Dispatch_type_ | ( | IRP_MJ_POWER | ) |
◆ _Dispatch_type_() [3/3]
| _Dispatch_type_ | ( | IRP_MJ_SYSTEM_CONTROL | ) |
Definition at line 5748 of file btrfs.c.
5750 {
5753 bool top_level;
5754
5755 FsRtlEnterFileSystem();
5756
5758
5759 Irp->IoStatus.Information = 0;
5760
5763
5765
5767
5771
5773
5777
5779
5781
5783 }
5784
5787
5788exit:
5789 if (top_level)
5791
5792 FsRtlExitFileSystem();
5793
5795}
#define FsRtlEnterFileSystem
#define FsRtlExitFileSystem
Definition: btrfs_drv.h:758
Definition: btrfs_drv.h:872
Definition: btrfs_drv.h:846
◆ _In_reads_()
| _In_ ULONG _In_reads_ | ( | MAX_IDE_DEVICE | ) |
◆ _IRQL_requires_()
| _IRQL_requires_ | ( | DISPATCH_LEVEL | ) |
◆ _IRQL_requires_max_() [1/2]
| _IRQL_requires_max_ | ( | APC_LEVEL | ) |
Definition at line 37 of file cddata.c.
254{
255 THREAD_CONTEXT ThreadContext = {0};
258
259#ifdef CD_SANITY
260 PVOID PreviousTopLevel;
261#endif
262
264
265#if DBG
266
268
269#endif
270
272
274
275 FsRtlEnterFileSystem();
276
277#ifdef CD_SANITY
278 PreviousTopLevel = IoGetTopLevelIrp();
279#endif
280
281 //
282 // Loop until this request has been completed or posted.
283 //
284
285 do {
286
287 //
288 // Use a try-except to handle the exception cases.
289 //
290
291 _SEH2_TRY {
292
293 //
294 // If the IrpContext is NULL then this is the first pass through
295 // this loop.
296 //
297
299
300 //
301 // Decide if this request is waitable an allocate the IrpContext.
302 // If the file object in the stack location is NULL then this
303 // is a mount which is always waitable. Otherwise we look at
304 // the file object flags.
305 //
306
308
310
311 } else {
312
314 }
315
317
318 //
319 // Update the thread context information.
320 //
321
322 CdSetThreadContext( IrpContext, &ThreadContext );
323
324#ifdef CD_SANITY
325 NT_ASSERT( !CdTestTopLevel ||
327#endif
328
329 //
330 // Otherwise cleanup the IrpContext for the retry.
331 //
332
333 } else {
334
335 //
336 // Set the MORE_PROCESSING flag to make sure the IrpContext
337 // isn't inadvertently deleted here. Then cleanup the
338 // IrpContext to perform the retry.
339 //
340
343 }
344
345 //
346 // Case on the major irp code.
347 //
348
349 switch (IrpContext->MajorFunction) {
350
352
354 break;
355
357
359 break;
360
362
363 //
364 // If this is an Mdl complete request, don't go through
365 // common read.
366 //
367
369
371
372 } else {
373
375 }
376
377 break;
378
380
382 break;
383
385
387 break;
388
390
392 break;
393
395
397 break;
398
400
402 break;
403
405
407 break;
408
410
412 break;
413
415
417 break;
418
420
422 break;
423
425
427 break;
428
430
432 break;
433
434 default :
435
438 }
439
441
443 } _SEH2_END;
444
446
447#ifdef CD_SANITY
448 NT_ASSERT( !CdTestTopLevel ||
449 (PreviousTopLevel == IoGetTopLevelIrp()) );
450#endif
451
452 FsRtlExitFileSystem();
453
455
457}
VOID CdCompleteRequest(_Inout_opt_ PIRP_CONTEXT IrpContext, _Inout_opt_ PIRP Irp, _In_ NTSTATUS Status)
Definition: cddata.c:914
LONG CdExceptionFilter(_Inout_ PIRP_CONTEXT IrpContext, _In_ PEXCEPTION_POINTERS ExceptionPointer)
Definition: cddata.c:525
VOID CdSetThreadContext(_Inout_ PIRP_CONTEXT IrpContext, _In_ PTHREAD_CONTEXT ThreadContext)
Definition: cddata.c:981
NTSTATUS CdCompleteMdl(_In_ PIRP_CONTEXT IrpContext, _Inout_ PIRP Irp)
Definition: cachesup.c:411
VOID CdCleanupIrpContext(_In_ PIRP_CONTEXT IrpContext, _In_ BOOLEAN Post)
Definition: strucsup.c:1733
NTSTATUS CdCommonLockControl(_Inout_ PIRP_CONTEXT IrpContext, _Inout_ PIRP Irp)
Definition: lockctrl.c:35
NTSTATUS CdCommonDevControl(_Inout_ PIRP_CONTEXT IrpContext, _Inout_ PIRP Irp)
Definition: devctrl.c:46
_Ret_valid_ PIRP_CONTEXT CdCreateIrpContext(_In_ PIRP Irp, _In_ BOOLEAN Wait)
Definition: strucsup.c:1573
Definition: nsiface.idl:2307
Definition: usbstor.h:98
Definition: cdstruc.h:1363
#define IRP_MJ_FILE_SYSTEM_CONTROL
#define IRP_MJ_SHUTDOWN
#define IRP_MJ_CLEANUP
◆ _IRQL_requires_max_() [2/2]
| _IRQL_requires_max_ | ( | DISPATCH_LEVEL | ) |
Definition at line 3557 of file common.c.
3587{
3590
3593 ULONG timeoutValue = DeviceExtension->TimeOutValue;
3594 ULONG retryCount = 1;
3595
3596 // reset some fields.
3597 DeviceExtension->PowerContext.RetryIntervalIn100ns = 0;
3598 status = PowerContextReuseRequest(DeviceExtension);
3599 RequestClearSendTime(DeviceExtension->PowerContext.PowerRequest);
3600
3602 {
3604 }
3605
3606 // set proper timeout value and max retry count.
3607 switch(DeviceExtension->PowerContext.PowerChangeState.PowerDown)
3608 {
3612 break;
3613
3615 // Case of issuing SYNC CACHE command. Do not use power irp timeout remaining time in this case
3616 // as we want to give best try on SYNC CACHE command.
3617 retryCount = MAXIMUM_RETRIES;
3618 timeoutValue = DeviceExtension->TimeOutValue;
3619 break;
3620
3622 {
3623 // Case of issuing STOP UNIT command
3624 // As "Imme" bit is set to '1', this command should be completed in short time.
3625 // This command is at low importance, failure of this command has very small impact.
3626 ULONG secondsRemaining = 0;
3627
3628#if (WINVER >= 0x0601)
3629 // this API is introduced in Windows7
3630 PoQueryWatchdogTime(DeviceExtension->LowerPdo, &secondsRemaining);
3631#endif
3632
3633 if (secondsRemaining == 0)
3634 {
3635 // not able to retrieve remaining time from PoQueryWatchdogTime API, use default values.
3636 retryCount = MAXIMUM_RETRIES;
3637 timeoutValue = SCSI_CDROM_TIMEOUT;
3638 }
3639 else
3640 {
3641 // plan to leave about 30 seconds to lower level drivers if possible.
3642 if (secondsRemaining >= 32)
3643 {
3644 retryCount = (secondsRemaining - 30)/SCSI_CDROM_TIMEOUT + 1;
3645 timeoutValue = SCSI_CDROM_TIMEOUT;
3646
3648 {
3649 retryCount = MAXIMUM_RETRIES;
3650 }
3651
3652 if (retryCount == 1)
3653 {
3654 timeoutValue = secondsRemaining - 30;
3655 }
3656 }
3657 else
3658 {
3659 // issue the command with minimal timeout value and do not retry on it.
3660 retryCount = 1;
3661 timeoutValue = 2;
3662 }
3663 }
3664 }
3665 break;
3666 default:
3670 }
3671
3672 DeviceExtension->PowerContext.RetryCount = retryCount;
3673
3674 // issue command.
3675 while (shouldRetry)
3676 {
3677
3678 // set SRB fields.
3679 DeviceExtension->PowerContext.Srb.SrbFlags = SRB_FLAGS_NO_DATA_TRANSFER |
3681 SRB_FLAGS_NO_QUEUE_FREEZE |
3683 SRB_FLAGS_D3_PROCESSING;
3684
3685 DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_EXECUTE_SCSI;
3686 DeviceExtension->PowerContext.Srb.TimeOutValue = timeoutValue;
3687
3689 {
3690 DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_LOCK_QUEUE;
3691 }
3693 {
3694 DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_QUIESCE_DEVICE;
3695 }
3697 {
3698 // Case of issuing SYNC CACHE command.
3699 DeviceExtension->PowerContext.Srb.CdbLength = 10;
3701 }
3703 {
3704 // Case of issuing STOP UNIT command.
3705 DeviceExtension->PowerContext.Srb.CdbLength = 6;
3707 cdb->START_STOP.Start = 0;
3708 cdb->START_STOP.Immediate = 1;
3709 }
3711 {
3712 DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_UNLOCK_QUEUE;
3713 }
3714
3715 // Set up completion routine and context if requested
3717 {
3718 WdfRequestSetCompletionRoutine(DeviceExtension->PowerContext.PowerRequest,
3719 CompletionRoutine,
3720 Context);
3721 }
3722
3724 DeviceExtension->PowerContext.PowerRequest,
3725 DeviceExtension->IoTarget,
3727 &requestSent);
3728
3729 if (requestSent)
3730 {
3733 {
3734 TracePrint((TRACE_LEVEL_ERROR,
3735 TRACE_FLAG_POWER,
3736 "%p\tError occured when issuing %s command to device. Srb %p, Status %x\n",
3737 DeviceExtension->PowerContext.PowerRequest,
3738 (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceQuiesced) ? "SYNC CACHE" : "STOP UNIT",
3739 &DeviceExtension->PowerContext.Srb,
3740 DeviceExtension->PowerContext.Srb.SrbStatus));
3741
3743
3744 shouldRetry = RequestSenseInfoInterpret(DeviceExtension,
3745 DeviceExtension->PowerContext.PowerRequest,
3746 &(DeviceExtension->PowerContext.Srb),
3747 retryCount - DeviceExtension->PowerContext.RetryCount,
3748 &status,
3749 &(DeviceExtension->PowerContext.RetryIntervalIn100ns));
3750
3751 if (shouldRetry && (DeviceExtension->PowerContext.RetryCount-- == 0))
3752 {
3753 shouldRetry = FALSE;
3754 }
3755 }
3756 else
3757 {
3758 // succeeded, do not need to retry.
3759 shouldRetry = FALSE;
3760 }
3761
3762 }
3763 else
3764 {
3765 // request failed to be sent
3766 shouldRetry = FALSE;
3767 }
3768
3769 if (shouldRetry)
3770 {
3772 t.QuadPart = -DeviceExtension->PowerContext.RetryIntervalIn100ns;
3774
3775 status = PowerContextReuseRequest(DeviceExtension);
3777 {
3778 shouldRetry = FALSE;
3779 }
3780 }
3781 }
3782
3784 {
3785 // record SYNC CACHE command completion time stamp.
3786 KeQueryTickCount(&DeviceExtension->PowerContext.Step1CompleteTime);
3787 }
3788
3790}
BOOLEAN RequestSenseInfoInterpret(_In_ PCDROM_DEVICE_EXTENSION DeviceExtension, _In_ WDFREQUEST Request, _In_ PSCSI_REQUEST_BLOCK Srb, _In_ ULONG RetriedCount, _Out_ NTSTATUS *Status, _Out_opt_ _Deref_out_range_(0, MAXIMUM_RETRY_FOR_SINGLE_IO_IN_100NS_UNITS) LONGLONG *RetryIntervalIn100ns)
Definition: sense.c:2467
union _CDB * PCDB
NTSTATUS RequestSend(_In_ PCDROM_DEVICE_EXTENSION DeviceExtension, _In_ WDFREQUEST Request, _In_ WDFIOTARGET IoTarget, _In_ ULONG Flags, _Out_opt_ PBOOLEAN RequestSent)
Definition: common.c:3793
Definition: cdrw_hw.h:28
struct _CDB::_START_STOP START_STOP
struct _CDB::_SYNCHRONIZE_CACHE10 SYNCHRONIZE_CACHE10
Definition: typedefs.h:103
@ WDF_REQUEST_SEND_OPTION_SYNCHRONOUS
Definition: wdfrequest.h:109
_In_ WDFREQUEST _In_opt_ PFN_WDF_REQUEST_COMPLETION_ROUTINE CompletionRoutine
Definition: wdfrequest.h:895
◆ AhciGetControllerProperties()
| NTSTATUS AhciGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 625 of file ahci_generic.c.
627{
628 PCM_PARTIAL_RESOURCE_DESCRIPTOR InterruptDesc = &Controller->InterruptDesc;
631
632 PAGED_CODE();
633
636
638 {
641 }
642
643 Controller->IoBase = AtaAhciGetAbar(Controller);
644 if (!Controller->IoBase)
646
648 Controller->Start = AtaAhciHbaStart;
649 Controller->Stop = AtaAhciHbaStop;
650 Controller->FreeResources = AtaAhciHbaFreeResouces;
651 Controller->AttachChannel = AtaAhciAttachChannel;
652
653 /* Set AE before accessing other AHCI registers */
655 GlobalControl |= AHCI_GHC_AE;
657
660 Controller->MaxChannels = CountSetBits(Controller->ChannelBitmap);
661 if (Controller->MaxChannels == 0)
662 {
663 ASSERT(Controller->MaxChannels == 0);
665 }
666
669 {
671
673 AtaAhciHbaRequestOsOwnership(Controller->IoBase);
674 }
675
676 /* Reset the HBA into a consistent state */
678 GlobalControl |= AHCI_GHC_HR;
680
681 /* HBA reset may take up to 1 second */
683 {
686 break;
687
688 KeStallExecutionProcessor(10);
689 }
691 {
694 }
695
696 /* Re-enable AE */
697 GlobalControl |= AHCI_GHC_AE;
699
700 /* Disable interrupts */
703 {
704 GlobalControl &= ~AHCI_GHC_IE;
706 }
707
708#if DBG
709 /* On virtual machines, this will allow us to test the PMP support code */
710 if (AtaAhciIsVbox())
711 Controller->AhciCapabilities |= AHCI_CAP_SPM;
712#endif
713
717
718 Controller->QueueDepth = ((Controller->AhciCapabilities & AHCI_CAP_NCS) >> 8) + 1;
719
721 Controller->Pci.VendorID,
722 Controller->Pci.DeviceID,
723 Controller->Pci.RevisionID,
724 Controller->AhciVersion,
725 Controller->ChannelBitmap,
726 Controller->AhciCapabilities,
727 Controller->AhciCapabilitiesEx);
728
729 /* Clear HBA interrupts */
731
733 AtaAhciHbaIsr,
734 Controller,
735 NULL,
743 FALSE);
745 {
749 }
750
752}
FORCEINLINE ULONG AHCI_HBA_READ(_In_ PVOID HbaIoBase, _In_ AHCI_HOST_BUS_ADAPTER_REGISTER Register)
Definition: ahci.h:529
FORCEINLINE VOID AHCI_HBA_WRITE(_In_ PVOID HbaIoBase, _In_ AHCI_HOST_BUS_ADAPTER_REGISTER Register, _In_ ULONG Value)
Definition: ahci.h:538
static PVOID AtaAhciGetAbar(_Inout_ PATA_CONTROLLER Controller)
Definition: ahci_generic.c:431
static NTSTATUS AtaAhciAttachChannel(_In_ PVOID ChannelContext, _In_ BOOLEAN Attach)
Definition: ahci_generic.c:474
static VOID AtaAhciHbaStop(_In_ PATA_CONTROLLER Controller)
Definition: ahci_generic.c:520
static BOOLEAN AhciMatchController(_In_ PATA_CONTROLLER Controller)
Definition: ahci_generic.c:583
static VOID AtaAhciHbaFreeResouces(_In_ PATA_CONTROLLER Controller)
Definition: ahci_generic.c:546
static NTSTATUS AtaAhciCreateChannelData(_In_ PATA_CONTROLLER Controller)
Definition: ahci_generic.c:348
static VOID AtaAhciHbaRequestOsOwnership(_In_ PVOID IoBase)
Definition: ahci_generic.c:291
static VOID AtaAhciHbaStart(_In_ PATA_CONTROLLER Controller)
Definition: ahci_generic.c:497
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
NTSTATUS NTAPI IoConnectInterrupt(OUT PKINTERRUPT *InterruptObject, IN PKSERVICE_ROUTINE ServiceRoutine, IN PVOID ServiceContext, IN PKSPIN_LOCK SpinLock, IN ULONG Vector, IN KIRQL Irql, IN KIRQL SynchronizeIrql, IN KINTERRUPT_MODE InterruptMode, IN BOOLEAN ShareVector, IN KAFFINITY ProcessorEnableMask, IN BOOLEAN FloatingSave)
Definition: irq.c:23
Definition: restypes.h:8
struct _CM_PARTIAL_RESOURCE_DESCRIPTOR::@384::@387 Interrupt
union _CM_PARTIAL_RESOURCE_DESCRIPTOR::@384 u
Referenced by PciIdeXFdoStartDevice().
◆ AmdGetControllerProperties()
| NTSTATUS AmdGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 329 of file amd.c.
331{
334
335 PAGED_CODE();
337
339 {
341
344 {
345 break;
346 }
347 }
350
354
356 {
357 SupportedMode = SATA_ALL;
358 }
359 else
360 {
362
364 {
366 SupportedMode &= ~UDMA_MODE6;
367 }
368 else
369 {
371 SupportedMode &= ~UDMA_MODE6;
373 SupportedMode &= ~UDMA_MODES(5, 6);
374 }
375
377 {
378 Controller->ChannelEnableBits = AmdEnableBits;
379 Controller->Start = AmdControllerStart;
380 }
381 else
382 {
383 Controller->ChannelEnableBits = NvEnableBits;
384 }
385 }
386
388 {
390
391 ChanData->HwFlags = HwFlags;
392 ChanData->TransferModeSupported = SupportedMode;
393
395 {
396 ChanData->ChanInfo |= CHANNEL_FLAG_NO_SLAVE;
397 ChanData->SetTransferMode = SataSetTransferMode;
398 }
399 else
400 {
401 ChanData->SetTransferMode = AmdSetTransferMode;
402
403 /* Check for 80-conductor cable */
405 {
407
409 {
411 ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
412 }
413 }
414 else
415 {
417
419 {
421 "assume 40-conductor cable\n",
422 ChanData->Channel);
423 ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
424 }
425 }
426 }
427 }
428
430}
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS NvEnableBits[MAX_IDE_CHANNEL]
Definition: amd.c:160
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS AmdEnableBits[MAX_IDE_CHANNEL]
Definition: amd.c:153
static PCIIDEX_PAGED_DATA const struct @1172 AmdControllerList[]
static VOID AmdControllerStart(_In_ PATA_CONTROLLER Controller)
Definition: amd.c:297
static BOOLEAN NvHasUdmaCable(_In_ USHORT UdmaTimReg, _In_ ULONG Drive)
Definition: amd.c:313
static VOID AmdSetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: amd.c:217
NTSTATUS PciIdeCreateChannelData(_In_ PATA_CONTROLLER Controller, _In_ ULONG HwExtensionSize)
Definition: pata_generic.c:1072
FORCEINLINE UCHAR PciRead8(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
Definition: pciidex.h:847
FORCEINLINE USHORT PciRead16(_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
Definition: pciidex.h:859
Definition: pciidex.h:293
Referenced by PciIdeGetControllerProperties().
◆ AtaAcpiGetTaskFile()
| PVOID AtaAcpiGetTaskFile | ( | _In_ PDEVICE_OBJECT | DeviceObject | ) |
Definition at line 212 of file acpi.c.
214{
217 ULONG RetryCount, OutputSize;
219
220 PAGED_CODE();
221 /*
222 * We invoke this routine within the PnP START handler only,
223 * and thus specify that the code is in a pageable section.
224 */
226
229
230 /*
231 * The output buffer must be large enough to hold the list of ATA commands to the drive.
232 * We assume that 10 commands is the common case.
233 */
236
237 for (RetryCount = 0; RetryCount < 2; ++RetryCount)
238 {
241 {
244 }
245
246 /* Evaluate the _GTF method */
248 &InputBuffer,
250 OutputBuffer,
251 OutputSize);
252
253 /* Increase the allocation size if it's too small */
255 {
256 OutputSize = OutputBuffer->Length;
257
259 continue;
260 }
261
262 break;
263 }
264
267
269 {
272 }
273
275 {
278 }
279
281 {
284 }
285
287
288Cleanup:
290
292}
#define ACPI_METHOD_ARGUMENT_LENGTH(DataLength)
Definition: acpiioct.h:153
ACPI_EVAL_OUTPUT_BUFFER UNALIGNED * PACPI_EVAL_OUTPUT_BUFFER
Definition: acpiioct.h:99
static PVOID ExAllocatePoolZero(ULONG PoolType, SIZE_T NumberOfBytes, ULONG Tag)
Definition: precomp.h:45
Definition: acpiioct.h:45
Definition: acpiioct.h:93
Definition: ata_shared.h:58
_Must_inspect_result_ _In_ WDFIOTARGET _In_opt_ WDFREQUEST _In_opt_ PWDF_MEMORY_DESCRIPTOR OutputBuffer
Definition: wdfiotarget.h:863
_Must_inspect_result_ _In_ WDFIOTARGET _In_opt_ WDFREQUEST _In_opt_ PWDF_MEMORY_DESCRIPTOR InputBuffer
Definition: wdfiotarget.h:953
Referenced by AtaCtrlGetInitTaskFile().
◆ AtaAcpiGetTimingMode()
| BOOLEAN AtaAcpiGetTimingMode | ( | _In_ PDEVICE_OBJECT | DeviceObject, |
| _Out_ PIDE_ACPI_TIMING_MODE_BLOCK | TimingMode | ||
| ) |
Definition at line 98 of file acpi.c.
101{
107
109
112
113 /* Evaluate the _GTM method */
115 &InputBuffer,
117 OutputBuffer,
119
121 {
123
126 }
127
129 {
133 }
134
136 {
139 }
140
142
144}
Definition: bufpool.h:45
Referenced by PciIdeAcpiSetTransferMode(), and PciIdeXPdoStartDevice().
◆ AtaAcpiSetDeviceData()
| VOID AtaAcpiSetDeviceData | ( | _In_ PDEVICE_OBJECT | DeviceObject, |
| _In_ PIDENTIFY_DEVICE_DATA | IdBlock | ||
| ) |
Definition at line 296 of file acpi.c.
299{
301 PACPI_METHOD_ARGUMENT Argument;
303 ULONG InputSize;
304
305 PAGED_CODE();
307
310
313 {
315 return;
316 }
319 InputBuffer->ArgumentCount = 1;
320 InputBuffer->Size = InputSize;
321
322 /* Argument 1: The ATA drive ID block */
323 Argument = InputBuffer->Argument;
325
326 /* Evaluate the _SDD method */
329 {
332 else
334 }
335
337}
#define ACPI_EVAL_INPUT_BUFFER_COMPLEX_SIGNATURE
Definition: acpiioct.h:15
ACPI_METHOD_ARGUMENT UNALIGNED * PACPI_METHOD_ARGUMENT
Definition: acpiioct.h:80
#define ACPI_METHOD_SET_ARGUMENT_BUFFER(Argument, BuffData, BuffLength)
Definition: acpiioct.h:174
Definition: acpiioct.h:82
Referenced by AtaCtrlSetDeviceData().
◆ AtaAcpiSetTimingMode()
| NTSTATUS AtaAcpiSetTimingMode | ( | _In_ PDEVICE_OBJECT | DeviceObject, |
| _In_ PIDE_ACPI_TIMING_MODE_BLOCK | TimingMode, | ||
| _In_opt_ PIDENTIFY_DEVICE_DATA | IdBlock1, | ||
| _In_opt_ PIDENTIFY_DEVICE_DATA | IdBlock2 | ||
| ) |
Definition at line 147 of file acpi.c.
152{
154 PACPI_METHOD_ARGUMENT Argument;
156 ULONG InputSize;
157
162
165 {
168 }
171 InputBuffer->ArgumentCount = 3;
172 InputBuffer->Size = InputSize;
173
174 /* Argument 1: The channel timing information block */
175 Argument = InputBuffer->Argument;
177
178 /* Argument 2: The ATA drive ID block */
179 Argument = ACPI_METHOD_NEXT_ARGUMENT(Argument);
180 Argument->Type = ACPI_METHOD_ARGUMENT_BUFFER;
181 Argument->DataLength = sizeof(*IdBlock1);
182 if (IdBlock1)
184 else
186
187 /* Argument 3: The ATA drive ID block */
188 Argument = ACPI_METHOD_NEXT_ARGUMENT(Argument);
189 Argument->Type = ACPI_METHOD_ARGUMENT_BUFFER;
190 Argument->DataLength = sizeof(*IdBlock2);
191 if (IdBlock2)
193 else
195
196 /* Evaluate the _STM method */
199 {
202 else
204 }
205
208}
Referenced by AtaCtrlSetTransferMode(), and PciIdeAcpiSetTransferMode().
◆ AtaAhciChannelGetMaximumDeviceCount()
Definition at line 1569 of file ahci_hw.c.
1571{
1572 PCHANNEL_DATA_AHCI ChanData = ChannelContext;
1573 PATA_CONTROLLER Controller = ChanData->Controller;
1574
1577
1579}
Definition: pciidex.h:170
Definition: pciidex.h:336
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaAhciDowngradeInterfaceSpeed()
| BOOLEAN AtaAhciDowngradeInterfaceSpeed | ( | _In_ PCHANNEL_DATA_AHCI | ChanData | ) |
Definition at line 1542 of file ahci_hw.c.
1544{
1545 ULONG SataSpeed, SataControl;
1546
1549 {
1551
1553 {
1554 SataControl &= ~AHCI_PXCTL_SPD_MASK;
1555 SataControl |= SataSpeed - AHCI_PXCTL_SPD_LIMIT_LEVEL;
1556
1558
1561 }
1562 }
1563
1566}
FORCEINLINE VOID AHCI_PORT_WRITE(_In_ PVOID PortIoBase, _In_ AHCI_PORT_REGISTER Register, _In_ ULONG Value)
Definition: ahci.h:557
FORCEINLINE ULONG AHCI_PORT_READ(_In_ PVOID PortIoBase, _In_ AHCI_PORT_REGISTER Register)
Definition: ahci.h:548
Referenced by AtaCtrlDowngradeInterfaceSpeed().
◆ AtaAhciHandleFatalError()
| VOID AtaAhciHandleFatalError | ( | _In_ PCHANNEL_DATA_AHCI | ChanData | ) |
Definition at line 1397 of file ahci_hw.c.
1399{
1400 ULONG CurrentCommandSlot, TaskFileData;
1403
1406
1407 /* Clear the ST bit. This also clears PxCI, PxSACT, and PxCMD.CCS */
1408 AtaAhciStopCommandListProcess(ChanData);
1409
1411 goto Done;
1412
1413 /* Wait for 500ms */
1415 {
1418 break;
1419
1420 KeStallExecutionProcessor(10);
1421 }
1423 {
1424 /* The interface is hung */
1426 ChanData->Channel,
1427 CmdStatus);
1428 goto Done;
1429 }
1430
1433 {
1434 /* Put the device to the idle state */
1436 goto Done;
1437 }
1438
1439 /* Clear errors */
1442
1443 /* NCQ recovery is needed */
1444 if (ChanData->ActiveQueuedSlotsBitmap != 0)
1445 {
1446 AtaAhciStartCommandListProcess(ChanData);
1447
1448 /* Find some active command */
1450
1451 Request = ChanData->Slots[FailedSlot];
1455 goto Done;
1456 }
1457
1459 {
1460 /* We have exactly one slot is outstanding */
1461 SlotsBitmap = ChanData->ActiveSlotsBitmap;
1462 }
1463 else if (ChanData->ActiveSlotsBitmap & (1 << CurrentCommandSlot))
1464 {
1465 SlotsBitmap = 1 << CurrentCommandSlot;
1466 }
1467 else
1468 {
1469 /* Indicates that the error bit is spurious *or* the exact slot is not known */
1470 if (ChanData->ActiveSlotsBitmap != 0)
1471 {
1473 ChanData->Channel,
1474 ChanData->ActiveSlotsBitmap,
1475 1 << CurrentCommandSlot);
1476 }
1477 else
1478 {
1480 ChanData->Channel,
1482 }
1483 goto Done;
1484 }
1485
1486 AtaAhciStartCommandListProcess(ChanData);
1487
1489
1490 Request = ChanData->Slots[FailedSlot];
1493
1494 /* Save the error */
1498
1499 /* Save the current task file for the "ATA LBA field" (SAT-6 11.7) */
1502 {
1504 }
1505
1506Done:
1507 /* Request arbitration from the port worker */
1509}
static VOID AtaAhciStopCommandListProcess(_In_ PCHANNEL_DATA_AHCI ChanData)
Definition: ahci_hw.c:122
static VOID AtaAhciStartCommandListProcess(_In_ PCHANNEL_DATA_AHCI ChanData)
Definition: ahci_hw.c:137
static BOOLEAN AtaAhciIsHbaHotRemoved(_In_ PCHANNEL_DATA_AHCI ChanData)
Definition: ahci_hw.c:74
VOID AtaAhciSaveTaskFile(_In_ PCHANNEL_DATA_AHCI ChanData, _Inout_ PATA_DEVICE_REQUEST Request, _In_ BOOLEAN ProcessErrorStatus)
Definition: ahci_hw.c:1325
unsigned char _BitScanForward(unsigned long *_Index, unsigned long _Mask)
Definition: intrin_arm.h:57
Definition: hwidep.h:159
Referenced by AtaAhciPortHandleInterrupt().
◆ AtaAhciHandlePortStateChange()
| VOID AtaAhciHandlePortStateChange | ( | _In_ PCHANNEL_DATA_AHCI | ChanData, |
| _In_ ULONG | InterruptStatus | ||
| ) |
Definition at line 1512 of file ahci_hw.c.
1515{
1516 ULONG SataStatus;
1517
1519 {
1521
1523 {
1525 ChanData->Channel, CmdStatus);
1527 }
1528 }
1529
1533 else
1535
1536Notify:
1537 /* Schedule a port reset */
1538 ChanData->PortNotification(AtaBusChangeDetected, ChanData->PortContext);
1539}
Referenced by AtaAhciPortHandleInterrupt().
◆ AtaAhciSaveTaskFile()
| VOID AtaAhciSaveTaskFile | ( | _In_ PCHANNEL_DATA_AHCI | ChanData, |
| _Inout_ PATA_DEVICE_REQUEST | Request, | ||
| _In_ BOOLEAN | ProcessErrorStatus | ||
| ) |
Definition at line 1325 of file ahci_hw.c.
1329{
1330 union
1331 {
1332 PAHCI_FIS_PIO_SETUP PioSetup;
1333 PAHCI_FIS_DEVICE_TO_HOST DeviceToHost;
1334 } Fis;
1335 PAHCI_RECEIVED_FIS ReceivedFis;
1336
1337 ReceivedFis = ChanData->ReceivedFis;
1338
1341
1343
1344 if (ProcessErrorStatus)
1345 {
1346 /*
1347 * Device to Host FIS on failed commands.
1348 * The Request->Output.Status and Request->Output.Error fields should have saved earlier.
1349 */
1350 Fis.DeviceToHost = &ReceivedFis->DeviceToHostFis;
1351 }
1352 else
1353 {
1354 /* Check for successful queued commands (see SATA 3.5 specification 11.14) */
1356 {
1357 PAHCI_FIS_SET_DEVICE_BITS SetDeviceBitsFis;
1358
1359 /*
1360 * The SDB FIS was received and we do not have enough information
1361 * for the rest of the registers. Emulate the content of the task file registers.
1362 */
1364
1365 SetDeviceBitsFis = &ReceivedFis->SetDeviceBitsFis;
1368 return;
1369 }
1370 /* Check for successful PIO Data-In commands (see SATA 3.5 specification 11.8) */
1372 {
1373 /* In this case we have received a PIO Setup FIS */
1374 Fis.PioSetup = &ReceivedFis->PioSetupFis;
1375
1377 Request->Output.Error = Fis.PioSetup->Error;
1378 }
1379 else
1380 {
1381 ULONG TaskFileData;
1382
1383 /* Otherwise, we have received a Device to Host FIS */
1384 Fis.DeviceToHost = &ReceivedFis->DeviceToHostFis;
1385
1388 Request->Output.Error =
1390 }
1391 }
1392
1394}
static VOID AtaAhciSaveReceivedFisArea(_In_ AHCI_FIS_DEVICE_TO_HOST *__restrict Fis, _Inout_ ATA_DEVICE_REQUEST *__restrict Request)
Captures and saves a dump of the AHCI task file registers, except the values in the Fis->Status and F...
Definition: ahci_hw.c:1302
Definition: ahci.h:409
Definition: ahci.h:383
Definition: ahci.h:434
Definition: ahci.h:447
Referenced by AtaAhciHandleFatalError(), and AtaAhciPortCompleteCommands().
◆ AtaAhciStopDma()
| VOID AtaAhciStopDma | ( | _In_ PCHANNEL_DATA_AHCI | ChanData | ) |
Definition at line 1280 of file ahci_hw.c.
1282{
1283 AtaAhciStopCommandListProcessAndWait(ChanData);
1284 AtaAhciPerformCommandListOverride(ChanData);
1285 AtaAhciStopFisReceiveProcessAndWait(ChanData);
1286}
static BOOLEAN AtaAhciPerformCommandListOverride(_In_ PCHANNEL_DATA_AHCI ChanData)
Definition: ahci_hw.c:267
static BOOLEAN AtaAhciStopCommandListProcessAndWait(_In_ PCHANNEL_DATA_AHCI ChanData)
Definition: ahci_hw.c:163
static BOOLEAN AtaAhciStopFisReceiveProcessAndWait(_In_ PCHANNEL_DATA_AHCI ChanData)
Definition: ahci_hw.c:207
Referenced by AtaAhciAttachChannel().
◆ AtaChanEnableInterruptsSync()
| DECLSPEC_NOINLINE_FROM_PAGED VOID AtaChanEnableInterruptsSync | ( | _In_ PVOID | ChannelContext, |
| _In_ BOOLEAN | Enable | ||
| ) |
Definition at line 62 of file fdo.c.
65{
66 PCHANNEL_DATA_COMMON ChanData = ChannelContext;
70
73 else
76
80}
KIRQL NTAPI KeAcquireInterruptSpinLock(IN PKINTERRUPT Interrupt)
Definition: spinlock.c:154
VOID NTAPI KeReleaseInterruptSpinLock(IN PKINTERRUPT Interrupt, IN KIRQL OldIrql)
Definition: spinlock.c:171
Definition: pciidex.h:237
PCHANNEL_ENABLE_INTERRUPTS EnableInterrupts
Definition: pciidex.h:247
Definition: ketypes.h:1059
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:778
Referenced by AtaAhciAttachChannel(), AtaAhciEnumerateChannel(), PataResetChannel(), PciIdeAttachChannel(), and PciIdeFreeResources().
◆ AtaCtrlPciMapBar()
| PVOID AtaCtrlPciMapBar | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_range_(0, PCI_TYPE0_ADDRESSES) ULONG | Index, | ||
| _In_ ULONG | MinimumIoLength | ||
| ) |
Definition at line 249 of file fdo.c.
253{
254 PAGED_CODE();
255
258
259 /* Validate the BAR length */
260 if (MinimumIoLength != 0)
261 {
263 {
265 Controller->Pci.VendorID,
266 Controller->Pci.DeviceID,
267 Controller->Pci.RevisionID,
268 Index,
269 Controller->AccessRange[Index].Length,
270 MinimumIoLength);
272 }
273 }
274
277 {
279
281
284 Controller->AccessRange[Index].Length,
285 MmNonCached);
286 }
287
289}
PVOID NTAPI MmMapIoSpace(IN PHYSICAL_ADDRESS PhysicalAddress, IN SIZE_T NumberOfBytes, IN MEMORY_CACHING_TYPE CacheType)
Definition: iosup.c:47
_Must_inspect_result_ typedef _In_ PHYSICAL_ADDRESS PhysicalAddress
Definition: iotypes.h:1098
Referenced by AtaAhciGetAbar(), PciIdeAssignNativeResources(), PciIdeControllerInitDma(), SvwSataGetControllerProperties(), and Via6421ParseResources().
◆ AtaReadBlock16()
| VOID AtaReadBlock16 | ( | _In_ PUSHORT | Port, |
| _In_ PUSHORT | Buffer, | ||
| _In_ ULONG | Count, | ||
| _In_ ULONG | MmioFlags | ||
| ) |
Definition at line 31 of file pata_io.c.
36{
39
40 if (MmioFlags)
42 else
44}
#define READ_PORT_BUFFER_USHORT(port, buffer, count)
Definition: hardware.h:31
NTKERNELAPI VOID NTAPI READ_REGISTER_BUFFER_USHORT(IN PUSHORT Register, IN PUSHORT Buffer, IN ULONG Count)
◆ AtaReadBlock32()
| VOID AtaReadBlock32 | ( | _In_ PULONG | Port, |
| _In_ PULONG | Buffer, | ||
| _In_ ULONG | Count, | ||
| _In_ ULONG | MmioFlags | ||
| ) |
◆ AtaReadPortUchar()
◆ AtaSelectTimings()
| VOID AtaSelectTimings | ( | _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG * | DeviceList, |
| _Out_writes_all_(MAX_IDE_DEVICE) PATA_TIMING | Timings, | ||
| _In_range_(>, 0) ULONG | ClockPeriodPs, | ||
| _In_ ULONG | Flags | ||
| ) |
Definition at line 116 of file pata_generic.c.
121{
123
125 {
128 ATA_TIMING DmaTiming;
129
131 {
133 continue;
134 }
135
136 /* PIO mode */
138
139 /* UDMA works independently of any PIO mode */
141 continue;
142
143 /* DMA mode */
145
146 /*
147 * Typically, the ATA port driver uses PIO commands along with DMA ones.
148 * Given that we program the chipset only once after device enumeration,
149 * we want to make sure the PIO commands would always work.
150 */
156 }
157
158 /* Merge timings shared between both drives */
160 {
161 Timings[0].AddressSetup = max(Timings[0].AddressSetup, Timings[1].AddressSetup);
162
163 Timings[1].AddressSetup = Timings[0].AddressSetup;
164 }
166 {
167 Timings[0].CmdActive = max(Timings[0].CmdActive, Timings[1].CmdActive);
168 Timings[0].CmdRecovery = max(Timings[0].CmdRecovery, Timings[1].CmdRecovery);
169
170 Timings[1].CmdActive = Timings[0].CmdActive;
171 Timings[1].CmdRecovery = Timings[0].CmdRecovery;
172 }
174 {
175 Timings[0].DataActive = max(Timings[0].DataActive, Timings[1].DataActive);
176 Timings[0].DataRecovery = max(Timings[0].DataRecovery, Timings[1].DataRecovery);
177
178 Timings[1].DataActive = Timings[0].DataActive;
179 Timings[1].DataRecovery = Timings[0].DataRecovery;
180 }
181}
static VOID AtaCalculateTimings(_In_ PCHANNEL_DEVICE_CONFIG Device, _Out_ PATA_TIMING Timing, _In_ ULONG Mode, _In_ ULONG ClockPeriodPs)
Definition: pata_generic.c:62
Definition: pata.h:220
Definition: ata_shared.h:132
Referenced by AmdSetTransferMode(), CmdSetTransferMode(), Via6421SetTransferMode(), and ViaSetTransferMode().
◆ AtaSleep()
Definition at line 100 of file pciidex.c.
101{
104
106
108
112}
Definition: cppunit_timer.h:24
#define KeWaitForSingleObject(pEvt, foo, a, b, c)
Definition: env_spec_w32.h:478
Definition: ketypes.h:903
BOOLEAN NTAPI KeSetTimer(IN OUT PKTIMER Timer, IN LARGE_INTEGER DueTime, IN PKDPC Dpc OPTIONAL)
Definition: timerobj.c:282
Referenced by AtaAhciPhyCheckDevicePresence(), AtaAhciPmpPhyCheckDevicePresence(), AtaAhciPmpPhyWaitForReady(), AtaAhciPollRegister(), AtaAhciWaitForDeviceReady(), and PataResetChannel().
◆ AtaWriteBlock16()
| VOID AtaWriteBlock16 | ( | _In_ PUSHORT | Port, |
| _In_ PUSHORT | Buffer, | ||
| _In_ ULONG | Count, | ||
| _In_ ULONG | MmioFlags | ||
| ) |
Definition at line 15 of file pata_io.c.
20{
23
24 if (MmioFlags)
26 else
28}
#define WRITE_PORT_BUFFER_USHORT(port, buffer, count)
Definition: hardware.h:34
NTKERNELAPI VOID NTAPI WRITE_REGISTER_BUFFER_USHORT(IN PUSHORT Register, IN PUSHORT Buffer, IN ULONG Count)
◆ AtaWriteBlock32()
| VOID AtaWriteBlock32 | ( | _In_ PULONG | Port, |
| _In_ PULONG | Buffer, | ||
| _In_ ULONG | Count, | ||
| _In_ ULONG | MmioFlags | ||
| ) |
Definition at line 47 of file pata_io.c.
52{
55
56 if (MmioFlags)
58 else
60}
#define WRITE_PORT_BUFFER_ULONG(port, buffer, count)
Definition: hardware.h:35
NTKERNELAPI VOID NTAPI WRITE_REGISTER_BUFFER_ULONG(IN PULONG Register, IN PULONG Buffer, IN ULONG Count)
◆ AtaWritePortUchar()
Definition at line 90 of file pata_io.c.
94{
95 if (MmioFlags)
97 else
99}
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING _Out_opt_ PUSHORT _Inout_opt_ PUNICODE_STRING Value
Definition: wdfregistry.h:413
NTKERNELAPI VOID NTAPI WRITE_REGISTER_UCHAR(IN PUCHAR Register, IN UCHAR Value)
◆ AtaWritePortUlong()
◆ AtiGetControllerProperties()
| NTSTATUS AtiGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 36 of file ati.c.
38{
41
42 PAGED_CODE();
44
46 Controller->Pci.DeviceID != PCI_DEV_IXP300_IDE &&
47 Controller->Pci.DeviceID != PCI_DEV_IXP400_IDE &&
48 Controller->Pci.DeviceID != PCI_DEV_IXP600_IDE &&
49 Controller->Pci.DeviceID != PCI_DEV_IXP700_IDE)
50 {
52 }
53
54 Controller->ChannelEnableBits = AtiEnableBits;
55
57 Controller->MaxChannels = 1;
58
62
64 {
66
67 ChanData->SetTransferMode = SvwSetTransferMode;
69
71 ChanData->TransferModeSupported &= ~UDMA_MODE5;
72
74 {
76 "assume 40-conductor cable\n",
77 ChanData->Channel);
78 ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
79 }
80 }
81
83}
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS AtiEnableBits[MAX_IDE_CHANNEL]
Definition: ati.c:26
BOOLEAN SvwHasUdmaCable(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel)
Definition: svw_pata.c:213
Referenced by PciIdeGetControllerProperties().
◆ CmdGetControllerProperties()
| NTSTATUS CmdGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 460 of file cmd.c.
462{
466
467 PAGED_CODE();
469
470 switch (Controller->Pci.DeviceID)
471 {
473 /*
474 * Errata: The CMD-640 has one set of task file registers per controller
475 * and thus the two channels cannot be used simultaneously.
476 * https://www.mindprod.com/jgloss/eideflaw.html
477 */
478 Controller->Flags |= CTRL_FLAG_IS_SIMPLEX;
479
480 SupportedMode = PIO_ALL;
482 break;
483
486
487 if (Controller->Pci.RevisionID < 6)
488 HwFlags |= HW_FLAGS_PRIMARY_ENABLED;
489 break;
490
493 HwFlags |= HW_FLAGS_HAS_UDMA_REG;
494
495 if (Controller->Pci.RevisionID < 3)
496 HwFlags |= HW_FLAGS_PRIMARY_ENABLED;
497 else
498 CheckInterrupt = CmdCheckInterruptMrdMode;
499
500 if (Controller->Pci.RevisionID == 5 || Controller->Pci.RevisionID == 6)
501 {
502 /*
503 * Early 646U2 revisions can support UDMA2 only at a PCI bus speed of 33MHz.
504 * When it runs at 25 MHz or 30 MHZ, the transfer speed must be limited to UDMA1.
505 */
506 SupportedMode |= UDMA_MODES(0, 1);
507 }
508 else if (Controller->Pci.RevisionID > 6)
509 {
510 SupportedMode |= UDMA_MODES(0, 2);
511 }
512 break;
513
516 /* Prefetch bits have different meaning on this controller */
518 CheckInterrupt = CmdCheckInterruptMrdMode;
519 break;
520
523 HwFlags |= HW_FLAGS_HAS_UDMA_REG;
524
525 if (Controller->Pci.RevisionID == 2)
526 HwFlags |= HW_FLAGS_NEED_PIO_FIX;
527
528 CheckInterrupt = CmdCheckInterruptMrdMode;
529 break;
530
531 default:
533 }
534
535 Controller->Start = CmdControllerStart;
536
537 Controller->Flags |= CTRL_FLAG_USE_TEST_FUNCTION;
538 Controller->ChannelEnabledTest = CmdChannelEnabledTest;
539
543
545 if (!Controller->HwExt)
547
549 {
551
552 ChanData->HwFlags = HwFlags;
553 ChanData->CheckInterrupt = CheckInterrupt;
554 ChanData->SetTransferMode = CmdSetTransferMode;
555 ChanData->TransferModeSupported = SupportedMode;
556
558 {
559 ChanData->ChanInfo &= ~CHANNEL_FLAG_IO32;
560 }
561 else
562 {
563 /* Check for 80-conductor cable */
565 {
568 {
570 ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
571 }
572 }
573 }
574 }
575
577}
static VOID CmdSetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: cmd.c:243
static BOOLEAN CmdCheckInterruptPci(_In_ PCHANNEL_DATA_PATA ChanData)
Definition: cmd.c:407
static IDE_CHANNEL_STATE CmdChannelEnabledTest(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel)
Definition: cmd.c:356
static BOOLEAN CmdCheckInterruptMrdMode(_In_ PCHANNEL_DATA_PATA ChanData)
Definition: cmd.c:376
static VOID CmdControllerStart(_In_ PATA_CONTROLLER Controller)
Definition: cmd.c:424
Definition: cmd.c:63
Referenced by PciIdeGetControllerProperties().
◆ CountSetBits()
| FORCEINLINE ULONG CountSetBits | ( | _In_ ULONG | x | ) |
◆ IntelGetControllerProperties()
| NTSTATUS IntelGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 969 of file intel.c.
971{
975
976 PAGED_CODE();
978
980 {
982
984 break;
985 }
988
989 Controller->Flags |= CTRL_FLAG_DMA_INTERRUPT;
990
992 Controller->MaxChannels = 1;
993
996 else
997 ExtensionSize = 0;
998
1002
1004 {
1006 /*
1007 * This is a bridge device and there are no PCI BAR resources allocated,
1008 * so mark the controller as a legacy device.
1009 */
1010 Controller->Flags &= ~CTRL_FLAG_NATIVE_PCI;
1011 Controller->ChannelEnableBits = IntelMpiixEnableBits;
1012 break;
1013
1018 Controller->ChannelEnableBits = IntelPiixEnableBits;
1019 break;
1020
1022 // TODO: Implement the map support
1023 //Controller->ChannelEnabledTest = IntelCombinedEnabledTest;
1024 //HwFlags = TYPE_ICH;
1025 break;
1026
1027 default:
1028 break;
1029 }
1030 HwFlags = ControllerInfo->Type;
1031
1033 HwFlags |= HW_FLAGS_DISABLE_DMA;
1034
1036 {
1038
1039 ChanData->HwFlags = HwFlags;
1040
1041 IntelInitChannel(Controller, ControllerInfo, ChanData);
1042
1044 ChanData->TransferModeSupported &= PIO_ALL;
1045 }
1046
1048}
static VOID IntelInitChannel(_In_ PATA_CONTROLLER Controller, _In_ const INTEL_CONTROLLER_INFO *ControllerInfo, _In_ PCHANNEL_DATA_PATA ChanData)
Definition: intel.c:836
static BOOLEAN IntelPciBridgeErrataMatch(_In_ PVOID Context, _In_ ULONG BusNumber, _In_ PCI_SLOT_NUMBER PciSlot, _In_ PPCI_COMMON_HEADER PciConfig)
Definition: intel.c:772
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelPiixEnableBits[MAX_IDE_CHANNEL]
Definition: intel.c:366
static PCIIDEX_PAGED_DATA const ATA_PCI_ENABLE_BITS IntelMpiixEnableBits[MAX_IDE_CHANNEL]
Definition: intel.c:373
static PCIIDEX_PAGED_DATA const INTEL_CONTROLLER_INFO IntelControllerList[]
Definition: intel.c:273
struct _INTEL_HW_EXTENSION INTEL_HW_EXTENSION
BOOLEAN PciFindDevice(_In_ __callback PATA_PCI_MATCH_FN MatchFunction, _In_ PVOID Context)
Definition: pciidex.c:13
Definition: intel.c:250
Referenced by PciIdeGetControllerProperties().
◆ IsPowerOfTwo()
| FORCEINLINE BOOLEAN IsPowerOfTwo | ( | _In_ ULONG | x | ) |
◆ PataChannelGetMaximumDeviceCount()
Definition at line 87 of file pata_hw.c.
89{
90 PCHANNEL_DATA_PATA ChanData = ChannelContext;
91
92#if defined(_M_IX86)
94 return 4;
95#endif
96
98}
Referenced by PataEnumerateChannel(), PataResetChannel(), and PciIdeXQueryPciIdeInterface().
◆ PciFindDevice()
| BOOLEAN PciFindDevice | ( | _In_ __callback PATA_PCI_MATCH_FN | MatchFunction, |
| _In_ PVOID | Context | ||
| ) |
Definition at line 13 of file pciidex.c.
16{
18
20 {
22 {
24 {
29
33
35 BusNumber,
37 &Buffer,
38 0,
42 PciConfig->VendorID == 0)
43 {
44 if (FunctionNumber == 0)
45 {
46 /* This slot has no single- or a multi-function device */
47 break;
48 }
49 else
50 {
51 /* Continue scanning the functions */
52 continue;
53 }
54 }
55
58
60 {
61 /* The device is a single function device */
62 break;
63 }
64 }
65 }
66 }
67
69}
ULONG NTAPI HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType, IN ULONG BusNumber, IN ULONG SlotNumber, IN PVOID Buffer, IN ULONG Offset, IN ULONG Length)
Definition: bus.c:73
Definition: iotypes.h:3580
Definition: iotypes.h:3491
struct _PCI_SLOT_NUMBER::@4498::@4499 bits
union _PCI_SLOT_NUMBER::@4498 u
_Must_inspect_result_ _In_ WDFIOTARGET _In_opt_ WDFREQUEST _In_opt_ PWDF_MEMORY_DESCRIPTOR _In_opt_ PLONGLONG _In_opt_ PWDF_REQUEST_SEND_OPTIONS _Out_opt_ PULONG_PTR BytesRead
Definition: wdfiotarget.h:870
struct _PCI_COMMON_HEADER * PPCI_COMMON_HEADER
Referenced by IntelGetControllerProperties(), SvwPataControllerStart(), and ViaPataGetControllerProperties().
◆ PciIdeConnectInterrupt()
Definition at line 1012 of file pata_generic.c.
1014{
1015 PCHANNEL_DATA_PATA ChanData = ChannelContext;
1016 PATA_CONTROLLER Controller = ChanData->Controller;
1017 PCM_PARTIAL_RESOURCE_DESCRIPTOR InterruptDesc;
1018 PKSERVICE_ROUTINE IsrHandler;
1020
1021 PAGED_CODE();
1022
1024 InterruptDesc = &Controller->InterruptDesc;
1025 else
1026 InterruptDesc = &ChanData->InterruptDesc;
1027 ASSERT(InterruptDesc);
1028
1030 IsrHandler = PciIdeChannelIsr;
1031 else
1032 IsrHandler = PataChannelIsr;
1034 IsrHandler,
1035 ChanData,
1036 NULL,
1044 FALSE);
1046 {
1050 }
1051
1053}
Referenced by PciIdeXPdoStartDevice().
◆ PciIdeCreateChannelData()
| NTSTATUS PciIdeCreateChannelData | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | HwExtensionSize | ||
| ) |
Definition at line 1072 of file pata_generic.c.
1075{
1076 PCHANNEL_DATA_PATA ChanData;
1078
1079 PAGED_CODE();
1080 ASSERT(Controller->MaxChannels != 0);
1081
1084 if (!ChanData)
1086
1087 Controller->ChanDataBlock = ChanData;
1088 Controller->ChannelBitmap = NUM_TO_BITMAP(Controller->MaxChannels);
1089
1091 {
1092 Controller->Channels[i] = ChanData;
1093
1094 ChanData->Channel = i;
1095 ChanData->Controller = Controller;
1096
1097 /* Set default values */
1098 ChanData->ChanInfo = CHANNEL_FLAG_IO32;
1099 ChanData->AllocateMemory = PciIdeAllocateMemory;
1100 ChanData->FreeMemory = PciIdeFreeMemory;
1101 ChanData->EnableInterrupts = PataEnableInterrupts;
1102 ChanData->PreparePrdTable = PciIdePreparePrdTable;
1103 ChanData->PrepareIo = PataPrepareIo;
1104 ChanData->StartIo = PataStartIo;
1108 ChanData->SetTransferMode = PciIdeGenericSetTransferMode;
1110
1112
1114 }
1115
1117}
VOID NTAPI KeInitializeDpc(IN PKDPC Dpc, IN PKDEFERRED_ROUTINE DeferredRoutine, IN PVOID DeferredContext)
Definition: dpc.c:712
static VOID PciIdeGenericSetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: pata_generic.c:416
static NTSTATUS PciIdeAllocateMemory(_In_ PVOID ChannelContext)
Definition: pata_generic.c:511
static VOID PciIdeFreeMemory(_In_ PVOID ChannelContext)
Definition: pata_generic.c:485
static VOID PataEnableInterrupts(_In_ PVOID ChannelContext, _In_ BOOLEAN Enable)
Definition: pata_generic.c:965
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_DEVICE_PROPERTY_DATA _In_ DEVPROPTYPE _In_ ULONG Size
Definition: wdfdevice.h:4539
Referenced by AmdGetControllerProperties(), AtiGetControllerProperties(), CmdGetControllerProperties(), IntelGetControllerProperties(), PataGetControllerProperties(), PciIdeGetControllerProperties(), PcTechGetControllerProperties(), Sil680GetControllerProperties(), SvwPataGetControllerProperties(), SvwSataGetControllerProperties(), ToshibaGetControllerProperties(), Via6421GetControllerProperties(), ViaCx700GetControllerProperties(), and ViaGetControllerProperties().
◆ PciIdeDmaStop()
| VOID PciIdeDmaStop | ( | _In_ PCHANNEL_DATA_PATA | ChanData | ) |
Definition at line 247 of file pata_io.c.
249{
250 PUCHAR IoBase = ChanData->Regs.Dma;
251
252 /* Wait one PIO transfer cycle */
254
255 /* Clear the interrupt bit in the status register */
258}
Referenced by PataResetChannel(), and PciIdeChannelIsr().
◆ PciIdeFreeResources()
Definition at line 877 of file pata_generic.c.
879{
880 PCHANNEL_DATA_PATA ChanData = ChannelContext;
881
882 PAGED_CODE();
883
884 if (ChanData->InterruptObject)
885 {
887
888 IoDisconnectInterrupt(ChanData->InterruptObject);
889 ChanData->InterruptObject = NULL;
890 }
891
893
894 ChanData->ChanInfo &= ~(CHANNEL_FLAG_DRIVE0_DMA_CAPABLE |
896
897 PataReleaseLegacyAddressRanges(ChanData);
898}
VOID NTAPI IoDisconnectInterrupt(PKINTERRUPT InterruptObject)
Definition: irq.c:142
static VOID PataReleaseLegacyAddressRanges(_In_ PCHANNEL_DATA_PATA ChanData)
Definition: pata_generic.c:433
DECLSPEC_NOINLINE_FROM_PAGED VOID AtaChanEnableInterruptsSync(_In_ PVOID ChannelContext, _In_ BOOLEAN Enable)
Definition: fdo.c:62
Referenced by PciIdeXPdoStopDevice().
◆ PciIdeGetChannelState()
| IDE_CHANNEL_STATE PciIdeGetChannelState | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | Channel | ||
| ) |
Definition at line 902 of file pata_generic.c.
905{
906 PAGED_CODE();
907
908 /* SFF-8038i compliant hardware */
910 {
911 /*
912 * If any native PCI IDE channel is enabled,
913 * its PCI I/O resources should be allocated as well:
914 *
915 * [BAR 0] I/O ports at FFC0 [size=8] Channel 0 task file registers
916 * [BAR 1] I/O ports at FF8C [size=4] Channel 0 device control
917 * [BAR 2] I/O ports at FF80 [size=8] Channel 1 task file registers
918 * [BAR 3] I/O ports at FF88 [size=4] Channel 1 device control
919 * [BAR 4] I/O ports at FFA0 [size=16] Bus Mastering registers
920 * [BAR 5] Memory at FE780000 Aux registers
921 */
923 {
925
927
928 /* Check task file registers */
931
932 /* Check device control */
935 }
936 }
937
938 if (Controller->ChannelEnableBits)
939 {
941 {
942 /* Device-specific test */
944 }
945 else
946 {
948 UCHAR RegisterValue;
949
950 /* Test PCI bits */
954 else
956 }
957 }
958
959 /* This channel is always enabled */
961}
Definition: pciidex.h:163
Referenced by PciIdeXGetChannelState().
◆ PciIdeGetControllerProperties()
| NTSTATUS PciIdeGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 1121 of file pata_generic.c.
1123{
1126
1127 PAGED_CODE();
1128
1129 Controller->MaxChannels = MAX_IDE_CHANNEL;
1130
1131 /* Match the controller through the PCI ID */
1132 switch (Controller->Pci.VendorID)
1133 {
1136 break;
1140 break;
1145 break;
1148 break;
1151 break;
1156 break;
1159 break;
1162 break;
1163
1164 default:
1166 break;
1167 }
1168
1169 /* Try to use the generic PCI IDE minidriver */
1171 {
1173 ((Controller->Pci.SubClass != PCI_SUBCLASS_MSC_IDE_CTLR) &&
1174 (Controller->Pci.SubClass != PCI_SUBCLASS_MSC_RAID_CTLR)))
1175 {
1178 }
1179
1181 Controller->Pci.VendorID,
1182 Controller->Pci.DeviceID,
1183 Controller->Pci.RevisionID);
1184
1188
1189 /* Disable 32-bit I/O for unknown controllers */
1191 {
1193
1194 ChanData->ChanInfo &= ~CHANNEL_FLAG_IO32;
1195 }
1196 }
1197
1200
1201 /*
1202 * Check for a legacy PCI IDE device.
1203 * NOTE: NT architecture does not support switching only one IDE channel to native mode.
1204 */
1206 (Controller->Pci.SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
1207 {
1209 !(Controller->Pci.ProgIf & PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE))
1210 {
1211 Controller->Flags &= ~CTRL_FLAG_NATIVE_PCI;
1212 }
1213 }
1214
1216 {
1218 {
1221 }
1222 }
1223
1225 {
1227 {
1229
1230 ChanData->TransferModeSupported &= PIO_ALL;
1231 }
1232 }
1233
1235 {
1237
1238 Controller->HwSyncObject = IoCreateController(0);
1239 if (!Controller->HwSyncObject)
1241 }
1242
1244}
NTSTATUS AmdGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: amd.c:329
NTSTATUS AtiGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: ati.c:36
PCONTROLLER_OBJECT NTAPI IoCreateController(IN ULONG Size)
Definition: controller.c:57
NTSTATUS CmdGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: cmd.c:460
NTSTATUS IntelGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: intel.c:969
#define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE
Definition: pata.h:97
#define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE
Definition: pata.h:95
static BOOLEAN PciIdeControllerInitDma(_In_ PATA_CONTROLLER Controller)
Definition: pata_generic.c:565
NTSTATUS PcTechGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: pctech.c:41
NTSTATUS Sil680GetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: sil680.c:214
NTSTATUS SvwPataGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: svw_pata.c:288
NTSTATUS SvwSataGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: svw_sata.c:215
NTSTATUS ToshibaGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: toshiba.c:102
NTSTATUS ViaGetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: via.c:859
◆ PciIdeInitTaskFileIoResources()
| VOID PciIdeInitTaskFileIoResources | ( | _In_ PCHANNEL_DATA_PATA | ChanData, |
| _In_ ULONG_PTR | CommandPortBase, | ||
| _In_ ULONG_PTR | ControlPortBase, | ||
| _In_ ULONG | CommandBlockSpare | ||
| ) |
Definition at line 663 of file pata_generic.c.
668{
669 PIDE_REGISTERS Registers = &ChanData->Regs;
670
671 PAGED_CODE();
672
673 /* Standard PATA register layout */
682
684}
Definition: hwidep.h:106
Referenced by PciIdeAssignLegacyResources(), PciIdeAssignNativeResources(), SvwSataParseResources(), and Via6421ParseResources().
◆ PciIdeParseResources()
| NTSTATUS PciIdeParseResources | ( | _In_ PCHANNEL_DATA_PATA | ChanData, |
| _In_ PCM_RESOURCE_LIST | ResourcesTranslated | ||
| ) |
Definition at line 849 of file pata_generic.c.
852{
853 PATA_CONTROLLER Controller = ChanData->Controller;
855
856 PAGED_CODE();
857
858 ASSERT(ChanData->Channel < 2);
859
862 else
865 {
868 }
869
870 PataClaimLegacyAddressRanges(ChanData);
871
873}
static VOID PataClaimLegacyAddressRanges(_In_ PCHANNEL_DATA_PATA ChanData)
Definition: pata_generic.c:452
static NTSTATUS PciIdeAssignNativeResources(_In_ PATA_CONTROLLER Controller, _In_ PCHANNEL_DATA_PATA ChanData)
Definition: pata_generic.c:689
static NTSTATUS PciIdeAssignLegacyResources(_In_ PCHANNEL_DATA_PATA ChanData, _In_ PCM_RESOURCE_LIST ResourcesTranslated)
Definition: pata_generic.c:723
_In_ WDFCMRESLIST _In_ WDFCMRESLIST ResourcesTranslated
Definition: wdfdevice.h:891
Referenced by PataGetControllerProperties(), and PciIdeXPdoStartDevice().
◆ PciIdeXChannelState()
| IDE_CHANNEL_STATE PciIdeXChannelState | ( | _In_ PFDO_DEVICE_EXTENSION | FdoExtension, |
| _In_ ULONG | Channel | ||
| ) |
Definition at line 15 of file miniport.c.
18{
19 PCIIDE_CHANNEL_ENABLED MiniportChannelEnabled;
20
21 PAGED_CODE();
22
23 MiniportChannelEnabled = FdoExtension->Properties.PciIdeChannelEnabled;
24 if (MiniportChannelEnabled)
26
28}
IDE_CHANNEL_STATE(NTAPI * PCIIDE_CHANNEL_ENABLED)(_In_ PVOID DeviceExtension, _In_ ULONG Channel)
Definition: ide.h:203
◆ PciIdeXFdoDispatchPnp()
| NTSTATUS PciIdeXFdoDispatchPnp | ( | _In_ PFDO_DEVICE_EXTENSION | FdoExtension, |
| _Inout_ PIRP | Irp | ||
| ) |
Definition at line 910 of file fdo.c.
913{
914 PIO_STACK_LOCATION IoStack;
916
917 PAGED_CODE();
918
921 {
924
926 }
927
930 {
932 {
934 {
937 }
941
943 IoStack->Parameters.
944 StartDevice.AllocatedResourcesTranslated);
946 }
947
949 {
951 break;
952 }
953
955 {
957
959
963
967 }
968
970 {
972 break;
973 }
974
976 {
978 break;
979
983
985 break;
986 }
987
989 {
991 break;
992 }
993
995 {
998 break;
999
1001 break;
1002 }
1003
1010 break;
1011
1014
1015 default:
1016 break;
1017 }
1018
1021
1024
1025CompleteIrp:
1028
1031}
VOID CompleteIrp(IN PIRP Irp, IN NTSTATUS Status, IN ULONG_PTR Information)
Definition: pnp.c:12
static BOOL StartDevice(IN HDEVINFO DeviceInfoSet, IN PSP_DEVINFO_DATA DevInfoData OPTIONAL, IN BOOL bEnable, IN DWORD HardwareProfile OPTIONAL, OUT BOOL *bNeedReboot OPTIONAL)
Definition: wizard.c:173
BOOLEAN NTAPI IoForwardIrpSynchronously(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp)
Definition: irp.c:1625
NTSTATUS PciIdeXPnpQueryDeviceUsageNotification(_In_ PCOMMON_DEVICE_EXTENSION CommonExt, _In_ PIRP Irp)
Definition: pciidex.c:214
NTSTATUS PciIdeXPnpQueryPnpDeviceState(_In_ PCOMMON_DEVICE_EXTENSION CommonExt, _In_ PIRP Irp)
Definition: pciidex.c:266
static NTSTATUS PciIdeXFdoQueryBusRelations(_In_ PFDO_DEVICE_EXTENSION FdoExt, _In_ PIRP Irp)
Definition: fdo.c:693
static NTSTATUS PciIdeXFdoQueryInterface(_In_ PFDO_DEVICE_EXTENSION FdoExtension, _In_ PIO_STACK_LOCATION IoStack)
Definition: fdo.c:803
static NTSTATUS PciIdeXFdoQueryId(_In_ PFDO_DEVICE_EXTENSION FdoExt, _In_ PIRP Irp, _In_ PIO_STACK_LOCATION IoStack)
Definition: fdo.c:845
static NTSTATUS PciIdeXFdoStopDevice(_In_ PFDO_DEVICE_EXTENSION FdoExtension)
Definition: fdo.c:574
union _IO_STACK_LOCATION::@1696 Parameters
struct _IO_STACK_LOCATION::@4454::@4479 QueryDeviceRelations
#define IoAcquireRemoveLock(RemoveLock, Tag)
#define IoReleaseRemoveLockAndWait(_RemoveLock, _Tag)
Definition: iofuncs.h:2774
#define IRP_MN_CANCEL_STOP_DEVICE
#define IRP_MN_QUERY_PNP_DEVICE_STATE
#define IRP_MN_QUERY_INTERFACE
#define IRP_MN_START_DEVICE
#define IRP_MN_DEVICE_USAGE_NOTIFICATION
#define IRP_MN_QUERY_ID
#define IRP_MN_REMOVE_DEVICE
#define IRP_MN_QUERY_DEVICE_RELATIONS
#define IRP_MN_QUERY_STOP_DEVICE
#define IRP_MN_CANCEL_REMOVE_DEVICE
#define IRP_MN_STOP_DEVICE
#define IRP_MN_QUERY_REMOVE_DEVICE
Referenced by PciIdeXDispatchPnp().
◆ PciIdeXGetChannelState()
| IDE_CHANNEL_STATE PciIdeXGetChannelState | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | Channel | ||
| ) |
Definition at line 678 of file fdo.c.
681{
682 PAGED_CODE();
683
686
688}
IDE_CHANNEL_STATE PciIdeGetChannelState(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel)
Definition: pata_generic.c:902
Referenced by PciIdeXFdoQueryBusRelations(), PciIdeXPdoQueryResourceRequirements(), and PciIdeXPdoQueryResources().
◆ PciIdeXPdoRemoveDevice()
| NTSTATUS PciIdeXPdoRemoveDevice | ( | _In_ PPDO_DEVICE_EXTENSION | PdoExtension, |
| _In_ PIRP | Irp, | ||
| _In_ BOOLEAN | FinalRemove | ||
| ) |
Definition at line 193 of file pdo.c.
197{
201
202 PAGED_CODE();
203
205
207 {
209
212
214
217
219 WasRemoved = TRUE;
220 }
221
224 {
227 }
228
229 if (!WasRemoved)
232}
static NTSTATUS PciIdeXPdoStopDevice(_In_ PPDO_DEVICE_EXTENSION PdoExt)
Definition: pdo.c:175
Definition: pci.h:82
Referenced by PciIdeXFdoRemoveDevice(), and PciIdeXPdoDispatchPnp().
◆ PciIdeXPnpQueryDeviceUsageNotification()
| NTSTATUS PciIdeXPnpQueryDeviceUsageNotification | ( | _In_ PCOMMON_DEVICE_EXTENSION | CommonExt, |
| _In_ PIRP | Irp | ||
| ) |
Definition at line 214 of file pciidex.c.
217{
218 PIO_STACK_LOCATION IoStack;
221
222 PAGED_CODE();
223
225 {
227 }
228 else
229 {
233 }
236
239 {
241 Counter = &CommonExt->PageFiles;
242 break;
243
245 Counter = &CommonExt->HibernateFiles;
246 break;
247
249 Counter = &CommonExt->DumpFiles;
250 break;
251
252 default:
254 }
255
257
259 IoInvalidateDeviceState(CommonExt->Self);
260
262}
NTSTATUS PciIdeXPnpRepeatRequest(_In_ PCOMMON_DEVICE_EXTENSION CommonExt, _In_ PIRP Irp, _In_opt_ PDEVICE_CAPABILITIES DeviceCapabilities)
Definition: pciidex.c:156
VOID NTAPI IoInvalidateDeviceState(IN PDEVICE_OBJECT DeviceObject)
Definition: pnpmgr.c:1847
struct _IO_STACK_LOCATION::@4454::@4487 UsageNotification
#define IoAdjustPagingPathCount(_Count, _Increment)
Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXPdoDispatchPnp().
◆ PciIdeXPnpQueryPnpDeviceState()
| NTSTATUS PciIdeXPnpQueryPnpDeviceState | ( | _In_ PCOMMON_DEVICE_EXTENSION | CommonExt, |
| _In_ PIRP | Irp | ||
| ) |
Definition at line 266 of file pciidex.c.
269{
270 PAGED_CODE();
271
272 if (CommonExt->PageFiles || CommonExt->HibernateFiles || CommonExt->DumpFiles)
274
277
279}
Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXPdoDispatchPnp().
◆ PciIdeXPnpRepeatRequest()
| NTSTATUS PciIdeXPnpRepeatRequest | ( | _In_ PCOMMON_DEVICE_EXTENSION | CommonExt, |
| _In_ PIRP | Irp, | ||
| _In_opt_ PDEVICE_CAPABILITIES | DeviceCapabilities | ||
| ) |
Definition at line 156 of file pciidex.c.
160{
162 PDEVICE_OBJECT TopDeviceObject;
163 PIO_STACK_LOCATION IoStack, SubStack;
164 PIRP SubIrp;
167
168 PAGED_CODE();
170
172
174 if (!SubIrp)
175 {
176 ObDereferenceObject(TopDeviceObject);
178 }
179
181
183 SubStack = IoGetNextIrpStackLocation(SubIrp);
185
188
189 IoSetCompletionRoutine(SubIrp,
191 &Event,
192 TRUE,
193 TRUE,
194 TRUE);
195
197
200 {
202 }
203
204 ObDereferenceObject(TopDeviceObject);
205
207 IoFreeIrp(SubIrp);
208
210}
#define IoSetCompletionRoutine(_Irp, _CompletionRoutine, _Context, _InvokeOnSuccess, _InvokeOnError, _InvokeOnCancel)
Definition: irp.cpp:490
_In_ PIOMMU_DEVICE_PATH _In_ PIOMMU_SVM_CAPABILITIES DeviceCapabilities
Definition: haltypes.h:1824
PDEVICE_OBJECT NTAPI IoGetAttachedDeviceReference(PDEVICE_OBJECT DeviceObject)
Definition: device.c:1407
PIRP NTAPI IoAllocateIrp(IN CCHAR StackSize, IN BOOLEAN ChargeQuota)
Definition: irp.c:615
IO_COMPLETION_ROUTINE PciIdeXPdoCompletionRoutine
Definition: pciidex.h:521
Definition: filtergraph.c:51
Definition: pci.h:44
Definition: env_spec_w32.h:413
struct _IO_STACK_LOCATION::@4454::@4481 DeviceCapabilities
Definition: Bus_PDO_EvalMethod.c:107
Definition: ketypes.h:863
__drv_aliasesMem FORCEINLINE PIO_STACK_LOCATION IoGetNextIrpStackLocation(_In_ PIRP Irp)
Definition: iofuncs.h:2695
Referenced by PciIdeXPdoQueryCapabilities(), and PciIdeXPnpQueryDeviceUsageNotification().
◆ PciRead()
| VOID PciRead | ( | _In_ PATA_CONTROLLER | Controller, |
| _Out_writes_bytes_all_(BufferLength) PVOID | Buffer, | ||
| _In_ ULONG | ConfigDataOffset, | ||
| _In_ ULONG | BufferLength | ||
| ) |
Definition at line 72 of file pciidex.c.
77{
78 Controller->GetBusData(Controller->BusInterfaceContext,
80 Buffer,
81 ConfigDataOffset,
82 BufferLength);
83}
_Must_inspect_result_ _In_ WDFDEVICE _In_ DEVICE_REGISTRY_PROPERTY _In_ ULONG BufferLength
Definition: wdfdevice.h:3777
Referenced by IntelInitChannel(), PciRead16(), PciRead32(), and PciRead8().
◆ PciRead16()
| FORCEINLINE USHORT PciRead16 | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | ConfigDataOffset | ||
| ) |
Definition at line 859 of file pciidex.h.
862{
864
867}
VOID PciRead(_In_ PATA_CONTROLLER Controller, _Out_writes_bytes_all_(BufferLength) PVOID Buffer, _In_ ULONG ConfigDataOffset, _In_ ULONG BufferLength)
Definition: pciidex.c:72
_At_(*)(_In_ PWSK_CLIENT Client, _In_opt_ PUNICODE_STRING NodeName, _In_opt_ PUNICODE_STRING ServiceName, _In_opt_ ULONG NameSpace, _In_opt_ GUID *Provider, _In_opt_ PADDRINFOEXW Hints, _Outptr_ PADDRINFOEXW *Result, _In_opt_ PEPROCESS OwningProcess, _In_opt_ PETHREAD OwningThread, _Inout_ PIRP Irp Result)(Mem)) NTSTATUS(WSKAPI *PFN_WSK_GET_ADDRESS_INFO
Definition: wsk.h:409
Referenced by AmdGetControllerProperties(), IntelInitChannel(), IntelPiixLegacySetTransferMode(), IntelPiixSetTransferMode(), PcTechControllerStart(), Sil680SetTransferMode(), and SvwSetTransferMode().
◆ PciRead32()
| FORCEINLINE ULONG PciRead32 | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | ConfigDataOffset | ||
| ) |
Definition at line 871 of file pciidex.h.
874{
876
879}
Referenced by AmdSetTransferMode(), IntelSchSetTransferMode(), Sil680SetTransferMode(), SvwSetTransferMode(), ToshibaSetTransferMode(), ViaPataGetControllerProperties(), ViaScrReadPci(), and ViaSetTransferMode().
◆ PciRead8()
| FORCEINLINE UCHAR PciRead8 | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | ConfigDataOffset | ||
| ) |
Definition at line 847 of file pciidex.h.
850{
852
855}
Referenced by AmdControllerStart(), AmdEnablePostedWriteBuffer(), AmdGetControllerProperties(), CmdChannelEnabledTest(), CmdCheckInterruptMrdMode(), CmdCheckInterruptPci(), CmdControllerStart(), CmdGetControllerProperties(), CmdSetTransferMode(), IntelInitChannel(), IntelPiixSetTransferMode(), PciIdeGetChannelState(), Sil680CheckInterrupt(), Sil680GetControllerProperties(), Sil680SetTransferMode(), SvwHasUdmaCable(), SvwPataControllerStart(), SvwSetTransferMode(), Via6410ControllerStart(), Via6421SetTransferMode(), ViaSataGetControllerProperties(), ViaSataSetTransferMode(), ViaScrReadPci(), and ViaSetTransferMode().
◆ PciWrite()
| VOID PciWrite | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_reads_bytes_(BufferLength) PVOID | Buffer, | ||
| _In_ ULONG | ConfigDataOffset, | ||
| _In_ ULONG | BufferLength | ||
| ) |
Definition at line 86 of file pciidex.c.
91{
92 Controller->SetBusData(Controller->BusInterfaceContext,
94 Buffer,
95 ConfigDataOffset,
96 BufferLength);
97}
Referenced by PciWrite16(), PciWrite32(), and PciWrite8().
◆ PciWrite16()
| FORCEINLINE VOID PciWrite16 | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | ConfigDataOffset, | ||
| _In_ USHORT | Value | ||
| ) |
Definition at line 893 of file pciidex.h.
897{
899}
VOID PciWrite(_In_ PATA_CONTROLLER Controller, _In_reads_bytes_(BufferLength) PVOID Buffer, _In_ ULONG ConfigDataOffset, _In_ ULONG BufferLength)
Definition: pciidex.c:86
Referenced by IntelPiixLegacyPrepareIo(), IntelPiixLegacySetTransferMode(), IntelPiixSetTransferMode(), PcTechControllerStart(), Sil680SetTransferMode(), and SvwSetTransferMode().
◆ PciWrite32()
| FORCEINLINE VOID PciWrite32 | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | ConfigDataOffset, | ||
| _In_ ULONG | Value | ||
| ) |
Definition at line 903 of file pciidex.h.
Referenced by AmdSetTransferMode(), IntelSchSetTransferMode(), Sil680SetTransferMode(), SvwSetTransferMode(), ToshibaSetTransferMode(), ViaScrWritePci(), and ViaSetTransferMode().
◆ PciWrite8()
| FORCEINLINE VOID PciWrite8 | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | ConfigDataOffset, | ||
| _In_ UCHAR | Value | ||
| ) |
Definition at line 883 of file pciidex.h.
Referenced by AmdControllerStart(), AmdEnablePostedWriteBuffer(), CmdCheckInterruptMrdMode(), CmdControllerStart(), CmdSetTransferMode(), IntelPiixSetTransferMode(), Sil680SetTransferMode(), SvwPataControllerStart(), SvwSetTransferMode(), Via6410ControllerStart(), Via6421SetTransferMode(), ViaSataSetTransferMode(), ViaScrWritePci(), and ViaSetTransferMode().
◆ PcTechGetControllerProperties()
| NTSTATUS PcTechGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 41 of file pctech.c.
43{
46
47 PAGED_CODE();
49
52
56
57 Controller->Start = PcTechControllerStart;
58
60 {
62
63 ChanData->ChanInfo &= ~CHANNEL_FLAG_IO32;
64 }
65
67}
static VOID PcTechControllerStart(_In_ PATA_CONTROLLER Controller)
Definition: pctech.c:29
Referenced by PciIdeGetControllerProperties().
◆ Sil680GetControllerProperties()
| NTSTATUS Sil680GetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 214 of file sil680.c.
216{
219
220 PAGED_CODE();
222
225
229
231 {
234
236 ChanData->SetTransferMode = Sil680SetTransferMode;
238
239 /* Check for 80-conductor cable */
242 {
244 ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
245 }
246 }
247
249}
static BOOLEAN Sil680CheckInterrupt(_In_ PCHANNEL_DATA_PATA ChanData)
Definition: sil680.c:202
static VOID Sil680SetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: sil680.c:71
_Must_inspect_result_ _In_ WDFDEVICE _In_ PWDF_CHILD_LIST_CONFIG Config
Definition: wdfchildlist.h:476
Referenced by PciIdeGetControllerProperties().
◆ SvwHasUdmaCable()
| BOOLEAN SvwHasUdmaCable | ( | _In_ PATA_CONTROLLER | Controller, |
| _In_ ULONG | Channel | ||
| ) |
Definition at line 213 of file svw_pata.c.
216{
217 UCHAR UdmaModeReg;
218
219 PAGED_CODE();
220
222
223 /* Check mode settings, see if UDMA3 or higher mode is active */
224 return ((UdmaModeReg & 0x07) > 2) || ((UdmaModeReg & 0x70) > 0x20);
225}
Referenced by AtiGetControllerProperties(), and SvwPataGetControllerProperties().
◆ SvwPataGetControllerProperties()
| NTSTATUS SvwPataGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 288 of file svw_pata.c.
290{
294
295 PAGED_CODE();
297
298 switch (Controller->Pci.DeviceID)
299 {
301 /* UDMA is supported but its use is discouraged */
303
304 No64KDma = TRUE;
305 break;
306
308 if (Controller->Pci.RevisionID < 0x92)
310 else
312 Controller->Flags |= CTRL_FLAG_DMA_INTERRUPT;
313 break;
314
317 Controller->MaxChannels = 1;
318 break;
319
322 break;
323
326 Controller->MaxChannels = 1;
327 No64KDma = TRUE;
328 break;
329
330 default:
332 }
333
337
338 Controller->Start = SvwPataControllerStart;
339
341 {
343
344 if (No64KDma)
345 ChanData->MaximumTransferLength = PCIIDE_PRD_LIMIT - 0x4000;
346
347 ChanData->SetTransferMode = SvwSetTransferMode;
348 ChanData->TransferModeSupported = SupportedMode;
349
350 /* Check for 80-conductor cable */
352 {
354 "assume 40-conductor cable\n",
355 ChanData->Channel);
356 ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
357 }
358 }
359
361}
static VOID SvwPataControllerStart(_In_ PATA_CONTROLLER Controller)
Definition: svw_pata.c:264
Referenced by PciIdeGetControllerProperties().
◆ SvwSataGetControllerProperties()
| NTSTATUS SvwSataGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 215 of file svw_sata.c.
217{
220 PUCHAR IoBase;
221
222 PAGED_CODE();
224
226 {
228
230 break;
231 }
234
236 Controller->MaxChannels = 8;
237 else
238 Controller->MaxChannels = 4;
239
240 Controller->Flags |= CTRL_FLAG_MANUAL_RES;
241
245
247 if (!IoBase)
249
250 /*
251 * Errata: Set SICR registers to turn off waiting for a status message
252 * before sending FIS, fixes some issues with Seagate hard drives.
253 */
256
257 /* Clear interrupts */
260
262 {
264
265 ChanData->TransferModeSupported = SATA_ALL;
266 ChanData->SetTransferMode = SataSetTransferMode;
267
269 ChanData->ChanInfo |= CHANNEL_FLAG_NO_ATAPI_DMA;
270
271 /*
272 * Errata: Enable the DMA engine before sending the drive command
273 * to avoid data corruption.
274 */
275 ChanData->ChanInfo |= CHANNEL_FLAG_DMA_BEFORE_CMD;
276
277 ChanData->ChanInfo |= CHANNEL_FLAG_NO_SLAVE;
284
286 }
287
289}
#define STATUS_DEVICE_CONFIGURATION_ERROR
Definition: ntstatus.h:713
PVOID AtaCtrlPciMapBar(_In_ PATA_CONTROLLER Controller, _In_range_(0, PCI_TYPE0_ADDRESSES) ULONG Index, _In_ ULONG MinimumIoLength)
Definition: fdo.c:249
static VOID SvwSataSaveTaskFile(_In_ PCHANNEL_DATA_PATA ChanData, _Inout_ PATA_DEVICE_REQUEST Request)
Definition: svw_sata.c:158
static VOID SvwSataLoadTaskFile(_In_ PCHANNEL_DATA_PATA ChanData, _In_ PATA_DEVICE_REQUEST Request)
Definition: svw_sata.c:124
static VOID SvwSataParseResources(_Inout_ PCHANNEL_DATA_PATA ChanData, _In_ PUCHAR IoBase, _In_ ULONG PortIndex)
Definition: svw_sata.c:193
static PCIIDEX_PAGED_DATA const struct @1176 SvwSataControllerList[]
static BOOLEAN SvwSataScrWrite(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ ULONG Value)
Definition: svw_sata.c:73
static BOOLEAN SvwSataScrRead(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ PULONG Result)
Definition: svw_sata.c:56
static UCHAR SvwSataReadStatus(_In_ PCHANNEL_DATA_PATA ChanData)
Definition: svw_sata.c:112
static ULONG SvwSataGetIoBarIndex(_In_ PATA_CONTROLLER Controller)
Definition: svw_sata.c:91
static BOOLEAN SvwSataCheckInterrupt(_In_ PCHANNEL_DATA_PATA ChanData)
Definition: svw_sata.c:99
Referenced by PciIdeGetControllerProperties().
◆ ToshibaGetControllerProperties()
| NTSTATUS ToshibaGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 102 of file toshiba.c.
104{
107
108 PAGED_CODE();
110
112 Controller->Pci.DeviceID != PCI_DEV_PICCOLO_2 &&
113 Controller->Pci.DeviceID != PCI_DEV_PICCOLO_3 &&
114 Controller->Pci.DeviceID != PCI_DEV_PICCOLO_5)
115 {
117 }
118
119 Controller->MaxChannels = 1;
120
124
126 {
128
130 ChanData->SetTransferMode = ToshibaSetTransferMode;
131 }
132
134}
static VOID ToshibaSetTransferMode(_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel, _In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
Definition: toshiba.c:58
Referenced by PciIdeGetControllerProperties().
◆ ViaClampTimings()
| VOID ViaClampTimings | ( | _Inout_ PATA_TIMING | Timing | ) |
Definition at line 165 of file via.c.
167{
168 Timing->AddressSetup = CLAMP_TIMING(Timing->AddressSetup, 1, 4) - 1;
169 Timing->CmdRecovery = CLAMP_TIMING(Timing->CmdRecovery, 1, 16) - 1;
170 Timing->CmdActive = CLAMP_TIMING(Timing->CmdActive, 1, 16) - 1;
171 Timing->DataRecovery = CLAMP_TIMING(Timing->DataRecovery, 1, 16) - 1;
172 Timing->DataActive = CLAMP_TIMING(Timing->DataActive, 1, 16) - 1;
173}
FORCEINLINE ATATIM CLAMP_TIMING(_In_ ATATIM Value, _In_ ATATIM Minimum, _In_ ATATIM Maximum)
Definition: pata.h:236
Referenced by AmdSetTransferMode(), Via6421SetTransferMode(), and ViaSetTransferMode().
◆ ViaGetControllerProperties()
| NTSTATUS ViaGetControllerProperties | ( | _Inout_ PATA_CONTROLLER | Controller | ) |
Definition at line 859 of file via.c.
861{
864
865 PAGED_CODE();
867
869 {
871 }
873 (Controller->Pci.DeviceID == PCI_DEV_CX700M2_IDE_SATA_RAID))
874 {
876 }
877
879 {
881
883 break;
884 }
887
889 Controller->MaxChannels = 1;
890
894
897
899}
static NTSTATUS Via6421GetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: via.c:536
static NTSTATUS ViaCx700GetControllerProperties(_Inout_ PATA_CONTROLLER Controller)
Definition: via.c:592
static NTSTATUS ViaPataGetControllerProperties(_Inout_ PATA_CONTROLLER Controller, _In_ ULONG HwFlags)
Definition: via.c:721
static NTSTATUS ViaSataGetControllerProperties(_Inout_ PATA_CONTROLLER Controller, _In_ ULONG HwFlags)
Definition: via.c:826
static PCIIDEX_PAGED_DATA const struct @1177 ViaControllerList[]
Referenced by PciIdeGetControllerProperties().
Variable Documentation
◆ AtaAhciAllocateSlot
| CHANNEL_ALLOCATE_SLOT AtaAhciAllocateSlot |
Definition at line 628 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaAhciEnableInterrupts
| CHANNEL_ENABLE_INTERRUPTS AtaAhciEnableInterrupts |
Definition at line 591 of file pciidex.h.
Referenced by AtaAhciCreateChannelData().
◆ AtaAhciEnumerateChannel
| CHANNEL_ENUMERATE_CHANNEL AtaAhciEnumerateChannel |
Definition at line 592 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaAhciHbaIsr
| KSERVICE_ROUTINE AtaAhciHbaIsr |
Definition at line 629 of file pciidex.h.
Referenced by AhciGetControllerProperties().
◆ AtaAhciIdentifyDevice
| CHANNEL_IDENTIFY_DEVICE AtaAhciIdentifyDevice |
Definition at line 593 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaAhciPrepareIo
| CHANNEL_PREPARE_IO AtaAhciPrepareIo |
Definition at line 626 of file pciidex.h.
Referenced by AtaAhciCreateChannelData().
◆ AtaAhciPreparePrdTable
| CHANNEL_PREPARE_PRD_TABLE AtaAhciPreparePrdTable |
Definition at line 627 of file pciidex.h.
Referenced by AtaAhciCreateChannelData().
◆ AtaAhciResetChannel
| CHANNEL_RESET_CHANNEL AtaAhciResetChannel |
Definition at line 594 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaAhciStartIo
| CHANNEL_START_IO AtaAhciStartIo |
Definition at line 625 of file pciidex.h.
Referenced by AtaAhciCreateChannelData().
◆ AtaCtrlAbortChannel
| CHANNEL_ABORT_CHANNEL AtaCtrlAbortChannel |
Definition at line 465 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaCtrlAttachChannel
| CONTROLLER_ATTACH_CHANNEL AtaCtrlAttachChannel |
Definition at line 455 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaCtrlDowngradeInterfaceSpeed
| CHANNEL_DOWNGRADE_INTERFACE_SPEED AtaCtrlDowngradeInterfaceSpeed |
Definition at line 464 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaCtrlGetInitTaskFile
| CHANNEL_GET_INIT_TASK_FILE AtaCtrlGetInitTaskFile |
Definition at line 461 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaCtrlSetDeviceData
| CHANNEL_SET_DEVICE_DATA AtaCtrlSetDeviceData |
Definition at line 458 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ AtaCtrlSetTransferMode
| CHANNEL_SET_MODE AtaCtrlSetTransferMode |
Definition at line 463 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ BusNumber
Definition at line 65 of file pciidex.h.
Referenced by AcpiHwGetPciDeviceInfo(), AcpiHwProcessPciList(), AddControllers(), AllocateAddressMapping(), AtapiFindDev(), AtapiFindListedDev(), BootTranslateBusAddress(), Bus_PDO_QueryResources(), CmpInitializeRegistryNode(), CmpSetupConfigurationTree(), CODE_SEG(), ConfigCallback(), FindBootDisplay(), FindBootDisplayFromLoaderARCTree(), FindBrokenController(), GetArcComponentInterface(), HalAssignSlotResources(), HalGetBusData(), HalGetBusDataByOffset(), HalGetInterruptVector(), HaliHandlerForBus(), HaliHandlerForConfigSpace(), HaliPciInterfaceReadConfig(), HaliReferenceHandlerForBus(), HaliReferenceHandlerForConfigSpace(), HaliRegisterBusHandler(), HaliTranslateBusAddress(), HalpAllocateBusHandler(), HalpAssignSlotResources(), HalpFindMatchingDebuggingDevice(), HalpGetCmosData(), HalpSetCmosData(), HalSetBusData(), HalSetBusDataByOffset(), HalTranslateBusAddress(), InitializeConfiguration(), IntelPciBridgeErrataMatch(), IntVideoPortEnumBusCallback(), IntVideoPortEnumBuses(), IntVideoPortFindAdapter(), IoQueryDeviceDescription(), IoTranslateBusAddress(), KdpSysReadBusData(), KdpSysReadIoSpace(), KdpSysWriteBusData(), KdpSysWriteIoSpace(), NdisOverrideBusNumber(), OslIsPciDevicePresent(), Pc98HwDetect(), PcHwDetect(), PciAllocateCmResourceList(), PciAllocateIoRequirementsList(), PciAssignSlotResources(), PciCacheLegacyDeviceRouting(), PciFindDevice(), PciFindPdoByLocation(), PciIdeXFdoQueryInterface(), PciIsDebuggingDevice(), PciLocateKdDevices(), PciTranslateBusAddress(), RegistryInitAdapterKey(), ScsiPortGetBusDataByOffset(), SpiGetPciConfigData(), SvwOsb4PciBridgeInit(), UefiHwDetect(), ViaQuerySouthBridgeInformation(), VidInitialize(), and XboxHwDetect().
◆ Channel
Definition at line 74 of file pciidex.h.
Referenced by AmdEnablePostedWriteBuffer(), AmdSetTransferMode(), AtapiCheckInterrupt__(), AtapiDmaDone(), AtapiDmaInit(), AtapiDmaStart(), AtapiInterrupt__(), AtapiResetController__(), BlasterCleanup(), ChanMgrChannelDestroy(), ChanMgrCloseChannel(), ChanMgrCloseChannelsWithFileObject(), ChanMgrCreateChannel(), ChanMgrGetByHandle(), ChanMgrGetChannelByName(), ChanMgrGetChannelCount(), ChanMgrGetChannelIndex(), ChanMgrIsUniqueName(), ChanMgrReleaseChannel(), ChannelClearRedrawEvent(), ChannelClose(), ChannelCreate(), ChannelDereferenceHandles(), ChannelDestroy(), ChannelGetApplicationType(), ChannelGetDescription(), ChannelGetFlags(), ChannelGetIndex(), ChannelGetName(), ChannelGetStatus(), ChannelHasNewIBufferData(), ChannelHasNewOBufferData(), ChannelHasRedrawEvent(), ChannelIBufferLength(), ChannelInitializeVTable(), ChannelIRead(), ChannelIReadLast(), ChannelIsActive(), ChannelIsClosed(), ChannelIsEqual(), ChannelIWrite(), ChannelOFlush(), ChannelOWrite(), ChannelSetDescription(), ChannelSetLockEvent(), ChannelSetName(), ChannelSetRedrawEvent(), ChannelSetStatus(), CmdChannelEnabledTest(), CmdSetTransferMode(), ConMgrAdvanceCurrentChannel(), ConMgrChannelClose(), ConMgrIsSacChannel(), ConMgrIsWriteEnabled(), ConMgrResetCurrentChannel(), ConMgrSetCurrentChannel(), DmaRequest(), EventDescCreate(), EventDescSetChannel(), FindDevices(), FindDmaDescriptor(), IdeMediaStatus(), IntelPiixChooseDeviceSpeed(), IntelPiixLegacySetTransferMode(), IntelPiixSetTransferMode(), IopFindDmaResource(), IsaConvertDmaRequirement(), IssueIdentify(), MMixerGetChannelCountLegacy(), MMixerSetGetControlDetails(), MMixerSetGetVolumeControlDetails(), MPU401Cleanup(), PciIdeChannelEnabled(), PciIdeGenericSetTransferMode(), PciIdeGetChannelState(), PciIdeXChannelState(), PciIdeXFdoQueryBusRelations(), PciIdeXGetChannelState(), PitDecrementCount(), PitGetReloadValue(), PitInitCounter(), PitLatchChannelCount(), PitLatchChannelStatus(), PitReadData(), PitSetGate(), PitSetOut(), PitSetOutFunction(), PitWriteCommand(), PitWriteData(), RawChannelCreate(), RawChannelDestroy(), RawChannelGetIBufferIndex(), RawChannelIBufferIsFull(), RawChannelIBufferLength(), RawChannelIRead(), RawChannelIReadLast(), RawChannelIWrite(), RawChannelOEcho(), RawChannelOFlush(), RawChannelORead(), RawChannelOWrite(), RawChannelOWrite2(), RawChannelSetIBufferIndex(), SataSetTransferMode(), SetDriveParameters(), Sil680SetTransferMode(), SvwChooseDeviceSpeed(), SvwHasUdmaCable(), SvwSetTransferMode(), ToshibaSetTransferMode(), UniataAhciStatus(), VDDQueryDMA(), VDDSetDMA(), Via6421SetTransferMode(), ViaSataSetTransferMode(), ViaSetTransferMode(), VTUTF8ChannelAnsiDispatch(), VTUTF8ChannelAssertCursor(), VTUTF8ChannelConsumeEscapeSequence(), VTUTF8ChannelCreate(), VTUTF8ChannelDestroy(), VTUTF8ChannelGetIBufferIndex(), VTUTF8ChannelIBufferIsFull(), VTUTF8ChannelIBufferLength(), VTUTF8ChannelIRead(), VTUTF8ChannelIReadLast(), VTUTF8ChannelIWrite(), VTUTF8ChannelOEcho(), VTUTF8ChannelOFlush(), VTUTF8ChannelOInit(), VTUTF8ChannelOWrite(), VTUTF8ChannelOWrite2(), VTUTF8ChannelProcessAttributes(), and VTUTF8ChannelSetIBufferIndex().
◆ DriverEntry
◆ InitSafeBootMode
◆ PataAllocateSlot
| CHANNEL_ALLOCATE_SLOT PataAllocateSlot |
Definition at line 698 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ PataChannelIsr
| KSERVICE_ROUTINE PataChannelIsr |
Definition at line 702 of file pciidex.h.
Referenced by PciIdeConnectInterrupt().
◆ PataEnumerateChannel
| CHANNEL_ENUMERATE_CHANNEL PataEnumerateChannel |
Definition at line 689 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ PataIdentifyDevice
| CHANNEL_IDENTIFY_DEVICE PataIdentifyDevice |
Definition at line 690 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ PataLoadTaskFile
| CHANNEL_LOAD_TASK_FILE PataLoadTaskFile |
Definition at line 705 of file pciidex.h.
Referenced by PciIdeCreateChannelData().
◆ PataPollingTimerDpc
| KDEFERRED_ROUTINE PataPollingTimerDpc |
Definition at line 708 of file pciidex.h.
Referenced by PciIdeCreateChannelData().
◆ PataPrepareIo
| CHANNEL_PREPARE_IO PataPrepareIo |
Definition at line 700 of file pciidex.h.
Referenced by IntelPiixLegacyPrepareIo(), and PciIdeCreateChannelData().
◆ PataReadStatus
| CHANNEL_READ_STATUS PataReadStatus |
Definition at line 707 of file pciidex.h.
Referenced by PciIdeCreateChannelData().
◆ PataResetChannel
| CHANNEL_RESET_CHANNEL PataResetChannel |
Definition at line 688 of file pciidex.h.
Referenced by PciIdeXQueryPciIdeInterface().
◆ PataSaveTaskFile
| CHANNEL_SAVE_TASK_FILE PataSaveTaskFile |
Definition at line 706 of file pciidex.h.
Referenced by PciIdeCreateChannelData().
◆ PataStartIo
| CHANNEL_START_IO PataStartIo |
Definition at line 701 of file pciidex.h.
Referenced by PciIdeCreateChannelData().
◆ PciConfig
| _In_ ULONG _In_ PCI_SLOT_NUMBER _In_ PPCI_COMMON_HEADER PciConfig |
Definition at line 67 of file pciidex.h.
Referenced by CheckPciDevice(), DcRecognizeHardware(), FdoEnumerateDevices(), FdoLocateChildDevice(), HalpAssignPCISlotResources(), HalpConfigureDebuggingDevice(), HalpFindMatchingDebuggingDevice(), HalpGetPCIData(), HalpMatchDebuggingDevice(), HalpSetPCIData(), IntelPciBridgeErrataMatch(), IntVideoPortGetLegacyResources(), MiniportInitialize(), NvNetRecognizeHardware(), OslIsPciDevicePresent(), PciFindDevice(), PdoQueryResourceRequirements(), PdoQueryResources(), SpiGetPciConfigData(), SvwOsb4PciBridgeInit(), USBPORT_StartDevice(), and ViaQuerySouthBridgeInformation().
◆ PciIdeAttachChannel
| CONTROLLER_ATTACH_CHANNEL_EX PciIdeAttachChannel |
Definition at line 636 of file pciidex.h.
Referenced by PciIdeXFdoStartDevice().
◆ PciIdeChannelIsr
| KSERVICE_ROUTINE PciIdeChannelIsr |
Definition at line 703 of file pciidex.h.
Referenced by PciIdeConnectInterrupt().
◆ PciIdeCheckInterrupt
| CHANNEL_CHECK_INTERRUPT PciIdeCheckInterrupt |
Definition at line 704 of file pciidex.h.
Referenced by PciIdeControllerInitDma().
◆ PciIdePreparePrdTable
| CHANNEL_PREPARE_PRD_TABLE PciIdePreparePrdTable |
Definition at line 699 of file pciidex.h.
Referenced by PciIdeCreateChannelData().
◆ PciIdeXAddDevice
| DRIVER_ADD_DEVICE PciIdeXAddDevice |
Definition at line 515 of file pciidex.h.
Referenced by PciIdeXInitialize().
◆ PciIdeXFdoRemoveDevice
| CONTROLLER_PNP_REMOVE_DEVICE PciIdeXFdoRemoveDevice |
Definition at line 471 of file pciidex.h.
Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXInitialize().
◆ PciIdeXFdoStartDevice
| CONTROLLER_PNP_START_DEVICE PciIdeXFdoStartDevice |
Definition at line 468 of file pciidex.h.
Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXInitialize().
◆ PciIdeXPdoCompletionRoutine
| IO_COMPLETION_ROUTINE PciIdeXPdoCompletionRoutine |
Definition at line 521 of file pciidex.h.
Referenced by _IRQL_requires_max_(), and PciIdeXPnpRepeatRequest().
◆ PciIdeXUnload
| DRIVER_UNLOAD PciIdeXUnload |
Definition at line 512 of file pciidex.h.
Referenced by PciIdeXInitialize().
◆ PciSlot
| _In_ ULONG _In_ PCI_SLOT_NUMBER PciSlot |
Definition at line 66 of file pciidex.h.
Referenced by HalpConfigureDebuggingDevice(), HalpDebugPciDumpBus(), HalpFindMatchingDebuggingDevice(), HalpGetISAFixedPCIIrq(), HalpGetPciBridgeConfig(), HalpInitializePciBus(), HalpMatchDebuggingDevice(), HalpPhase0GetPciDataByOffset(), HalpPhase0SetPciDataByOffset(), HalpRegisterPciDebuggingDeviceInfo(), HalpSetupPciDeviceForDebugging(), IntelPciBridgeErrataMatch(), PciFindDevice(), PciFindPdoByLocation(), PciLocateKdDevices(), PciScanBus(), SvwOsb4PciBridgeInit(), and ViaQuerySouthBridgeInformation().
◆ SataSetTransferMode
| CHANNEL_SET_MODE_EX SataSetTransferMode |
Definition at line 633 of file pciidex.h.
Referenced by AmdGetControllerProperties(), AtaAhciCreateChannelData(), IntelInitChannel(), SvwSataGetControllerProperties(), ViaCx700GetControllerProperties(), ViaSataGetControllerProperties(), and ViaSataSetTransferMode().
◆ SvwSetTransferMode
| CHANNEL_SET_MODE_EX SvwSetTransferMode |
Definition at line 813 of file pciidex.h.
Referenced by AtiGetControllerProperties(), and SvwPataGetControllerProperties().
