pciidex.h File Reference

#include <ntddk.h>
#include <ntstrsafe.h>
#include <ntintsafe.h>
#include <initguid.h>
#include <wdmguid.h>
#include <ata.h>
#include <ide.h>
#include <scsi.h>
#include <reactos/drivers/ata/ata_shared.h>
#include <reactos/drivers/ata/ata_user.h>
#include "debug.h"
#include "ahci.h"
#include <debug/driverdbg.h>
#include "pata.h"

Include dependency graph for pciidex.h:

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Go to the source code of this file.

Classes
struct	_ATA_PCI_ENABLE_BITS
struct	_ATA_CONTROLLER
struct	_CHANNEL_DATA_COMMON
struct	_CHANNEL_DATA_PATA
struct	_CHANNEL_INFO_AHCI
struct	_CHANNEL_DATA_AHCI
struct	_PCIIDEX_DRIVER_EXTENSION
struct	_COMMON_DEVICE_EXTENSION
struct	_FDO_DEVICE_EXTENSION
struct	_PDO_DEVICE_EXTENSION

Macros
#define	TAG_PCIIDEX   'XedI'
#define	ASSUME(cond)
#define	IS_FDO(p)    ((((PCOMMON_DEVICE_EXTENSION)(p))->Flags & DO_IS_FDO) != 0)
#define	IS_PRIMARY_CHANNEL(PdoExtension)   (PdoExtension->Channel == 0)
#define	PCIIDEX_PAGED_DATA   DATA_SEG("PAGECONS")
#define	MAX_CHANNELS   32
#define	PORT_TIMER_TICK_MS   10
#define	DEV_NUMBER(Device)   ((Device)->TransportFlags & DEVICE_NUMBER_MASK)
#define	RANGE_IS_VALID   0x01
#define	RANGE_IS_MEMORY   0x02
#define	RANGE_IS_MAPPED   0x04
#define	CTRL_FLAG_NATIVE_PCI   0x00000001
#define	CTRL_FLAG_IS_SIMPLEX   0x00000002
#define	CTRL_FLAG_SATA_HBA_ACPI   0x00000002
#define	CTRL_FLAG_USE_TEST_FUNCTION   0x00000004
#define	CTRL_FLAG_IS_AHCI   0x00000008
#define	CTRL_FLAG_NON_PNP   0x00000010
#define	CTRL_FLAG_MANUAL_RES   0x00000020
#define	CTRL_FLAG_DMA_INTERRUPT   0x00000040
#define	CHANNEL_FLAG_IO32   0x00000001
#define	CHANNEL_FLAG_DRIVE0_DMA_CAPABLE   0x00000002
#define	CHANNEL_FLAG_DRIVE1_DMA_CAPABLE   0x00000004
#define	CHANNEL_FLAG_CONTROL_PORT_BASE_MAPPED   0x00000008
#define	CHANNEL_FLAG_COMMAND_PORT_BASE_MAPPED   0x00000010
#define	CHANNEL_FLAG_DMA_PORT_BASE_MAPPED   0x00000020
#define	CHANNEL_FLAG_64_BIT_DMA   0x00000040
#define	CHANNEL_FLAG_PRIMARY_ADDRESS_CLAIMED   0x00000080
#define	CHANNEL_FLAG_SECONDARY_ADDRESS_CLAIMED   0x00000100
#define	CHANNEL_FLAG_PIO_VIA_DMA   0x00000200
#define	CHANNEL_FLAG_NO_SLAVE   0x00000400
#define	CHANNEL_FLAG_IS_EXTERNAL   0x00000800
#define	CHANNEL_FLAG_IS_PMP   0x00001000
#define	CHANNEL_FLAG_HAS_FBS   0x00002000
#define	CHANNEL_FLAG_FBS_ENABLED   0x00004000
#define	CHANNEL_FLAG_HAS_ACPI_GTM   0x00008000
#define	CHANNEL_FLAG_HAS_NCQ   0x00010000
#define	CHANNEL_FLAG_PIO_FOR_LBA48_XFER   0x00020000
#define	CHANNEL_FLAG_NO_ATAPI_DMA   0x00040000
#define	CHANNEL_FLAG_DMA_BEFORE_CMD   0x00080000
#define	CHANNEL_FLAG_MRES_TF   0x00100000
#define	CHANNEL_FLAG_MRES_DMA   0x00200000
#define	CHANNEL_FLAG_MRES_CTRL   0x00400000
#define	CHANNEL_FLAG_CBUS   0x80000000
#define	DO_IS_FDO   0x80000000
#define	PDO_FLAG_NOT_PRESENT   0x00000001
#define	PDO_FLAG_REPORTED_MISSING   0x00000002

Typedefs
typedef struct _CHANNEL_DATA_PATA	CHANNEL_DATA_PATA
typedef struct _CHANNEL_DATA_PATA *	PCHANNEL_DATA_PATA
typedef struct _CHANNEL_DATA_COMMON	CHANNEL_DATA_COMMON
typedef struct _CHANNEL_DATA_COMMON *	PCHANNEL_DATA_COMMON
typedef struct _PCIIDE_PRD_TABLE_ENTRY	PCIIDE_PRD_TABLE_ENTRY
typedef struct _PCIIDE_PRD_TABLE_ENTRY *	PPCIIDE_PRD_TABLE_ENTRY
typedef struct _PDO_DEVICE_EXTENSION	PDO_DEVICE_EXTENSION
typedef struct _PDO_DEVICE_EXTENSION *	PPDO_DEVICE_EXTENSION
typedef struct _ATA_CONTROLLER	ATA_CONTROLLER
typedef struct _ATA_CONTROLLER *	PATA_CONTROLLER
typedef ATA_PCI_MATCH_FN *	PATA_PCI_MATCH_FN
typedef CONTROLLER_CHANNEL_ENABLED *	PCONTROLLER_CHANNEL_ENABLED
typedef CONTROLLER_START *	PCONTROLLER_START
typedef CONTROLLER_STOP *	PCONTROLLER_STOP
typedef VOID()	CONTROLLER_FREE_RESOURCES(_In_ PATA_CONTROLLER Controller)
typedef CONTROLLER_FREE_RESOURCES *	PCONTROLLER_FREE_RESOURCES
typedef NTSTATUS()	CONTROLLER_ATTACH_CHANNEL_EX(_In_ PVOID ChannelContext, _In_ BOOLEAN Attach)
typedef CONTROLLER_ATTACH_CHANNEL_EX *	PCONTROLLER_ATTACH_CHANNEL_EX
typedef CHANNEL_SET_MODE_EX *	PCHANNEL_SET_MODE_EX
typedef NTSTATUS()	CHANNEL_ALLOCATE_MEMORY(_In_ PVOID ChannelContext)
typedef CHANNEL_ALLOCATE_MEMORY *	PCHANNEL_ALLOCATE_MEMORY
typedef VOID()	CHANNEL_FREE_MEMORY(_In_ PVOID ChannelContext)
typedef CHANNEL_FREE_MEMORY *	PCHANNEL_FREE_MEMORY
typedef VOID()	CHANNEL_ENABLE_INTERRUPTS(_In_ PVOID ChannelContext, _In_ BOOLEAN Enable)
typedef CHANNEL_ENABLE_INTERRUPTS *	PCHANNEL_ENABLE_INTERRUPTS
typedef BOOLEAN()	CHANNEL_CHECK_INTERRUPT(_In_ PCHANNEL_DATA_PATA ChanData)
typedef CHANNEL_CHECK_INTERRUPT *	PCHANNEL_CHECK_INTERRUPT
typedef VOID()	CHANNEL_LOAD_TASK_FILE(_In_ PCHANNEL_DATA_PATA ChanData, _In_ PATA_DEVICE_REQUEST Request)
typedef CHANNEL_LOAD_TASK_FILE *	PCHANNEL_LOAD_TASK_FILE
typedef VOID()	CHANNEL_SAVE_TASK_FILE(_In_ PCHANNEL_DATA_PATA ChanData, _Inout_ PATA_DEVICE_REQUEST Request)
typedef CHANNEL_SAVE_TASK_FILE *	PCHANNEL_SAVE_TASK_FILE
typedef UCHAR()	CHANNEL_READ_STATUS(_In_ PCHANNEL_DATA_PATA ChanData)
typedef CHANNEL_READ_STATUS *	PCHANNEL_READ_STATUS
typedef BOOLEAN()	CHANNEL_READ_SCR(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ PULONG Result)
typedef CHANNEL_READ_SCR *	PCHANNEL_READ_SCR
typedef BOOLEAN()	CHANNEL_WRITE_SCR(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ ULONG Value)
typedef CHANNEL_WRITE_SCR *	PCHANNEL_WRITE_SCR
typedef struct _ATA_PCI_ENABLE_BITS	ATA_PCI_ENABLE_BITS
typedef struct _ATA_PCI_ENABLE_BITS *	PATA_PCI_ENABLE_BITS
typedef struct _CHANNEL_INFO_AHCI	CHANNEL_INFO_AHCI
typedef struct _CHANNEL_INFO_AHCI *	PCHANNEL_INFO_AHCI
typedef struct _CHANNEL_DATA_AHCI	CHANNEL_DATA_AHCI
typedef struct _CHANNEL_DATA_AHCI *	PCHANNEL_DATA_AHCI
typedef struct _PCIIDEX_DRIVER_EXTENSION	PCIIDEX_DRIVER_EXTENSION
typedef struct _PCIIDEX_DRIVER_EXTENSION *	PPCIIDEX_DRIVER_EXTENSION
typedef struct _COMMON_DEVICE_EXTENSION	COMMON_DEVICE_EXTENSION
typedef struct _COMMON_DEVICE_EXTENSION *	PCOMMON_DEVICE_EXTENSION
typedef struct _FDO_DEVICE_EXTENSION	FDO_DEVICE_EXTENSION
typedef struct _FDO_DEVICE_EXTENSION *	PFDO_DEVICE_EXTENSION

Functions
	_IRQL_requires_max_ (APC_LEVEL) typedef BOOLEAN(ATA_PCI_MATCH_FN)(_In_ PVOID Context
	_IRQL_requires_max_ (DISPATCH_LEVEL) typedef VOID(CONTROLLER_START)(_In_ PATA_CONTROLLER Controller)
	_IRQL_requires_ (DISPATCH_LEVEL) typedef VOID(CHANNEL_SET_MODE_EX)(_In_ PATA_CONTROLLER Controller
_In_ ULONG	_In_reads_ (MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList)
VOID	AtaWritePortUchar (_In_ PUCHAR Port, _In_ UCHAR Value, _In_ ULONG MmioFlags)
BOOLEAN	AtaAcpiGetTimingMode (_In_ PDEVICE_OBJECT DeviceObject, _Out_ PIDE_ACPI_TIMING_MODE_BLOCK TimingMode)
NTSTATUS	AtaAcpiSetTimingMode (_In_ PDEVICE_OBJECT DeviceObject, _In_ PIDE_ACPI_TIMING_MODE_BLOCK TimingMode, _In_opt_ PIDENTIFY_DEVICE_DATA IdBlock1, _In_opt_ PIDENTIFY_DEVICE_DATA IdBlock2)
PVOID	AtaAcpiGetTaskFile (_In_ PDEVICE_OBJECT DeviceObject)
VOID	AtaAcpiSetDeviceData (_In_ PDEVICE_OBJECT DeviceObject, _In_ PIDENTIFY_DEVICE_DATA IdBlock)
DECLSPEC_NOINLINE_FROM_PAGED VOID	AtaChanEnableInterruptsSync (_In_ PVOID ChannelContext, _In_ BOOLEAN Enable)
PVOID	AtaCtrlPciMapBar (_In_ PATA_CONTROLLER Controller, _In_range_(0, PCI_TYPE0_ADDRESSES) ULONG Index, _In_ ULONG MinimumIoLength)
IDE_CHANNEL_STATE	PciIdeXGetChannelState (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel)
NTSTATUS	PciIdeXFdoDispatchPnp (_In_ PFDO_DEVICE_EXTENSION FdoExtension, _Inout_ PIRP Irp)
IDE_CHANNEL_STATE	PciIdeXChannelState (_In_ PFDO_DEVICE_EXTENSION FdoExtension, _In_ ULONG Channel)
NTSTATUS NTAPI	PciIdexGetBusLocation (_In_ PVOID DeviceExtension, _Out_ PULONG BusLocation)
	_Dispatch_type_ (IRP_MJ_SYSTEM_CONTROL) DRIVER_DISPATCH_PAGED PciIdeXDispatchWmi
BOOLEAN	PciFindDevice (_In_ __callback PATA_PCI_MATCH_FN MatchFunction, _In_ PVOID Context)
VOID	PciRead (_In_ PATA_CONTROLLER Controller, _Out_writes_bytes_all_(BufferLength) PVOID Buffer, _In_ ULONG ConfigDataOffset, _In_ ULONG BufferLength)
VOID	PciWrite (_In_ PATA_CONTROLLER Controller, _In_reads_bytes_(BufferLength) PVOID Buffer, _In_ ULONG ConfigDataOffset, _In_ ULONG BufferLength)
VOID	AtaSleep (VOID)
NTSTATUS	PciIdeXPnpRepeatRequest (_In_ PCOMMON_DEVICE_EXTENSION CommonExt, _In_ PIRP Irp, _In_opt_ PDEVICE_CAPABILITIES DeviceCapabilities)
NTSTATUS	PciIdeXPnpQueryDeviceUsageNotification (_In_ PCOMMON_DEVICE_EXTENSION CommonExt, _In_ PIRP Irp)
NTSTATUS	PciIdeXPnpQueryPnpDeviceState (_In_ PCOMMON_DEVICE_EXTENSION CommonExt, _In_ PIRP Irp)
	_Dispatch_type_ (IRP_MJ_PNP) DRIVER_DISPATCH_PAGED PciIdeXDispatchPnp
NTSTATUS	PciIdeXPdoRemoveDevice (_In_ PPDO_DEVICE_EXTENSION PdoExtension, _In_ PIRP Irp, _In_ BOOLEAN FinalRemove)
	_Dispatch_type_ (IRP_MJ_POWER) DRIVER_DISPATCH_RAISED PciIdeXDispatchPower
NTSTATUS	AhciGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
VOID	AtaAhciStopDma (_In_ PCHANNEL_DATA_AHCI ChanData)
VOID	AtaAhciSaveTaskFile (_In_ PCHANNEL_DATA_AHCI ChanData, _Inout_ PATA_DEVICE_REQUEST Request, _In_ BOOLEAN ProcessErrorStatus)
VOID	AtaAhciHandleFatalError (_In_ PCHANNEL_DATA_AHCI ChanData)
VOID	AtaAhciHandlePortStateChange (_In_ PCHANNEL_DATA_AHCI ChanData, _In_ ULONG InterruptStatus)
BOOLEAN	AtaAhciDowngradeInterfaceSpeed (_In_ PCHANNEL_DATA_AHCI ChanData)
ULONG	AtaAhciChannelGetMaximumDeviceCount (_In_ PVOID ChannelContext)
VOID	AtaSelectTimings (_In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *DeviceList, _Out_writes_all_(MAX_IDE_DEVICE) PATA_TIMING Timings, _In_range_(>, 0) ULONG ClockPeriodPs, _In_ ULONG Flags)
VOID	PciIdeInitTaskFileIoResources (_In_ PCHANNEL_DATA_PATA ChanData, _In_ ULONG_PTR CommandPortBase, _In_ ULONG_PTR ControlPortBase, _In_ ULONG CommandBlockSpare)
IDE_CHANNEL_STATE	PciIdeGetChannelState (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel)
NTSTATUS	PciIdeParseResources (_In_ PCHANNEL_DATA_PATA ChanData, _In_ PCM_RESOURCE_LIST ResourcesTranslated)
VOID	PciIdeFreeResources (_In_ PVOID ChannelContext)
NTSTATUS	PciIdeConnectInterrupt (_In_ PVOID ChannelContext)
NTSTATUS	PciIdeCreateChannelData (_In_ PATA_CONTROLLER Controller, _In_ ULONG HwExtensionSize)
NTSTATUS	PciIdeGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
ULONG	PataChannelGetMaximumDeviceCount (_In_ PVOID ChannelContext)
VOID	AtaWriteBlock16 (_In_ PUSHORT Port, _In_ PUSHORT Buffer, _In_ ULONG Count, _In_ ULONG MmioFlags)
VOID	AtaReadBlock16 (_In_ PUSHORT Port, _In_ PUSHORT Buffer, _In_ ULONG Count, _In_ ULONG MmioFlags)
VOID	AtaWriteBlock32 (_In_ PULONG Port, _In_ PULONG Buffer, _In_ ULONG Count, _In_ ULONG MmioFlags)
VOID	AtaReadBlock32 (_In_ PULONG Port, _In_ PULONG Buffer, _In_ ULONG Count, _In_ ULONG MmioFlags)
UCHAR	AtaReadPortUchar (_In_ PUCHAR Port, _In_ ULONG MmioFlags)
VOID	AtaWritePortUlong (_In_ PULONG Port, _In_ ULONG Value, _In_ ULONG MmioFlags)
VOID	PciIdeDmaStop (_In_ PCHANNEL_DATA_PATA ChanData)
NTSTATUS	AmdGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	AtiGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	CmdGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	HptGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	Sil680GetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	IntelGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	PcTechGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	SvwPataGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	SvwSataGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	ToshibaGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
NTSTATUS	ViaGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)
BOOLEAN	SvwHasUdmaCable (_In_ PATA_CONTROLLER Controller, _In_ ULONG Channel)
VOID	ViaClampTimings (_Inout_ PATA_TIMING Timing)
FORCEINLINE ULONG	CountSetBits (_In_ ULONG x)
FORCEINLINE BOOLEAN	IsPowerOfTwo (_In_ ULONG x)
FORCEINLINE UCHAR	PciRead8 (_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
FORCEINLINE USHORT	PciRead16 (_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
FORCEINLINE ULONG	PciRead32 (_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset)
FORCEINLINE VOID	PciWrite8 (_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset, _In_ UCHAR Value)
FORCEINLINE VOID	PciWrite16 (_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset, _In_ USHORT Value)
FORCEINLINE VOID	PciWrite32 (_In_ PATA_CONTROLLER Controller, _In_ ULONG ConfigDataOffset, _In_ ULONG Value)

Variables
_In_ ULONG	BusNumber
_In_ ULONG _In_ PCI_SLOT_NUMBER	PciSlot
_In_ ULONG _In_ PCI_SLOT_NUMBER _In_ PPCI_COMMON_HEADER	PciConfig
_In_ ULONG	Channel
NTSYSAPI ULONG	InitSafeBootMode
CONTROLLER_ATTACH_CHANNEL	AtaCtrlAttachChannel
CHANNEL_SET_DEVICE_DATA	AtaCtrlSetDeviceData
CHANNEL_GET_INIT_TASK_FILE	AtaCtrlGetInitTaskFile
CHANNEL_SET_MODE	AtaCtrlSetTransferMode
CHANNEL_DOWNGRADE_INTERFACE_SPEED	AtaCtrlDowngradeInterfaceSpeed
CHANNEL_ABORT_CHANNEL	AtaCtrlAbortChannel
CONTROLLER_PNP_START_DEVICE	PciIdeXFdoStartDevice
CONTROLLER_PNP_REMOVE_DEVICE	PciIdeXFdoRemoveDevice
DRIVER_INITIALIZE	DriverEntry
DRIVER_UNLOAD	PciIdeXUnload
DRIVER_ADD_DEVICE	PciIdeXAddDevice
IO_COMPLETION_ROUTINE	PciIdeXPdoCompletionRoutine
CHANNEL_ENABLE_INTERRUPTS	AtaAhciEnableInterrupts
CHANNEL_ENUMERATE_CHANNEL	AtaAhciEnumerateChannel
CHANNEL_IDENTIFY_DEVICE	AtaAhciIdentifyDevice
CHANNEL_RESET_CHANNEL	AtaAhciResetChannel
CHANNEL_START_IO	AtaAhciStartIo
CHANNEL_PREPARE_IO	AtaAhciPrepareIo
CHANNEL_PREPARE_PRD_TABLE	AtaAhciPreparePrdTable
CHANNEL_ALLOCATE_SLOT	AtaAhciAllocateSlot
KSERVICE_ROUTINE	AtaAhciHbaIsr
CHANNEL_SET_MODE_EX	SataSetTransferMode
CHANNEL_SET_MODE_EX	PciIdeGenericSetTransferMode
CONTROLLER_ATTACH_CHANNEL_EX	PciIdeAttachChannel
CHANNEL_RESET_CHANNEL	PataResetChannel
CHANNEL_ENUMERATE_CHANNEL	PataEnumerateChannel
CHANNEL_IDENTIFY_DEVICE	PataIdentifyDevice
CHANNEL_ALLOCATE_SLOT	PataAllocateSlot
CHANNEL_PREPARE_PRD_TABLE	PciIdePreparePrdTable
CHANNEL_PREPARE_IO	PataPrepareIo
CHANNEL_START_IO	PataStartIo
KSERVICE_ROUTINE	PataChannelIsr
KSERVICE_ROUTINE	PciIdeChannelIsr
CHANNEL_CHECK_INTERRUPT	PciIdeCheckInterrupt
CHANNEL_LOAD_TASK_FILE	PataLoadTaskFile
CHANNEL_SAVE_TASK_FILE	PataSaveTaskFile
CHANNEL_READ_STATUS	PataReadStatus
KDEFERRED_ROUTINE	PataPollingTimerDpc
CHANNEL_SET_MODE_EX	SvwSetTransferMode

Macro Definition Documentation

ASSUME

#define ASSUME

(

cond

)

Value:

    do { \
        ASSERT(cond); \
        __assume(cond); \
    } while (0)

Definition at line 34 of file pciidex.h.

CHANNEL_FLAG_64_BIT_DMA

#define CHANNEL_FLAG_64_BIT_DMA   0x00000040

Definition at line 267 of file pciidex.h.

CHANNEL_FLAG_CBUS

#define CHANNEL_FLAG_CBUS   0x80000000

Definition at line 284 of file pciidex.h.

CHANNEL_FLAG_COMMAND_PORT_BASE_MAPPED

#define CHANNEL_FLAG_COMMAND_PORT_BASE_MAPPED   0x00000010

Definition at line 265 of file pciidex.h.

CHANNEL_FLAG_CONTROL_PORT_BASE_MAPPED

#define CHANNEL_FLAG_CONTROL_PORT_BASE_MAPPED   0x00000008

Definition at line 264 of file pciidex.h.

CHANNEL_FLAG_DMA_BEFORE_CMD

#define CHANNEL_FLAG_DMA_BEFORE_CMD   0x00080000

Definition at line 280 of file pciidex.h.

CHANNEL_FLAG_DMA_PORT_BASE_MAPPED

#define CHANNEL_FLAG_DMA_PORT_BASE_MAPPED   0x00000020

Definition at line 266 of file pciidex.h.

CHANNEL_FLAG_DRIVE0_DMA_CAPABLE

#define CHANNEL_FLAG_DRIVE0_DMA_CAPABLE   0x00000002

Definition at line 262 of file pciidex.h.

CHANNEL_FLAG_DRIVE1_DMA_CAPABLE

#define CHANNEL_FLAG_DRIVE1_DMA_CAPABLE   0x00000004

Definition at line 263 of file pciidex.h.

CHANNEL_FLAG_FBS_ENABLED

#define CHANNEL_FLAG_FBS_ENABLED   0x00004000

Definition at line 275 of file pciidex.h.

CHANNEL_FLAG_HAS_ACPI_GTM

#define CHANNEL_FLAG_HAS_ACPI_GTM   0x00008000

Definition at line 276 of file pciidex.h.

CHANNEL_FLAG_HAS_FBS

#define CHANNEL_FLAG_HAS_FBS   0x00002000

Definition at line 274 of file pciidex.h.

CHANNEL_FLAG_HAS_NCQ

#define CHANNEL_FLAG_HAS_NCQ   0x00010000

Definition at line 277 of file pciidex.h.

CHANNEL_FLAG_IO32

#define CHANNEL_FLAG_IO32   0x00000001

Definition at line 261 of file pciidex.h.

CHANNEL_FLAG_IS_EXTERNAL

#define CHANNEL_FLAG_IS_EXTERNAL   0x00000800

Definition at line 272 of file pciidex.h.

CHANNEL_FLAG_IS_PMP

#define CHANNEL_FLAG_IS_PMP   0x00001000

Definition at line 273 of file pciidex.h.

CHANNEL_FLAG_MRES_CTRL

#define CHANNEL_FLAG_MRES_CTRL   0x00400000

Definition at line 283 of file pciidex.h.

CHANNEL_FLAG_MRES_DMA

#define CHANNEL_FLAG_MRES_DMA   0x00200000

Definition at line 282 of file pciidex.h.

CHANNEL_FLAG_MRES_TF

#define CHANNEL_FLAG_MRES_TF   0x00100000

Definition at line 281 of file pciidex.h.

CHANNEL_FLAG_NO_ATAPI_DMA

#define CHANNEL_FLAG_NO_ATAPI_DMA   0x00040000

Definition at line 279 of file pciidex.h.

CHANNEL_FLAG_NO_SLAVE

#define CHANNEL_FLAG_NO_SLAVE   0x00000400

Definition at line 271 of file pciidex.h.

CHANNEL_FLAG_PIO_FOR_LBA48_XFER

#define CHANNEL_FLAG_PIO_FOR_LBA48_XFER   0x00020000

Definition at line 278 of file pciidex.h.

CHANNEL_FLAG_PIO_VIA_DMA

#define CHANNEL_FLAG_PIO_VIA_DMA   0x00000200

Definition at line 270 of file pciidex.h.

CHANNEL_FLAG_PRIMARY_ADDRESS_CLAIMED

#define CHANNEL_FLAG_PRIMARY_ADDRESS_CLAIMED   0x00000080

Definition at line 268 of file pciidex.h.

CHANNEL_FLAG_SECONDARY_ADDRESS_CLAIMED

#define CHANNEL_FLAG_SECONDARY_ADDRESS_CLAIMED   0x00000100

Definition at line 269 of file pciidex.h.

CTRL_FLAG_DMA_INTERRUPT

#define CTRL_FLAG_DMA_INTERRUPT   0x00000040

Definition at line 231 of file pciidex.h.

CTRL_FLAG_IS_AHCI

#define CTRL_FLAG_IS_AHCI   0x00000008

Definition at line 228 of file pciidex.h.

CTRL_FLAG_IS_SIMPLEX

#define CTRL_FLAG_IS_SIMPLEX   0x00000002

Definition at line 225 of file pciidex.h.

CTRL_FLAG_MANUAL_RES

#define CTRL_FLAG_MANUAL_RES   0x00000020

Definition at line 230 of file pciidex.h.

CTRL_FLAG_NATIVE_PCI

#define CTRL_FLAG_NATIVE_PCI   0x00000001

Definition at line 224 of file pciidex.h.

CTRL_FLAG_NON_PNP

#define CTRL_FLAG_NON_PNP   0x00000010

Definition at line 229 of file pciidex.h.

CTRL_FLAG_SATA_HBA_ACPI

#define CTRL_FLAG_SATA_HBA_ACPI   0x00000002

Definition at line 226 of file pciidex.h.

CTRL_FLAG_USE_TEST_FUNCTION

#define CTRL_FLAG_USE_TEST_FUNCTION   0x00000004

Definition at line 227 of file pciidex.h.

DEV_NUMBER

#define DEV_NUMBER

(

Device

)

((Device)->TransportFlags & DEVICE_NUMBER_MASK)

Definition at line 56 of file pciidex.h.

DO_IS_FDO

#define DO_IS_FDO   0x80000000

Definition at line 380 of file pciidex.h.

IS_FDO

#define IS_FDO

(

p

)

((((PCOMMON_DEVICE_EXTENSION)(p))->Flags & DO_IS_FDO) != 0)

Definition at line 40 of file pciidex.h.

IS_PRIMARY_CHANNEL

#define IS_PRIMARY_CHANNEL

(

PdoExtension

)

(PdoExtension->Channel == 0)

Definition at line 43 of file pciidex.h.

MAX_CHANNELS

#define MAX_CHANNELS   32

Definition at line 52 of file pciidex.h.

PCIIDEX_PAGED_DATA

#define PCIIDEX_PAGED_DATA   DATA_SEG("PAGECONS")

Pageable read-only data

Definition at line 50 of file pciidex.h.

PDO_FLAG_NOT_PRESENT

#define PDO_FLAG_NOT_PRESENT   0x00000001

Definition at line 410 of file pciidex.h.

PDO_FLAG_REPORTED_MISSING

#define PDO_FLAG_REPORTED_MISSING   0x00000002

Definition at line 411 of file pciidex.h.

PORT_TIMER_TICK_MS

#define PORT_TIMER_TICK_MS   10

Definition at line 54 of file pciidex.h.

RANGE_IS_MAPPED

#define RANGE_IS_MAPPED   0x04

Definition at line 192 of file pciidex.h.

RANGE_IS_MEMORY

#define RANGE_IS_MEMORY   0x02

Definition at line 191 of file pciidex.h.

RANGE_IS_VALID

#define RANGE_IS_VALID   0x01

Definition at line 190 of file pciidex.h.

TAG_PCIIDEX

#define TAG_PCIIDEX   'XedI'

Definition at line 32 of file pciidex.h.

Typedef Documentation

ATA_CONTROLLER

typedef struct _ATA_CONTROLLER ATA_CONTROLLER

Definition at line 59 of file pciidex.h.

ATA_PCI_ENABLE_BITS

typedef struct _ATA_PCI_ENABLE_BITS ATA_PCI_ENABLE_BITS

CHANNEL_ALLOCATE_MEMORY

typedef NTSTATUS() CHANNEL_ALLOCATE_MEMORY(_In_ PVOID ChannelContext)

Definition at line 108 of file pciidex.h.

CHANNEL_CHECK_INTERRUPT

typedef BOOLEAN() CHANNEL_CHECK_INTERRUPT(_In_ PCHANNEL_DATA_PATA ChanData)

Definition at line 124 of file pciidex.h.

CHANNEL_DATA_AHCI

typedef struct _CHANNEL_DATA_AHCI CHANNEL_DATA_AHCI

CHANNEL_DATA_COMMON

typedef struct _CHANNEL_DATA_COMMON CHANNEL_DATA_COMMON

Definition at line 29 of file pciidex.h.

CHANNEL_DATA_PATA

typedef struct _CHANNEL_DATA_PATA CHANNEL_DATA_PATA

Definition at line 28 of file pciidex.h.

CHANNEL_ENABLE_INTERRUPTS

typedef VOID() CHANNEL_ENABLE_INTERRUPTS(_In_ PVOID ChannelContext, _In_ BOOLEAN Enable)

Definition at line 118 of file pciidex.h.

CHANNEL_FREE_MEMORY

typedef VOID() CHANNEL_FREE_MEMORY(_In_ PVOID ChannelContext)

Definition at line 113 of file pciidex.h.

CHANNEL_INFO_AHCI

typedef struct _CHANNEL_INFO_AHCI CHANNEL_INFO_AHCI

CHANNEL_LOAD_TASK_FILE

typedef VOID() CHANNEL_LOAD_TASK_FILE(_In_ PCHANNEL_DATA_PATA ChanData, _In_ PATA_DEVICE_REQUEST Request)

Definition at line 129 of file pciidex.h.

CHANNEL_READ_SCR

typedef BOOLEAN() CHANNEL_READ_SCR(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ PULONG Result)

Definition at line 146 of file pciidex.h.

CHANNEL_READ_STATUS

typedef UCHAR() CHANNEL_READ_STATUS(_In_ PCHANNEL_DATA_PATA ChanData)

Definition at line 141 of file pciidex.h.

CHANNEL_SAVE_TASK_FILE

typedef VOID() CHANNEL_SAVE_TASK_FILE(_In_ PCHANNEL_DATA_PATA ChanData, _Inout_ PATA_DEVICE_REQUEST Request)

Definition at line 135 of file pciidex.h.

CHANNEL_WRITE_SCR

typedef BOOLEAN() CHANNEL_WRITE_SCR(_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ ULONG Value)

Definition at line 154 of file pciidex.h.

COMMON_DEVICE_EXTENSION

typedef struct _COMMON_DEVICE_EXTENSION COMMON_DEVICE_EXTENSION

CONTROLLER_ATTACH_CHANNEL_EX

typedef NTSTATUS() CONTROLLER_ATTACH_CHANNEL_EX(_In_ PVOID ChannelContext, _In_ BOOLEAN Attach)

Definition at line 94 of file pciidex.h.

CONTROLLER_FREE_RESOURCES

typedef VOID() CONTROLLER_FREE_RESOURCES(_In_ PATA_CONTROLLER Controller)

Definition at line 89 of file pciidex.h.

FDO_DEVICE_EXTENSION

typedef struct _FDO_DEVICE_EXTENSION FDO_DEVICE_EXTENSION

PATA_CONTROLLER

typedef struct _ATA_CONTROLLER * PATA_CONTROLLER

Definition at line 59 of file pciidex.h.

PATA_PCI_ENABLE_BITS

typedef struct _ATA_PCI_ENABLE_BITS * PATA_PCI_ENABLE_BITS

PATA_PCI_MATCH_FN

typedef ATA_PCI_MATCH_FN* PATA_PCI_MATCH_FN

Definition at line 68 of file pciidex.h.

PCHANNEL_ALLOCATE_MEMORY

typedef CHANNEL_ALLOCATE_MEMORY* PCHANNEL_ALLOCATE_MEMORY

Definition at line 111 of file pciidex.h.

PCHANNEL_CHECK_INTERRUPT

typedef CHANNEL_CHECK_INTERRUPT* PCHANNEL_CHECK_INTERRUPT

Definition at line 127 of file pciidex.h.

PCHANNEL_DATA_AHCI

typedef struct _CHANNEL_DATA_AHCI * PCHANNEL_DATA_AHCI

PCHANNEL_DATA_COMMON

typedef struct _CHANNEL_DATA_COMMON * PCHANNEL_DATA_COMMON

Definition at line 29 of file pciidex.h.

PCHANNEL_DATA_PATA

typedef struct _CHANNEL_DATA_PATA * PCHANNEL_DATA_PATA

Definition at line 28 of file pciidex.h.

PCHANNEL_ENABLE_INTERRUPTS

typedef CHANNEL_ENABLE_INTERRUPTS* PCHANNEL_ENABLE_INTERRUPTS

Definition at line 122 of file pciidex.h.

PCHANNEL_FREE_MEMORY

typedef CHANNEL_FREE_MEMORY* PCHANNEL_FREE_MEMORY

Definition at line 116 of file pciidex.h.

PCHANNEL_INFO_AHCI

typedef struct _CHANNEL_INFO_AHCI * PCHANNEL_INFO_AHCI

PCHANNEL_LOAD_TASK_FILE

typedef CHANNEL_LOAD_TASK_FILE* PCHANNEL_LOAD_TASK_FILE

Definition at line 133 of file pciidex.h.

PCHANNEL_READ_SCR

typedef CHANNEL_READ_SCR* PCHANNEL_READ_SCR

Definition at line 152 of file pciidex.h.

PCHANNEL_READ_STATUS

typedef CHANNEL_READ_STATUS* PCHANNEL_READ_STATUS

Definition at line 144 of file pciidex.h.

PCHANNEL_SAVE_TASK_FILE

typedef CHANNEL_SAVE_TASK_FILE* PCHANNEL_SAVE_TASK_FILE

Definition at line 139 of file pciidex.h.

PCHANNEL_SET_MODE_EX

typedef CHANNEL_SET_MODE_EX* PCHANNEL_SET_MODE_EX

Definition at line 106 of file pciidex.h.

PCHANNEL_WRITE_SCR

typedef CHANNEL_WRITE_SCR* PCHANNEL_WRITE_SCR

Definition at line 160 of file pciidex.h.

PCIIDE_PRD_TABLE_ENTRY

typedef struct _PCIIDE_PRD_TABLE_ENTRY PCIIDE_PRD_TABLE_ENTRY

Definition at line 30 of file pciidex.h.

PCIIDEX_DRIVER_EXTENSION

typedef struct _PCIIDEX_DRIVER_EXTENSION PCIIDEX_DRIVER_EXTENSION

PCOMMON_DEVICE_EXTENSION

typedef struct _COMMON_DEVICE_EXTENSION * PCOMMON_DEVICE_EXTENSION

PCONTROLLER_ATTACH_CHANNEL_EX

typedef CONTROLLER_ATTACH_CHANNEL_EX* PCONTROLLER_ATTACH_CHANNEL_EX

Definition at line 98 of file pciidex.h.

PCONTROLLER_CHANNEL_ENABLED

typedef CONTROLLER_CHANNEL_ENABLED* PCONTROLLER_CHANNEL_ENABLED

Definition at line 75 of file pciidex.h.

PCONTROLLER_FREE_RESOURCES

typedef CONTROLLER_FREE_RESOURCES* PCONTROLLER_FREE_RESOURCES

Definition at line 92 of file pciidex.h.

PCONTROLLER_START

typedef CONTROLLER_START* PCONTROLLER_START

Definition at line 81 of file pciidex.h.

PCONTROLLER_STOP

typedef CONTROLLER_STOP* PCONTROLLER_STOP

Definition at line 87 of file pciidex.h.

PDO_DEVICE_EXTENSION

typedef struct _PDO_DEVICE_EXTENSION PDO_DEVICE_EXTENSION

Definition at line 58 of file pciidex.h.

PFDO_DEVICE_EXTENSION

typedef struct _FDO_DEVICE_EXTENSION * PFDO_DEVICE_EXTENSION

PPCIIDE_PRD_TABLE_ENTRY

typedef struct _PCIIDE_PRD_TABLE_ENTRY * PPCIIDE_PRD_TABLE_ENTRY

Definition at line 30 of file pciidex.h.

PPCIIDEX_DRIVER_EXTENSION

typedef struct _PCIIDEX_DRIVER_EXTENSION * PPCIIDEX_DRIVER_EXTENSION

PPDO_DEVICE_EXTENSION

typedef struct _PDO_DEVICE_EXTENSION * PPDO_DEVICE_EXTENSION

Definition at line 58 of file pciidex.h.

Function Documentation

_Dispatch_type_() [1/3]

_Dispatch_type_

(

IRP_MJ_PNP

)

Definition at line 1331 of file isapnp.c.

{
    PIO_STACK_LOCATION IrpSp = IoGetCurrentIrpStackLocation(Irp);
    PISAPNP_COMMON_EXTENSION DevExt = DeviceObject->DeviceExtension;
 
    PAGED_CODE();
 
    if (DevExt->Signature == IsaPnpBus)
        return IsaFdoPnp((PISAPNP_FDO_EXTENSION)DevExt, Irp, IrpSp);
    else
        return IsaPdoPnp((PISAPNP_PDO_EXTENSION)DevExt, Irp, IrpSp);
}

_Dispatch_type_() [2/3]

_Dispatch_type_

(

IRP_MJ_POWER

)

Definition at line 1293 of file isapnp.c.

{
    PISAPNP_COMMON_EXTENSION DevExt = DeviceObject->DeviceExtension;
    NTSTATUS Status;
 
    if (DevExt->Signature != IsaPnpBus)
    {
        switch (IoGetCurrentIrpStackLocation(Irp)->MinorFunction)
        {
            case IRP_MN_SET_POWER:
            case IRP_MN_QUERY_POWER:
                Status = STATUS_SUCCESS;
                Irp->IoStatus.Status = Status;
                break;
 
            default:
                Status = Irp->IoStatus.Status;
                break;
        }
 
        PoStartNextPowerIrp(Irp);
        IoCompleteRequest(Irp, IO_NO_INCREMENT);
        return Status;
    }
 
    PoStartNextPowerIrp(Irp);
    IoSkipCurrentIrpStackLocation(Irp);
    return PoCallDriver(((PISAPNP_FDO_EXTENSION)DevExt)->Ldo, Irp);
}

_Dispatch_type_() [3/3]

_Dispatch_type_

(

IRP_MJ_SYSTEM_CONTROL

)

Definition at line 5748 of file btrfs.c.

                                                                                              {
    NTSTATUS Status;
    device_extension* Vcb = DeviceObject->DeviceExtension;
    bool top_level;
 
    FsRtlEnterFileSystem();
 
    top_level = is_top_level(Irp);
 
    Irp->IoStatus.Information = 0;
 
    if (Vcb && Vcb->type == VCB_TYPE_VOLUME) {
        volume_device_extension* vde = DeviceObject->DeviceExtension;
 
        IoSkipCurrentIrpStackLocation(Irp);
 
        Status = IoCallDriver(vde->attached_device, Irp);
 
        goto exit;
    } else if (Vcb && Vcb->type == VCB_TYPE_FS) {
        IoSkipCurrentIrpStackLocation(Irp);
 
        Status = IoCallDriver(Vcb->Vpb->RealDevice, Irp);
 
        goto exit;
    } else if (Vcb && Vcb->type == VCB_TYPE_BUS) {
        bus_device_extension* bde = DeviceObject->DeviceExtension;
 
        IoSkipCurrentIrpStackLocation(Irp);
 
        Status = IoCallDriver(bde->attached_device, Irp);
 
        goto exit;
    }
 
    Status = Irp->IoStatus.Status;
    IoCompleteRequest(Irp, IO_NO_INCREMENT);
 
exit:
    if (top_level)
        IoSetTopLevelIrp(NULL);
 
    FsRtlExitFileSystem();
 
    return Status;
}

_In_reads_()

_In_ ULONG _In_reads_

(

MAX_IDE_DEVICE

)

_IRQL_requires_()

_IRQL_requires_

(

DISPATCH_LEVEL

)

_IRQL_requires_max_() [1/2]

_IRQL_requires_max_

(

APC_LEVEL

)

Definition at line 37 of file cddata.c.

{
    THREAD_CONTEXT ThreadContext = {0};
    PIRP_CONTEXT IrpContext = NULL;
    BOOLEAN Wait;
 
#ifdef CD_SANITY
    PVOID PreviousTopLevel;
#endif
 
    NTSTATUS Status;
 
#if DBG
 
    KIRQL SaveIrql = KeGetCurrentIrql();
 
#endif
 
    ASSERT_OPTIONAL_IRP( Irp );
 
    UNREFERENCED_PARAMETER( DeviceObject );
 
    FsRtlEnterFileSystem();
 
#ifdef CD_SANITY
    PreviousTopLevel = IoGetTopLevelIrp();
#endif
 
    //
    //  Loop until this request has been completed or posted.
    //
 
    do {
 
        //
        //  Use a try-except to handle the exception cases.
        //
 
        _SEH2_TRY {
 
            //
            //  If the IrpContext is NULL then this is the first pass through
            //  this loop.
            //
 
            if (IrpContext == NULL) {
 
                //
                //  Decide if this request is waitable an allocate the IrpContext.
                //  If the file object in the stack location is NULL then this
                //  is a mount which is always waitable.  Otherwise we look at
                //  the file object flags.
                //
 
                if (IoGetCurrentIrpStackLocation( Irp )->FileObject == NULL) {
 
                    Wait = TRUE;
 
                } else {
 
                    Wait = CanFsdWait( Irp );
                }
 
                IrpContext = CdCreateIrpContext( Irp, Wait );
 
                //
                //  Update the thread context information.
                //
 
                CdSetThreadContext( IrpContext, &ThreadContext );
 
#ifdef CD_SANITY
                NT_ASSERT( !CdTestTopLevel ||
                        SafeNodeType( IrpContext->TopLevel ) == CDFS_NTC_IRP_CONTEXT );
#endif
 
            //
            //  Otherwise cleanup the IrpContext for the retry.
            //
 
            } else {
 
                //
                //  Set the MORE_PROCESSING flag to make sure the IrpContext
                //  isn't inadvertently deleted here.  Then cleanup the
                //  IrpContext to perform the retry.
                //
 
                SetFlag( IrpContext->Flags, IRP_CONTEXT_FLAG_MORE_PROCESSING );
                CdCleanupIrpContext( IrpContext, FALSE );
            }
 
            //
            //  Case on the major irp code.
            //
 
            switch (IrpContext->MajorFunction) {
 
            case IRP_MJ_CREATE :
 
                Status = CdCommonCreate( IrpContext, Irp );
                break;
 
            case IRP_MJ_CLOSE :
 
                Status = CdCommonClose( IrpContext, Irp );
                break;
 
            case IRP_MJ_READ :
 
                //
                //  If this is an Mdl complete request, don't go through
                //  common read.
                //
 
                if (FlagOn( IrpContext->MinorFunction, IRP_MN_COMPLETE )) {
 
                    Status = CdCompleteMdl( IrpContext, Irp );
 
                } else {
 
                    Status = CdCommonRead( IrpContext, Irp );
                }
 
                break;
 
            case IRP_MJ_WRITE :
 
                Status = CdCommonWrite( IrpContext, Irp );
                break;
 
            case IRP_MJ_QUERY_INFORMATION :
 
                Status = CdCommonQueryInfo( IrpContext, Irp );
                break;
 
            case IRP_MJ_SET_INFORMATION :
 
                Status = CdCommonSetInfo( IrpContext, Irp );
                break;
 
            case IRP_MJ_QUERY_VOLUME_INFORMATION :
 
                Status = CdCommonQueryVolInfo( IrpContext, Irp );
                break;
 
            case IRP_MJ_DIRECTORY_CONTROL :
 
                Status = CdCommonDirControl( IrpContext, Irp );
                break;
 
            case IRP_MJ_FILE_SYSTEM_CONTROL :
 
                Status = CdCommonFsControl( IrpContext, Irp );
                break;
 
            case IRP_MJ_DEVICE_CONTROL :
 
                Status = CdCommonDevControl( IrpContext, Irp );
                break;
 
            case IRP_MJ_LOCK_CONTROL :
 
                Status = CdCommonLockControl( IrpContext, Irp );
                break;
 
            case IRP_MJ_CLEANUP :
 
                Status = CdCommonCleanup( IrpContext, Irp );
                break;
 
            case IRP_MJ_PNP :
 
                Status = CdCommonPnp( IrpContext, Irp );
                break;
 
            case IRP_MJ_SHUTDOWN :
 
                Status = CdCommonShutdown( IrpContext, Irp );
                break;
 
            default :
 
                Status = STATUS_INVALID_DEVICE_REQUEST;
                CdCompleteRequest( IrpContext, Irp, Status );
            }
 
        } _SEH2_EXCEPT( CdExceptionFilter( IrpContext, _SEH2_GetExceptionInformation() )) {
 
            Status = CdProcessException( IrpContext, Irp, _SEH2_GetExceptionCode() );
        } _SEH2_END;
 
    } while (Status == STATUS_CANT_WAIT);
 
#ifdef CD_SANITY
    NT_ASSERT( !CdTestTopLevel ||
            (PreviousTopLevel == IoGetTopLevelIrp()) );
#endif
 
    FsRtlExitFileSystem();
 
    NT_ASSERT( SaveIrql == KeGetCurrentIrql( ));
 
    return Status;
}

_IRQL_requires_max_() [2/2]

_IRQL_requires_max_

(

DISPATCH_LEVEL

)

Priority 1 to 3, forwarded to the HCD's EvtEndpointSetCharacteristic.

Definition at line 3557 of file common.c.

{
    NTSTATUS                    status;
    BOOLEAN                     requestSent = FALSE;
 
    BOOLEAN                     shouldRetry = TRUE;
    PCDB                        cdb = (PCDB)DeviceExtension->PowerContext.Srb.Cdb;
    ULONG                       timeoutValue = DeviceExtension->TimeOutValue;
    ULONG                       retryCount = 1;
 
    // reset some fields.
    DeviceExtension->PowerContext.RetryIntervalIn100ns = 0;
    status = PowerContextReuseRequest(DeviceExtension);
    RequestClearSendTime(DeviceExtension->PowerContext.PowerRequest);
 
    if (!NT_SUCCESS(status))
    {
        return status;
    }
 
    // set proper timeout value and max retry count.
    switch(DeviceExtension->PowerContext.PowerChangeState.PowerDown)
    {
    case PowerDownDeviceInitial:
    case PowerDownDeviceQuiesced:
    case PowerDownDeviceStopped:
        break;
 
    case PowerDownDeviceLocked:
        // Case of issuing SYNC CACHE command. Do not use power irp timeout remaining time in this case
        // as we want to give best try on SYNC CACHE command.
        retryCount = MAXIMUM_RETRIES;
        timeoutValue = DeviceExtension->TimeOutValue;
        break;
 
    case PowerDownDeviceFlushed:
    {
        // Case of issuing STOP UNIT command
        // As "Imme" bit is set to '1', this command should be completed in short time.
        // This command is at low importance, failure of this command has very small impact.
        ULONG secondsRemaining = 0;
 
#if (WINVER >= 0x0601)
        // this API is introduced in Windows7
        PoQueryWatchdogTime(DeviceExtension->LowerPdo, &secondsRemaining);
#endif
 
        if (secondsRemaining == 0)
        {
            // not able to retrieve remaining time from PoQueryWatchdogTime API, use default values.
            retryCount = MAXIMUM_RETRIES;
            timeoutValue = SCSI_CDROM_TIMEOUT;
        }
        else
        {
            // plan to leave about 30 seconds to lower level drivers if possible.
            if (secondsRemaining >= 32)
            {
                retryCount = (secondsRemaining - 30)/SCSI_CDROM_TIMEOUT + 1;
                timeoutValue = SCSI_CDROM_TIMEOUT;
 
                if (retryCount > MAXIMUM_RETRIES)
                {
                    retryCount = MAXIMUM_RETRIES;
                }
 
                if (retryCount == 1)
                {
                    timeoutValue = secondsRemaining - 30;
                }
            }
            else
            {
                // issue the command with minimal timeout value and do not retry on it.
                retryCount = 1;
                timeoutValue = 2;
            }
        }
    }
        break;
    default:
        NT_ASSERT( FALSE );
        status = STATUS_NOT_IMPLEMENTED;
        return status;
    }
 
    DeviceExtension->PowerContext.RetryCount = retryCount;
 
    // issue command.
    while (shouldRetry)
    {
 
        // set SRB fields.
        DeviceExtension->PowerContext.Srb.SrbFlags = SRB_FLAGS_NO_DATA_TRANSFER |
                                                     SRB_FLAGS_DISABLE_SYNCH_TRANSFER |
                                                     SRB_FLAGS_NO_QUEUE_FREEZE |
                                                     SRB_FLAGS_BYPASS_LOCKED_QUEUE |
                                                     SRB_FLAGS_D3_PROCESSING;
 
        DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_EXECUTE_SCSI;
        DeviceExtension->PowerContext.Srb.TimeOutValue = timeoutValue;
 
        if (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceInitial)
        {
            DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_LOCK_QUEUE;
        }
        else if (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceLocked)
        {
            DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_QUIESCE_DEVICE;
        }
        else if (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceQuiesced)
        {
            // Case of issuing SYNC CACHE command.
            DeviceExtension->PowerContext.Srb.CdbLength = 10;
            cdb->SYNCHRONIZE_CACHE10.OperationCode = SCSIOP_SYNCHRONIZE_CACHE;
        }
        else if (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceFlushed)
        {
            // Case of issuing STOP UNIT command.
            DeviceExtension->PowerContext.Srb.CdbLength = 6;
            cdb->START_STOP.OperationCode = SCSIOP_START_STOP_UNIT;
            cdb->START_STOP.Start = 0;
            cdb->START_STOP.Immediate = 1;
        }
        else if (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceStopped)
        {
            DeviceExtension->PowerContext.Srb.Function = SRB_FUNCTION_UNLOCK_QUEUE;
        }
 
        // Set up completion routine and context if requested
        if (CompletionRoutine)
        {
            WdfRequestSetCompletionRoutine(DeviceExtension->PowerContext.PowerRequest,
                                           CompletionRoutine,
                                           Context);
        }
 
        status = RequestSend(DeviceExtension,
                             DeviceExtension->PowerContext.PowerRequest,
                             DeviceExtension->IoTarget,
                             CompletionRoutine ? 0 : WDF_REQUEST_SEND_OPTION_SYNCHRONOUS,
                             &requestSent);
 
        if (requestSent)
        {
            if ((CompletionRoutine == NULL) &&
                (SRB_STATUS(DeviceExtension->PowerContext.Srb.SrbStatus) != SRB_STATUS_SUCCESS))
            {
                TracePrint((TRACE_LEVEL_ERROR,
                            TRACE_FLAG_POWER,
                            "%p\tError occured when issuing %s command to device. Srb %p, Status %x\n",
                            DeviceExtension->PowerContext.PowerRequest,
                            (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceQuiesced) ? "SYNC CACHE" : "STOP UNIT",
                            &DeviceExtension->PowerContext.Srb,
                            DeviceExtension->PowerContext.Srb.SrbStatus));
 
                NT_ASSERT(!(TEST_FLAG(DeviceExtension->PowerContext.Srb.SrbStatus, SRB_STATUS_QUEUE_FROZEN)));
 
                shouldRetry = RequestSenseInfoInterpret(DeviceExtension,
                                                        DeviceExtension->PowerContext.PowerRequest,
                                                        &(DeviceExtension->PowerContext.Srb),
                                                        retryCount - DeviceExtension->PowerContext.RetryCount,
                                                        &status,
                                                        &(DeviceExtension->PowerContext.RetryIntervalIn100ns));
 
                if (shouldRetry && (DeviceExtension->PowerContext.RetryCount-- == 0))
                {
                    shouldRetry = FALSE;
                }
            }
            else
            {
                // succeeded, do not need to retry.
                shouldRetry = FALSE;
            }
 
        }
        else
        {
            // request failed to be sent
            shouldRetry = FALSE;
        }
 
        if (shouldRetry)
        {
            LARGE_INTEGER t;
            t.QuadPart = -DeviceExtension->PowerContext.RetryIntervalIn100ns;
            KeDelayExecutionThread(KernelMode, FALSE, &t);
 
            status = PowerContextReuseRequest(DeviceExtension);
            if (!NT_SUCCESS(status))
            {
                shouldRetry = FALSE;
            }
        }
    }
 
    if (DeviceExtension->PowerContext.PowerChangeState.PowerDown == PowerDownDeviceQuiesced)
    {
        // record SYNC CACHE command completion time stamp.
        KeQueryTickCount(&DeviceExtension->PowerContext.Step1CompleteTime);
    }
 
    return status;
}

AhciGetControllerProperties()

NTSTATUS AhciGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 625 of file ahci_generic.c.

{
    PCM_PARTIAL_RESOURCE_DESCRIPTOR InterruptDesc = &Controller->InterruptDesc;
    ULONG i, GlobalControl;
    NTSTATUS Status;
 
    PAGED_CODE();
 
    if (!AhciMatchController(Controller))
        return STATUS_NO_MATCH;
 
    if (Controller->InterruptDesc.Type != CmResourceTypeInterrupt)
    {
        ERR("No interrupt resource\n");
        return STATUS_INSUFFICIENT_RESOURCES;
    }
 
    Controller->IoBase = AtaAhciGetAbar(Controller);
    if (!Controller->IoBase)
        return STATUS_NO_MATCH; // Try IDE/RAID
 
    Controller->Flags |= CTRL_FLAG_IS_AHCI | CTRL_FLAG_SATA_HBA_ACPI;
    Controller->Start = AtaAhciHbaStart;
    Controller->Stop = AtaAhciHbaStop;
    Controller->FreeResources = AtaAhciHbaFreeResouces;
    Controller->AttachChannel = AtaAhciAttachChannel;
 
    /* Set AE before accessing other AHCI registers */
    GlobalControl = AHCI_HBA_READ(Controller->IoBase, HbaGlobalControl);
    GlobalControl |= AHCI_GHC_AE;
    AHCI_HBA_WRITE(Controller->IoBase, HbaGlobalControl, GlobalControl);
 
    Controller->AhciCapabilities = AHCI_HBA_READ(Controller->IoBase, HbaCapabilities);
    Controller->ChannelBitmap = AHCI_HBA_READ(Controller->IoBase, HbaPortBitmap);
    Controller->MaxChannels = CountSetBits(Controller->ChannelBitmap);
    if (Controller->MaxChannels == 0)
    {
        ASSERT(Controller->MaxChannels == 0);
        return STATUS_DEVICE_HARDWARE_ERROR;
    }
 
    Controller->AhciVersion = AHCI_HBA_READ(Controller->IoBase, HbaAhciVersion);
    if (Controller->AhciVersion >= AHCI_VERSION_1_2)
    {
        Controller->AhciCapabilitiesEx = AHCI_HBA_READ(Controller->IoBase, HbaCapabilitiesEx);
 
        if (Controller->AhciCapabilitiesEx & AHCI_CAP2_BOH)
            AtaAhciHbaRequestOsOwnership(Controller->IoBase);
    }
 
    /* Reset the HBA into a consistent state */
    GlobalControl = AHCI_HBA_READ(Controller->IoBase, HbaGlobalControl);
    GlobalControl |= AHCI_GHC_HR;
    AHCI_HBA_WRITE(Controller->IoBase, HbaGlobalControl, GlobalControl);
 
    /* HBA reset may take up to 1 second */
    for (i = 100000; i > 0; i--)
    {
        GlobalControl = AHCI_HBA_READ(Controller->IoBase, HbaGlobalControl);
        if (!(GlobalControl & AHCI_GHC_HR))
            break;
 
        KeStallExecutionProcessor(10);
    }
    if (i == 0)
    {
        ERR("HBA reset failed %08lx\n", GlobalControl);
        return STATUS_IO_TIMEOUT;
    }
 
    /* Re-enable AE */
    GlobalControl |= AHCI_GHC_AE;
    AHCI_HBA_WRITE(Controller->IoBase, HbaGlobalControl, GlobalControl);
 
    /* Disable interrupts */
    GlobalControl = AHCI_HBA_READ(Controller->IoBase, HbaGlobalControl);
    if (GlobalControl & AHCI_GHC_IE)
    {
        GlobalControl &= ~AHCI_GHC_IE;
        AHCI_HBA_WRITE(Controller->IoBase, HbaGlobalControl, GlobalControl);
    }
 
#if DBG
    /* On virtual machines, this will allow us to test the PMP support code */
    if (AtaAhciIsVbox())
        Controller->AhciCapabilities |= AHCI_CAP_SPM;
#endif
 
    Status = AtaAhciCreateChannelData(Controller);
    if (!NT_SUCCESS(Status))
        return Status;
 
    Controller->QueueDepth = ((Controller->AhciCapabilities & AHCI_CAP_NCS) >> 8) + 1;
 
    INFO("%04X:%04X.%02X: Ver %08lX, PI %08lX, CAP %08lX, CAP2 %08lX\n",
         Controller->Pci.VendorID,
         Controller->Pci.DeviceID,
         Controller->Pci.RevisionID,
         Controller->AhciVersion,
         Controller->ChannelBitmap,
         Controller->AhciCapabilities,
         Controller->AhciCapabilitiesEx);
 
    /* Clear HBA interrupts */
    AHCI_HBA_WRITE(Controller->IoBase, HbaInterruptStatus, 0xFFFFFFFF);
 
    Status = IoConnectInterrupt(&Controller->InterruptObject,
                                AtaAhciHbaIsr,
                                Controller,
                                NULL,
                                InterruptDesc->u.Interrupt.Vector,
                                InterruptDesc->u.Interrupt.Level,
                                InterruptDesc->u.Interrupt.Level,
                                (InterruptDesc->Flags & CM_RESOURCE_INTERRUPT_LATCHED)
                                ? Latched : LevelSensitive,
                                (InterruptDesc->ShareDisposition == CmResourceShareShared),
                                InterruptDesc->u.Interrupt.Affinity,
                                FALSE);
    if (!NT_SUCCESS(Status))
    {
        ERR("Could not connect to interrupt %lu, status 0x%lx\n",
            InterruptDesc->u.Interrupt.Vector, Status);
        return Status;
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeXFdoStartDevice().

AmdGetControllerProperties()

NTSTATUS AmdGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 329 of file amd.c.

{
    NTSTATUS Status;
    ULONG i, HwFlags, SupportedMode;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_AMD || Controller->Pci.VendorID == PCI_VEN_NVIDIA);
 
    for (i = 0; i < RTL_NUMBER_OF(AmdControllerList); ++i)
    {
        HwFlags = AmdControllerList[i].Flags;
 
        if ((Controller->Pci.VendorID == AmdControllerList[i].VendorID) &&
            (Controller->Pci.DeviceID == AmdControllerList[i].DeviceID))
        {
            break;
        }
    }
    if (i == RTL_NUMBER_OF(AmdControllerList))
        return STATUS_NO_MATCH;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    if (HwFlags & HW_FLAGS_SATA)
    {
        SupportedMode = SATA_ALL;
    }
    else
    {
        SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_ALL;
 
        if (HwFlags & HW_FLAGS_CHECK_SYSBOARD)
        {
            if (Controller->Pci.SubSystemID == PCI_SUBSYSTEM_AMD_SERENADE)
                SupportedMode &= ~UDMA_MODE6;
        }
        else
        {
            if (HwFlags & HW_FLAGS_UDMA5)
                SupportedMode &= ~UDMA_MODE6;
            else if (HwFlags & HW_FLAGS_UDMA4)
                SupportedMode &= ~UDMA_MODES(5, 6);
        }
 
        if (Controller->Pci.VendorID == PCI_VEN_AMD)
        {
            Controller->ChannelEnableBits = AmdEnableBits;
            Controller->Start = AmdControllerStart;
        }
        else
        {
            Controller->ChannelEnableBits = NvEnableBits;
        }
    }
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->HwFlags = HwFlags;
        ChanData->TransferModeSupported = SupportedMode;
 
        if (HwFlags & HW_FLAGS_SATA)
        {
            ChanData->ChanInfo |= CHANNEL_FLAG_NO_SLAVE;
            ChanData->SetTransferMode = SataSetTransferMode;
        }
        else
        {
            ChanData->SetTransferMode = AmdSetTransferMode;
 
            /* Check for 80-conductor cable */
            if (Controller->Pci.VendorID == PCI_VEN_AMD)
            {
                UCHAR ConfigReg = PciRead8(Controller, AMD_REG_CONFIG_CR(AMD_CONFIG_BASE));
 
                if (!(ConfigReg & AMD_REG_CONFIG_CR(i)))
                {
                    INFO("CH %lu: BIOS detected 40-conductor cable\n", i);
                    ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
                }
            }
            else
            {
                USHORT UdmaTimReg = PciRead16(Controller, AMD_REG_UDMA(NV_CONFIG_BASE, i));
 
                if (!NvHasUdmaCable(UdmaTimReg, 0) && !NvHasUdmaCable(UdmaTimReg, 1))
                {
                    INFO("CH %lu: BIOS hasn't selected mode faster than UDMA 2, "
                         "assume 40-conductor cable\n",
                         ChanData->Channel);
                    ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
                }
            }
        }
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

AtaAcpiGetTaskFile()

PVOID AtaAcpiGetTaskFile

(

_In_ PDEVICE_OBJECT

DeviceObject

)

Definition at line 233 of file acpi.c.

{
    ACPI_EVAL_INPUT_BUFFER InputBuffer;
    PACPI_EVAL_OUTPUT_BUFFER OutputBuffer;
    ULONG RetryCount, OutputSize;
    NTSTATUS Status;
 
    PAGED_CODE();
    /*
     * We invoke this routine within the PnP START handler only,
     * and thus specify that the code is in a pageable section.
     */
    ASSERT(PsGetCurrentProcess() == PsInitialSystemProcess);
 
    InputBuffer.MethodNameAsUlong = 'FTG_'; // _GTF
    InputBuffer.Signature = ACPI_EVAL_INPUT_BUFFER_SIGNATURE;
 
    /*
     * The output buffer must be large enough to hold the list of ATA commands to the drive.
     * We assume that 10 commands is the common case.
     */
    OutputSize = FIELD_OFFSET(ACPI_EVAL_OUTPUT_BUFFER, Argument) +
                 ACPI_METHOD_ARGUMENT_LENGTH(sizeof(ATA_ACPI_TASK_FILE) * 10);
 
    for (RetryCount = 0; RetryCount < 2; ++RetryCount)
    {
        OutputBuffer = ExAllocatePoolZero(NonPagedPool, OutputSize, TAG_PCIIDEX);
        if (!OutputBuffer)
        {
            ERR("Failed to allocate memory of size %lu\n", OutputSize);
            return NULL;
        }
 
        /* Evaluate the _GTF method */
        Status = AtaAcpiEvaluateObject(DeviceObject,
                                       &InputBuffer,
                                       sizeof(InputBuffer),
                                       OutputBuffer,
                                       OutputSize);
 
        /* Increase the allocation size if it's too small */
        if (Status == STATUS_BUFFER_OVERFLOW)
        {
            OutputSize = OutputBuffer->Length;
 
            ExFreePoolWithTag(OutputBuffer, TAG_PCIIDEX);
            continue;
        }
 
        break;
    }
 
    if (!NT_SUCCESS(Status))
        goto Cleanup;
 
    if (OutputBuffer->Argument[0].Type != ACPI_METHOD_ARGUMENT_BUFFER)
    {
        ERR("Unexpected method type %u\n", OutputBuffer->Argument[0].Type);
        goto Cleanup;
    }
 
    if (OutputBuffer->Argument[0].DataLength % sizeof(ATA_ACPI_TASK_FILE))
    {
        ERR("Incorrect command stream length %u\n", OutputBuffer->Argument[0].DataLength);
        goto Cleanup;
    }
 
    if (OutputBuffer->Argument[0].DataLength == 0)
    {
        WARN("Empty command list\n");
        goto Cleanup;
    }
 
    return OutputBuffer;
 
Cleanup:
    ExFreePoolWithTag(OutputBuffer, TAG_PCIIDEX);
 
    return NULL;
}

Referenced by AtaCtrlGetInitTaskFile().

AtaAcpiGetTimingMode()

BOOLEAN AtaAcpiGetTimingMode	(	_In_ PDEVICE_OBJECT	DeviceObject,
		_Out_ PIDE_ACPI_TIMING_MODE_BLOCK	TimingMode
	)

Definition at line 119 of file acpi.c.

{
    UCHAR Buffer[FIELD_OFFSET(ACPI_EVAL_OUTPUT_BUFFER, Argument) +
                 ACPI_METHOD_ARGUMENT_LENGTH(sizeof(*TimingMode))];
    ACPI_EVAL_INPUT_BUFFER InputBuffer;
    NTSTATUS Status;
    PACPI_EVAL_OUTPUT_BUFFER OutputBuffer = (PACPI_EVAL_OUTPUT_BUFFER)Buffer;
 
    RtlZeroMemory(Buffer, sizeof(Buffer));
 
    InputBuffer.MethodNameAsUlong = 'MTG_'; // _GTM
    InputBuffer.Signature = ACPI_EVAL_INPUT_BUFFER_SIGNATURE;
 
    /* Evaluate the _GTM method */
    Status = AtaAcpiEvaluateObject(DeviceObject,
                                   &InputBuffer,
                                   sizeof(InputBuffer),
                                   OutputBuffer,
                                   sizeof(Buffer));
 
    if (!NT_SUCCESS(Status))
    {
        ASSERT(Status != STATUS_BUFFER_OVERFLOW);
 
        TRACE("Failed to evaluate the _GTM method, status 0x%lx\n", Status);
        return FALSE;
    }
 
    if (OutputBuffer->Argument[0].DataLength < sizeof(*TimingMode))
    {
        ERR("Buffer too small, size %u/%u\n",
            OutputBuffer->Argument[0].DataLength, sizeof(*TimingMode));
        return FALSE;
    }
 
    if (OutputBuffer->Argument[0].Type != ACPI_METHOD_ARGUMENT_BUFFER)
    {
        ERR("Unexpected method type %u\n", OutputBuffer->Argument[0].Type);
        return FALSE;
    }
 
    RtlCopyMemory(TimingMode, OutputBuffer->Argument[0].Data, sizeof(*TimingMode));
 
    return TRUE;
}

Referenced by PciIdeAcpiSetTransferMode(), and PciIdeXPdoStartDevice().

AtaAcpiSetDeviceData()

VOID AtaAcpiSetDeviceData	(	_In_ PDEVICE_OBJECT	DeviceObject,
		_In_ PIDENTIFY_DEVICE_DATA	IdBlock
	)

Definition at line 317 of file acpi.c.

{
    PACPI_EVAL_INPUT_BUFFER_COMPLEX InputBuffer;
    PACPI_METHOD_ARGUMENT Argument;
    NTSTATUS Status;
    ULONG InputSize;
 
    PAGED_CODE();
    ASSERT(PsGetCurrentProcess() == PsInitialSystemProcess);
 
    InputSize = FIELD_OFFSET(ACPI_EVAL_INPUT_BUFFER_COMPLEX, Argument) +
                ACPI_METHOD_ARGUMENT_LENGTH(sizeof(*IdBlock));
 
    InputBuffer = ExAllocatePoolUninitialized(NonPagedPool, InputSize, TAG_PCIIDEX);
    if (!InputBuffer)
    {
        ERR("Failed to allocate memory\n");
        return;
    }
    InputBuffer->MethodNameAsUlong = 'DDS_'; // _SDD
    InputBuffer->Signature = ACPI_EVAL_INPUT_BUFFER_COMPLEX_SIGNATURE;
    InputBuffer->ArgumentCount = 1;
    InputBuffer->Size = InputSize;
 
    /* Argument 1: The ATA drive ID block */
    Argument = InputBuffer->Argument;
    ACPI_METHOD_SET_ARGUMENT_BUFFER(Argument, IdBlock, sizeof(*IdBlock));
 
    /* Evaluate the _SDD method */
    Status = AtaAcpiEvaluateObject(DeviceObject, InputBuffer, InputSize, NULL, 0);
    if (!NT_SUCCESS(Status))
    {
        if (Status == STATUS_OBJECT_NAME_NOT_FOUND)
            TRACE("Failed to set device data, status 0x%lx\n", Status);
        else
            WARN("Failed to set device data, status 0x%lx\n", Status);
    }
 
    ExFreePoolWithTag(InputBuffer, TAG_PCIIDEX);
}

Referenced by AtaCtrlSetDeviceData().

AtaAcpiSetTimingMode()

NTSTATUS AtaAcpiSetTimingMode	(	_In_ PDEVICE_OBJECT	DeviceObject,
		_In_ PIDE_ACPI_TIMING_MODE_BLOCK	TimingMode,
		_In_opt_ PIDENTIFY_DEVICE_DATA	IdBlock1,
		_In_opt_ PIDENTIFY_DEVICE_DATA	IdBlock2
	)

Definition at line 168 of file acpi.c.

{
    PACPI_EVAL_INPUT_BUFFER_COMPLEX InputBuffer;
    PACPI_METHOD_ARGUMENT Argument;
    NTSTATUS Status;
    ULONG InputSize;
 
    InputSize = FIELD_OFFSET(ACPI_EVAL_INPUT_BUFFER_COMPLEX, Argument) +
                ACPI_METHOD_ARGUMENT_LENGTH(sizeof(*TimingMode)) +
                ACPI_METHOD_ARGUMENT_LENGTH(sizeof(*IdBlock1)) +
                ACPI_METHOD_ARGUMENT_LENGTH(sizeof(*IdBlock2));
 
    InputBuffer = ExAllocatePoolUninitialized(NonPagedPool, InputSize, TAG_PCIIDEX);
    if (!InputBuffer)
    {
        ERR("Failed to allocate memory\n");
        return STATUS_INSUFFICIENT_RESOURCES;
    }
    InputBuffer->MethodNameAsUlong = 'MTS_'; // _STM
    InputBuffer->Signature = ACPI_EVAL_INPUT_BUFFER_COMPLEX_SIGNATURE;
    InputBuffer->ArgumentCount = 3;
    InputBuffer->Size = InputSize;
 
    /* Argument 1: The channel timing information block */
    Argument = InputBuffer->Argument;
    ACPI_METHOD_SET_ARGUMENT_BUFFER(Argument, TimingMode, sizeof(*TimingMode));
 
    /* Argument 2: The ATA drive ID block */
    Argument = ACPI_METHOD_NEXT_ARGUMENT(Argument);
    Argument->Type = ACPI_METHOD_ARGUMENT_BUFFER;
    Argument->DataLength = sizeof(*IdBlock1);
    if (IdBlock1)
        RtlCopyMemory(Argument->Data, IdBlock1, sizeof(*IdBlock1));
    else
        RtlZeroMemory(Argument->Data, sizeof(*IdBlock1));
 
    /* Argument 3: The ATA drive ID block */
    Argument = ACPI_METHOD_NEXT_ARGUMENT(Argument);
    Argument->Type = ACPI_METHOD_ARGUMENT_BUFFER;
    Argument->DataLength = sizeof(*IdBlock2);
    if (IdBlock2)
        RtlCopyMemory(Argument->Data, IdBlock2, sizeof(*IdBlock2));
    else
        RtlZeroMemory(Argument->Data, sizeof(*IdBlock2));
 
    /* Evaluate the _STM method */
    Status = AtaAcpiEvaluateObject(DeviceObject, InputBuffer, InputSize, NULL, 0);
    if (!NT_SUCCESS(Status))
    {
        if (Status == STATUS_OBJECT_NAME_NOT_FOUND)
            INFO("Failed to set transfer timings, status 0x%lx\n", Status);
        else
            ERR("Failed to set transfer timings, status 0x%lx\n", Status);
    }
 
    ExFreePoolWithTag(InputBuffer, TAG_PCIIDEX);
    return Status;
}

Referenced by AtaCtrlSetTransferMode(), and PciIdeAcpiSetTransferMode().

AtaAhciChannelGetMaximumDeviceCount()

ULONG AtaAhciChannelGetMaximumDeviceCount

(

_In_ PVOID

ChannelContext

)

Definition at line 1569 of file ahci_hw.c.

{
    PCHANNEL_DATA_AHCI ChanData = ChannelContext;
    PATA_CONTROLLER Controller = ChanData->Controller;
 
    if (Controller->AhciCapabilities & AHCI_CAP_SPM)
        return AHCI_MAX_PMP_DEVICES;
 
    return AHCI_MAX_PORT_DEVICES;
}

Referenced by PciIdeXQueryPciIdeInterface().

AtaAhciDowngradeInterfaceSpeed()

BOOLEAN AtaAhciDowngradeInterfaceSpeed

(

_In_ PCHANNEL_DATA_AHCI

ChanData

)

Definition at line 1542 of file ahci_hw.c.

{
    ULONG SataSpeed, SataControl;
 
    SataSpeed = AHCI_PORT_READ(ChanData->IoBase, PxSataStatus) & AHCI_PXSSTS_SPD_MASK;
    if (SataSpeed != AHCI_PXSSTS_SPD_SATA1)
    {
        SataControl = AHCI_PORT_READ(ChanData->IoBase, PxSataControl);
 
        if ((SataControl & AHCI_PXCTL_SPD_MASK) != AHCI_PXCTL_SPD_LIMIT_NONE)
        {
            SataControl &= ~AHCI_PXCTL_SPD_MASK;
            SataControl |= SataSpeed - AHCI_PXCTL_SPD_LIMIT_LEVEL;
 
            WARN("CH %lu: Downgrading interface speed to %08lx\n", ChanData->Channel, SataControl);
 
            AHCI_PORT_WRITE(ChanData->IoBase, PxSataControl, SataControl);
            return TRUE;
        }
    }
 
    INFO("CH %lu: Unable to downgrade interface speed %08lx\n", ChanData->Channel, SataSpeed);
    return FALSE;
}

Referenced by AtaCtrlDowngradeInterfaceSpeed().

AtaAhciHandleFatalError()

VOID AtaAhciHandleFatalError

(

_In_ PCHANNEL_DATA_AHCI

ChanData

)

Definition at line 1397 of file ahci_hw.c.

{
    ULONG CurrentCommandSlot, TaskFileData;
    ULONG i, CmdStatus, SlotsBitmap, FailedSlot;
    PATA_DEVICE_REQUEST Request;
 
    Request = NULL;
    CurrentCommandSlot = AHCI_PXCMD_CCS(AHCI_PORT_READ(ChanData->IoBase, PxCmdStatus));
 
    /* Clear the ST bit. This also clears PxCI, PxSACT, and PxCMD.CCS */
    AtaAhciStopCommandListProcess(ChanData);
 
    if (AtaAhciIsHbaHotRemoved(ChanData))
        goto Done;
 
    /* Wait for 500ms */
    for (i = 50000; i > 0; i--)
    {
        CmdStatus = AHCI_PORT_READ(ChanData->IoBase, PxCmdStatus);
        if (!(CmdStatus & AHCI_PXCMD_CR))
            break;
 
        KeStallExecutionProcessor(10);
    }
    if (i == 0)
    {
        /* The interface is hung */
        ERR("CH %lu: Failed to stop the command list DMA engine %08lx\n",
            ChanData->Channel,
            CmdStatus);
        goto Done;
    }
 
    TaskFileData = AHCI_PORT_READ(ChanData->IoBase, PxTaskFileData);
    if (TaskFileData & (IDE_STATUS_BUSY | IDE_STATUS_DRQ))
    {
        /* Put the device to the idle state */
        ERR("CH %lu: Busy TFD %08lx\n", ChanData->Channel, TaskFileData);
        goto Done;
    }
 
    /* Clear errors */
    AHCI_PORT_WRITE(ChanData->IoBase, PxSataError,
                    AHCI_PORT_READ(ChanData->IoBase, PxSataError));
 
    /* NCQ recovery is needed */
    if (ChanData->ActiveQueuedSlotsBitmap != 0)
    {
        AtaAhciStartCommandListProcess(ChanData);
 
        /* Find some active command */
        NT_VERIFY(_BitScanForward(&FailedSlot, ChanData->ActiveQueuedSlotsBitmap) != 0);
 
        Request = ChanData->Slots[FailedSlot];
        ASSERT(Request);
        ASSERT(Request->Slot == FailedSlot);
        ASSERT(Request->Flags & REQUEST_FLAG_NCQ);
        goto Done;
    }
 
    if (IsPowerOfTwo(ChanData->ActiveSlotsBitmap))
    {
        /* We have exactly one slot is outstanding */
        SlotsBitmap = ChanData->ActiveSlotsBitmap;
    }
    else if (ChanData->ActiveSlotsBitmap & (1 << CurrentCommandSlot))
    {
        SlotsBitmap = 1 << CurrentCommandSlot;
    }
    else
    {
        /* Indicates that the error bit is spurious *or* the exact slot is not known */
        if (ChanData->ActiveSlotsBitmap != 0)
        {
            ERR("CH %lu: Invalid slot received from the HBA %08lX --> %08lX\n",
                ChanData->Channel,
                ChanData->ActiveSlotsBitmap,
                1 << CurrentCommandSlot);
        }
        else
        {
            WARN("CH %lu: Spurious error interrupt %08lX\n",
                 ChanData->Channel,
                 AHCI_PORT_READ(ChanData->IoBase, PxInterruptStatus));
        }
        goto Done;
    }
 
    AtaAhciStartCommandListProcess(ChanData);
 
    NT_VERIFY(_BitScanForward(&FailedSlot, SlotsBitmap) != 0);
 
    Request = ChanData->Slots[FailedSlot];
    ASSERT(Request);
    ASSERT(Request->Slot == FailedSlot);
 
    /* Save the error */
    Request->SrbStatus = SRB_STATUS_ERROR;
    Request->Output.Status = (TaskFileData & AHCI_PXTFD_STATUS_MASK);
    Request->Output.Error = (TaskFileData & AHCI_PXTFD_ERROR_MASK) >> AHCI_PXTFD_ERROR_SHIFT;
 
    /* Save the current task file for the "ATA LBA field" (SAT-6 11.7) */
    if (!(Request->Device->TransportFlags & DEVICE_IS_ATAPI) ||
        (Request->Flags & REQUEST_FLAG_SAVE_TASK_FILE))
    {
        AtaAhciSaveTaskFile(ChanData, Request, TRUE);
    }
 
Done:
    /* Request arbitration from the port worker */
    ChanData->PortNotification(AtaRequestFailed, ChanData->PortContext, Request);
}

Referenced by AtaAhciPortHandleInterrupt().

AtaAhciHandlePortStateChange()

VOID AtaAhciHandlePortStateChange	(	_In_ PCHANNEL_DATA_AHCI	ChanData,
		_In_ ULONG	InterruptStatus
	)

Definition at line 1512 of file ahci_hw.c.

{
    ULONG SataStatus;
 
    if (InterruptStatus & AHCI_PXIRQ_DMPS)
    {
        ULONG CmdStatus = AHCI_PORT_READ(ChanData->IoBase, PxCmdStatus);
 
        if (CmdStatus & AHCI_PXCMD_MPSP)
        {
            WARN("CH %lu: Mechanical presence switch has changed %08lx\n",
                 ChanData->Channel, CmdStatus);
            goto Notify;
        }
    }
 
    SataStatus = AHCI_PORT_READ(ChanData->IoBase, PxSataStatus) & AHCI_PXSSTS_DET_MASK;
    if (SataStatus == AHCI_PXSSTS_DET_PHY_OK)
        INFO("CH %lu: Device hot plug detected %08lx\n", ChanData->Channel, SataStatus);
    else
        INFO("CH %lu: Device removal detected %08lx\n", ChanData->Channel, SataStatus);
 
Notify:
    /* Schedule a port reset */
    ChanData->PortNotification(AtaBusChangeDetected, ChanData->PortContext);
}

Referenced by AtaAhciPortHandleInterrupt().

AtaAhciSaveTaskFile()

VOID AtaAhciSaveTaskFile	(	_In_ PCHANNEL_DATA_AHCI	ChanData,
		_Inout_ PATA_DEVICE_REQUEST	Request,
		_In_ BOOLEAN	ProcessErrorStatus
	)

Definition at line 1325 of file ahci_hw.c.

{
    union
    {
        PAHCI_FIS_PIO_SETUP PioSetup;
        PAHCI_FIS_DEVICE_TO_HOST DeviceToHost;
    } Fis;
    PAHCI_RECEIVED_FIS ReceivedFis;
 
    ReceivedFis = ChanData->ReceivedFis;
 
    if (ChanData->ChanInfo & CHANNEL_FLAG_FBS_ENABLED)
        ReceivedFis += DEV_NUMBER(Request->Device);
 
    Request->Flags |= REQUEST_FLAG_HAS_TASK_FILE;
 
    if (ProcessErrorStatus)
    {
        /*
         * Device to Host FIS on failed commands.
         * The Request->Output.Status and Request->Output.Error fields should have saved earlier.
         */
        Fis.DeviceToHost = &ReceivedFis->DeviceToHostFis;
    }
    else
    {
        /* Check for successful queued commands (see SATA 3.5 specification 11.14) */
        if (Request->Flags & REQUEST_FLAG_NCQ)
        {
            PAHCI_FIS_SET_DEVICE_BITS SetDeviceBitsFis;
 
            /*
             * The SDB FIS was received and we do not have enough information
             * for the rest of the registers. Emulate the content of the task file registers.
             */
            RtlCopyMemory(&Request->Output, &Request->TaskFile, sizeof(Request->TaskFile));
 
            SetDeviceBitsFis = &ReceivedFis->SetDeviceBitsFis;
            Request->Output.Status = SetDeviceBitsFis->Status;
            Request->Output.Error = SetDeviceBitsFis->Error;
            return;
        }
        /* Check for successful PIO Data-In commands (see SATA 3.5 specification 11.8) */
        else if (!(Request->Flags & REQUEST_FLAG_DMA) && (Request->Flags & REQUEST_FLAG_DATA_IN))
        {
            /* In this case we have received a PIO Setup FIS */
            Fis.PioSetup = &ReceivedFis->PioSetupFis;
 
            Request->Output.Status = Fis.PioSetup->EStatus;
            Request->Output.Error = Fis.PioSetup->Error;
        }
        else
        {
            ULONG TaskFileData;
 
            /* Otherwise, we have received a Device to Host FIS */
            Fis.DeviceToHost = &ReceivedFis->DeviceToHostFis;
 
            TaskFileData = AHCI_PORT_READ(ChanData->IoBase, PxTaskFileData);
            Request->Output.Status = (TaskFileData & AHCI_PXTFD_STATUS_MASK);
            Request->Output.Error =
                (TaskFileData & AHCI_PXTFD_ERROR_MASK) >> AHCI_PXTFD_ERROR_SHIFT;
        }
    }
 
    AtaAhciSaveReceivedFisArea(Fis.DeviceToHost, Request);
}

Referenced by AtaAhciHandleFatalError(), and AtaAhciPortCompleteCommands().

AtaAhciStopDma()

VOID AtaAhciStopDma

(

_In_ PCHANNEL_DATA_AHCI

ChanData

)

Definition at line 1280 of file ahci_hw.c.

{
    AtaAhciStopCommandListProcessAndWait(ChanData);
    AtaAhciPerformCommandListOverride(ChanData);
    AtaAhciStopFisReceiveProcessAndWait(ChanData);
}

Referenced by AtaAhciAttachChannel().

AtaChanEnableInterruptsSync()

DECLSPEC_NOINLINE_FROM_PAGED VOID AtaChanEnableInterruptsSync	(	_In_ PVOID	ChannelContext,
		_In_ BOOLEAN	Enable
	)

Definition at line 62 of file fdo.c.

{
    PCHANNEL_DATA_COMMON ChanData = ChannelContext;
    PATA_CONTROLLER Controller = ChanData->Controller;
    PKINTERRUPT InterruptObject;
    KIRQL OldIrql;
 
    if (Controller->Flags & CTRL_FLAG_IS_AHCI)
        InterruptObject = Controller->InterruptObject;
    else
        InterruptObject = ChanData->InterruptObject;
    ASSERT(InterruptObject);
 
    OldIrql = KeAcquireInterruptSpinLock(InterruptObject);
    ChanData->EnableInterrupts(ChanData, Enable);
    KeReleaseInterruptSpinLock(InterruptObject, OldIrql);
}

Referenced by AtaAhciAttachChannel(), AtaAhciEnumerateChannel(), PataResetChannel(), PciIdeAttachChannel(), and PciIdeFreeResources().

AtaCtrlPciMapBar()

PVOID AtaCtrlPciMapBar	(	_In_ PATA_CONTROLLER	Controller,
		_In_range_(0, PCI_TYPE0_ADDRESSES) ULONG	Index,
		_In_ ULONG	MinimumIoLength
	)

Definition at line 254 of file fdo.c.

{
    PAGED_CODE();
 
    if (!(Controller->AccessRange[Index].Flags & RANGE_IS_VALID))
        return NULL;
 
    /* Validate the BAR length */
    if (MinimumIoLength != 0)
    {
        if (Controller->AccessRange[Index].Length < MinimumIoLength)
        {
            ERR("%04X:%04X.%02X: Unexpected PCI BAR #%lu length 0x%lx, minimum required 0x%lx\n",
                Controller->Pci.VendorID,
                Controller->Pci.DeviceID,
                Controller->Pci.RevisionID,
                Index,
                Controller->AccessRange[Index].Length,
                MinimumIoLength);
            return NULL;
        }
    }
 
    if ((Controller->AccessRange[Index].Flags & RANGE_IS_MEMORY) &&
        !(Controller->AccessRange[Index].Flags & RANGE_IS_MAPPED))
    {
        PHYSICAL_ADDRESS PhysicalAddress;
 
        Controller->AccessRange[Index].Flags |= RANGE_IS_MAPPED;
 
        PhysicalAddress.QuadPart = (ULONG_PTR)Controller->AccessRange[Index].IoBase;
        Controller->AccessRange[Index].IoBase = MmMapIoSpace(PhysicalAddress,
                                                             Controller->AccessRange[Index].Length,
                                                             MmNonCached);
    }
 
    return Controller->AccessRange[Index].IoBase;
}

Referenced by AtaAhciGetAbar(), PciIdeAssignNativeResources(), PciIdeControllerInitDma(), SvwSataGetControllerProperties(), and Via6421ParseResources().

AtaReadBlock16()

VOID AtaReadBlock16	(	_In_ PUSHORT	Port,
		_In_ PUSHORT	Buffer,
		_In_ ULONG	Count,
		_In_ ULONG	MmioFlags
	)

Definition at line 31 of file pata_io.c.

{
    ASSERT(Buffer != NULL);
    ASSERT(Count != 0);
 
    if (MmioFlags)
        READ_REGISTER_BUFFER_USHORT(Port, Buffer, Count);
    else
        READ_PORT_BUFFER_USHORT(Port, Buffer, Count);
}

AtaReadBlock32()

VOID AtaReadBlock32	(	_In_ PULONG	Port,
		_In_ PULONG	Buffer,
		_In_ ULONG	Count,
		_In_ ULONG	MmioFlags
	)

Definition at line 63 of file pata_io.c.

{
    ASSERT(Buffer != NULL);
    ASSERT(Count != 0);
 
    if (MmioFlags)
        READ_REGISTER_BUFFER_ULONG(Port, Buffer, Count);
    else
        READ_PORT_BUFFER_ULONG(Port, Buffer, Count);
}

AtaReadPortUchar()

UCHAR AtaReadPortUchar	(	_In_ PUCHAR	Port,
		_In_ ULONG	MmioFlags
	)

Definition at line 79 of file pata_io.c.

{
    if (MmioFlags)
        return READ_REGISTER_UCHAR(Port);
    else
        return READ_PORT_UCHAR(Port);
}

AtaSelectTimings()

VOID AtaSelectTimings	(	_In_reads_(MAX_IDE_DEVICE) PCHANNEL_DEVICE_CONFIG *	DeviceList,
		_Out_writes_all_(MAX_IDE_DEVICE) PATA_TIMING	Timings,
		_In_range_(>, 0) ULONG	ClockPeriodPs,
		_In_ ULONG	Flags
	)

Definition at line 116 of file pata_generic.c.

{
    ULONG i;
 
    for (i = 0; i < MAX_IDE_DEVICE; ++i)
    {
        PCHANNEL_DEVICE_CONFIG Device = DeviceList[i];
        PATA_TIMING Timing = &Timings[i];
        ATA_TIMING DmaTiming;
 
        if (!Device)
        {
            RtlZeroMemory(Timing, sizeof(*Timing));
            continue;
        }
 
        /* PIO mode */
        AtaCalculateTimings(Device, Timing, Device->PioMode, ClockPeriodPs);
 
        /* UDMA works independently of any PIO mode */
        if (Device->DmaMode == PIO_MODE(0) || Device->DmaMode >= UDMA_MODE(0))
            continue;
 
        /* DMA mode */
        AtaCalculateTimings(Device, &DmaTiming, Device->DmaMode, ClockPeriodPs);
 
        /*
         * Typically, the ATA port driver uses PIO commands along with DMA ones.
         * Given that we program the chipset only once after device enumeration,
         * we want to make sure the PIO commands would always work.
         */
        Timing->AddressSetup = max(Timing->AddressSetup, DmaTiming.AddressSetup);
        Timing->CmdActive    = max(Timing->CmdActive,    DmaTiming.CmdActive);
        Timing->CmdRecovery  = max(Timing->CmdRecovery,  DmaTiming.CmdRecovery);
        Timing->DataActive   = max(Timing->DataActive,   DmaTiming.DataActive);
        Timing->DataRecovery = max(Timing->DataRecovery, DmaTiming.DataRecovery);
    }
 
    /* Merge timings shared between both drives */
    if (Flags & SHARED_ADDR_TIMINGS)
    {
        Timings[0].AddressSetup = max(Timings[0].AddressSetup, Timings[1].AddressSetup);
 
        Timings[1].AddressSetup = Timings[0].AddressSetup;
    }
    if (Flags & SHARED_CMD_TIMINGS)
    {
        Timings[0].CmdActive = max(Timings[0].CmdActive, Timings[1].CmdActive);
        Timings[0].CmdRecovery = max(Timings[0].CmdRecovery, Timings[1].CmdRecovery);
 
        Timings[1].CmdActive = Timings[0].CmdActive;
        Timings[1].CmdRecovery = Timings[0].CmdRecovery;
    }
    if (Flags & SHARED_DATA_TIMINGS)
    {
        Timings[0].DataActive = max(Timings[0].DataActive, Timings[1].DataActive);
        Timings[0].DataRecovery = max(Timings[0].DataRecovery, Timings[1].DataRecovery);
 
        Timings[1].DataActive = Timings[0].DataActive;
        Timings[1].DataRecovery = Timings[0].DataRecovery;
    }
}

Referenced by AmdSetTransferMode(), CmdSetTransferMode(), Via6421SetTransferMode(), and ViaSetTransferMode().

AtaSleep()

VOID AtaSleep

(

VOID

)

Definition at line 100 of file pciidex.c.

{
    KTIMER Timer;
    LARGE_INTEGER DueTime;
 
    ASSERT(KeGetCurrentIrql() < DISPATCH_LEVEL);
 
    DueTime.QuadPart = PORT_TIMER_TICK_MS * -10000LL;
 
    KeInitializeTimer(&Timer);
    KeSetTimer(&Timer, DueTime, 0);
    KeWaitForSingleObject(&Timer, Executive, KernelMode, FALSE, 0);
}

Referenced by AtaAhciPhyCheckDevicePresence(), AtaAhciPmpPhyCheckDevicePresence(), AtaAhciPmpPhyWaitForReady(), AtaAhciPollRegister(), AtaAhciWaitForDeviceReady(), and PataResetChannel().

AtaWriteBlock16()

VOID AtaWriteBlock16	(	_In_ PUSHORT	Port,
		_In_ PUSHORT	Buffer,
		_In_ ULONG	Count,
		_In_ ULONG	MmioFlags
	)

Definition at line 15 of file pata_io.c.

{
    ASSERT(Buffer != NULL);
    ASSERT(Count != 0);
 
    if (MmioFlags)
        WRITE_REGISTER_BUFFER_USHORT(Port, Buffer, Count);
    else
        WRITE_PORT_BUFFER_USHORT(Port, Buffer, Count);
}

AtaWriteBlock32()

VOID AtaWriteBlock32	(	_In_ PULONG	Port,
		_In_ PULONG	Buffer,
		_In_ ULONG	Count,
		_In_ ULONG	MmioFlags
	)

Definition at line 47 of file pata_io.c.

{
    ASSERT(Buffer != NULL);
    ASSERT(Count != 0);
 
    if (MmioFlags)
        WRITE_REGISTER_BUFFER_ULONG(Port, Buffer, Count);
    else
        WRITE_PORT_BUFFER_ULONG(Port, Buffer, Count);
}

AtaWritePortUchar()

VOID AtaWritePortUchar	(	_In_ PUCHAR	Port,
		_In_ UCHAR	Value,
		_In_ ULONG	MmioFlags
	)

Definition at line 90 of file pata_io.c.

{
    if (MmioFlags)
        WRITE_REGISTER_UCHAR(Port, Value);
    else
        WRITE_PORT_UCHAR(Port, Value);
}

AtaWritePortUlong()

VOID AtaWritePortUlong	(	_In_ PULONG	Port,
		_In_ ULONG	Value,
		_In_ ULONG	MmioFlags
	)

Definition at line 102 of file pata_io.c.

{
    if (MmioFlags)
        WRITE_REGISTER_ULONG(Port, Value);
    else
        WRITE_PORT_ULONG(Port, Value);
}

AtiGetControllerProperties()

NTSTATUS AtiGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 36 of file ati.c.

{
    NTSTATUS Status;
    ULONG i;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_ATI);
 
    if (Controller->Pci.DeviceID != PCI_DEV_IXP200_IDE &&
        Controller->Pci.DeviceID != PCI_DEV_IXP300_IDE &&
        Controller->Pci.DeviceID != PCI_DEV_IXP400_IDE &&
        Controller->Pci.DeviceID != PCI_DEV_IXP600_IDE &&
        Controller->Pci.DeviceID != PCI_DEV_IXP700_IDE)
    {
        return STATUS_NO_MATCH;
    }
 
    Controller->ChannelEnableBits = AtiEnableBits;
 
    if (Controller->Pci.DeviceID == PCI_DEV_IXP600_IDE)
        Controller->MaxChannels = 1;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->SetTransferMode = SvwSetTransferMode;
        ChanData->TransferModeSupported = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 5);
 
        if (Controller->Pci.DeviceID == PCI_DEV_IXP200_IDE)
            ChanData->TransferModeSupported &= ~UDMA_MODE5;
 
        if (!SvwHasUdmaCable(Controller, i))
        {
            INFO("CH %lu: BIOS hasn't selected mode faster than UDMA 2, "
                 "assume 40-conductor cable\n",
                 ChanData->Channel);
            ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
        }
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

CmdGetControllerProperties()

NTSTATUS CmdGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 460 of file cmd.c.

{
    NTSTATUS Status;
    ULONG i, SupportedMode, HwFlags = 0;
    PCHANNEL_CHECK_INTERRUPT CheckInterrupt = CmdCheckInterruptPci;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_CMD);
 
    switch (Controller->Pci.DeviceID)
    {
        case PCI_DEV_PCI0640:
            /*
             * Errata: The CMD-640 has one set of task file registers per controller
             * and thus the two channels cannot be used simultaneously.
             * https://www.mindprod.com/jgloss/eideflaw.html
             */
            Controller->Flags |= CTRL_FLAG_IS_SIMPLEX;
 
            SupportedMode = PIO_ALL;
            HwFlags |= HW_FLAGS_PRIMARY_ENABLED | HW_FLAGS_NO_PREFETCH;
            break;
 
        case PCI_DEV_PCI0643:
            SupportedMode = PIO_ALL | SWDMA_ALL | MWDMA_ALL;
 
            if (Controller->Pci.RevisionID < 6)
                HwFlags |= HW_FLAGS_PRIMARY_ENABLED;
            break;
 
        case PCI_DEV_PCI0646:
            SupportedMode = PIO_ALL | SWDMA_ALL | MWDMA_ALL;
            HwFlags |= HW_FLAGS_HAS_UDMA_REG;
 
            if (Controller->Pci.RevisionID < 3)
                HwFlags |= HW_FLAGS_PRIMARY_ENABLED;
            else
                CheckInterrupt = CmdCheckInterruptMrdMode;
 
            if (Controller->Pci.RevisionID == 5 || Controller->Pci.RevisionID == 6)
            {
                /*
                 * Early 646U2 revisions can support UDMA2 only at a PCI bus speed of 33MHz.
                 * When it runs at 25 MHz or 30 MHZ, the transfer speed must be limited to UDMA1.
                 */
                SupportedMode |= UDMA_MODES(0, 1);
            }
            else if (Controller->Pci.RevisionID > 6)
            {
                SupportedMode |= UDMA_MODES(0, 2);
            }
            break;
 
        case PCI_DEV_PCI0648:
            SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 4);
            /* Prefetch bits have different meaning on this controller */
            HwFlags |= HW_FLAGS_HAS_UDMA_REG | HW_FLAGS_NO_PREFETCH;
            CheckInterrupt = CmdCheckInterruptMrdMode;
            break;
 
        case PCI_DEV_CMD0649:
            SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 5);
            HwFlags |= HW_FLAGS_HAS_UDMA_REG;
 
            if (Controller->Pci.RevisionID == 2)
                HwFlags |= HW_FLAGS_NEED_PIO_FIX;
 
            CheckInterrupt = CmdCheckInterruptMrdMode;
            break;
 
        default:
            return STATUS_NO_MATCH;
    }
 
    Controller->Start = CmdControllerStart;
 
    Controller->Flags |= CTRL_FLAG_USE_TEST_FUNCTION;
    Controller->ChannelEnabledTest = CmdChannelEnabledTest;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    Controller->HwExt = ExAllocatePoolZero(NonPagedPool, sizeof(CMD_HW_EXTENSION), TAG_PCIIDEX);
    if (!Controller->HwExt)
        return STATUS_INSUFFICIENT_RESOURCES;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->HwFlags = HwFlags;
        ChanData->CheckInterrupt = CheckInterrupt;
        ChanData->SetTransferMode = CmdSetTransferMode;
        ChanData->TransferModeSupported = SupportedMode;
 
        if (Controller->Pci.DeviceID == PCI_DEV_PCI0640)
        {
            ChanData->ChanInfo &= ~CHANNEL_FLAG_IO32;
        }
        else
        {
            /* Check for 80-conductor cable */
            if (ChanData->TransferModeSupported & UDMA_80C_ALL)
            {
                UCHAR BmControl = PciRead8(Controller, CMD_REG_BMIDECSR);
                if (!(BmControl & CMD_BMIDECSR_CR(i)))
                {
                    INFO("CH %lu: BIOS detected 40-conductor cable\n", ChanData->Channel);
                    ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
                }
            }
        }
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

CountSetBits()

FORCEINLINE ULONG CountSetBits

(

_In_ ULONG

x

)

Definition at line 840 of file pciidex.h.

{
    x -= x >> 1 & 0x55555555;
    x = (x & 0x33333333) + (x >> 2 & 0x33333333);
 
    return ((x + (x >> 4)) & 0x0F0F0F0F) * 0x01010101 >> 24;
}

Referenced by AhciGetControllerProperties().

HptGetControllerProperties()

NTSTATUS HptGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 316 of file hpt.c.

{
    NTSTATUS Status;
    ULONG i, HwFlags;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_HIGHPOINT);
 
    for (i = 0; i < RTL_NUMBER_OF(HptControllerList); ++i)
    {
        HwFlags = HptControllerList[i].Flags;
 
        if ((Controller->Pci.DeviceID == HptControllerList[i].DeviceID) &&
            (Controller->Pci.RevisionID >= HptControllerList[i].MinimumRevisionID))
        {
            break;
        }
    }
    if (i == RTL_NUMBER_OF(HptControllerList))
        return STATUS_NO_MATCH;
 
    Controller->Flags |= CTRL_FLAG_DMA_INTERRUPT;
    Controller->Start = HptControllerStart;
 
    if (HwFlags & HW_FLAGS_SINGLE_CHAN)
        Controller->MaxChannels = 1;
 
    if (GET_TYPE(HwFlags) == TYPE_366)
        Controller->ChannelEnableBits = Hpt366EnableBits;
    else
        Controller->ChannelEnableBits = Hpt37xEnableBits;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->HwFlags = HwFlags;
        ChanData->SetTransferMode = HptSetTransferMode;
 
        ChanData->TransferModeSupported = PIO_ALL | MWDMA_ALL | UDMA_ALL;
        if (HwFlags & HW_FLAGS_UDMA5)
            ChanData->TransferModeSupported &= ~UDMA_MODE6;
        else if (HwFlags & HW_FLAGS_UDMA4)
            ChanData->TransferModeSupported &= ~(UDMA_MODE6 | UDMA_MODE5);
 
        /* Check for 80-conductor cable */
        if (!HptHasUdmaCable(Controller, HwFlags, i))
        {
            INFO("CH %lu: BIOS detected 40-conductor cable\n", ChanData->Channel);
            ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
        }
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

IntelGetControllerProperties()

NTSTATUS IntelGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 969 of file intel.c.

{
    const INTEL_CONTROLLER_INFO* ControllerInfo;
    ULONG i, ExtensionSize, HwFlags;
    NTSTATUS Status;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_INTEL);
 
    for (i = 0; i < RTL_NUMBER_OF(IntelControllerList); ++i)
    {
        ControllerInfo = &IntelControllerList[i];
 
        if (Controller->Pci.DeviceID == ControllerInfo->DeviceID)
            break;
    }
    if (i == RTL_NUMBER_OF(IntelControllerList))
        return STATUS_NO_MATCH;
 
    Controller->Flags |= CTRL_FLAG_DMA_INTERRUPT;
 
    if (ControllerInfo->Type == TYPE_SCH)
        Controller->MaxChannels = 1;
 
    if (ControllerInfo->Type == TYPE_PIIX || ControllerInfo->Type == TYPE_MPIIX)
        ExtensionSize = sizeof(INTEL_HW_EXTENSION);
    else
        ExtensionSize = 0;
 
    Status = PciIdeCreateChannelData(Controller, ExtensionSize);
    if (!NT_SUCCESS(Status))
        return Status;
 
    switch (ControllerInfo->Type)
    {
        case TYPE_MPIIX:
            /*
             * This is a bridge device and there are no PCI BAR resources allocated,
             * so mark the controller as a legacy device.
             */
            Controller->Flags &= ~CTRL_FLAG_NATIVE_PCI;
            Controller->ChannelEnableBits = IntelMpiixEnableBits;
            break;
 
        case TYPE_PIIX:
        case TYPE_PIIX3:
        case TYPE_PIIX4:
        case TYPE_ICH:
            Controller->ChannelEnableBits = IntelPiixEnableBits;
            break;
 
        case TYPE_SATA:
            // TODO: Implement the map support
            //Controller->ChannelEnabledTest = IntelCombinedEnabledTest;
            //HwFlags = TYPE_ICH;
            break;
 
        default:
            break;
    }
    HwFlags = ControllerInfo->Type;
 
    if (PciFindDevice(IntelPciBridgeErrataMatch, NULL))
        HwFlags |= HW_FLAGS_DISABLE_DMA;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->HwFlags = HwFlags;
 
        IntelInitChannel(Controller, ControllerInfo, ChanData);
 
        if (HwFlags & HW_FLAGS_DISABLE_DMA)
            ChanData->TransferModeSupported &= PIO_ALL;
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

IsPowerOfTwo()

FORCEINLINE BOOLEAN IsPowerOfTwo

(

_In_ ULONG

x

)

Definition at line 851 of file pciidex.h.

{
    /* Also exclude zero numbers */
    return (x != 0) && ((x & (x - 1)) == 0);
}

PataChannelGetMaximumDeviceCount()

ULONG PataChannelGetMaximumDeviceCount

(

_In_ PVOID

ChannelContext

)

Definition at line 87 of file pata_hw.c.

{
    PCHANNEL_DATA_PATA ChanData = ChannelContext;
 
#if defined(_M_IX86)
    if (ChanData->ChanInfo & CHANNEL_FLAG_CBUS)
        return 4;
#endif
 
    return (ChanData->ChanInfo & CHANNEL_FLAG_NO_SLAVE) ? 1 : 2;
}

Referenced by PataEnumerateChannel(), PataResetChannel(), and PciIdeXQueryPciIdeInterface().

PciFindDevice()

BOOLEAN PciFindDevice	(	_In_ __callback PATA_PCI_MATCH_FN	MatchFunction,
		_In_ PVOID	Context
	)

Definition at line 13 of file pciidex.c.

{
    ULONG BusNumber, DeviceNumber, FunctionNumber;
 
    for (BusNumber = 0; BusNumber < 0xFF; ++BusNumber)
    {
        for (DeviceNumber = 0; DeviceNumber < PCI_MAX_DEVICES; ++DeviceNumber)
        {
            for (FunctionNumber = 0; FunctionNumber < PCI_MAX_FUNCTION; ++FunctionNumber)
            {
                UCHAR Buffer[RTL_SIZEOF_THROUGH_FIELD(PCI_COMMON_HEADER, RevisionID)];
                PPCI_COMMON_HEADER PciConfig = (PPCI_COMMON_HEADER)Buffer; // Partial PCI header
                PCI_SLOT_NUMBER PciSlot;
                ULONG BytesRead;
 
                PciSlot.u.AsULONG = 0;
                PciSlot.u.bits.DeviceNumber = DeviceNumber;
                PciSlot.u.bits.FunctionNumber = FunctionNumber;
 
                BytesRead = HalGetBusDataByOffset(PCIConfiguration,
                                                  BusNumber,
                                                  PciSlot.u.AsULONG,
                                                  &Buffer,
                                                  0,
                                                  sizeof(Buffer));
                if (BytesRead != sizeof(Buffer) ||
                    PciConfig->VendorID == PCI_INVALID_VENDORID ||
                    PciConfig->VendorID == 0)
                {
                    if (FunctionNumber == 0)
                    {
                        /* This slot has no single- or a multi-function device */
                        break;
                    }
                    else
                    {
                        /* Continue scanning the functions */
                        continue;
                    }
                }
 
                if (MatchFunction(Context, BusNumber, PciSlot, PciConfig))
                    return TRUE;
 
                if (!PCI_MULTIFUNCTION_DEVICE(PciConfig))
                {
                    /* The device is a single function device */
                    break;
                }
            }
        }
    }
 
    return FALSE;
}

Referenced by IntelGetControllerProperties(), SvwPataControllerStart(), and ViaPataGetControllerProperties().

PciIdeConnectInterrupt()

NTSTATUS PciIdeConnectInterrupt

(

_In_ PVOID

ChannelContext

)

Definition at line 1022 of file pata_generic.c.

{
    PCHANNEL_DATA_PATA ChanData = ChannelContext;
    PATA_CONTROLLER Controller = ChanData->Controller;
    PCM_PARTIAL_RESOURCE_DESCRIPTOR InterruptDesc;
    PKSERVICE_ROUTINE IsrHandler;
    NTSTATUS Status;
 
    PAGED_CODE();
 
    if (Controller->Flags & CTRL_FLAG_NATIVE_PCI)
        InterruptDesc = &Controller->InterruptDesc;
    else
        InterruptDesc = &ChanData->InterruptDesc;
    ASSERT(InterruptDesc);
 
    if (ChanData->Regs.Dma != NULL)
        IsrHandler = PciIdeChannelIsr;
    else
        IsrHandler = PataChannelIsr;
    Status = IoConnectInterrupt(&ChanData->InterruptObject,
                                IsrHandler,
                                ChanData,
                                NULL,
                                InterruptDesc->u.Interrupt.Vector,
                                InterruptDesc->u.Interrupt.Level,
                                InterruptDesc->u.Interrupt.Level,
                                (InterruptDesc->Flags & CM_RESOURCE_INTERRUPT_LATCHED)
                                ? Latched : LevelSensitive,
                                (InterruptDesc->ShareDisposition == CmResourceShareShared),
                                InterruptDesc->u.Interrupt.Affinity,
                                FALSE);
    if (!NT_SUCCESS(Status))
    {
        ERR("Could not connect to interrupt %lu, status 0x%lx\n",
            InterruptDesc->u.Interrupt.Vector, Status);
        return Status;
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeXPdoStartDevice().

PciIdeCreateChannelData()

NTSTATUS PciIdeCreateChannelData	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	HwExtensionSize
	)

Definition at line 1082 of file pata_generic.c.

{
    PCHANNEL_DATA_PATA ChanData;
    ULONG i, Size;
 
    PAGED_CODE();
    ASSERT(Controller->MaxChannels != 0);
 
    Size = FIELD_OFFSET(CHANNEL_DATA_PATA, HwExt) + HwExtensionSize;
    ChanData = ExAllocatePoolZero(NonPagedPool, Size * Controller->MaxChannels, TAG_PCIIDEX);
    if (!ChanData)
        return STATUS_INSUFFICIENT_RESOURCES;
 
    Controller->ChanDataBlock = ChanData;
    Controller->ChannelBitmap = NUM_TO_BITMAP(Controller->MaxChannels);
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        Controller->Channels[i] = ChanData;
 
        ChanData->Channel = i;
        ChanData->Controller = Controller;
 
        /* Set default values */
        ChanData->ChanInfo = CHANNEL_FLAG_IO32;
        ChanData->AllocateMemory = PciIdeAllocateMemory;
        ChanData->FreeMemory = PciIdeFreeMemory;
        ChanData->EnableInterrupts = PataEnableInterrupts;
        ChanData->PreparePrdTable = PciIdePreparePrdTable;
        ChanData->PrepareIo = PataPrepareIo;
        ChanData->StartIo = PataStartIo;
        ChanData->LoadTaskFile = PataLoadTaskFile;
        ChanData->SaveTaskFile = PataSaveTaskFile;
        ChanData->ReadStatus = PataReadStatus;
        ChanData->SetTransferMode = PciIdeGenericSetTransferMode;
        ChanData->TransferModeSupported = PIO_ALL | SWDMA_ALL | MWDMA_ALL | UDMA_ALL;
 
        KeInitializeDpc(&ChanData->PollingTimerDpc, PataPollingTimerDpc, ChanData);
 
        ChanData = (PVOID)((ULONG_PTR)ChanData + Size);
    }
 
    return STATUS_SUCCESS;
}

Referenced by AmdGetControllerProperties(), AtiGetControllerProperties(), CmdGetControllerProperties(), HptGetControllerProperties(), IntelGetControllerProperties(), PataGetControllerProperties(), PciIdeGetControllerProperties(), PcTechGetControllerProperties(), Sil680GetControllerProperties(), SvwPataGetControllerProperties(), SvwSataGetControllerProperties(), ToshibaGetControllerProperties(), Via6421GetControllerProperties(), ViaCx700GetControllerProperties(), and ViaGetControllerProperties().

PciIdeDmaStop()

VOID PciIdeDmaStop

(

_In_ PCHANNEL_DATA_PATA

ChanData

)

Definition at line 247 of file pata_io.c.

{
    PUCHAR IoBase = ChanData->Regs.Dma;
 
    /* Wait one PIO transfer cycle */
    (VOID)ATA_READ(IoBase + PCIIDE_DMA_STATUS, ChanData, MRES_DMA);
 
    /* Clear the interrupt bit in the status register */
    ATA_WRITE(IoBase + PCIIDE_DMA_COMMAND, PCIIDE_DMA_COMMAND_STOP, ChanData, MRES_DMA);
    ATA_WRITE(IoBase + PCIIDE_DMA_STATUS, PCIIDE_DMA_STATUS_INTERRUPT, ChanData, MRES_DMA);
}

Referenced by PataResetChannel(), and PciIdeChannelIsr().

PciIdeFreeResources()

VOID PciIdeFreeResources

(

_In_ PVOID

ChannelContext

)

Definition at line 887 of file pata_generic.c.

{
    PCHANNEL_DATA_PATA ChanData = ChannelContext;
 
    PAGED_CODE();
 
    if (ChanData->InterruptObject)
    {
        AtaChanEnableInterruptsSync(ChanData, FALSE);
 
        IoDisconnectInterrupt(ChanData->InterruptObject);
        ChanData->InterruptObject = NULL;
    }
 
    ChanData->Regs.Dma = NULL;
 
    ChanData->ChanInfo &= ~(CHANNEL_FLAG_DRIVE0_DMA_CAPABLE |
                            CHANNEL_FLAG_DRIVE1_DMA_CAPABLE);
 
    PataReleaseLegacyAddressRanges(ChanData);
}

Referenced by PciIdeXPdoStopDevice().

PciIdeGetChannelState()

IDE_CHANNEL_STATE PciIdeGetChannelState	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	Channel
	)

Definition at line 912 of file pata_generic.c.

{
    PAGED_CODE();
 
    /* SFF-8038i compliant hardware */
    if (Controller->Flags & CTRL_FLAG_NATIVE_PCI)
    {
        /*
         * If any native PCI IDE channel is enabled,
         * its PCI I/O resources should be allocated as well:
         *
         * [BAR 0] I/O ports at FFC0 [size=8]     Channel 0 task file registers
         * [BAR 1] I/O ports at FF8C [size=4]     Channel 0 device control
         * [BAR 2] I/O ports at FF80 [size=8]     Channel 1 task file registers
         * [BAR 3] I/O ports at FF88 [size=4]     Channel 1 device control
         * [BAR 4] I/O ports at FFA0 [size=16]    Bus Mastering registers
         * [BAR 5] Memory at FE780000             Aux registers
         */
        if (!(Controller->Flags & CTRL_FLAG_MANUAL_RES))
        {
            const ULONG BarIndex = Channel * 2;
 
            ASSERT(Channel < 2);
 
            /* Check task file registers */
            if (!(Controller->AccessRange[BarIndex].Flags & RANGE_IS_VALID))
                return ChannelDisabled;
 
            /* Check device control */
            if (!(Controller->AccessRange[BarIndex + 1].Flags & RANGE_IS_VALID))
                return ChannelDisabled;
        }
    }
 
    if (Controller->ChannelEnableBits)
    {
        if (Controller->Flags & CTRL_FLAG_USE_TEST_FUNCTION)
        {
            /* Device-specific test */
            return Controller->ChannelEnabledTest(Controller, Channel);
        }
        else
        {
            const ATA_PCI_ENABLE_BITS* EnableBits = &Controller->ChannelEnableBits[Channel];
            UCHAR RegisterValue;
 
            /* Test PCI bits */
            RegisterValue = PciRead8(Controller, EnableBits->Register);
            if ((RegisterValue & EnableBits->Mask) == EnableBits->ValueEnabled)
                return ChannelEnabled;
            else
                return ChannelDisabled;
        }
    }
 
    /* This channel is always enabled */
    return ChannelStateUnknown;
}

Referenced by PciIdeXGetChannelState().

PciIdeGetControllerProperties()

NTSTATUS PciIdeGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 1131 of file pata_generic.c.

{
    NTSTATUS Status;
    ULONG i;
 
    PAGED_CODE();
 
    Controller->MaxChannels = MAX_IDE_CHANNEL;
 
    /* Match the controller through the PCI ID */
    switch (Controller->Pci.VendorID)
    {
        case PCI_VEN_ATI:
            Status = AtiGetControllerProperties(Controller);
            break;
        case PCI_VEN_AMD:
        case PCI_VEN_NVIDIA:
            Status = AmdGetControllerProperties(Controller);
            break;
        case PCI_VEN_CMD:
            Status = CmdGetControllerProperties(Controller);
            if (Status == STATUS_NO_MATCH)
                Status = Sil680GetControllerProperties(Controller);
            break;
        case PCI_VEN_HIGHPOINT:
            Status = HptGetControllerProperties(Controller);
            break;
        case PCI_VEN_INTEL:
            Status = IntelGetControllerProperties(Controller);
            break;
        case PCI_VEN_PC_TECH:
            Status = PcTechGetControllerProperties(Controller);
            break;
        case PCI_VEN_SERVERWORKS:
            Status = SvwPataGetControllerProperties(Controller);
            if (Status == STATUS_NO_MATCH)
                Status = SvwSataGetControllerProperties(Controller);
            break;
        case PCI_VEN_TOSHIBA:
            Status = ToshibaGetControllerProperties(Controller);
            break;
        case PCI_VEN_VIA:
            Status = ViaGetControllerProperties(Controller);
            break;
 
        default:
            Status = STATUS_NO_MATCH;
            break;
    }
 
    /* Try to use the generic PCI IDE minidriver */
    if (Status == STATUS_NO_MATCH)
    {
        if ((Controller->Pci.BaseClass != PCI_CLASS_MASS_STORAGE_CTLR) ||
            ((Controller->Pci.SubClass != PCI_SUBCLASS_MSC_IDE_CTLR) &&
             (Controller->Pci.SubClass != PCI_SUBCLASS_MSC_RAID_CTLR)))
        {
            ERR("%04X:%04X.%02X: Unsupported controller\n",
                Controller->Pci.VendorID,
                Controller->Pci.DeviceID,
                Controller->Pci.RevisionID);
            return Status;
        }
 
        WARN("%04X:%04X.%02X: Using generic PCI IDE minidriver\n",
             Controller->Pci.VendorID,
             Controller->Pci.DeviceID,
             Controller->Pci.RevisionID);
 
        Status = PciIdeCreateChannelData(Controller, 0);
        if (!NT_SUCCESS(Status))
            return Status;
 
        /* Disable 32-bit I/O for unknown controllers */
        for (i = 0; i < Controller->MaxChannels; ++i)
        {
            PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
            ChanData->ChanInfo &= ~CHANNEL_FLAG_IO32;
        }
    }
 
    if (!NT_SUCCESS(Status))
        return Status;
 
    /*
     * Check for a legacy PCI IDE device.
     * NOTE: NT architecture does not support switching only one IDE channel to native mode.
     */
    if ((Controller->Pci.BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
        (Controller->Pci.SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
    {
        if (!(Controller->Pci.ProgIf & PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE) ||
            !(Controller->Pci.ProgIf & PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE))
        {
            Controller->Flags &= ~CTRL_FLAG_NATIVE_PCI;
        }
    }
 
    if (Controller->Flags & CTRL_FLAG_NATIVE_PCI)
    {
        if (Controller->InterruptDesc.Type != CmResourceTypeInterrupt)
        {
            ERR("No interrupt resource\n");
            return STATUS_INSUFFICIENT_RESOURCES;
        }
    }
 
    if (!PciIdeControllerInitDma(Controller))
    {
        for (i = 0; i < Controller->MaxChannels; ++i)
        {
            PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
            ChanData->TransferModeSupported &= PIO_ALL;
        }
    }
 
    if (Controller->Flags & CTRL_FLAG_IS_SIMPLEX)
    {
        WARN("Sync access for hardware is required\n");
 
        Controller->HwSyncObject = IoCreateController(0);
        if (!Controller->HwSyncObject)
            return STATUS_INSUFFICIENT_RESOURCES;
    }
 
    return STATUS_SUCCESS;
}

PciIdeInitTaskFileIoResources()

VOID PciIdeInitTaskFileIoResources	(	_In_ PCHANNEL_DATA_PATA	ChanData,
		_In_ ULONG_PTR	CommandPortBase,
		_In_ ULONG_PTR	ControlPortBase,
		_In_ ULONG	CommandBlockSpare
	)

Definition at line 673 of file pata_generic.c.

{
    PIDE_REGISTERS Registers = &ChanData->Regs;
 
    PAGED_CODE();
 
    /* Standard PATA register layout */
    Registers->Data        = (PVOID)(CommandPortBase + 0 * CommandBlockSpare);
    Registers->Error       = (PVOID)(CommandPortBase + 1 * CommandBlockSpare);
    Registers->SectorCount = (PVOID)(CommandPortBase + 2 * CommandBlockSpare);
    Registers->LbaLow      = (PVOID)(CommandPortBase + 3 * CommandBlockSpare);
    Registers->LbaMid      = (PVOID)(CommandPortBase + 4 * CommandBlockSpare);
    Registers->LbaHigh     = (PVOID)(CommandPortBase + 5 * CommandBlockSpare);
    Registers->Device      = (PVOID)(CommandPortBase + 6 * CommandBlockSpare);
    Registers->Status      = (PVOID)(CommandPortBase + 7 * CommandBlockSpare);
 
    Registers->Control     = (PVOID)ControlPortBase;
}

Referenced by PciIdeAssignLegacyResources(), PciIdeAssignNativeResources(), SvwSataParseResources(), and Via6421ParseResources().

PciIdeParseResources()

NTSTATUS PciIdeParseResources	(	_In_ PCHANNEL_DATA_PATA	ChanData,
		_In_ PCM_RESOURCE_LIST	ResourcesTranslated
	)

Definition at line 859 of file pata_generic.c.

{
    PATA_CONTROLLER Controller = ChanData->Controller;
    NTSTATUS Status;
 
    PAGED_CODE();
 
    ASSERT(ChanData->Channel < 2);
 
    if (Controller->Flags & CTRL_FLAG_NATIVE_PCI)
        Status = PciIdeAssignNativeResources(Controller, ChanData);
    else
        Status = PciIdeAssignLegacyResources(ChanData, ResourcesTranslated);
    if (!NT_SUCCESS(Status))
    {
        ERR("CH %lu: Failed to assign I/O resources 0x%lx\n", ChanData->Channel, Status);
        return Status;
    }
 
    PataClaimLegacyAddressRanges(ChanData);
 
    return STATUS_SUCCESS;
}

Referenced by PataGetControllerProperties(), and PciIdeXPdoStartDevice().

PciIdeXChannelState()

IDE_CHANNEL_STATE PciIdeXChannelState	(	_In_ PFDO_DEVICE_EXTENSION	FdoExtension,
		_In_ ULONG	Channel
	)

Definition at line 15 of file miniport.c.

{
    PCIIDE_CHANNEL_ENABLED MiniportChannelEnabled;
 
    PAGED_CODE();
 
    MiniportChannelEnabled = FdoExtension->Properties.PciIdeChannelEnabled;
    if (MiniportChannelEnabled)
        return MiniportChannelEnabled(FdoExtension->MiniControllerExtension, Channel);
 
    return ChannelStateUnknown;
}

PciIdeXFdoDispatchPnp()

NTSTATUS PciIdeXFdoDispatchPnp	(	_In_ PFDO_DEVICE_EXTENSION	FdoExtension,
		_Inout_ PIRP	Irp
	)

Definition at line 915 of file fdo.c.

{
    PIO_STACK_LOCATION IoStack;
    NTSTATUS Status;
 
    PAGED_CODE();
 
    Status = IoAcquireRemoveLock(&FdoExtension->Common.RemoveLock, Irp);
    if (!NT_SUCCESS(Status))
    {
        Irp->IoStatus.Status = Status;
        IoCompleteRequest(Irp, IO_NO_INCREMENT);
 
        return Status;
    }
 
    IoStack = IoGetCurrentIrpStackLocation(Irp);
    switch (IoStack->MinorFunction)
    {
        case IRP_MN_START_DEVICE:
        {
            if (!NT_VERIFY(IoForwardIrpSynchronously(FdoExtension->Common.LowerDeviceObject, Irp)))
            {
                Status = STATUS_UNSUCCESSFUL;
                goto CompleteIrp;
            }
            Status = Irp->IoStatus.Status;
            if (!NT_SUCCESS(Status))
                goto CompleteIrp;
 
            Status = PciIdeXFdoStartDevice(FdoExtension,
                                           IoStack->Parameters.
                                           StartDevice.AllocatedResourcesTranslated);
            goto CompleteIrp;
        }
 
        case IRP_MN_STOP_DEVICE:
        {
            Status = PciIdeXFdoStopDevice(FdoExtension);
            break;
        }
 
        case IRP_MN_REMOVE_DEVICE:
        {
            IoReleaseRemoveLockAndWait(&FdoExtension->Common.RemoveLock, Irp);
 
            PciIdeXFdoRemoveDevice(FdoExtension);
 
            Irp->IoStatus.Status = STATUS_SUCCESS;
            IoSkipCurrentIrpStackLocation(Irp);
            Status = IoCallDriver(FdoExtension->Common.LowerDeviceObject, Irp);
 
            IoDetachDevice(FdoExtension->Common.LowerDeviceObject);
            IoDeleteDevice(FdoExtension->Common.Self);
            return Status;
        }
 
        case IRP_MN_QUERY_PNP_DEVICE_STATE:
        {
            Status = PciIdeXPnpQueryPnpDeviceState(&FdoExtension->Common, Irp);
            break;
        }
 
        case IRP_MN_QUERY_DEVICE_RELATIONS:
        {
            if (IoStack->Parameters.QueryDeviceRelations.Type != BusRelations)
                break;
 
            Status = PciIdeXFdoQueryBusRelations(FdoExtension, Irp);
            if (!NT_SUCCESS(Status))
                goto CompleteIrp;
 
            Irp->IoStatus.Status = Status;
            break;
        }
 
        case IRP_MN_DEVICE_USAGE_NOTIFICATION:
        {
            Status = PciIdeXPnpQueryDeviceUsageNotification(&FdoExtension->Common, Irp);
            break;
        }
 
        case IRP_MN_QUERY_INTERFACE:
        {
            Status = PciIdeXFdoQueryInterface(FdoExtension, IoStack);
            if (Status == STATUS_NOT_SUPPORTED)
                break;
 
            Irp->IoStatus.Status = Status;
            break;
        }
 
        case IRP_MN_QUERY_STOP_DEVICE:
        case IRP_MN_QUERY_REMOVE_DEVICE:
        case IRP_MN_SURPRISE_REMOVAL:
        case IRP_MN_CANCEL_STOP_DEVICE:
        case IRP_MN_CANCEL_REMOVE_DEVICE:
            Irp->IoStatus.Status = STATUS_SUCCESS;
            break;
 
        case IRP_MN_QUERY_ID:
            return PciIdeXFdoQueryId(FdoExtension, Irp, IoStack);
 
        default:
            break;
    }
 
    IoSkipCurrentIrpStackLocation(Irp);
    Status = IoCallDriver(FdoExtension->Common.LowerDeviceObject, Irp);
 
    IoReleaseRemoveLock(&FdoExtension->Common.RemoveLock, Irp);
    return Status;
 
CompleteIrp:
    Irp->IoStatus.Status = Status;
    IoCompleteRequest(Irp, IO_NO_INCREMENT);
 
    IoReleaseRemoveLock(&FdoExtension->Common.RemoveLock, Irp);
    return Status;
}

Referenced by PciIdeXDispatchPnp().

PciIdexGetBusLocation()

NTSTATUS NTAPI PciIdexGetBusLocation	(	_In_ PVOID	DeviceExtension,
		_Out_ PULONG	BusLocation
	)

Definition at line 159 of file miniport.c.

{
    PFDO_DEVICE_EXTENSION FdoExt;
    ULONG Length;
    NTSTATUS Status;
 
    FdoExt = CONTAINING_RECORD(DeviceExtension, FDO_DEVICE_EXTENSION, MiniControllerExtension);
 
    Status = IoGetDeviceProperty(FdoExt->Pdo,
                                 DevicePropertyAddress,
                                 sizeof(*BusLocation),
                                 BusLocation,
                                 &Length);
    return Status;
}

Referenced by PciIdeXAddDeviceEx().

PciIdeXGetChannelState()

IDE_CHANNEL_STATE PciIdeXGetChannelState	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	Channel
	)

Definition at line 683 of file fdo.c.

{
    PAGED_CODE();
 
    if (Controller->Flags & CTRL_FLAG_IS_AHCI)
        return ChannelStateUnknown;
 
    return PciIdeGetChannelState(Controller, Channel);
}

Referenced by PciIdeXFdoQueryBusRelations(), PciIdeXPdoQueryResourceRequirements(), and PciIdeXPdoQueryResources().

PciIdeXPdoRemoveDevice()

NTSTATUS PciIdeXPdoRemoveDevice	(	_In_ PPDO_DEVICE_EXTENSION	PdoExtension,
		_In_ PIRP	Irp,
		_In_ BOOLEAN	FinalRemove
	)

Definition at line 193 of file pdo.c.

{
    PFDO_DEVICE_EXTENSION FdoExtension = PdoExtension->Common.FdoExt;
    NTSTATUS Status;
    BOOLEAN WasRemoved = FALSE;
 
    PAGED_CODE();
 
    PciIdeXPdoStopDevice(PdoExtension);
 
    if (FinalRemove && (PdoExtension->Flags & PDO_FLAG_REPORTED_MISSING))
    {
        IoReleaseRemoveLockAndWait(&PdoExtension->Common.RemoveLock, Irp);
 
        if (Irp)
            ExAcquireFastMutex(&FdoExtension->PdoListSyncMutex);
 
        RemoveEntryList(&PdoExtension->ListEntry);
 
        if (Irp)
            ExReleaseFastMutex(&FdoExtension->PdoListSyncMutex);
 
        IoDeleteDevice(PdoExtension->Common.Self);
        WasRemoved = TRUE;
    }
 
    Status = STATUS_SUCCESS;
    if (Irp)
    {
        Irp->IoStatus.Status = Status;
        IoCompleteRequest(Irp, IO_NO_INCREMENT);
    }
 
    if (!WasRemoved)
        IoReleaseRemoveLock(&PdoExtension->Common.RemoveLock, Irp);
    return Status;
}

Referenced by PciIdeXFdoRemoveDevice(), and PciIdeXPdoDispatchPnp().

PciIdeXPnpQueryDeviceUsageNotification()

NTSTATUS PciIdeXPnpQueryDeviceUsageNotification	(	_In_ PCOMMON_DEVICE_EXTENSION	CommonExt,
		_In_ PIRP	Irp
	)

Definition at line 214 of file pciidex.c.

{
    PIO_STACK_LOCATION IoStack;
    NTSTATUS Status;
    volatile LONG* Counter;
 
    PAGED_CODE();
 
    if (!IS_FDO(CommonExt))
    {
        Status = PciIdeXPnpRepeatRequest(CommonExt, Irp, NULL);
    }
    else
    {
        if (!NT_VERIFY(IoForwardIrpSynchronously(CommonExt->LowerDeviceObject, Irp)))
            return STATUS_UNSUCCESSFUL;
        Status = Irp->IoStatus.Status;
    }
    if (!NT_SUCCESS(Status))
        return Status;
 
    IoStack = IoGetCurrentIrpStackLocation(Irp);
    switch (IoStack->Parameters.UsageNotification.Type)
    {
        case DeviceUsageTypePaging:
            Counter = &CommonExt->PageFiles;
            break;
 
        case DeviceUsageTypeHibernation:
            Counter = &CommonExt->HibernateFiles;
            break;
 
        case DeviceUsageTypeDumpFile:
            Counter = &CommonExt->DumpFiles;
            break;
 
        default:
            return Status;
    }
 
    IoAdjustPagingPathCount(Counter, IoStack->Parameters.UsageNotification.InPath);
 
    if (!IS_FDO(CommonExt))
        IoInvalidateDeviceState(CommonExt->Self);
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXPdoDispatchPnp().

PciIdeXPnpQueryPnpDeviceState()

NTSTATUS PciIdeXPnpQueryPnpDeviceState	(	_In_ PCOMMON_DEVICE_EXTENSION	CommonExt,
		_In_ PIRP	Irp
	)

Definition at line 266 of file pciidex.c.

{
    PAGED_CODE();
 
    if (CommonExt->PageFiles || CommonExt->HibernateFiles || CommonExt->DumpFiles)
        Irp->IoStatus.Information |= PNP_DEVICE_NOT_DISABLEABLE;
 
    if (IS_FDO(CommonExt))
        Irp->IoStatus.Status = STATUS_SUCCESS;
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXPdoDispatchPnp().

PciIdeXPnpRepeatRequest()

NTSTATUS PciIdeXPnpRepeatRequest	(	_In_ PCOMMON_DEVICE_EXTENSION	CommonExt,
		_In_ PIRP	Irp,
		_In_opt_ PDEVICE_CAPABILITIES	DeviceCapabilities
	)

Definition at line 156 of file pciidex.c.

{
    PCOMMON_DEVICE_EXTENSION FdoExt = CommonExt->FdoExt;
    PDEVICE_OBJECT TopDeviceObject;
    PIO_STACK_LOCATION IoStack, SubStack;
    PIRP SubIrp;
    KEVENT Event;
    NTSTATUS Status;
 
    PAGED_CODE();
    ASSERT(!IS_FDO(CommonExt));
 
    TopDeviceObject = IoGetAttachedDeviceReference(FdoExt->Self);
 
    SubIrp = IoAllocateIrp(TopDeviceObject->StackSize, FALSE);
    if (!SubIrp)
    {
        ObDereferenceObject(TopDeviceObject);
        return STATUS_INSUFFICIENT_RESOURCES;
    }
 
    KeInitializeEvent(&Event, NotificationEvent, FALSE);
 
    IoStack = IoGetCurrentIrpStackLocation(Irp);
    SubStack = IoGetNextIrpStackLocation(SubIrp);
    RtlCopyMemory(SubStack, IoStack, sizeof(*SubStack));
 
    if (DeviceCapabilities)
        SubStack->Parameters.DeviceCapabilities.Capabilities = DeviceCapabilities;
 
    IoSetCompletionRoutine(SubIrp,
                           PciIdeXPdoCompletionRoutine,
                           &Event,
                           TRUE,
                           TRUE,
                           TRUE);
 
    SubIrp->IoStatus.Status = STATUS_NOT_SUPPORTED;
 
    Status = IoCallDriver(TopDeviceObject, SubIrp);
    if (Status == STATUS_PENDING)
    {
        KeWaitForSingleObject(&Event, Executive, KernelMode, FALSE, NULL);
    }
 
    ObDereferenceObject(TopDeviceObject);
 
    Status = SubIrp->IoStatus.Status;
    IoFreeIrp(SubIrp);
 
    return Status;
}

Referenced by PciIdeXPdoQueryCapabilities(), and PciIdeXPnpQueryDeviceUsageNotification().

PciRead()

VOID PciRead	(	_In_ PATA_CONTROLLER	Controller,
		_Out_writes_bytes_all_(BufferLength) PVOID	Buffer,
		_In_ ULONG	ConfigDataOffset,
		_In_ ULONG	BufferLength
	)

Definition at line 72 of file pciidex.c.

{
    Controller->GetBusData(Controller->BusInterfaceContext,
                           PCI_WHICHSPACE_CONFIG,
                           Buffer,
                           ConfigDataOffset,
                           BufferLength);
}

Referenced by IntelInitChannel(), PciRead16(), PciRead32(), and PciRead8().

PciRead16()

FORCEINLINE USHORT PciRead16	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	ConfigDataOffset
	)

Definition at line 872 of file pciidex.h.

{
    USHORT Result;
 
    PciRead(Controller, &Result, ConfigDataOffset, sizeof(Result));
    return Result;
}

Referenced by AmdGetControllerProperties(), IntelInitChannel(), IntelPiixLegacySetTransferMode(), IntelPiixSetTransferMode(), PcTechControllerStart(), Sil680SetTransferMode(), and SvwSetTransferMode().

PciRead32()

FORCEINLINE ULONG PciRead32	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	ConfigDataOffset
	)

Definition at line 884 of file pciidex.h.

{
    ULONG Result;
 
    PciRead(Controller, &Result, ConfigDataOffset, sizeof(Result));
    return Result;
}

Referenced by AmdSetTransferMode(), HptSetTransferMode(), IntelSchSetTransferMode(), Sil680SetTransferMode(), SvwSetTransferMode(), ToshibaSetTransferMode(), ViaPataGetControllerProperties(), ViaScrReadPci(), and ViaSetTransferMode().

PciRead8()

FORCEINLINE UCHAR PciRead8	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	ConfigDataOffset
	)

Definition at line 860 of file pciidex.h.

{
    UCHAR Result;
 
    PciRead(Controller, &Result, ConfigDataOffset, sizeof(Result));
    return Result;
}

Referenced by AmdControllerStart(), AmdEnablePostedWriteBuffer(), AmdGetControllerProperties(), CmdChannelEnabledTest(), CmdCheckInterruptMrdMode(), CmdCheckInterruptPci(), CmdControllerStart(), CmdGetControllerProperties(), CmdSetTransferMode(), HptControllerStart(), HptHasUdmaCable(), IntelInitChannel(), IntelPiixSetTransferMode(), PciIdeGetChannelState(), Sil680CheckInterrupt(), Sil680GetControllerProperties(), Sil680SetTransferMode(), SvwHasUdmaCable(), SvwPataControllerStart(), SvwSetTransferMode(), Via6410ControllerStart(), Via6421SetTransferMode(), ViaSataGetControllerProperties(), ViaSataSetTransferMode(), ViaScrReadPci(), and ViaSetTransferMode().

PciWrite()

VOID PciWrite	(	_In_ PATA_CONTROLLER	Controller,
		_In_reads_bytes_(BufferLength) PVOID	Buffer,
		_In_ ULONG	ConfigDataOffset,
		_In_ ULONG	BufferLength
	)

Definition at line 86 of file pciidex.c.

{
    Controller->SetBusData(Controller->BusInterfaceContext,
                           PCI_WHICHSPACE_CONFIG,
                           Buffer,
                           ConfigDataOffset,
                           BufferLength);
}

Referenced by PciWrite16(), PciWrite32(), and PciWrite8().

PciWrite16()

FORCEINLINE VOID PciWrite16	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	ConfigDataOffset,
		_In_ USHORT	Value
	)

Definition at line 906 of file pciidex.h.

{
    PciWrite(Controller, &Value, ConfigDataOffset, sizeof(Value));
}

Referenced by IntelPiixLegacyPrepareIo(), IntelPiixLegacySetTransferMode(), IntelPiixSetTransferMode(), PcTechControllerStart(), Sil680SetTransferMode(), and SvwSetTransferMode().

PciWrite32()

FORCEINLINE VOID PciWrite32	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	ConfigDataOffset,
		_In_ ULONG	Value
	)

Definition at line 916 of file pciidex.h.

{
    PciWrite(Controller, &Value, ConfigDataOffset, sizeof(Value));
}

Referenced by AmdSetTransferMode(), HptSetTransferMode(), IntelSchSetTransferMode(), Sil680SetTransferMode(), SvwSetTransferMode(), ToshibaSetTransferMode(), ViaScrWritePci(), and ViaSetTransferMode().

PciWrite8()

FORCEINLINE VOID PciWrite8	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	ConfigDataOffset,
		_In_ UCHAR	Value
	)

Definition at line 896 of file pciidex.h.

{
    PciWrite(Controller, &Value, ConfigDataOffset, sizeof(Value));
}

Referenced by AmdControllerStart(), AmdEnablePostedWriteBuffer(), CmdCheckInterruptMrdMode(), CmdControllerStart(), CmdSetTransferMode(), HptControllerStart(), HptHasUdmaCable(), IntelPiixSetTransferMode(), Sil680SetTransferMode(), SvwPataControllerStart(), SvwSetTransferMode(), Via6410ControllerStart(), Via6421SetTransferMode(), ViaSataSetTransferMode(), ViaScrWritePci(), and ViaSetTransferMode().

PcTechGetControllerProperties()

NTSTATUS PcTechGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 41 of file pctech.c.

{
    NTSTATUS Status;
    ULONG i;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_PC_TECH);
 
    if (Controller->Pci.DeviceID != PCI_DEV_RZ1000 && Controller->Pci.DeviceID != PCI_DEV_RZ1001)
        return STATUS_NO_MATCH;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    Controller->Start = PcTechControllerStart;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->ChanInfo &= ~CHANNEL_FLAG_IO32;
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

Sil680GetControllerProperties()

NTSTATUS Sil680GetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 214 of file sil680.c.

{
    NTSTATUS Status;
    ULONG i;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_CMD);
 
    if (Controller->Pci.VendorID != PCI_DEV_SIL0680)
        return STATUS_NO_MATCH;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
        UCHAR Config;
 
        ChanData->CheckInterrupt = Sil680CheckInterrupt;
        ChanData->SetTransferMode = Sil680SetTransferMode;
        ChanData->TransferModeSupported = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 6);
 
        /* Check for 80-conductor cable */
        Config = PciRead8(Controller, SIL_REG_CFG(i));
        if (!(Config & SIL_CFG_CABLE_80))
        {
            INFO("CH %lu: BIOS detected 40-conductor cable\n", ChanData->Channel);
            ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
        }
    }
 
    return STATUS_NOT_IMPLEMENTED;
}

Referenced by PciIdeGetControllerProperties().

SvwHasUdmaCable()

BOOLEAN SvwHasUdmaCable	(	_In_ PATA_CONTROLLER	Controller,
		_In_ ULONG	Channel
	)

Definition at line 213 of file svw_pata.c.

{
    UCHAR UdmaModeReg;
 
    PAGED_CODE();
 
    UdmaModeReg = PciRead8(Controller, SVW_REG_UDMA_MODE + Channel);
 
    /* Check mode settings, see if UDMA3 or higher mode is active */
    return ((UdmaModeReg & 0x07) > 2) || ((UdmaModeReg & 0x70) > 0x20);
}

Referenced by AtiGetControllerProperties(), and SvwPataGetControllerProperties().

SvwPataGetControllerProperties()

NTSTATUS SvwPataGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 288 of file svw_pata.c.

{
    NTSTATUS Status;
    ULONG i, SupportedMode;
    BOOLEAN No64KDma = FALSE;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_SERVERWORKS);
 
    switch (Controller->Pci.DeviceID)
    {
        case PCI_DEV_OSB4_IDE:
            /* UDMA is supported but its use is discouraged */
            SupportedMode = PIO_ALL | MWDMA_ALL;
 
            No64KDma = TRUE;
            break;
 
        case PCI_DEV_CSB5_IDE:
            if (Controller->Pci.RevisionID < 0x92)
                SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 4);
            else
                SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 5);
            Controller->Flags |= CTRL_FLAG_DMA_INTERRUPT;
            break;
 
        case PCI_DEV_CSB6_IDE_THIRD:
            SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 4);
            Controller->MaxChannels = 1;
            break;
 
        case PCI_DEV_CSB6_IDE:
            SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 5);
            break;
 
        case PCI_DEV_HT1000_IDE:
            SupportedMode = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 5);
            Controller->MaxChannels = 1;
            No64KDma = TRUE;
            break;
 
        default:
            return STATUS_NO_MATCH;
    }
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    Controller->Start = SvwPataControllerStart;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        if (No64KDma)
            ChanData->MaximumTransferLength = PCIIDE_PRD_LIMIT - 0x4000;
 
        ChanData->SetTransferMode = SvwSetTransferMode;
        ChanData->TransferModeSupported = SupportedMode;
 
        /* Check for 80-conductor cable */
        if ((ChanData->TransferModeSupported & UDMA_80C_ALL) && !SvwHasUdmaCable(Controller, i))
        {
            INFO("CH %lu: BIOS hasn't selected mode faster than UDMA 2, "
                 "assume 40-conductor cable\n",
                 ChanData->Channel);
            ChanData->TransferModeSupported &= ~UDMA_80C_ALL;
        }
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

SvwSataGetControllerProperties()

NTSTATUS SvwSataGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 215 of file svw_sata.c.

{
    NTSTATUS Status;
    ULONG i, HwFlags;
    PUCHAR IoBase;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_SERVERWORKS);
 
    for (i = 0; i < RTL_NUMBER_OF(SvwSataControllerList); ++i)
    {
        HwFlags = SvwSataControllerList[i].Flags;
 
        if (Controller->Pci.DeviceID == SvwSataControllerList[i].DeviceID)
            break;
    }
    if (i == RTL_NUMBER_OF(SvwSataControllerList))
        return STATUS_NO_MATCH;
 
    if (HwFlags & HW_FLAGS_8_PORTS)
        Controller->MaxChannels = 8;
    else
        Controller->MaxChannels = 4;
 
    Controller->Flags |= CTRL_FLAG_MANUAL_RES;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    IoBase = AtaCtrlPciMapBar(Controller, SvwSataGetIoBarIndex(Controller), 0);
    if (!IoBase)
        return STATUS_DEVICE_CONFIGURATION_ERROR;
 
    /*
     * Errata: Set SICR registers to turn off waiting for a status message
     * before sending FIS, fixes some issues with Seagate hard drives.
     */
    WRITE_REGISTER_ULONG((PULONG)(IoBase + 0x80),
                         READ_REGISTER_ULONG((PULONG)(IoBase + 0x80)) & ~0x00040000);
 
    /* Clear interrupts */
    WRITE_REGISTER_ULONG((PULONG)(IoBase + 0x44), 0xFFFFFFFF);
    WRITE_REGISTER_ULONG((PULONG)(IoBase + 0x88), 0);
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->TransferModeSupported = SATA_ALL;
        ChanData->SetTransferMode = SataSetTransferMode;
 
        if (HwFlags & HW_FLAGS_NO_ATAPI_DMA)
            ChanData->ChanInfo |= CHANNEL_FLAG_NO_ATAPI_DMA;
 
        /*
         * Errata: Enable the DMA engine before sending the drive command
         * to avoid data corruption.
         */
        ChanData->ChanInfo |= CHANNEL_FLAG_DMA_BEFORE_CMD;
 
        ChanData->ChanInfo |= CHANNEL_FLAG_NO_SLAVE;
        ChanData->ReadStatus = SvwSataReadStatus;
        ChanData->LoadTaskFile = SvwSataLoadTaskFile;
        ChanData->SaveTaskFile = SvwSataSaveTaskFile;
        ChanData->CheckInterrupt = SvwSataCheckInterrupt;
        ChanData->ScrRead = SvwSataScrRead;
        ChanData->ScrWrite = SvwSataScrWrite;
 
        SvwSataParseResources(ChanData, IoBase, i);
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

ToshibaGetControllerProperties()

NTSTATUS ToshibaGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 102 of file toshiba.c.

{
    NTSTATUS Status;
    ULONG i;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_TOSHIBA);
 
    if (Controller->Pci.DeviceID != PCI_DEV_PICCOLO_1 &&
        Controller->Pci.DeviceID != PCI_DEV_PICCOLO_2 &&
        Controller->Pci.DeviceID != PCI_DEV_PICCOLO_3 &&
        Controller->Pci.DeviceID != PCI_DEV_PICCOLO_5)
    {
        return STATUS_NO_MATCH;
    }
 
    Controller->MaxChannels = 1;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->TransferModeSupported = PIO_ALL | MWDMA_ALL | UDMA_MODES(0, 2);
        ChanData->SetTransferMode = ToshibaSetTransferMode;
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

ViaClampTimings()

VOID ViaClampTimings

(

_Inout_ PATA_TIMING

Timing

)

Definition at line 165 of file via.c.

{
    Timing->AddressSetup = CLAMP_TIMING(Timing->AddressSetup, 1, 4) - 1;
    Timing->CmdRecovery  = CLAMP_TIMING(Timing->CmdRecovery, 1, 16) - 1;
    Timing->CmdActive    = CLAMP_TIMING(Timing->CmdActive, 1, 16) - 1;
    Timing->DataRecovery = CLAMP_TIMING(Timing->DataRecovery, 1, 16) - 1;
    Timing->DataActive   = CLAMP_TIMING(Timing->DataActive, 1, 16) - 1;
}

Referenced by AmdSetTransferMode(), Via6421SetTransferMode(), and ViaSetTransferMode().

ViaGetControllerProperties()

NTSTATUS ViaGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 859 of file via.c.

{
    NTSTATUS Status;
    ULONG i, HwFlags;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_VIA);
 
    if (Controller->Pci.DeviceID == PCI_DEV_VT6421A_RAID)
    {
        return Via6421GetControllerProperties(Controller);
    }
    else if ((Controller->Pci.DeviceID == PCI_DEV_CX700M2_IDE_SATA) ||
             (Controller->Pci.DeviceID == PCI_DEV_CX700M2_IDE_SATA_RAID))
    {
        return ViaCx700GetControllerProperties(Controller);
    }
 
    for (i = 0; i < RTL_NUMBER_OF(ViaControllerList); ++i)
    {
        HwFlags = ViaControllerList[i].Flags;
 
        if (Controller->Pci.DeviceID == ViaControllerList[i].DeviceID)
            break;
    }
    if (i == RTL_NUMBER_OF(ViaControllerList))
        return STATUS_NO_MATCH;
 
    if (HwFlags & HW_FLAGS_SINGLE_CHAN)
        Controller->MaxChannels = 1;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    if (GET_TYPE(HwFlags) == TYPE_SATA)
        return ViaSataGetControllerProperties(Controller, HwFlags);
 
    return ViaPataGetControllerProperties(Controller, HwFlags);
}

Referenced by PciIdeGetControllerProperties().

Variable Documentation

AtaAhciAllocateSlot

CHANNEL_ALLOCATE_SLOT AtaAhciAllocateSlot

Definition at line 635 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaAhciEnableInterrupts

CHANNEL_ENABLE_INTERRUPTS AtaAhciEnableInterrupts

Definition at line 598 of file pciidex.h.

Referenced by AtaAhciCreateChannelData().

AtaAhciEnumerateChannel

CHANNEL_ENUMERATE_CHANNEL AtaAhciEnumerateChannel

Definition at line 599 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaAhciHbaIsr

KSERVICE_ROUTINE AtaAhciHbaIsr

Definition at line 636 of file pciidex.h.

Referenced by AhciGetControllerProperties().

AtaAhciIdentifyDevice

CHANNEL_IDENTIFY_DEVICE AtaAhciIdentifyDevice

Definition at line 600 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaAhciPrepareIo

CHANNEL_PREPARE_IO AtaAhciPrepareIo

Definition at line 633 of file pciidex.h.

Referenced by AtaAhciCreateChannelData().

AtaAhciPreparePrdTable

CHANNEL_PREPARE_PRD_TABLE AtaAhciPreparePrdTable

Definition at line 634 of file pciidex.h.

Referenced by AtaAhciCreateChannelData().

AtaAhciResetChannel

CHANNEL_RESET_CHANNEL AtaAhciResetChannel

Definition at line 601 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaAhciStartIo

CHANNEL_START_IO AtaAhciStartIo

Definition at line 632 of file pciidex.h.

Referenced by AtaAhciCreateChannelData().

AtaCtrlAbortChannel

CHANNEL_ABORT_CHANNEL AtaCtrlAbortChannel

Definition at line 466 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaCtrlAttachChannel

CONTROLLER_ATTACH_CHANNEL AtaCtrlAttachChannel

Definition at line 456 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaCtrlDowngradeInterfaceSpeed

CHANNEL_DOWNGRADE_INTERFACE_SPEED AtaCtrlDowngradeInterfaceSpeed

Definition at line 465 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaCtrlGetInitTaskFile

CHANNEL_GET_INIT_TASK_FILE AtaCtrlGetInitTaskFile

Definition at line 462 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaCtrlSetDeviceData

CHANNEL_SET_DEVICE_DATA AtaCtrlSetDeviceData

Definition at line 459 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

AtaCtrlSetTransferMode

CHANNEL_SET_MODE AtaCtrlSetTransferMode

Definition at line 464 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

BusNumber

_In_ ULONG BusNumber

Definition at line 65 of file pciidex.h.

Referenced by _Requires_lock_held_(), AcpiHwGetPciDeviceInfo(), AcpiHwProcessPciList(), AddControllers(), AllocateAddressMapping(), AtapiFindDev(), AtapiFindListedDev(), BootTranslateBusAddress(), Bus_PDO_QueryResources(), CmpInitializeRegistryNode(), CmpSetupConfigurationTree(), CODE_SEG(), ConfigCallback(), DetectPciBus(), FindBootDisplay(), FindBootDisplayFromLoaderARCTree(), FindBrokenController(), GetArcComponentInterface(), HalAssignSlotResources(), HalGetBusData(), HalGetBusDataByOffset(), HalGetInterruptVector(), HaliHandlerForBus(), HaliHandlerForConfigSpace(), HaliPciInterfaceReadConfig(), HaliPciInterfaceWriteConfig(), HaliReferenceHandlerForBus(), HaliReferenceHandlerForConfigSpace(), HaliRegisterBusHandler(), HaliTranslateBusAddress(), HalpAllocateBusHandler(), HalpAssignSlotResources(), HalpFindMatchingDebuggingDevice(), HalpGetCmosData(), HalpSetCmosData(), HalSetBusData(), HalSetBusDataByOffset(), HalTranslateBusAddress(), InitializeConfiguration(), IntelPciBridgeErrataMatch(), IntVideoPortEnumBusCallback(), IntVideoPortEnumBuses(), IntVideoPortFindAdapter(), IoQueryDeviceDescription(), IoTranslateBusAddress(), KdpSysReadBusData(), KdpSysReadIoSpace(), KdpSysWriteBusData(), KdpSysWriteIoSpace(), NdisOverrideBusNumber(), OslIsPciDevicePresent(), Pc98HwDetect(), PcHwDetect(), PciAllocateCmResourceList(), PciAllocateIoRequirementsList(), PciAssignSlotResources(), PciCacheLegacyDeviceRouting(), PciFindDevice(), PciIdeXFdoQueryInterface(), PciIsDebuggingDevice(), PciLocateKdDevices(), PciTranslateBusAddress(), RegistryInitAdapterKey(), ScsiPortGetBusDataByOffset(), SpiGetPciConfigData(), SvwOsb4PciBridgeInit(), UCX_CONTROLLER_CONFIG_SET_PCI_INFO(), UefiHwDetect(), ViaQuerySouthBridgeInformation(), VidInitialize(), XboxDetectPciBus(), and XboxHwDetect().

Channel

_In_ ULONG Channel

Definition at line 74 of file pciidex.h.

Referenced by AmdEnablePostedWriteBuffer(), AmdSetTransferMode(), AtapiCheckInterrupt__(), AtapiDmaDone(), AtapiDmaInit(), AtapiDmaStart(), AtapiInterrupt__(), AtapiResetController__(), BlasterCleanup(), ChanMgrChannelDestroy(), ChanMgrCloseChannel(), ChanMgrCloseChannelsWithFileObject(), ChanMgrCreateChannel(), ChanMgrGetByHandle(), ChanMgrGetChannelByName(), ChanMgrGetChannelCount(), ChanMgrGetChannelIndex(), ChanMgrIsUniqueName(), ChanMgrReleaseChannel(), ChannelClearRedrawEvent(), ChannelClose(), ChannelCreate(), ChannelDereferenceHandles(), ChannelDestroy(), ChannelGetApplicationType(), ChannelGetDescription(), ChannelGetFlags(), ChannelGetIndex(), ChannelGetName(), ChannelGetStatus(), ChannelHasNewIBufferData(), ChannelHasNewOBufferData(), ChannelHasRedrawEvent(), ChannelIBufferLength(), ChannelInitializeVTable(), ChannelIRead(), ChannelIReadLast(), ChannelIsActive(), ChannelIsClosed(), ChannelIsEqual(), ChannelIWrite(), ChannelOFlush(), ChannelOWrite(), ChannelSetDescription(), ChannelSetLockEvent(), ChannelSetName(), ChannelSetRedrawEvent(), ChannelSetStatus(), CmdChannelEnabledTest(), CmdSetTransferMode(), ConMgrAdvanceCurrentChannel(), ConMgrChannelClose(), ConMgrIsSacChannel(), ConMgrIsWriteEnabled(), ConMgrResetCurrentChannel(), ConMgrSetCurrentChannel(), DmaRequest(), EventDescCreate(), EventDescSetChannel(), FindDevices(), FindDmaDescriptor(), HptHasUdmaCable(), HptSetTransferMode(), IdeMediaStatus(), IntelPiixChooseDeviceSpeed(), IntelPiixLegacySetTransferMode(), IntelPiixSetTransferMode(), IopFindDmaResource(), IsaConvertDmaRequirement(), IssueIdentify(), MMixerGetChannelCountLegacy(), MMixerSetGetControlDetails(), MMixerSetGetVolumeControlDetails(), MPU401Cleanup(), PciIdeChannelEnabled(), PciIdeGenericSetTransferMode(), PciIdeGetChannelState(), PciIdeXChannelState(), PciIdeXFdoQueryBusRelations(), PciIdeXGetChannelState(), PitDecrementCount(), PitGetReloadValue(), PitInitCounter(), PitLatchChannelCount(), PitLatchChannelStatus(), PitReadData(), PitSetGate(), PitSetOut(), PitSetOutFunction(), PitWriteCommand(), PitWriteData(), RawChannelCreate(), RawChannelDestroy(), RawChannelGetIBufferIndex(), RawChannelIBufferIsFull(), RawChannelIBufferLength(), RawChannelIRead(), RawChannelIReadLast(), RawChannelIWrite(), RawChannelOEcho(), RawChannelOFlush(), RawChannelORead(), RawChannelOWrite(), RawChannelOWrite2(), RawChannelSetIBufferIndex(), SataSetTransferMode(), SetDriveParameters(), Sil680SetTransferMode(), SvwChooseDeviceSpeed(), SvwHasUdmaCable(), SvwSetTransferMode(), ToshibaSetTransferMode(), UniataAhciStatus(), VDDQueryDMA(), VDDSetDMA(), Via6421SetTransferMode(), ViaSataSetTransferMode(), ViaSetTransferMode(), VTUTF8ChannelAnsiDispatch(), VTUTF8ChannelAssertCursor(), VTUTF8ChannelConsumeEscapeSequence(), VTUTF8ChannelCreate(), VTUTF8ChannelDestroy(), VTUTF8ChannelGetIBufferIndex(), VTUTF8ChannelIBufferIsFull(), VTUTF8ChannelIBufferLength(), VTUTF8ChannelIRead(), VTUTF8ChannelIReadLast(), VTUTF8ChannelIWrite(), VTUTF8ChannelOEcho(), VTUTF8ChannelOFlush(), VTUTF8ChannelOInit(), VTUTF8ChannelOWrite(), VTUTF8ChannelOWrite2(), VTUTF8ChannelProcessAttributes(), and VTUTF8ChannelSetIBufferIndex().

DriverEntry

DRIVER_INITIALIZE DriverEntry

Definition at line 516 of file pciidex.h.

InitSafeBootMode

NTSYSAPI ULONG InitSafeBootMode

extern

Definition at line 75 of file init.c.

PataAllocateSlot

CHANNEL_ALLOCATE_SLOT PataAllocateSlot

Definition at line 706 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

PataChannelIsr

KSERVICE_ROUTINE PataChannelIsr

Definition at line 710 of file pciidex.h.

Referenced by PciIdeConnectInterrupt().

PataEnumerateChannel

CHANNEL_ENUMERATE_CHANNEL PataEnumerateChannel

Definition at line 697 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

PataIdentifyDevice

CHANNEL_IDENTIFY_DEVICE PataIdentifyDevice

Definition at line 698 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

PataLoadTaskFile

CHANNEL_LOAD_TASK_FILE PataLoadTaskFile

Definition at line 713 of file pciidex.h.

Referenced by PciIdeCreateChannelData().

PataPollingTimerDpc

KDEFERRED_ROUTINE PataPollingTimerDpc

Definition at line 716 of file pciidex.h.

Referenced by PciIdeCreateChannelData().

PataPrepareIo

CHANNEL_PREPARE_IO PataPrepareIo

Definition at line 708 of file pciidex.h.

Referenced by IntelPiixLegacyPrepareIo(), and PciIdeCreateChannelData().

PataReadStatus

CHANNEL_READ_STATUS PataReadStatus

Definition at line 715 of file pciidex.h.

Referenced by PciIdeCreateChannelData().

PataResetChannel

CHANNEL_RESET_CHANNEL PataResetChannel

Definition at line 696 of file pciidex.h.

Referenced by PciIdeXQueryPciIdeInterface().

PataSaveTaskFile

CHANNEL_SAVE_TASK_FILE PataSaveTaskFile

Definition at line 714 of file pciidex.h.

Referenced by PciIdeCreateChannelData().

PataStartIo

CHANNEL_START_IO PataStartIo

Definition at line 709 of file pciidex.h.

Referenced by PciIdeCreateChannelData().

PciConfig

_In_ ULONG _In_ PCI_SLOT_NUMBER _In_ PPCI_COMMON_HEADER PciConfig

Definition at line 67 of file pciidex.h.

Referenced by CheckPciDevice(), DcRecognizeHardware(), FdoEnumerateDevices(), FdoLocateChildDevice(), HalpAssignPCISlotResources(), HalpConfigureDebuggingDevice(), HalpFindMatchingDebuggingDevice(), HalpGetPCIData(), HalpMatchDebuggingDevice(), HalpSetPCIData(), IntelPciBridgeErrataMatch(), IntVideoPortGetLegacyResources(), MiniportInitialize(), NvNetRecognizeHardware(), OslIsPciDevicePresent(), PciFindDevice(), PdoQueryResourceRequirements(), PdoQueryResources(), SpiGetPciConfigData(), SvwOsb4PciBridgeInit(), USBPORT_StartDevice(), and ViaQuerySouthBridgeInformation().

PciIdeAttachChannel

CONTROLLER_ATTACH_CHANNEL_EX PciIdeAttachChannel

Definition at line 644 of file pciidex.h.

Referenced by PciIdeXFdoStartDevice().

PciIdeChannelIsr

KSERVICE_ROUTINE PciIdeChannelIsr

Definition at line 711 of file pciidex.h.

Referenced by PciIdeConnectInterrupt().

PciIdeCheckInterrupt

CHANNEL_CHECK_INTERRUPT PciIdeCheckInterrupt

Definition at line 712 of file pciidex.h.

Referenced by PciIdeControllerInitDma().

PciIdeGenericSetTransferMode

CHANNEL_SET_MODE_EX PciIdeGenericSetTransferMode

Definition at line 641 of file pciidex.h.

Referenced by AtaCtrlSetTransferMode(), and PciIdeCreateChannelData().

PciIdePreparePrdTable

CHANNEL_PREPARE_PRD_TABLE PciIdePreparePrdTable

Definition at line 707 of file pciidex.h.

Referenced by PciIdeCreateChannelData().

PciIdeXAddDevice

DRIVER_ADD_DEVICE PciIdeXAddDevice

Definition at line 522 of file pciidex.h.

Referenced by PciIdeXInitialize().

PciIdeXFdoRemoveDevice

CONTROLLER_PNP_REMOVE_DEVICE PciIdeXFdoRemoveDevice

Definition at line 472 of file pciidex.h.

Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXInitialize().

PciIdeXFdoStartDevice

CONTROLLER_PNP_START_DEVICE PciIdeXFdoStartDevice

Definition at line 469 of file pciidex.h.

Referenced by PciIdeXFdoDispatchPnp(), and PciIdeXInitialize().

PciIdeXPdoCompletionRoutine

IO_COMPLETION_ROUTINE PciIdeXPdoCompletionRoutine

Definition at line 528 of file pciidex.h.

Referenced by _IRQL_requires_max_(), and PciIdeXPnpRepeatRequest().

PciIdeXUnload

DRIVER_UNLOAD PciIdeXUnload

Definition at line 519 of file pciidex.h.

Referenced by PciIdeXInitialize().

PciSlot

_In_ ULONG _In_ PCI_SLOT_NUMBER PciSlot

Definition at line 66 of file pciidex.h.

Referenced by _Requires_lock_held_(), HalpConfigureDebuggingDevice(), HalpDebugPciDumpBus(), HalpFindMatchingDebuggingDevice(), HalpGetISAFixedPCIIrq(), HalpGetPciBridgeConfig(), HalpInitializePciBus(), HalpMatchDebuggingDevice(), HalpPhase0GetPciDataByOffset(), HalpPhase0SetPciDataByOffset(), HalpRegisterPciDebuggingDeviceInfo(), HalpSetupPciDeviceForDebugging(), IntelPciBridgeErrataMatch(), PciFindDevice(), PciLocateKdDevices(), PciScanBus(), routeintrf_GetInterruptRouting(), SvwOsb4PciBridgeInit(), and ViaQuerySouthBridgeInformation().

SataSetTransferMode

CHANNEL_SET_MODE_EX SataSetTransferMode

Definition at line 640 of file pciidex.h.

Referenced by AmdGetControllerProperties(), AtaAhciCreateChannelData(), IntelInitChannel(), SvwSataGetControllerProperties(), ViaCx700GetControllerProperties(), ViaSataGetControllerProperties(), and ViaSataSetTransferMode().

SvwSetTransferMode

CHANNEL_SET_MODE_EX SvwSetTransferMode

Definition at line 826 of file pciidex.h.

Referenced by AtiGetControllerProperties(), and SvwPataGetControllerProperties().