svw_sata.c File Reference

#include "pciidex.h"

Include dependency graph for svw_sata.c:

Go to the source code of this file.

Macros
#define	PCI_DEV_K2_SATA   0x0240
#define	PCI_DEV_BCM5770_SATA   0x0241
#define	PCI_DEV_BCM5770R_SATA   0x0242
#define	PCI_DEV_HT1000_SATA   0x024A
#define	PCI_DEV_HT1000_SATA_2   0x024B
#define	PCI_DEV_HT1100_SATA   0x0410
#define	PCI_DEV_HT1100_SATA_2   0x0411
#define	SVW_SATA_PORT_BASE_OFFSET   0x100
#define	SVW_SATA_PORT_CONTROL_OFFSET   0x20
#define	SVW_SATA_PORT_DMA_OFFSET   0x30
#define	SVW_SATA_PORT_SCR_OFFSET   0x40
#define	SVW_SATA_PORT_TF_STRIDE   4
#define	HW_FLAGS_8_PORTS   0x01
#define	HW_FLAGS_NO_ATAPI_DMA   0x02

Functions
static BOOLEAN	SvwSataScrRead (_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ PULONG Result)
static BOOLEAN	SvwSataScrWrite (_In_ PCHANNEL_DATA_PATA ChanData, _In_ SATA_SCR_REGISTER Register, _In_ ULONG PortNumber, _In_ ULONG Value)
static ULONG	SvwSataGetIoBarIndex (_In_ PATA_CONTROLLER Controller)
static BOOLEAN	SvwSataCheckInterrupt (_In_ PCHANNEL_DATA_PATA ChanData)
static UCHAR	SvwSataReadStatus (_In_ PCHANNEL_DATA_PATA ChanData)
static VOID	SvwSataLoadTaskFile (_In_ PCHANNEL_DATA_PATA ChanData, _In_ PATA_DEVICE_REQUEST Request)
static VOID	SvwSataSaveTaskFile (_In_ PCHANNEL_DATA_PATA ChanData, _Inout_ PATA_DEVICE_REQUEST Request)
static VOID	SvwSataParseResources (_Inout_ PCHANNEL_DATA_PATA ChanData, _In_ PUCHAR IoBase, _In_ ULONG PortIndex)
NTSTATUS	SvwSataGetControllerProperties (_Inout_ PATA_CONTROLLER Controller)

Variables
struct {
USHORT   DeviceID
USHORT   Flags
}	SvwSataControllerList []

Macro Definition Documentation

HW_FLAGS_8_PORTS

#define HW_FLAGS_8_PORTS   0x01

Definition at line 33 of file svw_sata.c.

HW_FLAGS_NO_ATAPI_DMA

#define HW_FLAGS_NO_ATAPI_DMA   0x02

Definition at line 34 of file svw_sata.c.

PCI_DEV_BCM5770_SATA

#define PCI_DEV_BCM5770_SATA   0x0241

Definition at line 20 of file svw_sata.c.

PCI_DEV_BCM5770R_SATA

#define PCI_DEV_BCM5770R_SATA   0x0242

Definition at line 21 of file svw_sata.c.

PCI_DEV_HT1000_SATA

#define PCI_DEV_HT1000_SATA   0x024A

Definition at line 22 of file svw_sata.c.

PCI_DEV_HT1000_SATA_2

#define PCI_DEV_HT1000_SATA_2   0x024B

Definition at line 23 of file svw_sata.c.

PCI_DEV_HT1100_SATA

#define PCI_DEV_HT1100_SATA   0x0410

Definition at line 24 of file svw_sata.c.

PCI_DEV_HT1100_SATA_2

#define PCI_DEV_HT1100_SATA_2   0x0411

Definition at line 25 of file svw_sata.c.

PCI_DEV_K2_SATA

#define PCI_DEV_K2_SATA   0x0240

Definition at line 19 of file svw_sata.c.

SVW_SATA_PORT_BASE_OFFSET

#define SVW_SATA_PORT_BASE_OFFSET   0x100

Definition at line 27 of file svw_sata.c.

SVW_SATA_PORT_CONTROL_OFFSET

#define SVW_SATA_PORT_CONTROL_OFFSET   0x20

Definition at line 28 of file svw_sata.c.

SVW_SATA_PORT_DMA_OFFSET

#define SVW_SATA_PORT_DMA_OFFSET   0x30

Definition at line 29 of file svw_sata.c.

SVW_SATA_PORT_SCR_OFFSET

#define SVW_SATA_PORT_SCR_OFFSET   0x40

Definition at line 30 of file svw_sata.c.

SVW_SATA_PORT_TF_STRIDE

#define SVW_SATA_PORT_TF_STRIDE   4

Definition at line 31 of file svw_sata.c.

Function Documentation

SvwSataCheckInterrupt()

static BOOLEAN SvwSataCheckInterrupt ( _In_ PCHANNEL_DATA_PATA  ChanData )

static

Definition at line 99 of file svw_sata.c.

{
    PATA_CONTROLLER Controller = ChanData->Controller;
    PUCHAR IoBase = Controller->AccessRange[SvwSataGetIoBarIndex(Controller)].IoBase;
    ULONG InterruptStatus;
 
    InterruptStatus = READ_REGISTER_ULONG((PULONG)(IoBase + 0x1F80));
    return !!(InterruptStatus & (1 << ChanData->Channel));
}

Referenced by SvwSataGetControllerProperties().

SvwSataGetControllerProperties()

NTSTATUS SvwSataGetControllerProperties

(

_Inout_ PATA_CONTROLLER

Controller

)

Definition at line 215 of file svw_sata.c.

{
    NTSTATUS Status;
    ULONG i, HwFlags;
    PUCHAR IoBase;
 
    PAGED_CODE();
    ASSERT(Controller->Pci.VendorID == PCI_VEN_SERVERWORKS);
 
    for (i = 0; i < RTL_NUMBER_OF(SvwSataControllerList); ++i)
    {
        HwFlags = SvwSataControllerList[i].Flags;
 
        if (Controller->Pci.DeviceID == SvwSataControllerList[i].DeviceID)
            break;
    }
    if (i == RTL_NUMBER_OF(SvwSataControllerList))
        return STATUS_NO_MATCH;
 
    if (HwFlags & HW_FLAGS_8_PORTS)
        Controller->MaxChannels = 8;
    else
        Controller->MaxChannels = 4;
 
    Controller->Flags |= CTRL_FLAG_MANUAL_RES;
 
    Status = PciIdeCreateChannelData(Controller, 0);
    if (!NT_SUCCESS(Status))
        return Status;
 
    IoBase = AtaCtrlPciMapBar(Controller, SvwSataGetIoBarIndex(Controller), 0);
    if (!IoBase)
        return STATUS_DEVICE_CONFIGURATION_ERROR;
 
    /*
     * Errata: Set SICR registers to turn off waiting for a status message
     * before sending FIS, fixes some issues with Seagate hard drives.
     */
    WRITE_REGISTER_ULONG((PULONG)(IoBase + 0x80),
                         READ_REGISTER_ULONG((PULONG)(IoBase + 0x80)) & ~0x00040000);
 
    /* Clear interrupts */
    WRITE_REGISTER_ULONG((PULONG)(IoBase + 0x44), 0xFFFFFFFF);
    WRITE_REGISTER_ULONG((PULONG)(IoBase + 0x88), 0);
 
    for (i = 0; i < Controller->MaxChannels; ++i)
    {
        PCHANNEL_DATA_PATA ChanData = Controller->Channels[i];
 
        ChanData->TransferModeSupported = SATA_ALL;
        ChanData->SetTransferMode = SataSetTransferMode;
 
        if (HwFlags & HW_FLAGS_NO_ATAPI_DMA)
            ChanData->ChanInfo |= CHANNEL_FLAG_NO_ATAPI_DMA;
 
        /*
         * Errata: Enable the DMA engine before sending the drive command
         * to avoid data corruption.
         */
        ChanData->ChanInfo |= CHANNEL_FLAG_DMA_BEFORE_CMD;
 
        ChanData->ChanInfo |= CHANNEL_FLAG_NO_SLAVE;
        ChanData->ReadStatus = SvwSataReadStatus;
        ChanData->LoadTaskFile = SvwSataLoadTaskFile;
        ChanData->SaveTaskFile = SvwSataSaveTaskFile;
        ChanData->CheckInterrupt = SvwSataCheckInterrupt;
        ChanData->ScrRead = SvwSataScrRead;
        ChanData->ScrWrite = SvwSataScrWrite;
 
        SvwSataParseResources(ChanData, IoBase, i);
    }
 
    return STATUS_SUCCESS;
}

Referenced by PciIdeGetControllerProperties().

SvwSataGetIoBarIndex()

static ULONG SvwSataGetIoBarIndex ( _In_ PATA_CONTROLLER  Controller )

inlinestatic

Definition at line 91 of file svw_sata.c.

{
    return (Controller->Pci.DeviceID == PCI_DEV_HT1100_SATA) ? 3 : 5;
}

Referenced by SvwSataCheckInterrupt(), and SvwSataGetControllerProperties().

SvwSataLoadTaskFile()

static VOID SvwSataLoadTaskFile ( _In_ PCHANNEL_DATA_PATA  ChanData, _In_ PATA_DEVICE_REQUEST  Request  )

static

Definition at line 124 of file svw_sata.c.

{
    USHORT Features, SectorCount, LbaLow, LbaMid, LbaHigh;
 
    Features = Request->TaskFile.Feature;
    SectorCount = Request->TaskFile.SectorCount;
    LbaLow = Request->TaskFile.LowLba;
    LbaMid = Request->TaskFile.MidLba;
    LbaHigh = Request->TaskFile.HighLba;
 
    if (Request->Flags & REQUEST_FLAG_LBA48)
    {
        Features |= (USHORT)Request->TaskFile.FeatureEx << 8;
        SectorCount |= (USHORT)Request->TaskFile.SectorCountEx << 8;
        LbaLow |= (USHORT)Request->TaskFile.LowLbaEx << 8;
        LbaMid |= (USHORT)Request->TaskFile.MidLbaEx << 8;
        LbaHigh |= (USHORT)Request->TaskFile.HighLbaEx << 8;
    }
 
    /* The SATA hardware needs 16-bit accesses for the second byte of FIFO */
    WRITE_REGISTER_USHORT((PUSHORT)ChanData->Regs.Features, Features);
    WRITE_REGISTER_USHORT((PUSHORT)ChanData->Regs.SectorCount, SectorCount);
    WRITE_REGISTER_USHORT((PUSHORT)ChanData->Regs.LbaLow, LbaLow);
    WRITE_REGISTER_USHORT((PUSHORT)ChanData->Regs.LbaMid, LbaMid);
    WRITE_REGISTER_USHORT((PUSHORT)ChanData->Regs.LbaHigh, LbaHigh);
 
    if (Request->Flags & REQUEST_FLAG_SET_DEVICE_REGISTER)
        WRITE_REGISTER_UCHAR(ChanData->Regs.Device, Request->TaskFile.DriveSelect);
}

Referenced by SvwSataGetControllerProperties().

SvwSataParseResources()

static VOID SvwSataParseResources ( _Inout_ PCHANNEL_DATA_PATA  ChanData, _In_ PUCHAR  IoBase, _In_ ULONG  PortIndex  )

static

Definition at line 193 of file svw_sata.c.

{
    PUCHAR ChanBase = IoBase + (PortIndex * SVW_SATA_PORT_BASE_OFFSET);
 
    PAGED_CODE();
 
    ChanData->ChanInfo |= CHANNEL_FLAG_MRES_TF | CHANNEL_FLAG_MRES_CTRL | CHANNEL_FLAG_MRES_DMA;
 
    ChanData->Regs.Dma = ChanBase + SVW_SATA_PORT_DMA_OFFSET;
    ChanData->Regs.Scr = ChanBase + SVW_SATA_PORT_SCR_OFFSET;
 
    PciIdeInitTaskFileIoResources(ChanData,
                                  (ULONG_PTR)ChanBase,
                                  (ULONG_PTR)ChanBase + SVW_SATA_PORT_CONTROL_OFFSET,
                                  SVW_SATA_PORT_TF_STRIDE);
}

Referenced by SvwSataGetControllerProperties().

SvwSataReadStatus()

static UCHAR SvwSataReadStatus ( _In_ PCHANNEL_DATA_PATA  ChanData )

static

Definition at line 112 of file svw_sata.c.

{
    /*
     * The SATA hardware expects 32-bit reads on the status register
     * to get it latched propertly.
     */
    return READ_REGISTER_ULONG((PULONG)ChanData->Regs.Status);
}

Referenced by SvwSataGetControllerProperties().

SvwSataSaveTaskFile()

static VOID SvwSataSaveTaskFile ( _In_ PCHANNEL_DATA_PATA  ChanData, _Inout_ PATA_DEVICE_REQUEST  Request  )

static

Definition at line 158 of file svw_sata.c.

{
    PATA_TASKFILE TaskFile = &Request->Output;
    USHORT Error, SectorCount, LbaLow, LbaMid, LbaHigh;
 
    TaskFile->DriveSelect = READ_REGISTER_UCHAR(ChanData->Regs.Device);
    TaskFile->Command = READ_REGISTER_UCHAR(ChanData->Regs.Command);
 
    Error = READ_REGISTER_USHORT((PUSHORT)ChanData->Regs.Error);
    SectorCount = READ_REGISTER_USHORT((PUSHORT)ChanData->Regs.SectorCount);
    LbaLow = READ_REGISTER_USHORT((PUSHORT)ChanData->Regs.LbaLow);
    LbaMid = READ_REGISTER_USHORT((PUSHORT)ChanData->Regs.LbaMid);
    LbaHigh = READ_REGISTER_USHORT((PUSHORT)ChanData->Regs.LbaHigh);
 
    TaskFile->Error = Error & 0xFF;
    TaskFile->SectorCount = SectorCount & 0xFF;
    TaskFile->LowLba = LbaLow & 0xFF;
    TaskFile->MidLba = LbaMid & 0xFF;
    TaskFile->HighLba = LbaHigh & 0xFF;
 
    if (Request->Flags & REQUEST_FLAG_LBA48)
    {
        TaskFile->FeatureEx = Error >> 8;
        TaskFile->SectorCountEx = SectorCount >> 8;
        TaskFile->LowLbaEx = LbaLow >> 8;
        TaskFile->MidLbaEx = LbaMid >> 8;
        TaskFile->HighLbaEx = LbaHigh >> 8;
    }
}

Referenced by SvwSataGetControllerProperties().

SvwSataScrRead()

static BOOLEAN SvwSataScrRead ( _In_ PCHANNEL_DATA_PATA  ChanData, _In_ SATA_SCR_REGISTER  Register, _In_ ULONG  PortNumber, _In_ PULONG  Result  )

static

Definition at line 56 of file svw_sata.c.

{
    UNREFERENCED_PARAMETER(PortNumber);
 
    if (Register > ATA_SCONTROL)
        return FALSE;
 
    *Result = READ_REGISTER_ULONG((PULONG)(ChanData->Regs.Scr + (Register * 4)));
    return TRUE;
}

Referenced by SvwSataGetControllerProperties().

SvwSataScrWrite()

static BOOLEAN SvwSataScrWrite ( _In_ PCHANNEL_DATA_PATA  ChanData, _In_ SATA_SCR_REGISTER  Register, _In_ ULONG  PortNumber, _In_ ULONG  Value  )

static

Definition at line 73 of file svw_sata.c.

{
    UNREFERENCED_PARAMETER(PortNumber);
 
    if (Register > ATA_SCONTROL)
        return FALSE;
 
    WRITE_REGISTER_ULONG((PULONG)(ChanData->Regs.Scr + (Register * 4)), Value);
    return TRUE;
}

Referenced by SvwSataGetControllerProperties().

Variable Documentation

DeviceID

USHORT DeviceID

Definition at line 39 of file svw_sata.c.

Flags

USHORT Flags

Definition at line 40 of file svw_sata.c.

PCIIDEX_PAGED_DATA const struct { ... } SvwSataControllerList[]

Initial value:

=
{
    { PCI_DEV_K2_SATA,       HW_FLAGS_NO_ATAPI_DMA },
    { PCI_DEV_BCM5770_SATA,  HW_FLAGS_NO_ATAPI_DMA | HW_FLAGS_8_PORTS },
    { PCI_DEV_BCM5770R_SATA, HW_FLAGS_NO_ATAPI_DMA },
    { PCI_DEV_HT1000_SATA,   HW_FLAGS_NO_ATAPI_DMA },
    { PCI_DEV_HT1000_SATA_2, HW_FLAGS_NO_ATAPI_DMA },
    { PCI_DEV_HT1100_SATA,   0 },
    { PCI_DEV_HT1100_SATA_2, 0 },
}

Referenced by SvwSataGetControllerProperties().