cpu.h File Reference

#include <string.h>
#include "mem.h"

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Go to the source code of this file.

Classes
struct	ZSTD_cpuid_t

Macros
#define	X(name, r, bit)
#define	C(name, bit)   X(name, f1c, bit)
#define	D(name, bit)   X(name, f1d, bit)
#define	B(name, bit)   X(name, f7b, bit)
#define	C(name, bit)   X(name, f7c, bit)

Functions
MEM_STATIC ZSTD_cpuid_t	ZSTD_cpuid (void)
	C (sse3, 0) C(pclmuldq
	C (dtes64, 2) C(monitor
	C (dscpl, 4) C(vmx
	C (smx, 6) C(eist
	C (tm2, 8) C(ssse3
	C (cnxtid, 10) C(fma
	C (cx16, 13) C(xtpr
	C (pdcm, 15) C(pcid
	C (dca, 18) C(sse41
	C (sse42, 20) C(x2apic
	C (movbe, 22) C(popcnt
	C (tscdeadline, 24) C(aes
	C (xsave, 26) C(osxsave
	C (avx, 28) C(f16c
	C (rdrand, 30) D(fpu
	D (vme, 1) D(de
	D (pse, 3) D(tsc
	D (msr, 5) D(pae
	D (mce, 7) D(cx8
	D (apic, 9) D(sep
	D (mtrr, 12) D(pge
	D (mca, 14) D(cmov
	D (pat, 16) D(pse36
	D (psn, 18) D(clfsh
	D (ds, 21) D(acpi
	D (mmx, 23) D(fxsr
	D (sse, 25) D(sse2
	D (ss, 27) D(htt
	D (tm, 29) D(pbe
	B (bmi1, 3) B(hle
	B (avx2, 5) B(smep
	B (bmi2, 8) B(erms
	B (invpcid, 10) B(rtm
	B (mpx, 14) B(avx512f
	B (avx512dq, 17) B(rdseed
	B (adx, 19) B(smap
	B (avx512ifma, 21) B(pcommit
	B (clflushopt, 23) B(clwb
	B (avx512pf, 26) B(avx512er
	B (avx512cd, 28) B(sha
	B (avx512bw, 30) B(avx512vl
	C (prefetchwt1, 0) C(avx512vbmi

Macro Definition Documentation

B

#define B	(		name,
			bit
	)		X(name, f7b, bit)

Definition at line 182 of file cpu.h.

C [1/2]

#define C	(		name,
			bit
	)		X(name, f1c, bit)

Definition at line 208 of file cpu.h.

C [2/2]

#define C	(		name,
			bit
	)		X(name, f7c, bit)

Definition at line 208 of file cpu.h.

D

#define D	(		name,
			bit
	)		X(name, f1d, bit)

X

#define X	(		name,
			r,
			bit
	)

Value:

  MEM_STATIC int ZSTD_cpuid_##name(ZSTD_cpuid_t const cpuid) {                 \
    return ((cpuid.r) & (1U << bit)) != 0;                                     \
  }

Definition at line 112 of file cpu.h.

Function Documentation

B() [1/12]

B	(	adx	,
		19
	)

B() [2/12]

B	(	avx2	,
		5
	)

B() [3/12]

B	(	avx512bw	,
		30
	)

B() [4/12]

B	(	avx512cd	,
		28
	)

B() [5/12]

B	(	avx512dq	,
		17
	)

B() [6/12]

B	(	avx512ifma	,
		21
	)

B() [7/12]

B	(	avx512pf	,
		26
	)

B() [8/12]

B	(	bmi1	,
		3
	)

B() [9/12]

B	(	bmi2	,
		8
	)

B() [10/12]

B	(	clflushopt	,
		23
	)

B() [11/12]

B	(	invpcid	,
		10
	)

B() [12/12]

B	(	mpx	,
		14
	)

C() [1/16]

C	(	avx	,
		28
	)

C() [2/16]

C	(	cnxtid	,
		10
	)

C() [3/16]

C	(	cx16	,
		13
	)

C() [4/16]

C	(	dca	,
		18
	)

C() [5/16]

C	(	dscpl	,
		4
	)

C() [6/16]

C	(	dtes64	,
		2
	)

C() [7/16]

C	(	movbe	,
		22
	)

C() [8/16]

C	(	pdcm	,
		15
	)

C() [9/16]

C	(	prefetchwt1	,
		0
	)

C() [10/16]

C	(	rdrand	,
		30
	)

C() [11/16]

C	(	smx	,
		6
	)

C() [12/16]

C	(	sse3	,
		0
	)

C() [13/16]

C	(	sse42	,
		20
	)

C() [14/16]

C	(	tm2	,
		8
	)

C() [15/16]

C	(	tscdeadline	,
		24
	)

C() [16/16]

C	(	xsave	,
		26
	)

D() [1/14]

D	(	apic	,
		9
	)

D() [2/14]

D	(	ds	,
		21
	)

D() [3/14]

D	(	mca	,
		14
	)

D() [4/14]

D	(	mce	,
		7
	)

D() [5/14]

D	(	mmx	,
		23
	)

D() [6/14]

D	(	msr	,
		5
	)

D() [7/14]

D	(	mtrr	,
		12
	)

D() [8/14]

D	(	pat	,
		16
	)

D() [9/14]

D	(	pse	,
		3
	)

D() [10/14]

D	(	psn	,
		18
	)

D() [11/14]

D	(	ss	,
		27
	)

D() [12/14]

D	(	sse	,
		25
	)

D() [13/14]

D	(	tm	,
		29
	)

D() [14/14]

D	(	vme	,
		1
	)

ZSTD_cpuid()

MEM_STATIC ZSTD_cpuid_t ZSTD_cpuid

(

void

)

Definition at line 34 of file cpu.h.

                                         {
    U32 f1c = 0;
    U32 f1d = 0;
    U32 f7b = 0;
    U32 f7c = 0;
#if defined(_MSC_VER) && (defined(_M_X64) || defined(_M_IX86))
    int reg[4];
    __cpuid((int*)reg, 0);
    {
        int const n = reg[0];
        if (n >= 1) {
            __cpuid((int*)reg, 1);
            f1c = (U32)reg[2];
            f1d = (U32)reg[3];
        }
        if (n >= 7) {
            __cpuidex((int*)reg, 7, 0);
            f7b = (U32)reg[1];
            f7c = (U32)reg[2];
        }
    }
#elif defined(__i386__) && defined(__PIC__) && !defined(__clang__) && defined(__GNUC__)
    /* The following block like the normal cpuid branch below, but gcc
     * reserves ebx for use of its pic register so we must specially
     * handle the save and restore to avoid clobbering the register
     */
    U32 n;
    __asm__(
        "pushl %%ebx\n\t"
        "cpuid\n\t"
        "popl %%ebx\n\t"
        : "=a"(n)
        : "a"(0)
        : "ecx", "edx");
    if (n >= 1) {
      U32 f1a;
      __asm__(
          "pushl %%ebx\n\t"
          "cpuid\n\t"
          "popl %%ebx\n\t"
          : "=a"(f1a), "=c"(f1c), "=d"(f1d)
          : "a"(1));
    }
    if (n >= 7) {
      __asm__(
          "pushl %%ebx\n\t"
          "cpuid\n\t"
          "movl %%ebx, %%eax\n\t"
          "popl %%ebx"
          : "=a"(f7b), "=c"(f7c)
          : "a"(7), "c"(0)
          : "edx");
    }
#elif defined(__x86_64__) || defined(_M_X64) || defined(__i386__)
    U32 n;
    __asm__("cpuid" : "=a"(n) : "a"(0) : "ebx", "ecx", "edx");
    if (n >= 1) {
      U32 f1a;
      __asm__("cpuid" : "=a"(f1a), "=c"(f1c), "=d"(f1d) : "a"(1) : "ebx");
    }
    if (n >= 7) {
      U32 f7a;
      __asm__("cpuid"
              : "=a"(f7a), "=b"(f7b), "=c"(f7c)
              : "a"(7), "c"(0)
              : "edx");
    }
#endif
    {
        ZSTD_cpuid_t cpuid;
        cpuid.f1c = f1c;
        cpuid.f1d = f1d;
        cpuid.f7b = f7b;
        cpuid.f7c = f7c;
        return cpuid;
    }
}

Referenced by ZSTD_initCCtx(), ZSTD_initDCtx_internal(), and ZSTD_initStaticCCtx().